nv04_software.c 3.7 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "drmP.h"
  25. #include "nouveau_drv.h"
  26. #include "nouveau_ramht.h"
  27. #include "nouveau_fence.h"
  28. #include "nouveau_software.h"
  29. #include "nouveau_hw.h"
  30. struct nv04_software_priv {
  31. struct nouveau_software_priv base;
  32. };
  33. struct nv04_software_chan {
  34. struct nouveau_software_chan base;
  35. };
  36. static int
  37. mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
  38. {
  39. struct nouveau_page_flip_state state;
  40. if (!nouveau_finish_page_flip(chan, &state)) {
  41. nv_set_crtc_base(chan->dev, state.crtc, state.offset +
  42. state.y * state.pitch +
  43. state.x * state.bpp / 8);
  44. }
  45. return 0;
  46. }
  47. static int
  48. nv04_software_context_new(struct nouveau_channel *chan, int engine)
  49. {
  50. struct nv04_software_chan *pch;
  51. pch = kzalloc(sizeof(*pch), GFP_KERNEL);
  52. if (!pch)
  53. return -ENOMEM;
  54. nouveau_software_context_new(&pch->base);
  55. chan->engctx[engine] = pch;
  56. return 0;
  57. }
  58. static void
  59. nv04_software_context_del(struct nouveau_channel *chan, int engine)
  60. {
  61. struct nv04_software_chan *pch = chan->engctx[engine];
  62. chan->engctx[engine] = NULL;
  63. kfree(pch);
  64. }
  65. static int
  66. nv04_software_object_new(struct nouveau_channel *chan, int engine,
  67. u32 handle, u16 class)
  68. {
  69. struct drm_device *dev = chan->dev;
  70. struct nouveau_gpuobj *obj = NULL;
  71. int ret;
  72. ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
  73. if (ret)
  74. return ret;
  75. obj->engine = 0;
  76. obj->class = class;
  77. ret = nouveau_ramht_insert(chan, handle, obj);
  78. nouveau_gpuobj_ref(NULL, &obj);
  79. return ret;
  80. }
  81. static int
  82. nv04_software_init(struct drm_device *dev, int engine)
  83. {
  84. return 0;
  85. }
  86. static int
  87. nv04_software_fini(struct drm_device *dev, int engine, bool suspend)
  88. {
  89. return 0;
  90. }
  91. static void
  92. nv04_software_destroy(struct drm_device *dev, int engine)
  93. {
  94. struct nv04_software_priv *psw = nv_engine(dev, engine);
  95. NVOBJ_ENGINE_DEL(dev, SW);
  96. kfree(psw);
  97. }
  98. int
  99. nv04_software_create(struct drm_device *dev)
  100. {
  101. struct drm_nouveau_private *dev_priv = dev->dev_private;
  102. struct nv04_software_priv *psw;
  103. psw = kzalloc(sizeof(*psw), GFP_KERNEL);
  104. if (!psw)
  105. return -ENOMEM;
  106. psw->base.base.destroy = nv04_software_destroy;
  107. psw->base.base.init = nv04_software_init;
  108. psw->base.base.fini = nv04_software_fini;
  109. psw->base.base.context_new = nv04_software_context_new;
  110. psw->base.base.context_del = nv04_software_context_del;
  111. psw->base.base.object_new = nv04_software_object_new;
  112. nouveau_software_create(&psw->base);
  113. NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
  114. if (dev_priv->card_type <= NV_04) {
  115. NVOBJ_CLASS(dev, 0x006e, SW);
  116. NVOBJ_MTHD (dev, 0x006e, 0x0150, nv04_fence_mthd);
  117. NVOBJ_MTHD (dev, 0x006e, 0x0500, mthd_flip);
  118. } else {
  119. NVOBJ_CLASS(dev, 0x016e, SW);
  120. NVOBJ_MTHD (dev, 0x016e, 0x0500, mthd_flip);
  121. }
  122. return 0;
  123. }