i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/slab.h>
  39. #include <linux/pagemap.h>
  40. #define I810_BUF_FREE 2
  41. #define I810_BUF_CLIENT 1
  42. #define I810_BUF_HARDWARE 0
  43. #define I810_BUF_UNMAPPED 0
  44. #define I810_BUF_MAPPED 1
  45. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  46. {
  47. struct drm_device_dma *dma = dev->dma;
  48. int i;
  49. int used;
  50. /* Linear search might not be the best solution */
  51. for (i = 0; i < dma->buf_count; i++) {
  52. struct drm_buf *buf = dma->buflist[i];
  53. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  54. /* In use is already a pointer */
  55. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  56. I810_BUF_CLIENT);
  57. if (used == I810_BUF_FREE)
  58. return buf;
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. dev = priv->minor->dev;
  85. dev_priv = dev->dev_private;
  86. buf = dev_priv->mmap_buffer;
  87. buf_priv = buf->dev_private;
  88. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  89. buf_priv->currently_mapped = I810_BUF_MAPPED;
  90. if (io_remap_pfn_range(vma, vma->vm_start,
  91. vma->vm_pgoff,
  92. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  93. return -EAGAIN;
  94. return 0;
  95. }
  96. static const struct file_operations i810_buffer_fops = {
  97. .open = drm_open,
  98. .release = drm_release,
  99. .unlocked_ioctl = drm_ioctl,
  100. .mmap = i810_mmap_buffers,
  101. .fasync = drm_fasync,
  102. .llseek = noop_llseek,
  103. };
  104. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  105. {
  106. struct drm_device *dev = file_priv->minor->dev;
  107. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  108. drm_i810_private_t *dev_priv = dev->dev_private;
  109. const struct file_operations *old_fops;
  110. int retcode = 0;
  111. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  112. return -EINVAL;
  113. /* This is all entirely broken */
  114. old_fops = file_priv->filp->f_op;
  115. file_priv->filp->f_op = &i810_buffer_fops;
  116. dev_priv->mmap_buffer = buf;
  117. buf_priv->virtual = (void *)vm_mmap(file_priv->filp, 0, buf->total,
  118. PROT_READ | PROT_WRITE,
  119. MAP_SHARED, buf->bus_address);
  120. dev_priv->mmap_buffer = NULL;
  121. file_priv->filp->f_op = old_fops;
  122. if (IS_ERR(buf_priv->virtual)) {
  123. /* Real error */
  124. DRM_ERROR("mmap error\n");
  125. retcode = PTR_ERR(buf_priv->virtual);
  126. buf_priv->virtual = NULL;
  127. }
  128. return retcode;
  129. }
  130. static int i810_unmap_buffer(struct drm_buf *buf)
  131. {
  132. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  133. int retcode = 0;
  134. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  135. return -EINVAL;
  136. retcode = vm_munmap((unsigned long)buf_priv->virtual,
  137. (size_t) buf->total);
  138. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  139. buf_priv->virtual = NULL;
  140. return retcode;
  141. }
  142. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  143. struct drm_file *file_priv)
  144. {
  145. struct drm_buf *buf;
  146. drm_i810_buf_priv_t *buf_priv;
  147. int retcode = 0;
  148. buf = i810_freelist_get(dev);
  149. if (!buf) {
  150. retcode = -ENOMEM;
  151. DRM_DEBUG("retcode=%d\n", retcode);
  152. return retcode;
  153. }
  154. retcode = i810_map_buffer(buf, file_priv);
  155. if (retcode) {
  156. i810_freelist_put(dev, buf);
  157. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  158. return retcode;
  159. }
  160. buf->file_priv = file_priv;
  161. buf_priv = buf->dev_private;
  162. d->granted = 1;
  163. d->request_idx = buf->idx;
  164. d->request_size = buf->total;
  165. d->virtual = buf_priv->virtual;
  166. return retcode;
  167. }
  168. static int i810_dma_cleanup(struct drm_device *dev)
  169. {
  170. struct drm_device_dma *dma = dev->dma;
  171. /* Make sure interrupts are disabled here because the uninstall ioctl
  172. * may not have been called from userspace and after dev_private
  173. * is freed, it's too late.
  174. */
  175. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  176. drm_irq_uninstall(dev);
  177. if (dev->dev_private) {
  178. int i;
  179. drm_i810_private_t *dev_priv =
  180. (drm_i810_private_t *) dev->dev_private;
  181. if (dev_priv->ring.virtual_start)
  182. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  183. if (dev_priv->hw_status_page) {
  184. pci_free_consistent(dev->pdev, PAGE_SIZE,
  185. dev_priv->hw_status_page,
  186. dev_priv->dma_status_page);
  187. }
  188. kfree(dev->dev_private);
  189. dev->dev_private = NULL;
  190. for (i = 0; i < dma->buf_count; i++) {
  191. struct drm_buf *buf = dma->buflist[i];
  192. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  193. if (buf_priv->kernel_virtual && buf->total)
  194. drm_core_ioremapfree(&buf_priv->map, dev);
  195. }
  196. }
  197. return 0;
  198. }
  199. static int i810_wait_ring(struct drm_device *dev, int n)
  200. {
  201. drm_i810_private_t *dev_priv = dev->dev_private;
  202. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  203. int iters = 0;
  204. unsigned long end;
  205. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  206. end = jiffies + (HZ * 3);
  207. while (ring->space < n) {
  208. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  209. ring->space = ring->head - (ring->tail + 8);
  210. if (ring->space < 0)
  211. ring->space += ring->Size;
  212. if (ring->head != last_head) {
  213. end = jiffies + (HZ * 3);
  214. last_head = ring->head;
  215. }
  216. iters++;
  217. if (time_before(end, jiffies)) {
  218. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  219. DRM_ERROR("lockup\n");
  220. goto out_wait_ring;
  221. }
  222. udelay(1);
  223. }
  224. out_wait_ring:
  225. return iters;
  226. }
  227. static void i810_kernel_lost_context(struct drm_device *dev)
  228. {
  229. drm_i810_private_t *dev_priv = dev->dev_private;
  230. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  231. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  232. ring->tail = I810_READ(LP_RING + RING_TAIL);
  233. ring->space = ring->head - (ring->tail + 8);
  234. if (ring->space < 0)
  235. ring->space += ring->Size;
  236. }
  237. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  238. {
  239. struct drm_device_dma *dma = dev->dma;
  240. int my_idx = 24;
  241. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  242. int i;
  243. if (dma->buf_count > 1019) {
  244. /* Not enough space in the status page for the freelist */
  245. return -EINVAL;
  246. }
  247. for (i = 0; i < dma->buf_count; i++) {
  248. struct drm_buf *buf = dma->buflist[i];
  249. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  250. buf_priv->in_use = hw_status++;
  251. buf_priv->my_use_idx = my_idx;
  252. my_idx += 4;
  253. *buf_priv->in_use = I810_BUF_FREE;
  254. buf_priv->map.offset = buf->bus_address;
  255. buf_priv->map.size = buf->total;
  256. buf_priv->map.type = _DRM_AGP;
  257. buf_priv->map.flags = 0;
  258. buf_priv->map.mtrr = 0;
  259. drm_core_ioremap(&buf_priv->map, dev);
  260. buf_priv->kernel_virtual = buf_priv->map.handle;
  261. }
  262. return 0;
  263. }
  264. static int i810_dma_initialize(struct drm_device *dev,
  265. drm_i810_private_t *dev_priv,
  266. drm_i810_init_t *init)
  267. {
  268. struct drm_map_list *r_list;
  269. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  270. list_for_each_entry(r_list, &dev->maplist, head) {
  271. if (r_list->map &&
  272. r_list->map->type == _DRM_SHM &&
  273. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  274. dev_priv->sarea_map = r_list->map;
  275. break;
  276. }
  277. }
  278. if (!dev_priv->sarea_map) {
  279. dev->dev_private = (void *)dev_priv;
  280. i810_dma_cleanup(dev);
  281. DRM_ERROR("can not find sarea!\n");
  282. return -EINVAL;
  283. }
  284. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  285. if (!dev_priv->mmio_map) {
  286. dev->dev_private = (void *)dev_priv;
  287. i810_dma_cleanup(dev);
  288. DRM_ERROR("can not find mmio map!\n");
  289. return -EINVAL;
  290. }
  291. dev->agp_buffer_token = init->buffers_offset;
  292. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  293. if (!dev->agp_buffer_map) {
  294. dev->dev_private = (void *)dev_priv;
  295. i810_dma_cleanup(dev);
  296. DRM_ERROR("can not find dma buffer map!\n");
  297. return -EINVAL;
  298. }
  299. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  300. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  301. dev_priv->ring.Start = init->ring_start;
  302. dev_priv->ring.End = init->ring_end;
  303. dev_priv->ring.Size = init->ring_size;
  304. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  305. dev_priv->ring.map.size = init->ring_size;
  306. dev_priv->ring.map.type = _DRM_AGP;
  307. dev_priv->ring.map.flags = 0;
  308. dev_priv->ring.map.mtrr = 0;
  309. drm_core_ioremap(&dev_priv->ring.map, dev);
  310. if (dev_priv->ring.map.handle == NULL) {
  311. dev->dev_private = (void *)dev_priv;
  312. i810_dma_cleanup(dev);
  313. DRM_ERROR("can not ioremap virtual address for"
  314. " ring buffer\n");
  315. return -ENOMEM;
  316. }
  317. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  318. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  319. dev_priv->w = init->w;
  320. dev_priv->h = init->h;
  321. dev_priv->pitch = init->pitch;
  322. dev_priv->back_offset = init->back_offset;
  323. dev_priv->depth_offset = init->depth_offset;
  324. dev_priv->front_offset = init->front_offset;
  325. dev_priv->overlay_offset = init->overlay_offset;
  326. dev_priv->overlay_physical = init->overlay_physical;
  327. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  328. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  329. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  330. /* Program Hardware Status Page */
  331. dev_priv->hw_status_page =
  332. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  333. &dev_priv->dma_status_page);
  334. if (!dev_priv->hw_status_page) {
  335. dev->dev_private = (void *)dev_priv;
  336. i810_dma_cleanup(dev);
  337. DRM_ERROR("Can not allocate hardware status page\n");
  338. return -ENOMEM;
  339. }
  340. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  341. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  342. I810_WRITE(0x02080, dev_priv->dma_status_page);
  343. DRM_DEBUG("Enabled hardware status page\n");
  344. /* Now we need to init our freelist */
  345. if (i810_freelist_init(dev, dev_priv) != 0) {
  346. dev->dev_private = (void *)dev_priv;
  347. i810_dma_cleanup(dev);
  348. DRM_ERROR("Not enough space in the status page for"
  349. " the freelist\n");
  350. return -ENOMEM;
  351. }
  352. dev->dev_private = (void *)dev_priv;
  353. return 0;
  354. }
  355. static int i810_dma_init(struct drm_device *dev, void *data,
  356. struct drm_file *file_priv)
  357. {
  358. drm_i810_private_t *dev_priv;
  359. drm_i810_init_t *init = data;
  360. int retcode = 0;
  361. switch (init->func) {
  362. case I810_INIT_DMA_1_4:
  363. DRM_INFO("Using v1.4 init.\n");
  364. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  365. if (dev_priv == NULL)
  366. return -ENOMEM;
  367. retcode = i810_dma_initialize(dev, dev_priv, init);
  368. break;
  369. case I810_CLEANUP_DMA:
  370. DRM_INFO("DMA Cleanup\n");
  371. retcode = i810_dma_cleanup(dev);
  372. break;
  373. default:
  374. return -EINVAL;
  375. }
  376. return retcode;
  377. }
  378. /* Most efficient way to verify state for the i810 is as it is
  379. * emitted. Non-conformant state is silently dropped.
  380. *
  381. * Use 'volatile' & local var tmp to force the emitted values to be
  382. * identical to the verified ones.
  383. */
  384. static void i810EmitContextVerified(struct drm_device *dev,
  385. volatile unsigned int *code)
  386. {
  387. drm_i810_private_t *dev_priv = dev->dev_private;
  388. int i, j = 0;
  389. unsigned int tmp;
  390. RING_LOCALS;
  391. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  392. OUT_RING(GFX_OP_COLOR_FACTOR);
  393. OUT_RING(code[I810_CTXREG_CF1]);
  394. OUT_RING(GFX_OP_STIPPLE);
  395. OUT_RING(code[I810_CTXREG_ST1]);
  396. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  397. tmp = code[i];
  398. if ((tmp & (7 << 29)) == (3 << 29) &&
  399. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  400. OUT_RING(tmp);
  401. j++;
  402. } else
  403. printk("constext state dropped!!!\n");
  404. }
  405. if (j & 1)
  406. OUT_RING(0);
  407. ADVANCE_LP_RING();
  408. }
  409. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  410. {
  411. drm_i810_private_t *dev_priv = dev->dev_private;
  412. int i, j = 0;
  413. unsigned int tmp;
  414. RING_LOCALS;
  415. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  416. OUT_RING(GFX_OP_MAP_INFO);
  417. OUT_RING(code[I810_TEXREG_MI1]);
  418. OUT_RING(code[I810_TEXREG_MI2]);
  419. OUT_RING(code[I810_TEXREG_MI3]);
  420. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  421. tmp = code[i];
  422. if ((tmp & (7 << 29)) == (3 << 29) &&
  423. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  424. OUT_RING(tmp);
  425. j++;
  426. } else
  427. printk("texture state dropped!!!\n");
  428. }
  429. if (j & 1)
  430. OUT_RING(0);
  431. ADVANCE_LP_RING();
  432. }
  433. /* Need to do some additional checking when setting the dest buffer.
  434. */
  435. static void i810EmitDestVerified(struct drm_device *dev,
  436. volatile unsigned int *code)
  437. {
  438. drm_i810_private_t *dev_priv = dev->dev_private;
  439. unsigned int tmp;
  440. RING_LOCALS;
  441. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  442. tmp = code[I810_DESTREG_DI1];
  443. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  444. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  445. OUT_RING(tmp);
  446. } else
  447. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  448. tmp, dev_priv->front_di1, dev_priv->back_di1);
  449. /* invarient:
  450. */
  451. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  452. OUT_RING(dev_priv->zi1);
  453. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  454. OUT_RING(code[I810_DESTREG_DV1]);
  455. OUT_RING(GFX_OP_DRAWRECT_INFO);
  456. OUT_RING(code[I810_DESTREG_DR1]);
  457. OUT_RING(code[I810_DESTREG_DR2]);
  458. OUT_RING(code[I810_DESTREG_DR3]);
  459. OUT_RING(code[I810_DESTREG_DR4]);
  460. OUT_RING(0);
  461. ADVANCE_LP_RING();
  462. }
  463. static void i810EmitState(struct drm_device *dev)
  464. {
  465. drm_i810_private_t *dev_priv = dev->dev_private;
  466. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  467. unsigned int dirty = sarea_priv->dirty;
  468. DRM_DEBUG("%x\n", dirty);
  469. if (dirty & I810_UPLOAD_BUFFERS) {
  470. i810EmitDestVerified(dev, sarea_priv->BufferState);
  471. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  472. }
  473. if (dirty & I810_UPLOAD_CTX) {
  474. i810EmitContextVerified(dev, sarea_priv->ContextState);
  475. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  476. }
  477. if (dirty & I810_UPLOAD_TEX0) {
  478. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  479. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  480. }
  481. if (dirty & I810_UPLOAD_TEX1) {
  482. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  483. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  484. }
  485. }
  486. /* need to verify
  487. */
  488. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  489. unsigned int clear_color,
  490. unsigned int clear_zval)
  491. {
  492. drm_i810_private_t *dev_priv = dev->dev_private;
  493. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  494. int nbox = sarea_priv->nbox;
  495. struct drm_clip_rect *pbox = sarea_priv->boxes;
  496. int pitch = dev_priv->pitch;
  497. int cpp = 2;
  498. int i;
  499. RING_LOCALS;
  500. if (dev_priv->current_page == 1) {
  501. unsigned int tmp = flags;
  502. flags &= ~(I810_FRONT | I810_BACK);
  503. if (tmp & I810_FRONT)
  504. flags |= I810_BACK;
  505. if (tmp & I810_BACK)
  506. flags |= I810_FRONT;
  507. }
  508. i810_kernel_lost_context(dev);
  509. if (nbox > I810_NR_SAREA_CLIPRECTS)
  510. nbox = I810_NR_SAREA_CLIPRECTS;
  511. for (i = 0; i < nbox; i++, pbox++) {
  512. unsigned int x = pbox->x1;
  513. unsigned int y = pbox->y1;
  514. unsigned int width = (pbox->x2 - x) * cpp;
  515. unsigned int height = pbox->y2 - y;
  516. unsigned int start = y * pitch + x * cpp;
  517. if (pbox->x1 > pbox->x2 ||
  518. pbox->y1 > pbox->y2 ||
  519. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  520. continue;
  521. if (flags & I810_FRONT) {
  522. BEGIN_LP_RING(6);
  523. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  524. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  525. OUT_RING((height << 16) | width);
  526. OUT_RING(start);
  527. OUT_RING(clear_color);
  528. OUT_RING(0);
  529. ADVANCE_LP_RING();
  530. }
  531. if (flags & I810_BACK) {
  532. BEGIN_LP_RING(6);
  533. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  534. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  535. OUT_RING((height << 16) | width);
  536. OUT_RING(dev_priv->back_offset + start);
  537. OUT_RING(clear_color);
  538. OUT_RING(0);
  539. ADVANCE_LP_RING();
  540. }
  541. if (flags & I810_DEPTH) {
  542. BEGIN_LP_RING(6);
  543. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  544. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  545. OUT_RING((height << 16) | width);
  546. OUT_RING(dev_priv->depth_offset + start);
  547. OUT_RING(clear_zval);
  548. OUT_RING(0);
  549. ADVANCE_LP_RING();
  550. }
  551. }
  552. }
  553. static void i810_dma_dispatch_swap(struct drm_device *dev)
  554. {
  555. drm_i810_private_t *dev_priv = dev->dev_private;
  556. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  557. int nbox = sarea_priv->nbox;
  558. struct drm_clip_rect *pbox = sarea_priv->boxes;
  559. int pitch = dev_priv->pitch;
  560. int cpp = 2;
  561. int i;
  562. RING_LOCALS;
  563. DRM_DEBUG("swapbuffers\n");
  564. i810_kernel_lost_context(dev);
  565. if (nbox > I810_NR_SAREA_CLIPRECTS)
  566. nbox = I810_NR_SAREA_CLIPRECTS;
  567. for (i = 0; i < nbox; i++, pbox++) {
  568. unsigned int w = pbox->x2 - pbox->x1;
  569. unsigned int h = pbox->y2 - pbox->y1;
  570. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  571. unsigned int start = dst;
  572. if (pbox->x1 > pbox->x2 ||
  573. pbox->y1 > pbox->y2 ||
  574. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  575. continue;
  576. BEGIN_LP_RING(6);
  577. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  578. OUT_RING(pitch | (0xCC << 16));
  579. OUT_RING((h << 16) | (w * cpp));
  580. if (dev_priv->current_page == 0)
  581. OUT_RING(dev_priv->front_offset + start);
  582. else
  583. OUT_RING(dev_priv->back_offset + start);
  584. OUT_RING(pitch);
  585. if (dev_priv->current_page == 0)
  586. OUT_RING(dev_priv->back_offset + start);
  587. else
  588. OUT_RING(dev_priv->front_offset + start);
  589. ADVANCE_LP_RING();
  590. }
  591. }
  592. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  593. struct drm_buf *buf, int discard, int used)
  594. {
  595. drm_i810_private_t *dev_priv = dev->dev_private;
  596. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  597. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  598. struct drm_clip_rect *box = sarea_priv->boxes;
  599. int nbox = sarea_priv->nbox;
  600. unsigned long address = (unsigned long)buf->bus_address;
  601. unsigned long start = address - dev->agp->base;
  602. int i = 0;
  603. RING_LOCALS;
  604. i810_kernel_lost_context(dev);
  605. if (nbox > I810_NR_SAREA_CLIPRECTS)
  606. nbox = I810_NR_SAREA_CLIPRECTS;
  607. if (used > 4 * 1024)
  608. used = 0;
  609. if (sarea_priv->dirty)
  610. i810EmitState(dev);
  611. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  612. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  613. *(u32 *) buf_priv->kernel_virtual =
  614. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  615. if (used & 4) {
  616. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  617. used += 4;
  618. }
  619. i810_unmap_buffer(buf);
  620. }
  621. if (used) {
  622. do {
  623. if (i < nbox) {
  624. BEGIN_LP_RING(4);
  625. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  626. SC_ENABLE);
  627. OUT_RING(GFX_OP_SCISSOR_INFO);
  628. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  629. OUT_RING((box[i].x2 -
  630. 1) | ((box[i].y2 - 1) << 16));
  631. ADVANCE_LP_RING();
  632. }
  633. BEGIN_LP_RING(4);
  634. OUT_RING(CMD_OP_BATCH_BUFFER);
  635. OUT_RING(start | BB1_PROTECTED);
  636. OUT_RING(start + used - 4);
  637. OUT_RING(0);
  638. ADVANCE_LP_RING();
  639. } while (++i < nbox);
  640. }
  641. if (discard) {
  642. dev_priv->counter++;
  643. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  644. I810_BUF_HARDWARE);
  645. BEGIN_LP_RING(8);
  646. OUT_RING(CMD_STORE_DWORD_IDX);
  647. OUT_RING(20);
  648. OUT_RING(dev_priv->counter);
  649. OUT_RING(CMD_STORE_DWORD_IDX);
  650. OUT_RING(buf_priv->my_use_idx);
  651. OUT_RING(I810_BUF_FREE);
  652. OUT_RING(CMD_REPORT_HEAD);
  653. OUT_RING(0);
  654. ADVANCE_LP_RING();
  655. }
  656. }
  657. static void i810_dma_dispatch_flip(struct drm_device *dev)
  658. {
  659. drm_i810_private_t *dev_priv = dev->dev_private;
  660. int pitch = dev_priv->pitch;
  661. RING_LOCALS;
  662. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  663. dev_priv->current_page,
  664. dev_priv->sarea_priv->pf_current_page);
  665. i810_kernel_lost_context(dev);
  666. BEGIN_LP_RING(2);
  667. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  668. OUT_RING(0);
  669. ADVANCE_LP_RING();
  670. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  671. /* On i815 at least ASYNC is buggy */
  672. /* pitch<<5 is from 11.2.8 p158,
  673. its the pitch / 8 then left shifted 8,
  674. so (pitch >> 3) << 8 */
  675. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  676. if (dev_priv->current_page == 0) {
  677. OUT_RING(dev_priv->back_offset);
  678. dev_priv->current_page = 1;
  679. } else {
  680. OUT_RING(dev_priv->front_offset);
  681. dev_priv->current_page = 0;
  682. }
  683. OUT_RING(0);
  684. ADVANCE_LP_RING();
  685. BEGIN_LP_RING(2);
  686. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  687. OUT_RING(0);
  688. ADVANCE_LP_RING();
  689. /* Increment the frame counter. The client-side 3D driver must
  690. * throttle the framerate by waiting for this value before
  691. * performing the swapbuffer ioctl.
  692. */
  693. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  694. }
  695. static void i810_dma_quiescent(struct drm_device *dev)
  696. {
  697. drm_i810_private_t *dev_priv = dev->dev_private;
  698. RING_LOCALS;
  699. i810_kernel_lost_context(dev);
  700. BEGIN_LP_RING(4);
  701. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  702. OUT_RING(CMD_REPORT_HEAD);
  703. OUT_RING(0);
  704. OUT_RING(0);
  705. ADVANCE_LP_RING();
  706. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  707. }
  708. static int i810_flush_queue(struct drm_device *dev)
  709. {
  710. drm_i810_private_t *dev_priv = dev->dev_private;
  711. struct drm_device_dma *dma = dev->dma;
  712. int i, ret = 0;
  713. RING_LOCALS;
  714. i810_kernel_lost_context(dev);
  715. BEGIN_LP_RING(2);
  716. OUT_RING(CMD_REPORT_HEAD);
  717. OUT_RING(0);
  718. ADVANCE_LP_RING();
  719. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  720. for (i = 0; i < dma->buf_count; i++) {
  721. struct drm_buf *buf = dma->buflist[i];
  722. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  723. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  724. I810_BUF_FREE);
  725. if (used == I810_BUF_HARDWARE)
  726. DRM_DEBUG("reclaimed from HARDWARE\n");
  727. if (used == I810_BUF_CLIENT)
  728. DRM_DEBUG("still on client\n");
  729. }
  730. return ret;
  731. }
  732. /* Must be called with the lock held */
  733. static void i810_reclaim_buffers(struct drm_device *dev,
  734. struct drm_file *file_priv)
  735. {
  736. struct drm_device_dma *dma = dev->dma;
  737. int i;
  738. if (!dma)
  739. return;
  740. if (!dev->dev_private)
  741. return;
  742. if (!dma->buflist)
  743. return;
  744. i810_flush_queue(dev);
  745. for (i = 0; i < dma->buf_count; i++) {
  746. struct drm_buf *buf = dma->buflist[i];
  747. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  748. if (buf->file_priv == file_priv && buf_priv) {
  749. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  750. I810_BUF_FREE);
  751. if (used == I810_BUF_CLIENT)
  752. DRM_DEBUG("reclaimed from client\n");
  753. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  754. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  755. }
  756. }
  757. }
  758. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  759. struct drm_file *file_priv)
  760. {
  761. LOCK_TEST_WITH_RETURN(dev, file_priv);
  762. i810_flush_queue(dev);
  763. return 0;
  764. }
  765. static int i810_dma_vertex(struct drm_device *dev, void *data,
  766. struct drm_file *file_priv)
  767. {
  768. struct drm_device_dma *dma = dev->dma;
  769. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  770. u32 *hw_status = dev_priv->hw_status_page;
  771. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  772. dev_priv->sarea_priv;
  773. drm_i810_vertex_t *vertex = data;
  774. LOCK_TEST_WITH_RETURN(dev, file_priv);
  775. DRM_DEBUG("idx %d used %d discard %d\n",
  776. vertex->idx, vertex->used, vertex->discard);
  777. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  778. return -EINVAL;
  779. i810_dma_dispatch_vertex(dev,
  780. dma->buflist[vertex->idx],
  781. vertex->discard, vertex->used);
  782. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  783. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  784. sarea_priv->last_enqueue = dev_priv->counter - 1;
  785. sarea_priv->last_dispatch = (int)hw_status[5];
  786. return 0;
  787. }
  788. static int i810_clear_bufs(struct drm_device *dev, void *data,
  789. struct drm_file *file_priv)
  790. {
  791. drm_i810_clear_t *clear = data;
  792. LOCK_TEST_WITH_RETURN(dev, file_priv);
  793. /* GH: Someone's doing nasty things... */
  794. if (!dev->dev_private)
  795. return -EINVAL;
  796. i810_dma_dispatch_clear(dev, clear->flags,
  797. clear->clear_color, clear->clear_depth);
  798. return 0;
  799. }
  800. static int i810_swap_bufs(struct drm_device *dev, void *data,
  801. struct drm_file *file_priv)
  802. {
  803. DRM_DEBUG("\n");
  804. LOCK_TEST_WITH_RETURN(dev, file_priv);
  805. i810_dma_dispatch_swap(dev);
  806. return 0;
  807. }
  808. static int i810_getage(struct drm_device *dev, void *data,
  809. struct drm_file *file_priv)
  810. {
  811. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  812. u32 *hw_status = dev_priv->hw_status_page;
  813. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  814. dev_priv->sarea_priv;
  815. sarea_priv->last_dispatch = (int)hw_status[5];
  816. return 0;
  817. }
  818. static int i810_getbuf(struct drm_device *dev, void *data,
  819. struct drm_file *file_priv)
  820. {
  821. int retcode = 0;
  822. drm_i810_dma_t *d = data;
  823. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  824. u32 *hw_status = dev_priv->hw_status_page;
  825. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  826. dev_priv->sarea_priv;
  827. LOCK_TEST_WITH_RETURN(dev, file_priv);
  828. d->granted = 0;
  829. retcode = i810_dma_get_buffer(dev, d, file_priv);
  830. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  831. task_pid_nr(current), retcode, d->granted);
  832. sarea_priv->last_dispatch = (int)hw_status[5];
  833. return retcode;
  834. }
  835. static int i810_copybuf(struct drm_device *dev, void *data,
  836. struct drm_file *file_priv)
  837. {
  838. /* Never copy - 2.4.x doesn't need it */
  839. return 0;
  840. }
  841. static int i810_docopy(struct drm_device *dev, void *data,
  842. struct drm_file *file_priv)
  843. {
  844. /* Never copy - 2.4.x doesn't need it */
  845. return 0;
  846. }
  847. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  848. unsigned int last_render)
  849. {
  850. drm_i810_private_t *dev_priv = dev->dev_private;
  851. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  852. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  853. unsigned long address = (unsigned long)buf->bus_address;
  854. unsigned long start = address - dev->agp->base;
  855. int u;
  856. RING_LOCALS;
  857. i810_kernel_lost_context(dev);
  858. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  859. if (u != I810_BUF_CLIENT)
  860. DRM_DEBUG("MC found buffer that isn't mine!\n");
  861. if (used > 4 * 1024)
  862. used = 0;
  863. sarea_priv->dirty = 0x7f;
  864. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  865. dev_priv->counter++;
  866. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  867. DRM_DEBUG("start : %lx\n", start);
  868. DRM_DEBUG("used : %d\n", used);
  869. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  870. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  871. if (used & 4) {
  872. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  873. used += 4;
  874. }
  875. i810_unmap_buffer(buf);
  876. }
  877. BEGIN_LP_RING(4);
  878. OUT_RING(CMD_OP_BATCH_BUFFER);
  879. OUT_RING(start | BB1_PROTECTED);
  880. OUT_RING(start + used - 4);
  881. OUT_RING(0);
  882. ADVANCE_LP_RING();
  883. BEGIN_LP_RING(8);
  884. OUT_RING(CMD_STORE_DWORD_IDX);
  885. OUT_RING(buf_priv->my_use_idx);
  886. OUT_RING(I810_BUF_FREE);
  887. OUT_RING(0);
  888. OUT_RING(CMD_STORE_DWORD_IDX);
  889. OUT_RING(16);
  890. OUT_RING(last_render);
  891. OUT_RING(0);
  892. ADVANCE_LP_RING();
  893. }
  894. static int i810_dma_mc(struct drm_device *dev, void *data,
  895. struct drm_file *file_priv)
  896. {
  897. struct drm_device_dma *dma = dev->dma;
  898. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  899. u32 *hw_status = dev_priv->hw_status_page;
  900. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  901. dev_priv->sarea_priv;
  902. drm_i810_mc_t *mc = data;
  903. LOCK_TEST_WITH_RETURN(dev, file_priv);
  904. if (mc->idx >= dma->buf_count || mc->idx < 0)
  905. return -EINVAL;
  906. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  907. mc->last_render);
  908. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  909. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  910. sarea_priv->last_enqueue = dev_priv->counter - 1;
  911. sarea_priv->last_dispatch = (int)hw_status[5];
  912. return 0;
  913. }
  914. static int i810_rstatus(struct drm_device *dev, void *data,
  915. struct drm_file *file_priv)
  916. {
  917. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  918. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  919. }
  920. static int i810_ov0_info(struct drm_device *dev, void *data,
  921. struct drm_file *file_priv)
  922. {
  923. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  924. drm_i810_overlay_t *ov = data;
  925. ov->offset = dev_priv->overlay_offset;
  926. ov->physical = dev_priv->overlay_physical;
  927. return 0;
  928. }
  929. static int i810_fstatus(struct drm_device *dev, void *data,
  930. struct drm_file *file_priv)
  931. {
  932. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  933. LOCK_TEST_WITH_RETURN(dev, file_priv);
  934. return I810_READ(0x30008);
  935. }
  936. static int i810_ov0_flip(struct drm_device *dev, void *data,
  937. struct drm_file *file_priv)
  938. {
  939. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  940. LOCK_TEST_WITH_RETURN(dev, file_priv);
  941. /* Tell the overlay to update */
  942. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  943. return 0;
  944. }
  945. /* Not sure why this isn't set all the time:
  946. */
  947. static void i810_do_init_pageflip(struct drm_device *dev)
  948. {
  949. drm_i810_private_t *dev_priv = dev->dev_private;
  950. DRM_DEBUG("\n");
  951. dev_priv->page_flipping = 1;
  952. dev_priv->current_page = 0;
  953. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  954. }
  955. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  956. {
  957. drm_i810_private_t *dev_priv = dev->dev_private;
  958. DRM_DEBUG("\n");
  959. if (dev_priv->current_page != 0)
  960. i810_dma_dispatch_flip(dev);
  961. dev_priv->page_flipping = 0;
  962. return 0;
  963. }
  964. static int i810_flip_bufs(struct drm_device *dev, void *data,
  965. struct drm_file *file_priv)
  966. {
  967. drm_i810_private_t *dev_priv = dev->dev_private;
  968. DRM_DEBUG("\n");
  969. LOCK_TEST_WITH_RETURN(dev, file_priv);
  970. if (!dev_priv->page_flipping)
  971. i810_do_init_pageflip(dev);
  972. i810_dma_dispatch_flip(dev);
  973. return 0;
  974. }
  975. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  976. {
  977. /* i810 has 4 more counters */
  978. dev->counters += 4;
  979. dev->types[6] = _DRM_STAT_IRQ;
  980. dev->types[7] = _DRM_STAT_PRIMARY;
  981. dev->types[8] = _DRM_STAT_SECONDARY;
  982. dev->types[9] = _DRM_STAT_DMA;
  983. pci_set_master(dev->pdev);
  984. return 0;
  985. }
  986. void i810_driver_lastclose(struct drm_device *dev)
  987. {
  988. i810_dma_cleanup(dev);
  989. }
  990. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  991. {
  992. if (dev->dev_private) {
  993. drm_i810_private_t *dev_priv = dev->dev_private;
  994. if (dev_priv->page_flipping)
  995. i810_do_cleanup_pageflip(dev);
  996. }
  997. }
  998. void i810_driver_reclaim_buffers_locked(struct drm_device *dev,
  999. struct drm_file *file_priv)
  1000. {
  1001. i810_reclaim_buffers(dev, file_priv);
  1002. }
  1003. int i810_driver_dma_quiescent(struct drm_device *dev)
  1004. {
  1005. i810_dma_quiescent(dev);
  1006. return 0;
  1007. }
  1008. struct drm_ioctl_desc i810_ioctls[] = {
  1009. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1010. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1011. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1012. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1013. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1014. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1015. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1016. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1024. };
  1025. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1026. /**
  1027. * Determine if the device really is AGP or not.
  1028. *
  1029. * All Intel graphics chipsets are treated as AGP, even if they are really
  1030. * PCI-e.
  1031. *
  1032. * \param dev The device to be tested.
  1033. *
  1034. * \returns
  1035. * A value of 1 is always retured to indictate every i810 is AGP.
  1036. */
  1037. int i810_driver_device_is_agp(struct drm_device *dev)
  1038. {
  1039. return 1;
  1040. }