psb_intel_sdvo.c 81 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/module.h>
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "drm_crtc.h"
  35. #include "drm_edid.h"
  36. #include "psb_intel_drv.h"
  37. #include "gma_drm.h"
  38. #include "psb_drv.h"
  39. #include "psb_intel_sdvo_regs.h"
  40. #include "psb_intel_reg.h"
  41. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  42. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  43. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  44. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  45. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  46. SDVO_TV_MASK)
  47. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  48. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  49. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  50. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  51. static const char *tv_format_names[] = {
  52. "NTSC_M" , "NTSC_J" , "NTSC_443",
  53. "PAL_B" , "PAL_D" , "PAL_G" ,
  54. "PAL_H" , "PAL_I" , "PAL_M" ,
  55. "PAL_N" , "PAL_NC" , "PAL_60" ,
  56. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  57. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  58. "SECAM_60"
  59. };
  60. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  61. struct psb_intel_sdvo {
  62. struct psb_intel_encoder base;
  63. struct i2c_adapter *i2c;
  64. u8 slave_addr;
  65. struct i2c_adapter ddc;
  66. /* Register for the SDVO device: SDVOB or SDVOC */
  67. int sdvo_reg;
  68. /* Active outputs controlled by this SDVO output */
  69. uint16_t controlled_output;
  70. /*
  71. * Capabilities of the SDVO device returned by
  72. * i830_sdvo_get_capabilities()
  73. */
  74. struct psb_intel_sdvo_caps caps;
  75. /* Pixel clock limitations reported by the SDVO device, in kHz */
  76. int pixel_clock_min, pixel_clock_max;
  77. /*
  78. * For multiple function SDVO device,
  79. * this is for current attached outputs.
  80. */
  81. uint16_t attached_output;
  82. /**
  83. * This is used to select the color range of RBG outputs in HDMI mode.
  84. * It is only valid when using TMDS encoding and 8 bit per color mode.
  85. */
  86. uint32_t color_range;
  87. /**
  88. * This is set if we're going to treat the device as TV-out.
  89. *
  90. * While we have these nice friendly flags for output types that ought
  91. * to decide this for us, the S-Video output on our HDMI+S-Video card
  92. * shows up as RGB1 (VGA).
  93. */
  94. bool is_tv;
  95. /* This is for current tv format name */
  96. int tv_format_index;
  97. /**
  98. * This is set if we treat the device as HDMI, instead of DVI.
  99. */
  100. bool is_hdmi;
  101. bool has_hdmi_monitor;
  102. bool has_hdmi_audio;
  103. /**
  104. * This is set if we detect output of sdvo device as LVDS and
  105. * have a valid fixed mode to use with the panel.
  106. */
  107. bool is_lvds;
  108. /**
  109. * This is sdvo fixed pannel mode pointer
  110. */
  111. struct drm_display_mode *sdvo_lvds_fixed_mode;
  112. /* DDC bus used by this SDVO encoder */
  113. uint8_t ddc_bus;
  114. /* Input timings for adjusted_mode */
  115. struct psb_intel_sdvo_dtd input_dtd;
  116. };
  117. struct psb_intel_sdvo_connector {
  118. struct psb_intel_connector base;
  119. /* Mark the type of connector */
  120. uint16_t output_flag;
  121. int force_audio;
  122. /* This contains all current supported TV format */
  123. u8 tv_format_supported[TV_FORMAT_NUM];
  124. int format_supported_num;
  125. struct drm_property *tv_format;
  126. /* add the property for the SDVO-TV */
  127. struct drm_property *left;
  128. struct drm_property *right;
  129. struct drm_property *top;
  130. struct drm_property *bottom;
  131. struct drm_property *hpos;
  132. struct drm_property *vpos;
  133. struct drm_property *contrast;
  134. struct drm_property *saturation;
  135. struct drm_property *hue;
  136. struct drm_property *sharpness;
  137. struct drm_property *flicker_filter;
  138. struct drm_property *flicker_filter_adaptive;
  139. struct drm_property *flicker_filter_2d;
  140. struct drm_property *tv_chroma_filter;
  141. struct drm_property *tv_luma_filter;
  142. struct drm_property *dot_crawl;
  143. /* add the property for the SDVO-TV/LVDS */
  144. struct drm_property *brightness;
  145. /* Add variable to record current setting for the above property */
  146. u32 left_margin, right_margin, top_margin, bottom_margin;
  147. /* this is to get the range of margin.*/
  148. u32 max_hscan, max_vscan;
  149. u32 max_hpos, cur_hpos;
  150. u32 max_vpos, cur_vpos;
  151. u32 cur_brightness, max_brightness;
  152. u32 cur_contrast, max_contrast;
  153. u32 cur_saturation, max_saturation;
  154. u32 cur_hue, max_hue;
  155. u32 cur_sharpness, max_sharpness;
  156. u32 cur_flicker_filter, max_flicker_filter;
  157. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  158. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  159. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  160. u32 cur_tv_luma_filter, max_tv_luma_filter;
  161. u32 cur_dot_crawl, max_dot_crawl;
  162. };
  163. static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder)
  164. {
  165. return container_of(encoder, struct psb_intel_sdvo, base.base);
  166. }
  167. static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  168. {
  169. return container_of(psb_intel_attached_encoder(connector),
  170. struct psb_intel_sdvo, base);
  171. }
  172. static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
  173. {
  174. return container_of(to_psb_intel_connector(connector), struct psb_intel_sdvo_connector, base);
  175. }
  176. static bool
  177. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags);
  178. static bool
  179. psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  180. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  181. int type);
  182. static bool
  183. psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  184. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
  185. /**
  186. * Writes the SDVOB or SDVOC with the given value, but always writes both
  187. * SDVOB and SDVOC to work around apparent hardware issues (according to
  188. * comments in the BIOS).
  189. */
  190. static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
  191. {
  192. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  193. u32 bval = val, cval = val;
  194. int i;
  195. if (psb_intel_sdvo->sdvo_reg == SDVOB) {
  196. cval = REG_READ(SDVOC);
  197. } else {
  198. bval = REG_READ(SDVOB);
  199. }
  200. /*
  201. * Write the registers twice for luck. Sometimes,
  202. * writing them only once doesn't appear to 'stick'.
  203. * The BIOS does this too. Yay, magic
  204. */
  205. for (i = 0; i < 2; i++)
  206. {
  207. REG_WRITE(SDVOB, bval);
  208. REG_READ(SDVOB);
  209. REG_WRITE(SDVOC, cval);
  210. REG_READ(SDVOC);
  211. }
  212. }
  213. static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch)
  214. {
  215. struct i2c_msg msgs[] = {
  216. {
  217. .addr = psb_intel_sdvo->slave_addr,
  218. .flags = 0,
  219. .len = 1,
  220. .buf = &addr,
  221. },
  222. {
  223. .addr = psb_intel_sdvo->slave_addr,
  224. .flags = I2C_M_RD,
  225. .len = 1,
  226. .buf = ch,
  227. }
  228. };
  229. int ret;
  230. if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2)
  231. return true;
  232. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  233. return false;
  234. }
  235. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  236. /** Mapping of command numbers to names, for debug output */
  237. static const struct _sdvo_cmd_name {
  238. u8 cmd;
  239. const char *name;
  240. } sdvo_cmd_names[] = {
  241. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  242. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  243. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  244. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  245. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  246. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  284. /* Add the op code for SDVO enhancements */
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  329. /* HDMI op code */
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  350. };
  351. #define IS_SDVOB(reg) (reg == SDVOB)
  352. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  353. static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  354. const void *args, int args_len)
  355. {
  356. int i;
  357. DRM_DEBUG_KMS("%s: W: %02X ",
  358. SDVO_NAME(psb_intel_sdvo), cmd);
  359. for (i = 0; i < args_len; i++)
  360. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  361. for (; i < 8; i++)
  362. DRM_LOG_KMS(" ");
  363. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  364. if (cmd == sdvo_cmd_names[i].cmd) {
  365. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  366. break;
  367. }
  368. }
  369. if (i == ARRAY_SIZE(sdvo_cmd_names))
  370. DRM_LOG_KMS("(%02X)", cmd);
  371. DRM_LOG_KMS("\n");
  372. }
  373. static const char *cmd_status_names[] = {
  374. "Power on",
  375. "Success",
  376. "Not supported",
  377. "Invalid arg",
  378. "Pending",
  379. "Target not specified",
  380. "Scaling not supported"
  381. };
  382. static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  383. const void *args, int args_len)
  384. {
  385. u8 buf[args_len*2 + 2], status;
  386. struct i2c_msg msgs[args_len + 3];
  387. int i, ret;
  388. psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len);
  389. for (i = 0; i < args_len; i++) {
  390. msgs[i].addr = psb_intel_sdvo->slave_addr;
  391. msgs[i].flags = 0;
  392. msgs[i].len = 2;
  393. msgs[i].buf = buf + 2 *i;
  394. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  395. buf[2*i + 1] = ((u8*)args)[i];
  396. }
  397. msgs[i].addr = psb_intel_sdvo->slave_addr;
  398. msgs[i].flags = 0;
  399. msgs[i].len = 2;
  400. msgs[i].buf = buf + 2*i;
  401. buf[2*i + 0] = SDVO_I2C_OPCODE;
  402. buf[2*i + 1] = cmd;
  403. /* the following two are to read the response */
  404. status = SDVO_I2C_CMD_STATUS;
  405. msgs[i+1].addr = psb_intel_sdvo->slave_addr;
  406. msgs[i+1].flags = 0;
  407. msgs[i+1].len = 1;
  408. msgs[i+1].buf = &status;
  409. msgs[i+2].addr = psb_intel_sdvo->slave_addr;
  410. msgs[i+2].flags = I2C_M_RD;
  411. msgs[i+2].len = 1;
  412. msgs[i+2].buf = &status;
  413. ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3);
  414. if (ret < 0) {
  415. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  416. return false;
  417. }
  418. if (ret != i+3) {
  419. /* failure in I2C transfer */
  420. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  421. return false;
  422. }
  423. return true;
  424. }
  425. static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
  426. void *response, int response_len)
  427. {
  428. u8 retry = 5;
  429. u8 status;
  430. int i;
  431. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo));
  432. /*
  433. * The documentation states that all commands will be
  434. * processed within 15µs, and that we need only poll
  435. * the status byte a maximum of 3 times in order for the
  436. * command to be complete.
  437. *
  438. * Check 5 times in case the hardware failed to read the docs.
  439. */
  440. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  441. SDVO_I2C_CMD_STATUS,
  442. &status))
  443. goto log_fail;
  444. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  445. udelay(15);
  446. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  447. SDVO_I2C_CMD_STATUS,
  448. &status))
  449. goto log_fail;
  450. }
  451. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  452. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  453. else
  454. DRM_LOG_KMS("(??? %d)", status);
  455. if (status != SDVO_CMD_STATUS_SUCCESS)
  456. goto log_fail;
  457. /* Read the command response */
  458. for (i = 0; i < response_len; i++) {
  459. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  460. SDVO_I2C_RETURN_0 + i,
  461. &((u8 *)response)[i]))
  462. goto log_fail;
  463. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  464. }
  465. DRM_LOG_KMS("\n");
  466. return true;
  467. log_fail:
  468. DRM_LOG_KMS("... failed\n");
  469. return false;
  470. }
  471. static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  472. {
  473. if (mode->clock >= 100000)
  474. return 1;
  475. else if (mode->clock >= 50000)
  476. return 2;
  477. else
  478. return 4;
  479. }
  480. static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo,
  481. u8 ddc_bus)
  482. {
  483. /* This must be the immediately preceding write before the i2c xfer */
  484. return psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  485. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  486. &ddc_bus, 1);
  487. }
  488. static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len)
  489. {
  490. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len))
  491. return false;
  492. return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0);
  493. }
  494. static bool
  495. psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len)
  496. {
  497. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0))
  498. return false;
  499. return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len);
  500. }
  501. static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo)
  502. {
  503. struct psb_intel_sdvo_set_target_input_args targets = {0};
  504. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  505. SDVO_CMD_SET_TARGET_INPUT,
  506. &targets, sizeof(targets));
  507. }
  508. /**
  509. * Return whether each input is trained.
  510. *
  511. * This function is making an assumption about the layout of the response,
  512. * which should be checked against the docs.
  513. */
  514. static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2)
  515. {
  516. struct psb_intel_sdvo_get_trained_inputs_response response;
  517. BUILD_BUG_ON(sizeof(response) != 1);
  518. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  519. &response, sizeof(response)))
  520. return false;
  521. *input_1 = response.input0_trained;
  522. *input_2 = response.input1_trained;
  523. return true;
  524. }
  525. static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo,
  526. u16 outputs)
  527. {
  528. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  529. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  530. &outputs, sizeof(outputs));
  531. }
  532. static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo,
  533. int mode)
  534. {
  535. u8 state = SDVO_ENCODER_STATE_ON;
  536. switch (mode) {
  537. case DRM_MODE_DPMS_ON:
  538. state = SDVO_ENCODER_STATE_ON;
  539. break;
  540. case DRM_MODE_DPMS_STANDBY:
  541. state = SDVO_ENCODER_STATE_STANDBY;
  542. break;
  543. case DRM_MODE_DPMS_SUSPEND:
  544. state = SDVO_ENCODER_STATE_SUSPEND;
  545. break;
  546. case DRM_MODE_DPMS_OFF:
  547. state = SDVO_ENCODER_STATE_OFF;
  548. break;
  549. }
  550. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  551. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  552. }
  553. static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo,
  554. int *clock_min,
  555. int *clock_max)
  556. {
  557. struct psb_intel_sdvo_pixel_clock_range clocks;
  558. BUILD_BUG_ON(sizeof(clocks) != 4);
  559. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  560. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  561. &clocks, sizeof(clocks)))
  562. return false;
  563. /* Convert the values from units of 10 kHz to kHz. */
  564. *clock_min = clocks.min * 10;
  565. *clock_max = clocks.max * 10;
  566. return true;
  567. }
  568. static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo,
  569. u16 outputs)
  570. {
  571. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  572. SDVO_CMD_SET_TARGET_OUTPUT,
  573. &outputs, sizeof(outputs));
  574. }
  575. static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  576. struct psb_intel_sdvo_dtd *dtd)
  577. {
  578. return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  579. psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  580. }
  581. static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  582. struct psb_intel_sdvo_dtd *dtd)
  583. {
  584. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  585. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  586. }
  587. static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  588. struct psb_intel_sdvo_dtd *dtd)
  589. {
  590. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  591. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  592. }
  593. static bool
  594. psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  595. uint16_t clock,
  596. uint16_t width,
  597. uint16_t height)
  598. {
  599. struct psb_intel_sdvo_preferred_input_timing_args args;
  600. memset(&args, 0, sizeof(args));
  601. args.clock = clock;
  602. args.width = width;
  603. args.height = height;
  604. args.interlace = 0;
  605. if (psb_intel_sdvo->is_lvds &&
  606. (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  607. psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  608. args.scaled = 1;
  609. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  610. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  611. &args, sizeof(args));
  612. }
  613. static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  614. struct psb_intel_sdvo_dtd *dtd)
  615. {
  616. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  617. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  618. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  619. &dtd->part1, sizeof(dtd->part1)) &&
  620. psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  621. &dtd->part2, sizeof(dtd->part2));
  622. }
  623. static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
  624. {
  625. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  626. }
  627. static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd,
  628. const struct drm_display_mode *mode)
  629. {
  630. uint16_t width, height;
  631. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  632. uint16_t h_sync_offset, v_sync_offset;
  633. width = mode->crtc_hdisplay;
  634. height = mode->crtc_vdisplay;
  635. /* do some mode translations */
  636. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  637. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  638. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  639. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  640. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  641. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  642. dtd->part1.clock = mode->clock / 10;
  643. dtd->part1.h_active = width & 0xff;
  644. dtd->part1.h_blank = h_blank_len & 0xff;
  645. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  646. ((h_blank_len >> 8) & 0xf);
  647. dtd->part1.v_active = height & 0xff;
  648. dtd->part1.v_blank = v_blank_len & 0xff;
  649. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  650. ((v_blank_len >> 8) & 0xf);
  651. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  652. dtd->part2.h_sync_width = h_sync_len & 0xff;
  653. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  654. (v_sync_len & 0xf);
  655. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  656. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  657. ((v_sync_len & 0x30) >> 4);
  658. dtd->part2.dtd_flags = 0x18;
  659. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  660. dtd->part2.dtd_flags |= 0x2;
  661. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  662. dtd->part2.dtd_flags |= 0x4;
  663. dtd->part2.sdvo_flags = 0;
  664. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  665. dtd->part2.reserved = 0;
  666. }
  667. static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  668. const struct psb_intel_sdvo_dtd *dtd)
  669. {
  670. mode->hdisplay = dtd->part1.h_active;
  671. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  672. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  673. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  674. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  675. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  676. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  677. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  678. mode->vdisplay = dtd->part1.v_active;
  679. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  680. mode->vsync_start = mode->vdisplay;
  681. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  682. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  683. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  684. mode->vsync_end = mode->vsync_start +
  685. (dtd->part2.v_sync_off_width & 0xf);
  686. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  687. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  688. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  689. mode->clock = dtd->part1.clock * 10;
  690. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  691. if (dtd->part2.dtd_flags & 0x2)
  692. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  693. if (dtd->part2.dtd_flags & 0x4)
  694. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  695. }
  696. static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo)
  697. {
  698. struct psb_intel_sdvo_encode encode;
  699. BUILD_BUG_ON(sizeof(encode) != 2);
  700. return psb_intel_sdvo_get_value(psb_intel_sdvo,
  701. SDVO_CMD_GET_SUPP_ENCODE,
  702. &encode, sizeof(encode));
  703. }
  704. static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo,
  705. uint8_t mode)
  706. {
  707. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  708. }
  709. static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo,
  710. uint8_t mode)
  711. {
  712. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  713. }
  714. #if 0
  715. static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo)
  716. {
  717. int i, j;
  718. uint8_t set_buf_index[2];
  719. uint8_t av_split;
  720. uint8_t buf_size;
  721. uint8_t buf[48];
  722. uint8_t *pos;
  723. psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  724. for (i = 0; i <= av_split; i++) {
  725. set_buf_index[0] = i; set_buf_index[1] = 0;
  726. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  727. set_buf_index, 2);
  728. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  729. psb_intel_sdvo_read_response(encoder, &buf_size, 1);
  730. pos = buf;
  731. for (j = 0; j <= buf_size; j += 8) {
  732. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  733. NULL, 0);
  734. psb_intel_sdvo_read_response(encoder, pos, 8);
  735. pos += 8;
  736. }
  737. }
  738. }
  739. #endif
  740. static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo)
  741. {
  742. DRM_INFO("HDMI is not supported yet");
  743. return false;
  744. #if 0
  745. struct dip_infoframe avi_if = {
  746. .type = DIP_TYPE_AVI,
  747. .ver = DIP_VERSION_AVI,
  748. .len = DIP_LEN_AVI,
  749. };
  750. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  751. uint8_t set_buf_index[2] = { 1, 0 };
  752. uint64_t *data = (uint64_t *)&avi_if;
  753. unsigned i;
  754. intel_dip_infoframe_csum(&avi_if);
  755. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  756. SDVO_CMD_SET_HBUF_INDEX,
  757. set_buf_index, 2))
  758. return false;
  759. for (i = 0; i < sizeof(avi_if); i += 8) {
  760. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  761. SDVO_CMD_SET_HBUF_DATA,
  762. data, 8))
  763. return false;
  764. data++;
  765. }
  766. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  767. SDVO_CMD_SET_HBUF_TXRATE,
  768. &tx_rate, 1);
  769. #endif
  770. }
  771. static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo)
  772. {
  773. struct psb_intel_sdvo_tv_format format;
  774. uint32_t format_map;
  775. format_map = 1 << psb_intel_sdvo->tv_format_index;
  776. memset(&format, 0, sizeof(format));
  777. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  778. BUILD_BUG_ON(sizeof(format) != 6);
  779. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  780. SDVO_CMD_SET_TV_FORMAT,
  781. &format, sizeof(format));
  782. }
  783. static bool
  784. psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  785. struct drm_display_mode *mode)
  786. {
  787. struct psb_intel_sdvo_dtd output_dtd;
  788. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  789. psb_intel_sdvo->attached_output))
  790. return false;
  791. psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  792. if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd))
  793. return false;
  794. return true;
  795. }
  796. static bool
  797. psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  798. struct drm_display_mode *mode,
  799. struct drm_display_mode *adjusted_mode)
  800. {
  801. /* Reset the input timing to the screen. Assume always input 0. */
  802. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  803. return false;
  804. if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo,
  805. mode->clock / 10,
  806. mode->hdisplay,
  807. mode->vdisplay))
  808. return false;
  809. if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo,
  810. &psb_intel_sdvo->input_dtd))
  811. return false;
  812. psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd);
  813. drm_mode_set_crtcinfo(adjusted_mode, 0);
  814. return true;
  815. }
  816. static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  817. struct drm_display_mode *mode,
  818. struct drm_display_mode *adjusted_mode)
  819. {
  820. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  821. int multiplier;
  822. /* We need to construct preferred input timings based on our
  823. * output timings. To do that, we have to set the output
  824. * timings, even though this isn't really the right place in
  825. * the sequence to do it. Oh well.
  826. */
  827. if (psb_intel_sdvo->is_tv) {
  828. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
  829. return false;
  830. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  831. mode,
  832. adjusted_mode);
  833. } else if (psb_intel_sdvo->is_lvds) {
  834. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo,
  835. psb_intel_sdvo->sdvo_lvds_fixed_mode))
  836. return false;
  837. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  838. mode,
  839. adjusted_mode);
  840. }
  841. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  842. * SDVO device will factor out the multiplier during mode_set.
  843. */
  844. multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode);
  845. psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  846. return true;
  847. }
  848. static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
  849. struct drm_display_mode *mode,
  850. struct drm_display_mode *adjusted_mode)
  851. {
  852. struct drm_device *dev = encoder->dev;
  853. struct drm_crtc *crtc = encoder->crtc;
  854. struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
  855. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  856. u32 sdvox;
  857. struct psb_intel_sdvo_in_out_map in_out;
  858. struct psb_intel_sdvo_dtd input_dtd;
  859. int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
  860. int rate;
  861. if (!mode)
  862. return;
  863. /* First, set the input mapping for the first input to our controlled
  864. * output. This is only correct if we're a single-input device, in
  865. * which case the first input is the output from the appropriate SDVO
  866. * channel on the motherboard. In a two-input device, the first input
  867. * will be SDVOB and the second SDVOC.
  868. */
  869. in_out.in0 = psb_intel_sdvo->attached_output;
  870. in_out.in1 = 0;
  871. psb_intel_sdvo_set_value(psb_intel_sdvo,
  872. SDVO_CMD_SET_IN_OUT_MAP,
  873. &in_out, sizeof(in_out));
  874. /* Set the output timings to the screen */
  875. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  876. psb_intel_sdvo->attached_output))
  877. return;
  878. /* We have tried to get input timing in mode_fixup, and filled into
  879. * adjusted_mode.
  880. */
  881. if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) {
  882. input_dtd = psb_intel_sdvo->input_dtd;
  883. } else {
  884. /* Set the output timing to the screen */
  885. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  886. psb_intel_sdvo->attached_output))
  887. return;
  888. psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  889. (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd);
  890. }
  891. /* Set the input timing to the screen. Assume always input 0. */
  892. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  893. return;
  894. if (psb_intel_sdvo->has_hdmi_monitor) {
  895. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI);
  896. psb_intel_sdvo_set_colorimetry(psb_intel_sdvo,
  897. SDVO_COLORIMETRY_RGB256);
  898. psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo);
  899. } else
  900. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI);
  901. if (psb_intel_sdvo->is_tv &&
  902. !psb_intel_sdvo_set_tv_format(psb_intel_sdvo))
  903. return;
  904. (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd);
  905. switch (pixel_multiplier) {
  906. default:
  907. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  908. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  909. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  910. }
  911. if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate))
  912. return;
  913. /* Set the SDVO control regs. */
  914. sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
  915. switch (psb_intel_sdvo->sdvo_reg) {
  916. case SDVOB:
  917. sdvox &= SDVOB_PRESERVE_MASK;
  918. break;
  919. case SDVOC:
  920. sdvox &= SDVOC_PRESERVE_MASK;
  921. break;
  922. }
  923. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  924. if (psb_intel_crtc->pipe == 1)
  925. sdvox |= SDVO_PIPE_B_SELECT;
  926. if (psb_intel_sdvo->has_hdmi_audio)
  927. sdvox |= SDVO_AUDIO_ENABLE;
  928. /* FIXME: Check if this is needed for PSB
  929. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  930. */
  931. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
  932. sdvox |= SDVO_STALL_SELECT;
  933. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox);
  934. }
  935. static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  936. {
  937. struct drm_device *dev = encoder->dev;
  938. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  939. u32 temp;
  940. switch (mode) {
  941. case DRM_MODE_DPMS_ON:
  942. DRM_DEBUG("DPMS_ON");
  943. break;
  944. case DRM_MODE_DPMS_OFF:
  945. DRM_DEBUG("DPMS_OFF");
  946. break;
  947. default:
  948. DRM_DEBUG("DPMS: %d", mode);
  949. }
  950. if (mode != DRM_MODE_DPMS_ON) {
  951. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0);
  952. if (0)
  953. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  954. if (mode == DRM_MODE_DPMS_OFF) {
  955. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  956. if ((temp & SDVO_ENABLE) != 0) {
  957. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
  958. }
  959. }
  960. } else {
  961. bool input1, input2;
  962. int i;
  963. u8 status;
  964. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  965. if ((temp & SDVO_ENABLE) == 0)
  966. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
  967. for (i = 0; i < 2; i++)
  968. psb_intel_wait_for_vblank(dev);
  969. status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
  970. /* Warn if the device reported failure to sync.
  971. * A lot of SDVO devices fail to notify of sync, but it's
  972. * a given it the status is a success, we succeeded.
  973. */
  974. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  975. DRM_DEBUG_KMS("First %s output reported failure to "
  976. "sync\n", SDVO_NAME(psb_intel_sdvo));
  977. }
  978. if (0)
  979. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  980. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output);
  981. }
  982. return;
  983. }
  984. static int psb_intel_sdvo_mode_valid(struct drm_connector *connector,
  985. struct drm_display_mode *mode)
  986. {
  987. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  988. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  989. return MODE_NO_DBLESCAN;
  990. if (psb_intel_sdvo->pixel_clock_min > mode->clock)
  991. return MODE_CLOCK_LOW;
  992. if (psb_intel_sdvo->pixel_clock_max < mode->clock)
  993. return MODE_CLOCK_HIGH;
  994. if (psb_intel_sdvo->is_lvds) {
  995. if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  996. return MODE_PANEL;
  997. if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  998. return MODE_PANEL;
  999. }
  1000. return MODE_OK;
  1001. }
  1002. static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps)
  1003. {
  1004. BUILD_BUG_ON(sizeof(*caps) != 8);
  1005. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1006. SDVO_CMD_GET_DEVICE_CAPS,
  1007. caps, sizeof(*caps)))
  1008. return false;
  1009. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1010. " vendor_id: %d\n"
  1011. " device_id: %d\n"
  1012. " device_rev_id: %d\n"
  1013. " sdvo_version_major: %d\n"
  1014. " sdvo_version_minor: %d\n"
  1015. " sdvo_inputs_mask: %d\n"
  1016. " smooth_scaling: %d\n"
  1017. " sharp_scaling: %d\n"
  1018. " up_scaling: %d\n"
  1019. " down_scaling: %d\n"
  1020. " stall_support: %d\n"
  1021. " output_flags: %d\n",
  1022. caps->vendor_id,
  1023. caps->device_id,
  1024. caps->device_rev_id,
  1025. caps->sdvo_version_major,
  1026. caps->sdvo_version_minor,
  1027. caps->sdvo_inputs_mask,
  1028. caps->smooth_scaling,
  1029. caps->sharp_scaling,
  1030. caps->up_scaling,
  1031. caps->down_scaling,
  1032. caps->stall_support,
  1033. caps->output_flags);
  1034. return true;
  1035. }
  1036. /* No use! */
  1037. #if 0
  1038. struct drm_connector* psb_intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1039. {
  1040. struct drm_connector *connector = NULL;
  1041. struct psb_intel_sdvo *iout = NULL;
  1042. struct psb_intel_sdvo *sdvo;
  1043. /* find the sdvo connector */
  1044. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1045. iout = to_psb_intel_sdvo(connector);
  1046. if (iout->type != INTEL_OUTPUT_SDVO)
  1047. continue;
  1048. sdvo = iout->dev_priv;
  1049. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1050. return connector;
  1051. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1052. return connector;
  1053. }
  1054. return NULL;
  1055. }
  1056. int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1057. {
  1058. u8 response[2];
  1059. u8 status;
  1060. struct psb_intel_sdvo *psb_intel_sdvo;
  1061. DRM_DEBUG_KMS("\n");
  1062. if (!connector)
  1063. return 0;
  1064. psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1065. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1066. &response, 2) && response[0];
  1067. }
  1068. void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1069. {
  1070. u8 response[2];
  1071. u8 status;
  1072. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1073. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1074. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1075. if (on) {
  1076. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1077. status = psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1078. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1079. } else {
  1080. response[0] = 0;
  1081. response[1] = 0;
  1082. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1083. }
  1084. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1085. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1086. }
  1087. #endif
  1088. static bool
  1089. psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo)
  1090. {
  1091. /* Is there more than one type of output? */
  1092. int caps = psb_intel_sdvo->caps.output_flags & 0xf;
  1093. return caps & -caps;
  1094. }
  1095. static struct edid *
  1096. psb_intel_sdvo_get_edid(struct drm_connector *connector)
  1097. {
  1098. struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1099. return drm_get_edid(connector, &sdvo->ddc);
  1100. }
  1101. /* Mac mini hack -- use the same DDC as the analog connector */
  1102. static struct edid *
  1103. psb_intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1104. {
  1105. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1106. return drm_get_edid(connector,
  1107. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1108. return NULL;
  1109. }
  1110. static enum drm_connector_status
  1111. psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1112. {
  1113. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1114. enum drm_connector_status status;
  1115. struct edid *edid;
  1116. edid = psb_intel_sdvo_get_edid(connector);
  1117. if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) {
  1118. u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;
  1119. /*
  1120. * Don't use the 1 as the argument of DDC bus switch to get
  1121. * the EDID. It is used for SDVO SPD ROM.
  1122. */
  1123. for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1124. psb_intel_sdvo->ddc_bus = ddc;
  1125. edid = psb_intel_sdvo_get_edid(connector);
  1126. if (edid)
  1127. break;
  1128. }
  1129. /*
  1130. * If we found the EDID on the other bus,
  1131. * assume that is the correct DDC bus.
  1132. */
  1133. if (edid == NULL)
  1134. psb_intel_sdvo->ddc_bus = saved_ddc;
  1135. }
  1136. /*
  1137. * When there is no edid and no monitor is connected with VGA
  1138. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1139. */
  1140. if (edid == NULL)
  1141. edid = psb_intel_sdvo_get_analog_edid(connector);
  1142. status = connector_status_unknown;
  1143. if (edid != NULL) {
  1144. /* DDC bus is shared, match EDID to connector type */
  1145. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1146. status = connector_status_connected;
  1147. if (psb_intel_sdvo->is_hdmi) {
  1148. psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1149. psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1150. }
  1151. } else
  1152. status = connector_status_disconnected;
  1153. connector->display_info.raw_edid = NULL;
  1154. kfree(edid);
  1155. }
  1156. if (status == connector_status_connected) {
  1157. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1158. if (psb_intel_sdvo_connector->force_audio)
  1159. psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0;
  1160. }
  1161. return status;
  1162. }
  1163. static enum drm_connector_status
  1164. psb_intel_sdvo_detect(struct drm_connector *connector, bool force)
  1165. {
  1166. uint16_t response;
  1167. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1168. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1169. enum drm_connector_status ret;
  1170. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1171. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1172. return connector_status_unknown;
  1173. /* add 30ms delay when the output type might be TV */
  1174. if (psb_intel_sdvo->caps.output_flags &
  1175. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1176. mdelay(30);
  1177. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2))
  1178. return connector_status_unknown;
  1179. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1180. response & 0xff, response >> 8,
  1181. psb_intel_sdvo_connector->output_flag);
  1182. if (response == 0)
  1183. return connector_status_disconnected;
  1184. psb_intel_sdvo->attached_output = response;
  1185. psb_intel_sdvo->has_hdmi_monitor = false;
  1186. psb_intel_sdvo->has_hdmi_audio = false;
  1187. if ((psb_intel_sdvo_connector->output_flag & response) == 0)
  1188. ret = connector_status_disconnected;
  1189. else if (IS_TMDS(psb_intel_sdvo_connector))
  1190. ret = psb_intel_sdvo_hdmi_sink_detect(connector);
  1191. else {
  1192. struct edid *edid;
  1193. /* if we have an edid check it matches the connection */
  1194. edid = psb_intel_sdvo_get_edid(connector);
  1195. if (edid == NULL)
  1196. edid = psb_intel_sdvo_get_analog_edid(connector);
  1197. if (edid != NULL) {
  1198. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1199. ret = connector_status_disconnected;
  1200. else
  1201. ret = connector_status_connected;
  1202. connector->display_info.raw_edid = NULL;
  1203. kfree(edid);
  1204. } else
  1205. ret = connector_status_connected;
  1206. }
  1207. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1208. if (ret == connector_status_connected) {
  1209. psb_intel_sdvo->is_tv = false;
  1210. psb_intel_sdvo->is_lvds = false;
  1211. psb_intel_sdvo->base.needs_tv_clock = false;
  1212. if (response & SDVO_TV_MASK) {
  1213. psb_intel_sdvo->is_tv = true;
  1214. psb_intel_sdvo->base.needs_tv_clock = true;
  1215. }
  1216. if (response & SDVO_LVDS_MASK)
  1217. psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1218. }
  1219. return ret;
  1220. }
  1221. static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1222. {
  1223. struct edid *edid;
  1224. /* set the bus switch and get the modes */
  1225. edid = psb_intel_sdvo_get_edid(connector);
  1226. /*
  1227. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1228. * link between analog and digital outputs. So, if the regular SDVO
  1229. * DDC fails, check to see if the analog output is disconnected, in
  1230. * which case we'll look there for the digital DDC data.
  1231. */
  1232. if (edid == NULL)
  1233. edid = psb_intel_sdvo_get_analog_edid(connector);
  1234. if (edid != NULL) {
  1235. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1236. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1237. bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector);
  1238. if (connector_is_digital == monitor_is_digital) {
  1239. drm_mode_connector_update_edid_property(connector, edid);
  1240. drm_add_edid_modes(connector, edid);
  1241. }
  1242. connector->display_info.raw_edid = NULL;
  1243. kfree(edid);
  1244. }
  1245. }
  1246. /*
  1247. * Set of SDVO TV modes.
  1248. * Note! This is in reply order (see loop in get_tv_modes).
  1249. * XXX: all 60Hz refresh?
  1250. */
  1251. static const struct drm_display_mode sdvo_tv_modes[] = {
  1252. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1253. 416, 0, 200, 201, 232, 233, 0,
  1254. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1255. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1256. 416, 0, 240, 241, 272, 273, 0,
  1257. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1258. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1259. 496, 0, 300, 301, 332, 333, 0,
  1260. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1261. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1262. 736, 0, 350, 351, 382, 383, 0,
  1263. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1264. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1265. 736, 0, 400, 401, 432, 433, 0,
  1266. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1267. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1268. 736, 0, 480, 481, 512, 513, 0,
  1269. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1270. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1271. 800, 0, 480, 481, 512, 513, 0,
  1272. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1273. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1274. 800, 0, 576, 577, 608, 609, 0,
  1275. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1276. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1277. 816, 0, 350, 351, 382, 383, 0,
  1278. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1279. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1280. 816, 0, 400, 401, 432, 433, 0,
  1281. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1282. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1283. 816, 0, 480, 481, 512, 513, 0,
  1284. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1285. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1286. 816, 0, 540, 541, 572, 573, 0,
  1287. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1288. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1289. 816, 0, 576, 577, 608, 609, 0,
  1290. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1291. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1292. 864, 0, 576, 577, 608, 609, 0,
  1293. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1294. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1295. 896, 0, 600, 601, 632, 633, 0,
  1296. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1297. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1298. 928, 0, 624, 625, 656, 657, 0,
  1299. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1300. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1301. 1016, 0, 766, 767, 798, 799, 0,
  1302. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1303. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1304. 1120, 0, 768, 769, 800, 801, 0,
  1305. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1306. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1307. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1308. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1309. };
  1310. static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1311. {
  1312. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1313. struct psb_intel_sdvo_sdtv_resolution_request tv_res;
  1314. uint32_t reply = 0, format_map = 0;
  1315. int i;
  1316. /* Read the list of supported input resolutions for the selected TV
  1317. * format.
  1318. */
  1319. format_map = 1 << psb_intel_sdvo->tv_format_index;
  1320. memcpy(&tv_res, &format_map,
  1321. min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request)));
  1322. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output))
  1323. return;
  1324. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1325. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1326. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1327. &tv_res, sizeof(tv_res)))
  1328. return;
  1329. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3))
  1330. return;
  1331. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1332. if (reply & (1 << i)) {
  1333. struct drm_display_mode *nmode;
  1334. nmode = drm_mode_duplicate(connector->dev,
  1335. &sdvo_tv_modes[i]);
  1336. if (nmode)
  1337. drm_mode_probed_add(connector, nmode);
  1338. }
  1339. }
  1340. static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1341. {
  1342. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1343. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1344. struct drm_display_mode *newmode;
  1345. /*
  1346. * Attempt to get the mode list from DDC.
  1347. * Assume that the preferred modes are
  1348. * arranged in priority order.
  1349. */
  1350. psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c);
  1351. if (list_empty(&connector->probed_modes) == false)
  1352. goto end;
  1353. /* Fetch modes from VBT */
  1354. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1355. newmode = drm_mode_duplicate(connector->dev,
  1356. dev_priv->sdvo_lvds_vbt_mode);
  1357. if (newmode != NULL) {
  1358. /* Guarantee the mode is preferred */
  1359. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1360. DRM_MODE_TYPE_DRIVER);
  1361. drm_mode_probed_add(connector, newmode);
  1362. }
  1363. }
  1364. end:
  1365. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1366. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1367. psb_intel_sdvo->sdvo_lvds_fixed_mode =
  1368. drm_mode_duplicate(connector->dev, newmode);
  1369. drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode,
  1370. 0);
  1371. psb_intel_sdvo->is_lvds = true;
  1372. break;
  1373. }
  1374. }
  1375. }
  1376. static int psb_intel_sdvo_get_modes(struct drm_connector *connector)
  1377. {
  1378. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1379. if (IS_TV(psb_intel_sdvo_connector))
  1380. psb_intel_sdvo_get_tv_modes(connector);
  1381. else if (IS_LVDS(psb_intel_sdvo_connector))
  1382. psb_intel_sdvo_get_lvds_modes(connector);
  1383. else
  1384. psb_intel_sdvo_get_ddc_modes(connector);
  1385. return !list_empty(&connector->probed_modes);
  1386. }
  1387. static void
  1388. psb_intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1389. {
  1390. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1391. struct drm_device *dev = connector->dev;
  1392. if (psb_intel_sdvo_connector->left)
  1393. drm_property_destroy(dev, psb_intel_sdvo_connector->left);
  1394. if (psb_intel_sdvo_connector->right)
  1395. drm_property_destroy(dev, psb_intel_sdvo_connector->right);
  1396. if (psb_intel_sdvo_connector->top)
  1397. drm_property_destroy(dev, psb_intel_sdvo_connector->top);
  1398. if (psb_intel_sdvo_connector->bottom)
  1399. drm_property_destroy(dev, psb_intel_sdvo_connector->bottom);
  1400. if (psb_intel_sdvo_connector->hpos)
  1401. drm_property_destroy(dev, psb_intel_sdvo_connector->hpos);
  1402. if (psb_intel_sdvo_connector->vpos)
  1403. drm_property_destroy(dev, psb_intel_sdvo_connector->vpos);
  1404. if (psb_intel_sdvo_connector->saturation)
  1405. drm_property_destroy(dev, psb_intel_sdvo_connector->saturation);
  1406. if (psb_intel_sdvo_connector->contrast)
  1407. drm_property_destroy(dev, psb_intel_sdvo_connector->contrast);
  1408. if (psb_intel_sdvo_connector->hue)
  1409. drm_property_destroy(dev, psb_intel_sdvo_connector->hue);
  1410. if (psb_intel_sdvo_connector->sharpness)
  1411. drm_property_destroy(dev, psb_intel_sdvo_connector->sharpness);
  1412. if (psb_intel_sdvo_connector->flicker_filter)
  1413. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter);
  1414. if (psb_intel_sdvo_connector->flicker_filter_2d)
  1415. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_2d);
  1416. if (psb_intel_sdvo_connector->flicker_filter_adaptive)
  1417. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_adaptive);
  1418. if (psb_intel_sdvo_connector->tv_luma_filter)
  1419. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_luma_filter);
  1420. if (psb_intel_sdvo_connector->tv_chroma_filter)
  1421. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_chroma_filter);
  1422. if (psb_intel_sdvo_connector->dot_crawl)
  1423. drm_property_destroy(dev, psb_intel_sdvo_connector->dot_crawl);
  1424. if (psb_intel_sdvo_connector->brightness)
  1425. drm_property_destroy(dev, psb_intel_sdvo_connector->brightness);
  1426. }
  1427. static void psb_intel_sdvo_destroy(struct drm_connector *connector)
  1428. {
  1429. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1430. if (psb_intel_sdvo_connector->tv_format)
  1431. drm_property_destroy(connector->dev,
  1432. psb_intel_sdvo_connector->tv_format);
  1433. psb_intel_sdvo_destroy_enhance_property(connector);
  1434. drm_sysfs_connector_remove(connector);
  1435. drm_connector_cleanup(connector);
  1436. kfree(connector);
  1437. }
  1438. static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1439. {
  1440. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1441. struct edid *edid;
  1442. bool has_audio = false;
  1443. if (!psb_intel_sdvo->is_hdmi)
  1444. return false;
  1445. edid = psb_intel_sdvo_get_edid(connector);
  1446. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1447. has_audio = drm_detect_monitor_audio(edid);
  1448. return has_audio;
  1449. }
  1450. static int
  1451. psb_intel_sdvo_set_property(struct drm_connector *connector,
  1452. struct drm_property *property,
  1453. uint64_t val)
  1454. {
  1455. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1456. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1457. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1458. uint16_t temp_value;
  1459. uint8_t cmd;
  1460. int ret;
  1461. ret = drm_connector_property_set_value(connector, property, val);
  1462. if (ret)
  1463. return ret;
  1464. if (property == dev_priv->force_audio_property) {
  1465. int i = val;
  1466. bool has_audio;
  1467. if (i == psb_intel_sdvo_connector->force_audio)
  1468. return 0;
  1469. psb_intel_sdvo_connector->force_audio = i;
  1470. if (i == 0)
  1471. has_audio = psb_intel_sdvo_detect_hdmi_audio(connector);
  1472. else
  1473. has_audio = i > 0;
  1474. if (has_audio == psb_intel_sdvo->has_hdmi_audio)
  1475. return 0;
  1476. psb_intel_sdvo->has_hdmi_audio = has_audio;
  1477. goto done;
  1478. }
  1479. if (property == dev_priv->broadcast_rgb_property) {
  1480. if (val == !!psb_intel_sdvo->color_range)
  1481. return 0;
  1482. psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1483. goto done;
  1484. }
  1485. #define CHECK_PROPERTY(name, NAME) \
  1486. if (psb_intel_sdvo_connector->name == property) { \
  1487. if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1488. if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1489. cmd = SDVO_CMD_SET_##NAME; \
  1490. psb_intel_sdvo_connector->cur_##name = temp_value; \
  1491. goto set_value; \
  1492. }
  1493. if (property == psb_intel_sdvo_connector->tv_format) {
  1494. if (val >= TV_FORMAT_NUM)
  1495. return -EINVAL;
  1496. if (psb_intel_sdvo->tv_format_index ==
  1497. psb_intel_sdvo_connector->tv_format_supported[val])
  1498. return 0;
  1499. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val];
  1500. goto done;
  1501. } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) {
  1502. temp_value = val;
  1503. if (psb_intel_sdvo_connector->left == property) {
  1504. drm_connector_property_set_value(connector,
  1505. psb_intel_sdvo_connector->right, val);
  1506. if (psb_intel_sdvo_connector->left_margin == temp_value)
  1507. return 0;
  1508. psb_intel_sdvo_connector->left_margin = temp_value;
  1509. psb_intel_sdvo_connector->right_margin = temp_value;
  1510. temp_value = psb_intel_sdvo_connector->max_hscan -
  1511. psb_intel_sdvo_connector->left_margin;
  1512. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1513. goto set_value;
  1514. } else if (psb_intel_sdvo_connector->right == property) {
  1515. drm_connector_property_set_value(connector,
  1516. psb_intel_sdvo_connector->left, val);
  1517. if (psb_intel_sdvo_connector->right_margin == temp_value)
  1518. return 0;
  1519. psb_intel_sdvo_connector->left_margin = temp_value;
  1520. psb_intel_sdvo_connector->right_margin = temp_value;
  1521. temp_value = psb_intel_sdvo_connector->max_hscan -
  1522. psb_intel_sdvo_connector->left_margin;
  1523. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1524. goto set_value;
  1525. } else if (psb_intel_sdvo_connector->top == property) {
  1526. drm_connector_property_set_value(connector,
  1527. psb_intel_sdvo_connector->bottom, val);
  1528. if (psb_intel_sdvo_connector->top_margin == temp_value)
  1529. return 0;
  1530. psb_intel_sdvo_connector->top_margin = temp_value;
  1531. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1532. temp_value = psb_intel_sdvo_connector->max_vscan -
  1533. psb_intel_sdvo_connector->top_margin;
  1534. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1535. goto set_value;
  1536. } else if (psb_intel_sdvo_connector->bottom == property) {
  1537. drm_connector_property_set_value(connector,
  1538. psb_intel_sdvo_connector->top, val);
  1539. if (psb_intel_sdvo_connector->bottom_margin == temp_value)
  1540. return 0;
  1541. psb_intel_sdvo_connector->top_margin = temp_value;
  1542. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1543. temp_value = psb_intel_sdvo_connector->max_vscan -
  1544. psb_intel_sdvo_connector->top_margin;
  1545. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1546. goto set_value;
  1547. }
  1548. CHECK_PROPERTY(hpos, HPOS)
  1549. CHECK_PROPERTY(vpos, VPOS)
  1550. CHECK_PROPERTY(saturation, SATURATION)
  1551. CHECK_PROPERTY(contrast, CONTRAST)
  1552. CHECK_PROPERTY(hue, HUE)
  1553. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1554. CHECK_PROPERTY(sharpness, SHARPNESS)
  1555. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1556. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1557. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1558. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1559. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1560. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1561. }
  1562. return -EINVAL; /* unknown property */
  1563. set_value:
  1564. if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2))
  1565. return -EIO;
  1566. done:
  1567. if (psb_intel_sdvo->base.base.crtc) {
  1568. struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc;
  1569. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1570. crtc->y, crtc->fb);
  1571. }
  1572. return 0;
  1573. #undef CHECK_PROPERTY
  1574. }
  1575. static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
  1576. .dpms = psb_intel_sdvo_dpms,
  1577. .mode_fixup = psb_intel_sdvo_mode_fixup,
  1578. .prepare = psb_intel_encoder_prepare,
  1579. .mode_set = psb_intel_sdvo_mode_set,
  1580. .commit = psb_intel_encoder_commit,
  1581. };
  1582. static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
  1583. .dpms = drm_helper_connector_dpms,
  1584. .detect = psb_intel_sdvo_detect,
  1585. .fill_modes = drm_helper_probe_single_connector_modes,
  1586. .set_property = psb_intel_sdvo_set_property,
  1587. .destroy = psb_intel_sdvo_destroy,
  1588. };
  1589. static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
  1590. .get_modes = psb_intel_sdvo_get_modes,
  1591. .mode_valid = psb_intel_sdvo_mode_valid,
  1592. .best_encoder = psb_intel_best_encoder,
  1593. };
  1594. static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1595. {
  1596. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  1597. if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1598. drm_mode_destroy(encoder->dev,
  1599. psb_intel_sdvo->sdvo_lvds_fixed_mode);
  1600. i2c_del_adapter(&psb_intel_sdvo->ddc);
  1601. psb_intel_encoder_destroy(encoder);
  1602. }
  1603. static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
  1604. .destroy = psb_intel_sdvo_enc_destroy,
  1605. };
  1606. static void
  1607. psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo)
  1608. {
  1609. /* FIXME: At the moment, ddc_bus = 2 is the only thing that works.
  1610. * We need to figure out if this is true for all available poulsbo
  1611. * hardware, or if we need to fiddle with the guessing code above.
  1612. * The problem might go away if we can parse sdvo mappings from bios */
  1613. sdvo->ddc_bus = 2;
  1614. #if 0
  1615. uint16_t mask = 0;
  1616. unsigned int num_bits;
  1617. /* Make a mask of outputs less than or equal to our own priority in the
  1618. * list.
  1619. */
  1620. switch (sdvo->controlled_output) {
  1621. case SDVO_OUTPUT_LVDS1:
  1622. mask |= SDVO_OUTPUT_LVDS1;
  1623. case SDVO_OUTPUT_LVDS0:
  1624. mask |= SDVO_OUTPUT_LVDS0;
  1625. case SDVO_OUTPUT_TMDS1:
  1626. mask |= SDVO_OUTPUT_TMDS1;
  1627. case SDVO_OUTPUT_TMDS0:
  1628. mask |= SDVO_OUTPUT_TMDS0;
  1629. case SDVO_OUTPUT_RGB1:
  1630. mask |= SDVO_OUTPUT_RGB1;
  1631. case SDVO_OUTPUT_RGB0:
  1632. mask |= SDVO_OUTPUT_RGB0;
  1633. break;
  1634. }
  1635. /* Count bits to find what number we are in the priority list. */
  1636. mask &= sdvo->caps.output_flags;
  1637. num_bits = hweight16(mask);
  1638. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1639. if (num_bits > 3)
  1640. num_bits = 3;
  1641. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1642. sdvo->ddc_bus = 1 << num_bits;
  1643. #endif
  1644. }
  1645. /**
  1646. * Choose the appropriate DDC bus for control bus switch command for this
  1647. * SDVO output based on the controlled output.
  1648. *
  1649. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1650. * outputs, then LVDS outputs.
  1651. */
  1652. static void
  1653. psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,
  1654. struct psb_intel_sdvo *sdvo, u32 reg)
  1655. {
  1656. struct sdvo_device_mapping *mapping;
  1657. if (IS_SDVOB(reg))
  1658. mapping = &(dev_priv->sdvo_mappings[0]);
  1659. else
  1660. mapping = &(dev_priv->sdvo_mappings[1]);
  1661. if (mapping->initialized)
  1662. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1663. else
  1664. psb_intel_sdvo_guess_ddc_bus(sdvo);
  1665. }
  1666. static void
  1667. psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,
  1668. struct psb_intel_sdvo *sdvo, u32 reg)
  1669. {
  1670. struct sdvo_device_mapping *mapping;
  1671. u8 pin, speed;
  1672. if (IS_SDVOB(reg))
  1673. mapping = &dev_priv->sdvo_mappings[0];
  1674. else
  1675. mapping = &dev_priv->sdvo_mappings[1];
  1676. pin = GMBUS_PORT_DPB;
  1677. speed = GMBUS_RATE_1MHZ >> 8;
  1678. if (mapping->initialized) {
  1679. pin = mapping->i2c_pin;
  1680. speed = mapping->i2c_speed;
  1681. }
  1682. if (pin < GMBUS_NUM_PORTS) {
  1683. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1684. gma_intel_gmbus_set_speed(sdvo->i2c, speed);
  1685. gma_intel_gmbus_force_bit(sdvo->i2c, true);
  1686. } else
  1687. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1688. }
  1689. static bool
  1690. psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1691. {
  1692. return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo);
  1693. }
  1694. static u8
  1695. psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1696. {
  1697. struct drm_psb_private *dev_priv = dev->dev_private;
  1698. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1699. if (IS_SDVOB(sdvo_reg)) {
  1700. my_mapping = &dev_priv->sdvo_mappings[0];
  1701. other_mapping = &dev_priv->sdvo_mappings[1];
  1702. } else {
  1703. my_mapping = &dev_priv->sdvo_mappings[1];
  1704. other_mapping = &dev_priv->sdvo_mappings[0];
  1705. }
  1706. /* If the BIOS described our SDVO device, take advantage of it. */
  1707. if (my_mapping->slave_addr)
  1708. return my_mapping->slave_addr;
  1709. /* If the BIOS only described a different SDVO device, use the
  1710. * address that it isn't using.
  1711. */
  1712. if (other_mapping->slave_addr) {
  1713. if (other_mapping->slave_addr == 0x70)
  1714. return 0x72;
  1715. else
  1716. return 0x70;
  1717. }
  1718. /* No SDVO device info is found for another DVO port,
  1719. * so use mapping assumption we had before BIOS parsing.
  1720. */
  1721. if (IS_SDVOB(sdvo_reg))
  1722. return 0x70;
  1723. else
  1724. return 0x72;
  1725. }
  1726. static void
  1727. psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector,
  1728. struct psb_intel_sdvo *encoder)
  1729. {
  1730. drm_connector_init(encoder->base.base.dev,
  1731. &connector->base.base,
  1732. &psb_intel_sdvo_connector_funcs,
  1733. connector->base.base.connector_type);
  1734. drm_connector_helper_add(&connector->base.base,
  1735. &psb_intel_sdvo_connector_helper_funcs);
  1736. connector->base.base.interlace_allowed = 0;
  1737. connector->base.base.doublescan_allowed = 0;
  1738. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1739. psb_intel_connector_attach_encoder(&connector->base, &encoder->base);
  1740. drm_sysfs_connector_add(&connector->base.base);
  1741. }
  1742. static void
  1743. psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector)
  1744. {
  1745. /* FIXME: We don't support HDMI at the moment
  1746. struct drm_device *dev = connector->base.base.dev;
  1747. intel_attach_force_audio_property(&connector->base.base);
  1748. intel_attach_broadcast_rgb_property(&connector->base.base);
  1749. */
  1750. }
  1751. static bool
  1752. psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1753. {
  1754. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1755. struct drm_connector *connector;
  1756. struct psb_intel_connector *intel_connector;
  1757. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1758. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1759. if (!psb_intel_sdvo_connector)
  1760. return false;
  1761. if (device == 0) {
  1762. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1763. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1764. } else if (device == 1) {
  1765. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1766. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1767. }
  1768. intel_connector = &psb_intel_sdvo_connector->base;
  1769. connector = &intel_connector->base;
  1770. // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1771. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1772. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1773. if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) {
  1774. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1775. psb_intel_sdvo->is_hdmi = true;
  1776. }
  1777. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1778. (1 << INTEL_ANALOG_CLONE_BIT));
  1779. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1780. if (psb_intel_sdvo->is_hdmi)
  1781. psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector);
  1782. return true;
  1783. }
  1784. static bool
  1785. psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type)
  1786. {
  1787. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1788. struct drm_connector *connector;
  1789. struct psb_intel_connector *intel_connector;
  1790. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1791. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1792. if (!psb_intel_sdvo_connector)
  1793. return false;
  1794. intel_connector = &psb_intel_sdvo_connector->base;
  1795. connector = &intel_connector->base;
  1796. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1797. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1798. psb_intel_sdvo->controlled_output |= type;
  1799. psb_intel_sdvo_connector->output_flag = type;
  1800. psb_intel_sdvo->is_tv = true;
  1801. psb_intel_sdvo->base.needs_tv_clock = true;
  1802. psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1803. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1804. if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type))
  1805. goto err;
  1806. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1807. goto err;
  1808. return true;
  1809. err:
  1810. psb_intel_sdvo_destroy(connector);
  1811. return false;
  1812. }
  1813. static bool
  1814. psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1815. {
  1816. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1817. struct drm_connector *connector;
  1818. struct psb_intel_connector *intel_connector;
  1819. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1820. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1821. if (!psb_intel_sdvo_connector)
  1822. return false;
  1823. intel_connector = &psb_intel_sdvo_connector->base;
  1824. connector = &intel_connector->base;
  1825. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1826. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1827. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1828. if (device == 0) {
  1829. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1830. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1831. } else if (device == 1) {
  1832. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1833. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1834. }
  1835. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1836. (1 << INTEL_ANALOG_CLONE_BIT));
  1837. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector,
  1838. psb_intel_sdvo);
  1839. return true;
  1840. }
  1841. static bool
  1842. psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1843. {
  1844. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1845. struct drm_connector *connector;
  1846. struct psb_intel_connector *intel_connector;
  1847. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1848. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1849. if (!psb_intel_sdvo_connector)
  1850. return false;
  1851. intel_connector = &psb_intel_sdvo_connector->base;
  1852. connector = &intel_connector->base;
  1853. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1854. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1855. if (device == 0) {
  1856. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1857. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1858. } else if (device == 1) {
  1859. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1860. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1861. }
  1862. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1863. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1864. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1865. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1866. goto err;
  1867. return true;
  1868. err:
  1869. psb_intel_sdvo_destroy(connector);
  1870. return false;
  1871. }
  1872. static bool
  1873. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags)
  1874. {
  1875. psb_intel_sdvo->is_tv = false;
  1876. psb_intel_sdvo->base.needs_tv_clock = false;
  1877. psb_intel_sdvo->is_lvds = false;
  1878. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1879. if (flags & SDVO_OUTPUT_TMDS0)
  1880. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0))
  1881. return false;
  1882. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1883. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1))
  1884. return false;
  1885. /* TV has no XXX1 function block */
  1886. if (flags & SDVO_OUTPUT_SVID0)
  1887. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0))
  1888. return false;
  1889. if (flags & SDVO_OUTPUT_CVBS0)
  1890. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0))
  1891. return false;
  1892. if (flags & SDVO_OUTPUT_RGB0)
  1893. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0))
  1894. return false;
  1895. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1896. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1))
  1897. return false;
  1898. if (flags & SDVO_OUTPUT_LVDS0)
  1899. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0))
  1900. return false;
  1901. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1902. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1))
  1903. return false;
  1904. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1905. unsigned char bytes[2];
  1906. psb_intel_sdvo->controlled_output = 0;
  1907. memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2);
  1908. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1909. SDVO_NAME(psb_intel_sdvo),
  1910. bytes[0], bytes[1]);
  1911. return false;
  1912. }
  1913. psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1914. return true;
  1915. }
  1916. static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  1917. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1918. int type)
  1919. {
  1920. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1921. struct psb_intel_sdvo_tv_format format;
  1922. uint32_t format_map, i;
  1923. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type))
  1924. return false;
  1925. BUILD_BUG_ON(sizeof(format) != 6);
  1926. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1927. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1928. &format, sizeof(format)))
  1929. return false;
  1930. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1931. if (format_map == 0)
  1932. return false;
  1933. psb_intel_sdvo_connector->format_supported_num = 0;
  1934. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1935. if (format_map & (1 << i))
  1936. psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
  1937. psb_intel_sdvo_connector->tv_format =
  1938. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1939. "mode", psb_intel_sdvo_connector->format_supported_num);
  1940. if (!psb_intel_sdvo_connector->tv_format)
  1941. return false;
  1942. for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++)
  1943. drm_property_add_enum(
  1944. psb_intel_sdvo_connector->tv_format, i,
  1945. i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]);
  1946. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0];
  1947. drm_connector_attach_property(&psb_intel_sdvo_connector->base.base,
  1948. psb_intel_sdvo_connector->tv_format, 0);
  1949. return true;
  1950. }
  1951. #define ENHANCEMENT(name, NAME) do { \
  1952. if (enhancements.name) { \
  1953. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1954. !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1955. return false; \
  1956. psb_intel_sdvo_connector->max_##name = data_value[0]; \
  1957. psb_intel_sdvo_connector->cur_##name = response; \
  1958. psb_intel_sdvo_connector->name = \
  1959. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1960. if (!psb_intel_sdvo_connector->name) return false; \
  1961. drm_connector_attach_property(connector, \
  1962. psb_intel_sdvo_connector->name, \
  1963. psb_intel_sdvo_connector->cur_##name); \
  1964. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1965. data_value[0], data_value[1], response); \
  1966. } \
  1967. } while(0)
  1968. static bool
  1969. psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo,
  1970. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1971. struct psb_intel_sdvo_enhancements_reply enhancements)
  1972. {
  1973. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1974. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  1975. uint16_t response, data_value[2];
  1976. /* when horizontal overscan is supported, Add the left/right property */
  1977. if (enhancements.overscan_h) {
  1978. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1979. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1980. &data_value, 4))
  1981. return false;
  1982. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1983. SDVO_CMD_GET_OVERSCAN_H,
  1984. &response, 2))
  1985. return false;
  1986. psb_intel_sdvo_connector->max_hscan = data_value[0];
  1987. psb_intel_sdvo_connector->left_margin = data_value[0] - response;
  1988. psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin;
  1989. psb_intel_sdvo_connector->left =
  1990. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  1991. if (!psb_intel_sdvo_connector->left)
  1992. return false;
  1993. drm_connector_attach_property(connector,
  1994. psb_intel_sdvo_connector->left,
  1995. psb_intel_sdvo_connector->left_margin);
  1996. psb_intel_sdvo_connector->right =
  1997. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  1998. if (!psb_intel_sdvo_connector->right)
  1999. return false;
  2000. drm_connector_attach_property(connector,
  2001. psb_intel_sdvo_connector->right,
  2002. psb_intel_sdvo_connector->right_margin);
  2003. DRM_DEBUG_KMS("h_overscan: max %d, "
  2004. "default %d, current %d\n",
  2005. data_value[0], data_value[1], response);
  2006. }
  2007. if (enhancements.overscan_v) {
  2008. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2009. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2010. &data_value, 4))
  2011. return false;
  2012. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2013. SDVO_CMD_GET_OVERSCAN_V,
  2014. &response, 2))
  2015. return false;
  2016. psb_intel_sdvo_connector->max_vscan = data_value[0];
  2017. psb_intel_sdvo_connector->top_margin = data_value[0] - response;
  2018. psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin;
  2019. psb_intel_sdvo_connector->top =
  2020. drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]);
  2021. if (!psb_intel_sdvo_connector->top)
  2022. return false;
  2023. drm_connector_attach_property(connector,
  2024. psb_intel_sdvo_connector->top,
  2025. psb_intel_sdvo_connector->top_margin);
  2026. psb_intel_sdvo_connector->bottom =
  2027. drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]);
  2028. if (!psb_intel_sdvo_connector->bottom)
  2029. return false;
  2030. drm_connector_attach_property(connector,
  2031. psb_intel_sdvo_connector->bottom,
  2032. psb_intel_sdvo_connector->bottom_margin);
  2033. DRM_DEBUG_KMS("v_overscan: max %d, "
  2034. "default %d, current %d\n",
  2035. data_value[0], data_value[1], response);
  2036. }
  2037. ENHANCEMENT(hpos, HPOS);
  2038. ENHANCEMENT(vpos, VPOS);
  2039. ENHANCEMENT(saturation, SATURATION);
  2040. ENHANCEMENT(contrast, CONTRAST);
  2041. ENHANCEMENT(hue, HUE);
  2042. ENHANCEMENT(sharpness, SHARPNESS);
  2043. ENHANCEMENT(brightness, BRIGHTNESS);
  2044. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2045. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2046. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2047. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2048. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2049. if (enhancements.dot_crawl) {
  2050. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2051. return false;
  2052. psb_intel_sdvo_connector->max_dot_crawl = 1;
  2053. psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2054. psb_intel_sdvo_connector->dot_crawl =
  2055. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2056. if (!psb_intel_sdvo_connector->dot_crawl)
  2057. return false;
  2058. drm_connector_attach_property(connector,
  2059. psb_intel_sdvo_connector->dot_crawl,
  2060. psb_intel_sdvo_connector->cur_dot_crawl);
  2061. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2062. }
  2063. return true;
  2064. }
  2065. static bool
  2066. psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo,
  2067. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  2068. struct psb_intel_sdvo_enhancements_reply enhancements)
  2069. {
  2070. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  2071. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  2072. uint16_t response, data_value[2];
  2073. ENHANCEMENT(brightness, BRIGHTNESS);
  2074. return true;
  2075. }
  2076. #undef ENHANCEMENT
  2077. static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  2078. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector)
  2079. {
  2080. union {
  2081. struct psb_intel_sdvo_enhancements_reply reply;
  2082. uint16_t response;
  2083. } enhancements;
  2084. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2085. enhancements.response = 0;
  2086. psb_intel_sdvo_get_value(psb_intel_sdvo,
  2087. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2088. &enhancements, sizeof(enhancements));
  2089. if (enhancements.response == 0) {
  2090. DRM_DEBUG_KMS("No enhancement is supported\n");
  2091. return true;
  2092. }
  2093. if (IS_TV(psb_intel_sdvo_connector))
  2094. return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2095. else if(IS_LVDS(psb_intel_sdvo_connector))
  2096. return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2097. else
  2098. return true;
  2099. }
  2100. static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2101. struct i2c_msg *msgs,
  2102. int num)
  2103. {
  2104. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2105. if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2106. return -EIO;
  2107. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2108. }
  2109. static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2110. {
  2111. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2112. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2113. }
  2114. static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = {
  2115. .master_xfer = psb_intel_sdvo_ddc_proxy_xfer,
  2116. .functionality = psb_intel_sdvo_ddc_proxy_func
  2117. };
  2118. static bool
  2119. psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,
  2120. struct drm_device *dev)
  2121. {
  2122. sdvo->ddc.owner = THIS_MODULE;
  2123. sdvo->ddc.class = I2C_CLASS_DDC;
  2124. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2125. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2126. sdvo->ddc.algo_data = sdvo;
  2127. sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
  2128. return i2c_add_adapter(&sdvo->ddc) == 0;
  2129. }
  2130. bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2131. {
  2132. struct drm_psb_private *dev_priv = dev->dev_private;
  2133. struct psb_intel_encoder *psb_intel_encoder;
  2134. struct psb_intel_sdvo *psb_intel_sdvo;
  2135. int i;
  2136. psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL);
  2137. if (!psb_intel_sdvo)
  2138. return false;
  2139. psb_intel_sdvo->sdvo_reg = sdvo_reg;
  2140. psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2141. psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2142. if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) {
  2143. kfree(psb_intel_sdvo);
  2144. return false;
  2145. }
  2146. /* encoder type will be decided later */
  2147. psb_intel_encoder = &psb_intel_sdvo->base;
  2148. psb_intel_encoder->type = INTEL_OUTPUT_SDVO;
  2149. drm_encoder_init(dev, &psb_intel_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
  2150. /* Read the regs to test if we can talk to the device */
  2151. for (i = 0; i < 0x40; i++) {
  2152. u8 byte;
  2153. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) {
  2154. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2155. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2156. goto err;
  2157. }
  2158. }
  2159. if (IS_SDVOB(sdvo_reg))
  2160. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2161. else
  2162. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2163. drm_encoder_helper_add(&psb_intel_encoder->base, &psb_intel_sdvo_helper_funcs);
  2164. /* In default case sdvo lvds is false */
  2165. if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
  2166. goto err;
  2167. if (psb_intel_sdvo_output_setup(psb_intel_sdvo,
  2168. psb_intel_sdvo->caps.output_flags) != true) {
  2169. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2170. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2171. goto err;
  2172. }
  2173. psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2174. /* Set the input timing to the screen. Assume always input 0. */
  2175. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  2176. goto err;
  2177. if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo,
  2178. &psb_intel_sdvo->pixel_clock_min,
  2179. &psb_intel_sdvo->pixel_clock_max))
  2180. goto err;
  2181. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2182. "clock range %dMHz - %dMHz, "
  2183. "input 1: %c, input 2: %c, "
  2184. "output 1: %c, output 2: %c\n",
  2185. SDVO_NAME(psb_intel_sdvo),
  2186. psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id,
  2187. psb_intel_sdvo->caps.device_rev_id,
  2188. psb_intel_sdvo->pixel_clock_min / 1000,
  2189. psb_intel_sdvo->pixel_clock_max / 1000,
  2190. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2191. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2192. /* check currently supported outputs */
  2193. psb_intel_sdvo->caps.output_flags &
  2194. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2195. psb_intel_sdvo->caps.output_flags &
  2196. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2197. return true;
  2198. err:
  2199. drm_encoder_cleanup(&psb_intel_encoder->base);
  2200. i2c_del_adapter(&psb_intel_sdvo->ddc);
  2201. kfree(psb_intel_sdvo);
  2202. return false;
  2203. }