cdv_device.c 15 KB

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  1. /**************************************************************************
  2. * Copyright (c) 2011, Intel Corporation.
  3. * All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. **************************************************************************/
  19. #include <linux/backlight.h>
  20. #include <drm/drmP.h>
  21. #include <drm/drm.h>
  22. #include "gma_drm.h"
  23. #include "psb_drv.h"
  24. #include "psb_reg.h"
  25. #include "psb_intel_reg.h"
  26. #include "intel_bios.h"
  27. #include "cdv_device.h"
  28. #define VGA_SR_INDEX 0x3c4
  29. #define VGA_SR_DATA 0x3c5
  30. static void cdv_disable_vga(struct drm_device *dev)
  31. {
  32. u8 sr1;
  33. u32 vga_reg;
  34. vga_reg = VGACNTRL;
  35. outb(1, VGA_SR_INDEX);
  36. sr1 = inb(VGA_SR_DATA);
  37. outb(sr1 | 1<<5, VGA_SR_DATA);
  38. udelay(300);
  39. REG_WRITE(vga_reg, VGA_DISP_DISABLE);
  40. REG_READ(vga_reg);
  41. }
  42. static int cdv_output_init(struct drm_device *dev)
  43. {
  44. struct drm_psb_private *dev_priv = dev->dev_private;
  45. drm_mode_create_scaling_mode_property(dev);
  46. cdv_disable_vga(dev);
  47. cdv_intel_crt_init(dev, &dev_priv->mode_dev);
  48. cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
  49. /* These bits indicate HDMI not SDVO on CDV */
  50. if (REG_READ(SDVOB) & SDVO_DETECTED)
  51. cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
  52. if (REG_READ(SDVOC) & SDVO_DETECTED)
  53. cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
  54. return 0;
  55. }
  56. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  57. /*
  58. * Cedartrail Backlght Interfaces
  59. */
  60. static struct backlight_device *cdv_backlight_device;
  61. static int cdv_backlight_combination_mode(struct drm_device *dev)
  62. {
  63. return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
  64. }
  65. static int cdv_get_brightness(struct backlight_device *bd)
  66. {
  67. struct drm_device *dev = bl_get_data(bd);
  68. u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  69. if (cdv_backlight_combination_mode(dev)) {
  70. u8 lbpc;
  71. val &= ~1;
  72. pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
  73. val *= lbpc;
  74. }
  75. return val;
  76. }
  77. static u32 cdv_get_max_backlight(struct drm_device *dev)
  78. {
  79. u32 max = REG_READ(BLC_PWM_CTL);
  80. if (max == 0) {
  81. DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
  82. /* i915 does this, I believe which means that we should not
  83. * smash PWM control as firmware will take control of it. */
  84. return 1;
  85. }
  86. max >>= 16;
  87. if (cdv_backlight_combination_mode(dev))
  88. max *= 0xff;
  89. return max;
  90. }
  91. static int cdv_set_brightness(struct backlight_device *bd)
  92. {
  93. struct drm_device *dev = bl_get_data(bd);
  94. int level = bd->props.brightness;
  95. u32 blc_pwm_ctl;
  96. /* Percentage 1-100% being valid */
  97. if (level < 1)
  98. level = 1;
  99. if (cdv_backlight_combination_mode(dev)) {
  100. u32 max = cdv_get_max_backlight(dev);
  101. u8 lbpc;
  102. lbpc = level * 0xfe / max + 1;
  103. level /= lbpc;
  104. pci_write_config_byte(dev->pdev, 0xF4, lbpc);
  105. }
  106. blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  107. REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
  108. (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
  109. return 0;
  110. }
  111. static const struct backlight_ops cdv_ops = {
  112. .get_brightness = cdv_get_brightness,
  113. .update_status = cdv_set_brightness,
  114. };
  115. static int cdv_backlight_init(struct drm_device *dev)
  116. {
  117. struct drm_psb_private *dev_priv = dev->dev_private;
  118. struct backlight_properties props;
  119. memset(&props, 0, sizeof(struct backlight_properties));
  120. props.max_brightness = 100;
  121. props.type = BACKLIGHT_PLATFORM;
  122. cdv_backlight_device = backlight_device_register("psb-bl",
  123. NULL, (void *)dev, &cdv_ops, &props);
  124. if (IS_ERR(cdv_backlight_device))
  125. return PTR_ERR(cdv_backlight_device);
  126. cdv_backlight_device->props.brightness =
  127. cdv_get_brightness(cdv_backlight_device);
  128. cdv_backlight_device->props.max_brightness = cdv_get_max_backlight(dev);
  129. backlight_update_status(cdv_backlight_device);
  130. dev_priv->backlight_device = cdv_backlight_device;
  131. return 0;
  132. }
  133. #endif
  134. /*
  135. * Provide the Cedarview specific chip logic and low level methods
  136. * for power management
  137. *
  138. * FIXME: we need to implement the apm/ospm base management bits
  139. * for this and the MID devices.
  140. */
  141. static inline u32 CDV_MSG_READ32(uint port, uint offset)
  142. {
  143. int mcr = (0x10<<24) | (port << 16) | (offset << 8);
  144. uint32_t ret_val = 0;
  145. struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
  146. pci_write_config_dword(pci_root, 0xD0, mcr);
  147. pci_read_config_dword(pci_root, 0xD4, &ret_val);
  148. pci_dev_put(pci_root);
  149. return ret_val;
  150. }
  151. static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
  152. {
  153. int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
  154. struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
  155. pci_write_config_dword(pci_root, 0xD4, value);
  156. pci_write_config_dword(pci_root, 0xD0, mcr);
  157. pci_dev_put(pci_root);
  158. }
  159. #define PSB_PM_SSC 0x20
  160. #define PSB_PM_SSS 0x30
  161. #define PSB_PWRGT_GFX_ON 0x02
  162. #define PSB_PWRGT_GFX_OFF 0x01
  163. #define PSB_PWRGT_GFX_D0 0x00
  164. #define PSB_PWRGT_GFX_D3 0x03
  165. static void cdv_init_pm(struct drm_device *dev)
  166. {
  167. struct drm_psb_private *dev_priv = dev->dev_private;
  168. u32 pwr_cnt;
  169. int i;
  170. dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
  171. PSB_APMBA) & 0xFFFF;
  172. dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
  173. PSB_OSPMBA) & 0xFFFF;
  174. /* Power status */
  175. pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
  176. /* Enable the GPU */
  177. pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
  178. pwr_cnt |= PSB_PWRGT_GFX_ON;
  179. outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
  180. /* Wait for the GPU power */
  181. for (i = 0; i < 5; i++) {
  182. u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
  183. if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
  184. return;
  185. udelay(10);
  186. }
  187. dev_err(dev->dev, "GPU: power management timed out.\n");
  188. }
  189. static void cdv_errata(struct drm_device *dev)
  190. {
  191. /* Disable bonus launch.
  192. * CPU and GPU competes for memory and display misses updates and
  193. * flickers. Worst with dual core, dual displays.
  194. *
  195. * Fixes were done to Win 7 gfx driver to disable a feature called
  196. * Bonus Launch to work around the issue, by degrading
  197. * performance.
  198. */
  199. CDV_MSG_WRITE32(3, 0x30, 0x08027108);
  200. }
  201. /**
  202. * cdv_save_display_registers - save registers lost on suspend
  203. * @dev: our DRM device
  204. *
  205. * Save the state we need in order to be able to restore the interface
  206. * upon resume from suspend
  207. */
  208. static int cdv_save_display_registers(struct drm_device *dev)
  209. {
  210. struct drm_psb_private *dev_priv = dev->dev_private;
  211. struct psb_save_area *regs = &dev_priv->regs;
  212. struct drm_connector *connector;
  213. dev_dbg(dev->dev, "Saving GPU registers.\n");
  214. pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
  215. regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
  216. regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
  217. regs->cdv.saveDSPARB = REG_READ(DSPARB);
  218. regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
  219. regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
  220. regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
  221. regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
  222. regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
  223. regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
  224. regs->cdv.saveADPA = REG_READ(ADPA);
  225. regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
  226. regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
  227. regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
  228. regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
  229. regs->cdv.saveLVDS = REG_READ(LVDS);
  230. regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
  231. regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
  232. regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
  233. regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
  234. regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
  235. regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
  236. regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
  237. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  238. connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
  239. return 0;
  240. }
  241. /**
  242. * cdv_restore_display_registers - restore lost register state
  243. * @dev: our DRM device
  244. *
  245. * Restore register state that was lost during suspend and resume.
  246. *
  247. * FIXME: review
  248. */
  249. static int cdv_restore_display_registers(struct drm_device *dev)
  250. {
  251. struct drm_psb_private *dev_priv = dev->dev_private;
  252. struct psb_save_area *regs = &dev_priv->regs;
  253. struct drm_connector *connector;
  254. u32 temp;
  255. pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
  256. REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
  257. REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
  258. /* BIOS does below anyway */
  259. REG_WRITE(DPIO_CFG, 0);
  260. REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
  261. temp = REG_READ(DPLL_A);
  262. if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
  263. REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
  264. REG_READ(DPLL_A);
  265. }
  266. temp = REG_READ(DPLL_B);
  267. if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
  268. REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
  269. REG_READ(DPLL_B);
  270. }
  271. udelay(500);
  272. REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
  273. REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
  274. REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
  275. REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
  276. REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
  277. REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
  278. REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
  279. REG_WRITE(ADPA, regs->cdv.saveADPA);
  280. REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
  281. REG_WRITE(LVDS, regs->cdv.saveLVDS);
  282. REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
  283. REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
  284. REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
  285. REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
  286. REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
  287. REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
  288. REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
  289. REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
  290. REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
  291. REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
  292. /* Fix arbitration bug */
  293. cdv_errata(dev);
  294. drm_mode_config_reset(dev);
  295. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  296. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  297. /* Resume the modeset for every activated CRTC */
  298. drm_helper_resume_force_mode(dev);
  299. return 0;
  300. }
  301. static int cdv_power_down(struct drm_device *dev)
  302. {
  303. struct drm_psb_private *dev_priv = dev->dev_private;
  304. u32 pwr_cnt, pwr_mask, pwr_sts;
  305. int tries = 5;
  306. pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
  307. pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
  308. pwr_cnt |= PSB_PWRGT_GFX_OFF;
  309. pwr_mask = PSB_PWRGT_GFX_MASK;
  310. outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
  311. while (tries--) {
  312. pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
  313. if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
  314. return 0;
  315. udelay(10);
  316. }
  317. return 0;
  318. }
  319. static int cdv_power_up(struct drm_device *dev)
  320. {
  321. struct drm_psb_private *dev_priv = dev->dev_private;
  322. u32 pwr_cnt, pwr_mask, pwr_sts;
  323. int tries = 5;
  324. pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
  325. pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
  326. pwr_cnt |= PSB_PWRGT_GFX_ON;
  327. pwr_mask = PSB_PWRGT_GFX_MASK;
  328. outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
  329. while (tries--) {
  330. pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
  331. if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
  332. return 0;
  333. udelay(10);
  334. }
  335. return 0;
  336. }
  337. /* FIXME ? - shared with Poulsbo */
  338. static void cdv_get_core_freq(struct drm_device *dev)
  339. {
  340. uint32_t clock;
  341. struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
  342. struct drm_psb_private *dev_priv = dev->dev_private;
  343. pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
  344. pci_read_config_dword(pci_root, 0xD4, &clock);
  345. pci_dev_put(pci_root);
  346. switch (clock & 0x07) {
  347. case 0:
  348. dev_priv->core_freq = 100;
  349. break;
  350. case 1:
  351. dev_priv->core_freq = 133;
  352. break;
  353. case 2:
  354. dev_priv->core_freq = 150;
  355. break;
  356. case 3:
  357. dev_priv->core_freq = 178;
  358. break;
  359. case 4:
  360. dev_priv->core_freq = 200;
  361. break;
  362. case 5:
  363. case 6:
  364. case 7:
  365. dev_priv->core_freq = 266;
  366. default:
  367. dev_priv->core_freq = 0;
  368. }
  369. }
  370. static void cdv_hotplug_work_func(struct work_struct *work)
  371. {
  372. struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
  373. hotplug_work);
  374. struct drm_device *dev = dev_priv->dev;
  375. /* Just fire off a uevent and let userspace tell us what to do */
  376. drm_helper_hpd_irq_event(dev);
  377. }
  378. /* The core driver has received a hotplug IRQ. We are in IRQ context
  379. so extract the needed information and kick off queued processing */
  380. static int cdv_hotplug_event(struct drm_device *dev)
  381. {
  382. struct drm_psb_private *dev_priv = dev->dev_private;
  383. schedule_work(&dev_priv->hotplug_work);
  384. REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
  385. return 1;
  386. }
  387. static void cdv_hotplug_enable(struct drm_device *dev, bool on)
  388. {
  389. if (on) {
  390. u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
  391. hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN |
  392. HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN;
  393. REG_WRITE(PORT_HOTPLUG_EN, hotplug);
  394. } else {
  395. REG_WRITE(PORT_HOTPLUG_EN, 0);
  396. REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
  397. }
  398. }
  399. /* Cedarview */
  400. static const struct psb_offset cdv_regmap[2] = {
  401. {
  402. .fp0 = FPA0,
  403. .fp1 = FPA1,
  404. .cntr = DSPACNTR,
  405. .conf = PIPEACONF,
  406. .src = PIPEASRC,
  407. .dpll = DPLL_A,
  408. .dpll_md = DPLL_A_MD,
  409. .htotal = HTOTAL_A,
  410. .hblank = HBLANK_A,
  411. .hsync = HSYNC_A,
  412. .vtotal = VTOTAL_A,
  413. .vblank = VBLANK_A,
  414. .vsync = VSYNC_A,
  415. .stride = DSPASTRIDE,
  416. .size = DSPASIZE,
  417. .pos = DSPAPOS,
  418. .base = DSPABASE,
  419. .surf = DSPASURF,
  420. .addr = DSPABASE,
  421. .status = PIPEASTAT,
  422. .linoff = DSPALINOFF,
  423. .tileoff = DSPATILEOFF,
  424. .palette = PALETTE_A,
  425. },
  426. {
  427. .fp0 = FPB0,
  428. .fp1 = FPB1,
  429. .cntr = DSPBCNTR,
  430. .conf = PIPEBCONF,
  431. .src = PIPEBSRC,
  432. .dpll = DPLL_B,
  433. .dpll_md = DPLL_B_MD,
  434. .htotal = HTOTAL_B,
  435. .hblank = HBLANK_B,
  436. .hsync = HSYNC_B,
  437. .vtotal = VTOTAL_B,
  438. .vblank = VBLANK_B,
  439. .vsync = VSYNC_B,
  440. .stride = DSPBSTRIDE,
  441. .size = DSPBSIZE,
  442. .pos = DSPBPOS,
  443. .base = DSPBBASE,
  444. .surf = DSPBSURF,
  445. .addr = DSPBBASE,
  446. .status = PIPEBSTAT,
  447. .linoff = DSPBLINOFF,
  448. .tileoff = DSPBTILEOFF,
  449. .palette = PALETTE_B,
  450. }
  451. };
  452. static int cdv_chip_setup(struct drm_device *dev)
  453. {
  454. struct drm_psb_private *dev_priv = dev->dev_private;
  455. INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
  456. if (pci_enable_msi(dev->pdev))
  457. dev_warn(dev->dev, "Enabling MSI failed!\n");
  458. dev_priv->regmap = cdv_regmap;
  459. cdv_get_core_freq(dev);
  460. psb_intel_opregion_init(dev);
  461. psb_intel_init_bios(dev);
  462. cdv_hotplug_enable(dev, false);
  463. return 0;
  464. }
  465. /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
  466. const struct psb_ops cdv_chip_ops = {
  467. .name = "GMA3600/3650",
  468. .accel_2d = 0,
  469. .pipes = 2,
  470. .crtcs = 2,
  471. .hdmi_mask = (1 << 0) | (1 << 1),
  472. .lvds_mask = (1 << 1),
  473. .cursor_needs_phys = 0,
  474. .sgx_offset = MRST_SGX_OFFSET,
  475. .chip_setup = cdv_chip_setup,
  476. .errata = cdv_errata,
  477. .crtc_helper = &cdv_intel_helper_funcs,
  478. .crtc_funcs = &cdv_intel_crtc_funcs,
  479. .output_init = cdv_output_init,
  480. .hotplug = cdv_hotplug_event,
  481. .hotplug_enable = cdv_hotplug_enable,
  482. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  483. .backlight_init = cdv_backlight_init,
  484. #endif
  485. .init_pm = cdv_init_pm,
  486. .save_regs = cdv_save_display_registers,
  487. .restore_regs = cdv_restore_display_registers,
  488. .power_down = cdv_power_down,
  489. .power_up = cdv_power_up,
  490. };