exynos_drm_fimd.c 24 KB

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  1. /* exynos_drm_fimd.c
  2. *
  3. * Copyright (C) 2011 Samsung Electronics Co.Ltd
  4. * Authors:
  5. * Joonyoung Shim <jy0922.shim@samsung.com>
  6. * Inki Dae <inki.dae@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include "drmP.h"
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/pm_runtime.h>
  20. #include <drm/exynos_drm.h>
  21. #include <plat/regs-fb-v4.h>
  22. #include "exynos_drm_drv.h"
  23. #include "exynos_drm_fbdev.h"
  24. #include "exynos_drm_crtc.h"
  25. /*
  26. * FIMD is stand for Fully Interactive Mobile Display and
  27. * as a display controller, it transfers contents drawn on memory
  28. * to a LCD Panel through Display Interfaces such as RGB or
  29. * CPU Interface.
  30. */
  31. /* position control register for hardware window 0, 2 ~ 4.*/
  32. #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
  33. #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
  34. /* size control register for hardware window 0. */
  35. #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
  36. /* alpha control register for hardware window 1 ~ 4. */
  37. #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
  38. /* size control register for hardware window 1 ~ 4. */
  39. #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
  40. #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
  41. #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
  42. #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
  43. /* color key control register for hardware window 1 ~ 4. */
  44. #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
  45. /* color key value register for hardware window 1 ~ 4. */
  46. #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
  47. /* FIMD has totally five hardware windows. */
  48. #define WINDOWS_NR 5
  49. #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
  50. struct fimd_win_data {
  51. unsigned int offset_x;
  52. unsigned int offset_y;
  53. unsigned int ovl_width;
  54. unsigned int ovl_height;
  55. unsigned int fb_width;
  56. unsigned int fb_height;
  57. unsigned int bpp;
  58. dma_addr_t dma_addr;
  59. void __iomem *vaddr;
  60. unsigned int buf_offsize;
  61. unsigned int line_size; /* bytes */
  62. bool enabled;
  63. };
  64. struct fimd_context {
  65. struct exynos_drm_subdrv subdrv;
  66. int irq;
  67. struct drm_crtc *crtc;
  68. struct clk *bus_clk;
  69. struct clk *lcd_clk;
  70. struct resource *regs_res;
  71. void __iomem *regs;
  72. struct fimd_win_data win_data[WINDOWS_NR];
  73. unsigned int clkdiv;
  74. unsigned int default_win;
  75. unsigned long irq_flags;
  76. u32 vidcon0;
  77. u32 vidcon1;
  78. bool suspended;
  79. struct mutex lock;
  80. struct exynos_drm_panel_info *panel;
  81. };
  82. static bool fimd_display_is_connected(struct device *dev)
  83. {
  84. DRM_DEBUG_KMS("%s\n", __FILE__);
  85. /* TODO. */
  86. return true;
  87. }
  88. static void *fimd_get_panel(struct device *dev)
  89. {
  90. struct fimd_context *ctx = get_fimd_context(dev);
  91. DRM_DEBUG_KMS("%s\n", __FILE__);
  92. return ctx->panel;
  93. }
  94. static int fimd_check_timing(struct device *dev, void *timing)
  95. {
  96. DRM_DEBUG_KMS("%s\n", __FILE__);
  97. /* TODO. */
  98. return 0;
  99. }
  100. static int fimd_display_power_on(struct device *dev, int mode)
  101. {
  102. DRM_DEBUG_KMS("%s\n", __FILE__);
  103. /* TODO */
  104. return 0;
  105. }
  106. static struct exynos_drm_display_ops fimd_display_ops = {
  107. .type = EXYNOS_DISPLAY_TYPE_LCD,
  108. .is_connected = fimd_display_is_connected,
  109. .get_panel = fimd_get_panel,
  110. .check_timing = fimd_check_timing,
  111. .power_on = fimd_display_power_on,
  112. };
  113. static void fimd_dpms(struct device *subdrv_dev, int mode)
  114. {
  115. struct fimd_context *ctx = get_fimd_context(subdrv_dev);
  116. DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
  117. mutex_lock(&ctx->lock);
  118. switch (mode) {
  119. case DRM_MODE_DPMS_ON:
  120. /*
  121. * enable fimd hardware only if suspended status.
  122. *
  123. * P.S. fimd_dpms function would be called at booting time so
  124. * clk_enable could be called double time.
  125. */
  126. if (ctx->suspended)
  127. pm_runtime_get_sync(subdrv_dev);
  128. break;
  129. case DRM_MODE_DPMS_STANDBY:
  130. case DRM_MODE_DPMS_SUSPEND:
  131. case DRM_MODE_DPMS_OFF:
  132. if (!ctx->suspended)
  133. pm_runtime_put_sync(subdrv_dev);
  134. break;
  135. default:
  136. DRM_DEBUG_KMS("unspecified mode %d\n", mode);
  137. break;
  138. }
  139. mutex_unlock(&ctx->lock);
  140. }
  141. static void fimd_apply(struct device *subdrv_dev)
  142. {
  143. struct fimd_context *ctx = get_fimd_context(subdrv_dev);
  144. struct exynos_drm_manager *mgr = ctx->subdrv.manager;
  145. struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
  146. struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
  147. struct fimd_win_data *win_data;
  148. int i;
  149. DRM_DEBUG_KMS("%s\n", __FILE__);
  150. for (i = 0; i < WINDOWS_NR; i++) {
  151. win_data = &ctx->win_data[i];
  152. if (win_data->enabled && (ovl_ops && ovl_ops->commit))
  153. ovl_ops->commit(subdrv_dev, i);
  154. }
  155. if (mgr_ops && mgr_ops->commit)
  156. mgr_ops->commit(subdrv_dev);
  157. }
  158. static void fimd_commit(struct device *dev)
  159. {
  160. struct fimd_context *ctx = get_fimd_context(dev);
  161. struct exynos_drm_panel_info *panel = ctx->panel;
  162. struct fb_videomode *timing = &panel->timing;
  163. u32 val;
  164. if (ctx->suspended)
  165. return;
  166. DRM_DEBUG_KMS("%s\n", __FILE__);
  167. /* setup polarity values from machine code. */
  168. writel(ctx->vidcon1, ctx->regs + VIDCON1);
  169. /* setup vertical timing values. */
  170. val = VIDTCON0_VBPD(timing->upper_margin - 1) |
  171. VIDTCON0_VFPD(timing->lower_margin - 1) |
  172. VIDTCON0_VSPW(timing->vsync_len - 1);
  173. writel(val, ctx->regs + VIDTCON0);
  174. /* setup horizontal timing values. */
  175. val = VIDTCON1_HBPD(timing->left_margin - 1) |
  176. VIDTCON1_HFPD(timing->right_margin - 1) |
  177. VIDTCON1_HSPW(timing->hsync_len - 1);
  178. writel(val, ctx->regs + VIDTCON1);
  179. /* setup horizontal and vertical display size. */
  180. val = VIDTCON2_LINEVAL(timing->yres - 1) |
  181. VIDTCON2_HOZVAL(timing->xres - 1);
  182. writel(val, ctx->regs + VIDTCON2);
  183. /* setup clock source, clock divider, enable dma. */
  184. val = ctx->vidcon0;
  185. val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
  186. if (ctx->clkdiv > 1)
  187. val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
  188. else
  189. val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
  190. /*
  191. * fields of register with prefix '_F' would be updated
  192. * at vsync(same as dma start)
  193. */
  194. val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
  195. writel(val, ctx->regs + VIDCON0);
  196. }
  197. static int fimd_enable_vblank(struct device *dev)
  198. {
  199. struct fimd_context *ctx = get_fimd_context(dev);
  200. u32 val;
  201. DRM_DEBUG_KMS("%s\n", __FILE__);
  202. if (ctx->suspended)
  203. return -EPERM;
  204. if (!test_and_set_bit(0, &ctx->irq_flags)) {
  205. val = readl(ctx->regs + VIDINTCON0);
  206. val |= VIDINTCON0_INT_ENABLE;
  207. val |= VIDINTCON0_INT_FRAME;
  208. val &= ~VIDINTCON0_FRAMESEL0_MASK;
  209. val |= VIDINTCON0_FRAMESEL0_VSYNC;
  210. val &= ~VIDINTCON0_FRAMESEL1_MASK;
  211. val |= VIDINTCON0_FRAMESEL1_NONE;
  212. writel(val, ctx->regs + VIDINTCON0);
  213. }
  214. return 0;
  215. }
  216. static void fimd_disable_vblank(struct device *dev)
  217. {
  218. struct fimd_context *ctx = get_fimd_context(dev);
  219. u32 val;
  220. DRM_DEBUG_KMS("%s\n", __FILE__);
  221. if (ctx->suspended)
  222. return;
  223. if (test_and_clear_bit(0, &ctx->irq_flags)) {
  224. val = readl(ctx->regs + VIDINTCON0);
  225. val &= ~VIDINTCON0_INT_FRAME;
  226. val &= ~VIDINTCON0_INT_ENABLE;
  227. writel(val, ctx->regs + VIDINTCON0);
  228. }
  229. }
  230. static struct exynos_drm_manager_ops fimd_manager_ops = {
  231. .dpms = fimd_dpms,
  232. .apply = fimd_apply,
  233. .commit = fimd_commit,
  234. .enable_vblank = fimd_enable_vblank,
  235. .disable_vblank = fimd_disable_vblank,
  236. };
  237. static void fimd_win_mode_set(struct device *dev,
  238. struct exynos_drm_overlay *overlay)
  239. {
  240. struct fimd_context *ctx = get_fimd_context(dev);
  241. struct fimd_win_data *win_data;
  242. int win;
  243. unsigned long offset;
  244. DRM_DEBUG_KMS("%s\n", __FILE__);
  245. if (!overlay) {
  246. dev_err(dev, "overlay is NULL\n");
  247. return;
  248. }
  249. win = overlay->zpos;
  250. if (win == DEFAULT_ZPOS)
  251. win = ctx->default_win;
  252. if (win < 0 || win > WINDOWS_NR)
  253. return;
  254. offset = overlay->fb_x * (overlay->bpp >> 3);
  255. offset += overlay->fb_y * overlay->pitch;
  256. DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
  257. win_data = &ctx->win_data[win];
  258. win_data->offset_x = overlay->crtc_x;
  259. win_data->offset_y = overlay->crtc_y;
  260. win_data->ovl_width = overlay->crtc_width;
  261. win_data->ovl_height = overlay->crtc_height;
  262. win_data->fb_width = overlay->fb_width;
  263. win_data->fb_height = overlay->fb_height;
  264. win_data->dma_addr = overlay->dma_addr[0] + offset;
  265. win_data->vaddr = overlay->vaddr[0] + offset;
  266. win_data->bpp = overlay->bpp;
  267. win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
  268. (overlay->bpp >> 3);
  269. win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
  270. DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
  271. win_data->offset_x, win_data->offset_y);
  272. DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
  273. win_data->ovl_width, win_data->ovl_height);
  274. DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
  275. (unsigned long)win_data->dma_addr,
  276. (unsigned long)win_data->vaddr);
  277. DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
  278. overlay->fb_width, overlay->crtc_width);
  279. }
  280. static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
  281. {
  282. struct fimd_context *ctx = get_fimd_context(dev);
  283. struct fimd_win_data *win_data = &ctx->win_data[win];
  284. unsigned long val;
  285. DRM_DEBUG_KMS("%s\n", __FILE__);
  286. val = WINCONx_ENWIN;
  287. switch (win_data->bpp) {
  288. case 1:
  289. val |= WINCON0_BPPMODE_1BPP;
  290. val |= WINCONx_BITSWP;
  291. val |= WINCONx_BURSTLEN_4WORD;
  292. break;
  293. case 2:
  294. val |= WINCON0_BPPMODE_2BPP;
  295. val |= WINCONx_BITSWP;
  296. val |= WINCONx_BURSTLEN_8WORD;
  297. break;
  298. case 4:
  299. val |= WINCON0_BPPMODE_4BPP;
  300. val |= WINCONx_BITSWP;
  301. val |= WINCONx_BURSTLEN_8WORD;
  302. break;
  303. case 8:
  304. val |= WINCON0_BPPMODE_8BPP_PALETTE;
  305. val |= WINCONx_BURSTLEN_8WORD;
  306. val |= WINCONx_BYTSWP;
  307. break;
  308. case 16:
  309. val |= WINCON0_BPPMODE_16BPP_565;
  310. val |= WINCONx_HAWSWP;
  311. val |= WINCONx_BURSTLEN_16WORD;
  312. break;
  313. case 24:
  314. val |= WINCON0_BPPMODE_24BPP_888;
  315. val |= WINCONx_WSWP;
  316. val |= WINCONx_BURSTLEN_16WORD;
  317. break;
  318. case 32:
  319. val |= WINCON1_BPPMODE_28BPP_A4888
  320. | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
  321. val |= WINCONx_WSWP;
  322. val |= WINCONx_BURSTLEN_16WORD;
  323. break;
  324. default:
  325. DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
  326. val |= WINCON0_BPPMODE_24BPP_888;
  327. val |= WINCONx_WSWP;
  328. val |= WINCONx_BURSTLEN_16WORD;
  329. break;
  330. }
  331. DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
  332. writel(val, ctx->regs + WINCON(win));
  333. }
  334. static void fimd_win_set_colkey(struct device *dev, unsigned int win)
  335. {
  336. struct fimd_context *ctx = get_fimd_context(dev);
  337. unsigned int keycon0 = 0, keycon1 = 0;
  338. DRM_DEBUG_KMS("%s\n", __FILE__);
  339. keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
  340. WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
  341. keycon1 = WxKEYCON1_COLVAL(0xffffffff);
  342. writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
  343. writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
  344. }
  345. static void fimd_win_commit(struct device *dev, int zpos)
  346. {
  347. struct fimd_context *ctx = get_fimd_context(dev);
  348. struct fimd_win_data *win_data;
  349. int win = zpos;
  350. unsigned long val, alpha, size;
  351. DRM_DEBUG_KMS("%s\n", __FILE__);
  352. if (ctx->suspended)
  353. return;
  354. if (win == DEFAULT_ZPOS)
  355. win = ctx->default_win;
  356. if (win < 0 || win > WINDOWS_NR)
  357. return;
  358. win_data = &ctx->win_data[win];
  359. /*
  360. * SHADOWCON register is used for enabling timing.
  361. *
  362. * for example, once only width value of a register is set,
  363. * if the dma is started then fimd hardware could malfunction so
  364. * with protect window setting, the register fields with prefix '_F'
  365. * wouldn't be updated at vsync also but updated once unprotect window
  366. * is set.
  367. */
  368. /* protect windows */
  369. val = readl(ctx->regs + SHADOWCON);
  370. val |= SHADOWCON_WINx_PROTECT(win);
  371. writel(val, ctx->regs + SHADOWCON);
  372. /* buffer start address */
  373. val = (unsigned long)win_data->dma_addr;
  374. writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
  375. /* buffer end address */
  376. size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
  377. val = (unsigned long)(win_data->dma_addr + size);
  378. writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
  379. DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
  380. (unsigned long)win_data->dma_addr, val, size);
  381. DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
  382. win_data->ovl_width, win_data->ovl_height);
  383. /* buffer size */
  384. val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
  385. VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
  386. writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
  387. /* OSD position */
  388. val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
  389. VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
  390. writel(val, ctx->regs + VIDOSD_A(win));
  391. val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
  392. win_data->ovl_width - 1) |
  393. VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
  394. win_data->ovl_height - 1);
  395. writel(val, ctx->regs + VIDOSD_B(win));
  396. DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
  397. win_data->offset_x, win_data->offset_y,
  398. win_data->offset_x + win_data->ovl_width - 1,
  399. win_data->offset_y + win_data->ovl_height - 1);
  400. /* hardware window 0 doesn't support alpha channel. */
  401. if (win != 0) {
  402. /* OSD alpha */
  403. alpha = VIDISD14C_ALPHA1_R(0xf) |
  404. VIDISD14C_ALPHA1_G(0xf) |
  405. VIDISD14C_ALPHA1_B(0xf);
  406. writel(alpha, ctx->regs + VIDOSD_C(win));
  407. }
  408. /* OSD size */
  409. if (win != 3 && win != 4) {
  410. u32 offset = VIDOSD_D(win);
  411. if (win == 0)
  412. offset = VIDOSD_C_SIZE_W0;
  413. val = win_data->ovl_width * win_data->ovl_height;
  414. writel(val, ctx->regs + offset);
  415. DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
  416. }
  417. fimd_win_set_pixfmt(dev, win);
  418. /* hardware window 0 doesn't support color key. */
  419. if (win != 0)
  420. fimd_win_set_colkey(dev, win);
  421. /* wincon */
  422. val = readl(ctx->regs + WINCON(win));
  423. val |= WINCONx_ENWIN;
  424. writel(val, ctx->regs + WINCON(win));
  425. /* Enable DMA channel and unprotect windows */
  426. val = readl(ctx->regs + SHADOWCON);
  427. val |= SHADOWCON_CHx_ENABLE(win);
  428. val &= ~SHADOWCON_WINx_PROTECT(win);
  429. writel(val, ctx->regs + SHADOWCON);
  430. win_data->enabled = true;
  431. }
  432. static void fimd_win_disable(struct device *dev, int zpos)
  433. {
  434. struct fimd_context *ctx = get_fimd_context(dev);
  435. struct fimd_win_data *win_data;
  436. int win = zpos;
  437. u32 val;
  438. DRM_DEBUG_KMS("%s\n", __FILE__);
  439. if (win == DEFAULT_ZPOS)
  440. win = ctx->default_win;
  441. if (win < 0 || win > WINDOWS_NR)
  442. return;
  443. win_data = &ctx->win_data[win];
  444. /* protect windows */
  445. val = readl(ctx->regs + SHADOWCON);
  446. val |= SHADOWCON_WINx_PROTECT(win);
  447. writel(val, ctx->regs + SHADOWCON);
  448. /* wincon */
  449. val = readl(ctx->regs + WINCON(win));
  450. val &= ~WINCONx_ENWIN;
  451. writel(val, ctx->regs + WINCON(win));
  452. /* unprotect windows */
  453. val = readl(ctx->regs + SHADOWCON);
  454. val &= ~SHADOWCON_CHx_ENABLE(win);
  455. val &= ~SHADOWCON_WINx_PROTECT(win);
  456. writel(val, ctx->regs + SHADOWCON);
  457. win_data->enabled = false;
  458. }
  459. static struct exynos_drm_overlay_ops fimd_overlay_ops = {
  460. .mode_set = fimd_win_mode_set,
  461. .commit = fimd_win_commit,
  462. .disable = fimd_win_disable,
  463. };
  464. static struct exynos_drm_manager fimd_manager = {
  465. .pipe = -1,
  466. .ops = &fimd_manager_ops,
  467. .overlay_ops = &fimd_overlay_ops,
  468. .display_ops = &fimd_display_ops,
  469. };
  470. static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
  471. {
  472. struct exynos_drm_private *dev_priv = drm_dev->dev_private;
  473. struct drm_pending_vblank_event *e, *t;
  474. struct timeval now;
  475. unsigned long flags;
  476. bool is_checked = false;
  477. spin_lock_irqsave(&drm_dev->event_lock, flags);
  478. list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
  479. base.link) {
  480. /* if event's pipe isn't same as crtc then ignore it. */
  481. if (crtc != e->pipe)
  482. continue;
  483. is_checked = true;
  484. do_gettimeofday(&now);
  485. e->event.sequence = 0;
  486. e->event.tv_sec = now.tv_sec;
  487. e->event.tv_usec = now.tv_usec;
  488. list_move_tail(&e->base.link, &e->base.file_priv->event_list);
  489. wake_up_interruptible(&e->base.file_priv->event_wait);
  490. }
  491. if (is_checked) {
  492. /*
  493. * call drm_vblank_put only in case that drm_vblank_get was
  494. * called.
  495. */
  496. if (atomic_read(&drm_dev->vblank_refcount[crtc]) > 0)
  497. drm_vblank_put(drm_dev, crtc);
  498. /*
  499. * don't off vblank if vblank_disable_allowed is 1,
  500. * because vblank would be off by timer handler.
  501. */
  502. if (!drm_dev->vblank_disable_allowed)
  503. drm_vblank_off(drm_dev, crtc);
  504. }
  505. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  506. }
  507. static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
  508. {
  509. struct fimd_context *ctx = (struct fimd_context *)dev_id;
  510. struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
  511. struct drm_device *drm_dev = subdrv->drm_dev;
  512. struct exynos_drm_manager *manager = subdrv->manager;
  513. u32 val;
  514. val = readl(ctx->regs + VIDINTCON1);
  515. if (val & VIDINTCON1_INT_FRAME)
  516. /* VSYNC interrupt */
  517. writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
  518. /* check the crtc is detached already from encoder */
  519. if (manager->pipe < 0)
  520. goto out;
  521. drm_handle_vblank(drm_dev, manager->pipe);
  522. fimd_finish_pageflip(drm_dev, manager->pipe);
  523. out:
  524. return IRQ_HANDLED;
  525. }
  526. static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
  527. {
  528. DRM_DEBUG_KMS("%s\n", __FILE__);
  529. /*
  530. * enable drm irq mode.
  531. * - with irq_enabled = 1, we can use the vblank feature.
  532. *
  533. * P.S. note that we wouldn't use drm irq handler but
  534. * just specific driver own one instead because
  535. * drm framework supports only one irq handler.
  536. */
  537. drm_dev->irq_enabled = 1;
  538. /*
  539. * with vblank_disable_allowed = 1, vblank interrupt will be disabled
  540. * by drm timer once a current process gives up ownership of
  541. * vblank event.(after drm_vblank_put function is called)
  542. */
  543. drm_dev->vblank_disable_allowed = 1;
  544. return 0;
  545. }
  546. static void fimd_subdrv_remove(struct drm_device *drm_dev)
  547. {
  548. DRM_DEBUG_KMS("%s\n", __FILE__);
  549. /* TODO. */
  550. }
  551. static int fimd_calc_clkdiv(struct fimd_context *ctx,
  552. struct fb_videomode *timing)
  553. {
  554. unsigned long clk = clk_get_rate(ctx->lcd_clk);
  555. u32 retrace;
  556. u32 clkdiv;
  557. u32 best_framerate = 0;
  558. u32 framerate;
  559. DRM_DEBUG_KMS("%s\n", __FILE__);
  560. retrace = timing->left_margin + timing->hsync_len +
  561. timing->right_margin + timing->xres;
  562. retrace *= timing->upper_margin + timing->vsync_len +
  563. timing->lower_margin + timing->yres;
  564. /* default framerate is 60Hz */
  565. if (!timing->refresh)
  566. timing->refresh = 60;
  567. clk /= retrace;
  568. for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
  569. int tmp;
  570. /* get best framerate */
  571. framerate = clk / clkdiv;
  572. tmp = timing->refresh - framerate;
  573. if (tmp < 0) {
  574. best_framerate = framerate;
  575. continue;
  576. } else {
  577. if (!best_framerate)
  578. best_framerate = framerate;
  579. else if (tmp < (best_framerate - framerate))
  580. best_framerate = framerate;
  581. break;
  582. }
  583. }
  584. return clkdiv;
  585. }
  586. static void fimd_clear_win(struct fimd_context *ctx, int win)
  587. {
  588. u32 val;
  589. DRM_DEBUG_KMS("%s\n", __FILE__);
  590. writel(0, ctx->regs + WINCON(win));
  591. writel(0, ctx->regs + VIDOSD_A(win));
  592. writel(0, ctx->regs + VIDOSD_B(win));
  593. writel(0, ctx->regs + VIDOSD_C(win));
  594. if (win == 1 || win == 2)
  595. writel(0, ctx->regs + VIDOSD_D(win));
  596. val = readl(ctx->regs + SHADOWCON);
  597. val &= ~SHADOWCON_WINx_PROTECT(win);
  598. writel(val, ctx->regs + SHADOWCON);
  599. }
  600. static int fimd_power_on(struct fimd_context *ctx, bool enable)
  601. {
  602. struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
  603. struct device *dev = subdrv->dev;
  604. DRM_DEBUG_KMS("%s\n", __FILE__);
  605. if (enable != false && enable != true)
  606. return -EINVAL;
  607. if (enable) {
  608. int ret;
  609. ret = clk_enable(ctx->bus_clk);
  610. if (ret < 0)
  611. return ret;
  612. ret = clk_enable(ctx->lcd_clk);
  613. if (ret < 0) {
  614. clk_disable(ctx->bus_clk);
  615. return ret;
  616. }
  617. ctx->suspended = false;
  618. /* if vblank was enabled status, enable it again. */
  619. if (test_and_clear_bit(0, &ctx->irq_flags))
  620. fimd_enable_vblank(dev);
  621. fimd_apply(dev);
  622. } else {
  623. clk_disable(ctx->lcd_clk);
  624. clk_disable(ctx->bus_clk);
  625. ctx->suspended = true;
  626. }
  627. return 0;
  628. }
  629. static int __devinit fimd_probe(struct platform_device *pdev)
  630. {
  631. struct device *dev = &pdev->dev;
  632. struct fimd_context *ctx;
  633. struct exynos_drm_subdrv *subdrv;
  634. struct exynos_drm_fimd_pdata *pdata;
  635. struct exynos_drm_panel_info *panel;
  636. struct resource *res;
  637. int win;
  638. int ret = -EINVAL;
  639. DRM_DEBUG_KMS("%s\n", __FILE__);
  640. pdata = pdev->dev.platform_data;
  641. if (!pdata) {
  642. dev_err(dev, "no platform data specified\n");
  643. return -EINVAL;
  644. }
  645. panel = &pdata->panel;
  646. if (!panel) {
  647. dev_err(dev, "panel is null.\n");
  648. return -EINVAL;
  649. }
  650. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  651. if (!ctx)
  652. return -ENOMEM;
  653. ctx->bus_clk = clk_get(dev, "fimd");
  654. if (IS_ERR(ctx->bus_clk)) {
  655. dev_err(dev, "failed to get bus clock\n");
  656. ret = PTR_ERR(ctx->bus_clk);
  657. goto err_clk_get;
  658. }
  659. ctx->lcd_clk = clk_get(dev, "sclk_fimd");
  660. if (IS_ERR(ctx->lcd_clk)) {
  661. dev_err(dev, "failed to get lcd clock\n");
  662. ret = PTR_ERR(ctx->lcd_clk);
  663. goto err_bus_clk;
  664. }
  665. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  666. if (!res) {
  667. dev_err(dev, "failed to find registers\n");
  668. ret = -ENOENT;
  669. goto err_clk;
  670. }
  671. ctx->regs_res = request_mem_region(res->start, resource_size(res),
  672. dev_name(dev));
  673. if (!ctx->regs_res) {
  674. dev_err(dev, "failed to claim register region\n");
  675. ret = -ENOENT;
  676. goto err_clk;
  677. }
  678. ctx->regs = ioremap(res->start, resource_size(res));
  679. if (!ctx->regs) {
  680. dev_err(dev, "failed to map registers\n");
  681. ret = -ENXIO;
  682. goto err_req_region_io;
  683. }
  684. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  685. if (!res) {
  686. dev_err(dev, "irq request failed.\n");
  687. goto err_req_region_irq;
  688. }
  689. ctx->irq = res->start;
  690. ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
  691. if (ret < 0) {
  692. dev_err(dev, "irq request failed.\n");
  693. goto err_req_irq;
  694. }
  695. ctx->vidcon0 = pdata->vidcon0;
  696. ctx->vidcon1 = pdata->vidcon1;
  697. ctx->default_win = pdata->default_win;
  698. ctx->panel = panel;
  699. subdrv = &ctx->subdrv;
  700. subdrv->dev = dev;
  701. subdrv->manager = &fimd_manager;
  702. subdrv->probe = fimd_subdrv_probe;
  703. subdrv->remove = fimd_subdrv_remove;
  704. mutex_init(&ctx->lock);
  705. platform_set_drvdata(pdev, ctx);
  706. pm_runtime_enable(dev);
  707. pm_runtime_get_sync(dev);
  708. ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
  709. panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
  710. DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
  711. panel->timing.pixclock, ctx->clkdiv);
  712. for (win = 0; win < WINDOWS_NR; win++)
  713. fimd_clear_win(ctx, win);
  714. exynos_drm_subdrv_register(subdrv);
  715. return 0;
  716. err_req_irq:
  717. err_req_region_irq:
  718. iounmap(ctx->regs);
  719. err_req_region_io:
  720. release_resource(ctx->regs_res);
  721. kfree(ctx->regs_res);
  722. err_clk:
  723. clk_disable(ctx->lcd_clk);
  724. clk_put(ctx->lcd_clk);
  725. err_bus_clk:
  726. clk_disable(ctx->bus_clk);
  727. clk_put(ctx->bus_clk);
  728. err_clk_get:
  729. kfree(ctx);
  730. return ret;
  731. }
  732. static int __devexit fimd_remove(struct platform_device *pdev)
  733. {
  734. struct device *dev = &pdev->dev;
  735. struct fimd_context *ctx = platform_get_drvdata(pdev);
  736. DRM_DEBUG_KMS("%s\n", __FILE__);
  737. exynos_drm_subdrv_unregister(&ctx->subdrv);
  738. if (ctx->suspended)
  739. goto out;
  740. clk_disable(ctx->lcd_clk);
  741. clk_disable(ctx->bus_clk);
  742. pm_runtime_set_suspended(dev);
  743. pm_runtime_put_sync(dev);
  744. out:
  745. pm_runtime_disable(dev);
  746. clk_put(ctx->lcd_clk);
  747. clk_put(ctx->bus_clk);
  748. iounmap(ctx->regs);
  749. release_resource(ctx->regs_res);
  750. kfree(ctx->regs_res);
  751. free_irq(ctx->irq, ctx);
  752. kfree(ctx);
  753. return 0;
  754. }
  755. #ifdef CONFIG_PM_SLEEP
  756. static int fimd_suspend(struct device *dev)
  757. {
  758. struct fimd_context *ctx = get_fimd_context(dev);
  759. if (pm_runtime_suspended(dev))
  760. return 0;
  761. /*
  762. * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
  763. * called here, an error would be returned by that interface
  764. * because the usage_count of pm runtime is more than 1.
  765. */
  766. return fimd_power_on(ctx, false);
  767. }
  768. static int fimd_resume(struct device *dev)
  769. {
  770. struct fimd_context *ctx = get_fimd_context(dev);
  771. /*
  772. * if entered to sleep when lcd panel was on, the usage_count
  773. * of pm runtime would still be 1 so in this case, fimd driver
  774. * should be on directly not drawing on pm runtime interface.
  775. */
  776. if (!pm_runtime_suspended(dev))
  777. return fimd_power_on(ctx, true);
  778. return 0;
  779. }
  780. #endif
  781. #ifdef CONFIG_PM_RUNTIME
  782. static int fimd_runtime_suspend(struct device *dev)
  783. {
  784. struct fimd_context *ctx = get_fimd_context(dev);
  785. DRM_DEBUG_KMS("%s\n", __FILE__);
  786. return fimd_power_on(ctx, false);
  787. }
  788. static int fimd_runtime_resume(struct device *dev)
  789. {
  790. struct fimd_context *ctx = get_fimd_context(dev);
  791. DRM_DEBUG_KMS("%s\n", __FILE__);
  792. return fimd_power_on(ctx, true);
  793. }
  794. #endif
  795. static const struct dev_pm_ops fimd_pm_ops = {
  796. SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
  797. SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
  798. };
  799. struct platform_driver fimd_driver = {
  800. .probe = fimd_probe,
  801. .remove = __devexit_p(fimd_remove),
  802. .driver = {
  803. .name = "exynos4-fb",
  804. .owner = THIS_MODULE,
  805. .pm = &fimd_pm_ops,
  806. },
  807. };