base.S 4.1 KB

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  1. /*
  2. * arch/s390/kernel/base.S
  3. *
  4. * Copyright IBM Corp. 2006,2007
  5. * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  6. * Michael Holzheu <holzheu@de.ibm.com>
  7. */
  8. #include <linux/linkage.h>
  9. #include <asm/asm-offsets.h>
  10. #include <asm/ptrace.h>
  11. #ifdef CONFIG_64BIT
  12. ENTRY(s390_base_mcck_handler)
  13. basr %r13,0
  14. 0: lg %r15,__LC_PANIC_STACK # load panic stack
  15. aghi %r15,-STACK_FRAME_OVERHEAD
  16. larl %r1,s390_base_mcck_handler_fn
  17. lg %r1,0(%r1)
  18. ltgr %r1,%r1
  19. jz 1f
  20. basr %r14,%r1
  21. 1: la %r1,4095
  22. lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
  23. lpswe __LC_MCK_OLD_PSW
  24. .section .bss
  25. .align 8
  26. .globl s390_base_mcck_handler_fn
  27. s390_base_mcck_handler_fn:
  28. .quad 0
  29. .previous
  30. ENTRY(s390_base_ext_handler)
  31. stmg %r0,%r15,__LC_SAVE_AREA_ASYNC
  32. basr %r13,0
  33. 0: aghi %r15,-STACK_FRAME_OVERHEAD
  34. larl %r1,s390_base_ext_handler_fn
  35. lg %r1,0(%r1)
  36. ltgr %r1,%r1
  37. jz 1f
  38. basr %r14,%r1
  39. 1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
  40. ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
  41. lpswe __LC_EXT_OLD_PSW
  42. .section .bss
  43. .align 8
  44. .globl s390_base_ext_handler_fn
  45. s390_base_ext_handler_fn:
  46. .quad 0
  47. .previous
  48. ENTRY(s390_base_pgm_handler)
  49. stmg %r0,%r15,__LC_SAVE_AREA_SYNC
  50. basr %r13,0
  51. 0: aghi %r15,-STACK_FRAME_OVERHEAD
  52. larl %r1,s390_base_pgm_handler_fn
  53. lg %r1,0(%r1)
  54. ltgr %r1,%r1
  55. jz 1f
  56. basr %r14,%r1
  57. lmg %r0,%r15,__LC_SAVE_AREA_SYNC
  58. lpswe __LC_PGM_OLD_PSW
  59. 1: lpswe disabled_wait_psw-0b(%r13)
  60. .align 8
  61. disabled_wait_psw:
  62. .quad 0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler
  63. .section .bss
  64. .align 8
  65. .globl s390_base_pgm_handler_fn
  66. s390_base_pgm_handler_fn:
  67. .quad 0
  68. .previous
  69. #
  70. # Calls diag 308 subcode 1 and continues execution
  71. #
  72. # The following conditions must be ensured before calling this function:
  73. # * Prefix register = 0
  74. # * Lowcore protection is disabled
  75. #
  76. ENTRY(diag308_reset)
  77. larl %r4,.Lctlregs # Save control registers
  78. stctg %c0,%c15,0(%r4)
  79. larl %r4,.Lfpctl # Floating point control register
  80. stfpc 0(%r4)
  81. larl %r4,.Lcontinue_psw # Save PSW flags
  82. epsw %r2,%r3
  83. stm %r2,%r3,0(%r4)
  84. larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0
  85. lghi %r3,0
  86. lg %r4,0(%r4) # Save PSW
  87. sturg %r4,%r3 # Use sturg, because of large pages
  88. lghi %r1,1
  89. diag %r1,%r1,0x308
  90. .Lrestart_part2:
  91. lhi %r0,0 # Load r0 with zero
  92. lhi %r1,2 # Use mode 2 = ESAME (dump)
  93. sigp %r1,%r0,0x12 # Switch to ESAME mode
  94. sam64 # Switch to 64 bit addressing mode
  95. larl %r4,.Lctlregs # Restore control registers
  96. lctlg %c0,%c15,0(%r4)
  97. larl %r4,.Lfpctl # Restore floating point ctl register
  98. lfpc 0(%r4)
  99. larl %r4,.Lcontinue_psw # Restore PSW flags
  100. lpswe 0(%r4)
  101. .Lcontinue:
  102. br %r14
  103. .align 16
  104. .Lrestart_psw:
  105. .long 0x00080000,0x80000000 + .Lrestart_part2
  106. .section .data..nosave,"aw",@progbits
  107. .align 8
  108. .Lcontinue_psw:
  109. .quad 0,.Lcontinue
  110. .previous
  111. .section .bss
  112. .align 8
  113. .Lctlregs:
  114. .rept 16
  115. .quad 0
  116. .endr
  117. .Lfpctl:
  118. .long 0
  119. .previous
  120. #else /* CONFIG_64BIT */
  121. ENTRY(s390_base_mcck_handler)
  122. basr %r13,0
  123. 0: l %r15,__LC_PANIC_STACK # load panic stack
  124. ahi %r15,-STACK_FRAME_OVERHEAD
  125. l %r1,2f-0b(%r13)
  126. l %r1,0(%r1)
  127. ltr %r1,%r1
  128. jz 1f
  129. basr %r14,%r1
  130. 1: lm %r0,%r15,__LC_GPREGS_SAVE_AREA
  131. lpsw __LC_MCK_OLD_PSW
  132. 2: .long s390_base_mcck_handler_fn
  133. .section .bss
  134. .align 4
  135. .globl s390_base_mcck_handler_fn
  136. s390_base_mcck_handler_fn:
  137. .long 0
  138. .previous
  139. ENTRY(s390_base_ext_handler)
  140. stm %r0,%r15,__LC_SAVE_AREA_ASYNC
  141. basr %r13,0
  142. 0: ahi %r15,-STACK_FRAME_OVERHEAD
  143. l %r1,2f-0b(%r13)
  144. l %r1,0(%r1)
  145. ltr %r1,%r1
  146. jz 1f
  147. basr %r14,%r1
  148. 1: lm %r0,%r15,__LC_SAVE_AREA_ASYNC
  149. ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
  150. lpsw __LC_EXT_OLD_PSW
  151. 2: .long s390_base_ext_handler_fn
  152. .section .bss
  153. .align 4
  154. .globl s390_base_ext_handler_fn
  155. s390_base_ext_handler_fn:
  156. .long 0
  157. .previous
  158. ENTRY(s390_base_pgm_handler)
  159. stm %r0,%r15,__LC_SAVE_AREA_SYNC
  160. basr %r13,0
  161. 0: ahi %r15,-STACK_FRAME_OVERHEAD
  162. l %r1,2f-0b(%r13)
  163. l %r1,0(%r1)
  164. ltr %r1,%r1
  165. jz 1f
  166. basr %r14,%r1
  167. lm %r0,%r15,__LC_SAVE_AREA_SYNC
  168. lpsw __LC_PGM_OLD_PSW
  169. 1: lpsw disabled_wait_psw-0b(%r13)
  170. 2: .long s390_base_pgm_handler_fn
  171. disabled_wait_psw:
  172. .align 8
  173. .long 0x000a0000,0x00000000 + s390_base_pgm_handler
  174. .section .bss
  175. .align 4
  176. .globl s390_base_pgm_handler_fn
  177. s390_base_pgm_handler_fn:
  178. .long 0
  179. .previous
  180. #endif /* CONFIG_64BIT */