ezkit.c 30 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/mtd/mtd.h>
  11. #include <linux/mtd/partitions.h>
  12. #include <linux/mtd/physmap.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #include <linux/irq.h>
  16. #include <linux/i2c.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/usb/musb.h>
  19. #include <asm/bfin6xx_spi.h>
  20. #include <asm/dma.h>
  21. #include <asm/gpio.h>
  22. #include <asm/nand.h>
  23. #include <asm/dpmc.h>
  24. #include <asm/portmux.h>
  25. #include <asm/bfin_sdh.h>
  26. #include <linux/input.h>
  27. #include <linux/spi/ad7877.h>
  28. /*
  29. * Name the Board for the /proc/cpuinfo
  30. */
  31. const char bfin_board_name[] = "ADI BF609-EZKIT";
  32. /*
  33. * Driver needs to know address, irq and flag pin.
  34. */
  35. #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  36. #include <linux/usb/isp1760.h>
  37. static struct resource bfin_isp1760_resources[] = {
  38. [0] = {
  39. .start = 0x2C0C0000,
  40. .end = 0x2C0C0000 + 0xfffff,
  41. .flags = IORESOURCE_MEM,
  42. },
  43. [1] = {
  44. .start = IRQ_PG7,
  45. .end = IRQ_PG7,
  46. .flags = IORESOURCE_IRQ,
  47. },
  48. };
  49. static struct isp1760_platform_data isp1760_priv = {
  50. .is_isp1761 = 0,
  51. .bus_width_16 = 1,
  52. .port1_otg = 0,
  53. .analog_oc = 0,
  54. .dack_polarity_high = 0,
  55. .dreq_polarity_high = 0,
  56. };
  57. static struct platform_device bfin_isp1760_device = {
  58. .name = "isp1760",
  59. .id = 0,
  60. .dev = {
  61. .platform_data = &isp1760_priv,
  62. },
  63. .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
  64. .resource = bfin_isp1760_resources,
  65. };
  66. #endif
  67. #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
  68. #include <asm/bfin_rotary.h>
  69. static struct bfin_rotary_platform_data bfin_rotary_data = {
  70. /*.rotary_up_key = KEY_UP,*/
  71. /*.rotary_down_key = KEY_DOWN,*/
  72. .rotary_rel_code = REL_WHEEL,
  73. .rotary_button_key = KEY_ENTER,
  74. .debounce = 10, /* 0..17 */
  75. .mode = ROT_QUAD_ENC | ROT_DEBE,
  76. };
  77. static struct resource bfin_rotary_resources[] = {
  78. {
  79. .start = IRQ_CNT,
  80. .end = IRQ_CNT,
  81. .flags = IORESOURCE_IRQ,
  82. },
  83. };
  84. static struct platform_device bfin_rotary_device = {
  85. .name = "bfin-rotary",
  86. .id = -1,
  87. .num_resources = ARRAY_SIZE(bfin_rotary_resources),
  88. .resource = bfin_rotary_resources,
  89. .dev = {
  90. .platform_data = &bfin_rotary_data,
  91. },
  92. };
  93. #endif
  94. #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
  95. #include <linux/stmmac.h>
  96. static unsigned short pins[] = P_RMII0;
  97. static struct stmmac_mdio_bus_data phy_private_data = {
  98. .bus_id = 0,
  99. .phy_mask = 1,
  100. };
  101. static struct plat_stmmacenet_data eth_private_data = {
  102. .bus_id = 0,
  103. .enh_desc = 1,
  104. .phy_addr = 1,
  105. .mdio_bus_data = &phy_private_data,
  106. };
  107. static struct platform_device bfin_eth_device = {
  108. .name = "stmmaceth",
  109. .id = 0,
  110. .num_resources = 2,
  111. .resource = (struct resource[]) {
  112. {
  113. .start = EMAC0_MACCFG,
  114. .end = EMAC0_MACCFG + 0x1274,
  115. .flags = IORESOURCE_MEM,
  116. },
  117. {
  118. .name = "macirq",
  119. .start = IRQ_EMAC0_STAT,
  120. .end = IRQ_EMAC0_STAT,
  121. .flags = IORESOURCE_IRQ,
  122. },
  123. },
  124. .dev = {
  125. .power.can_wakeup = 1,
  126. .platform_data = &eth_private_data,
  127. }
  128. };
  129. #endif
  130. #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
  131. #include <linux/input/adxl34x.h>
  132. static const struct adxl34x_platform_data adxl34x_info = {
  133. .x_axis_offset = 0,
  134. .y_axis_offset = 0,
  135. .z_axis_offset = 0,
  136. .tap_threshold = 0x31,
  137. .tap_duration = 0x10,
  138. .tap_latency = 0x60,
  139. .tap_window = 0xF0,
  140. .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
  141. .act_axis_control = 0xFF,
  142. .activity_threshold = 5,
  143. .inactivity_threshold = 3,
  144. .inactivity_time = 4,
  145. .free_fall_threshold = 0x7,
  146. .free_fall_time = 0x20,
  147. .data_rate = 0x8,
  148. .data_range = ADXL_FULL_RES,
  149. .ev_type = EV_ABS,
  150. .ev_code_x = ABS_X, /* EV_REL */
  151. .ev_code_y = ABS_Y, /* EV_REL */
  152. .ev_code_z = ABS_Z, /* EV_REL */
  153. .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
  154. /* .ev_code_ff = KEY_F,*/ /* EV_KEY */
  155. /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
  156. .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
  157. .fifo_mode = ADXL_FIFO_STREAM,
  158. .orientation_enable = ADXL_EN_ORIENTATION_3D,
  159. .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
  160. .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
  161. /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
  162. .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
  163. };
  164. #endif
  165. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  166. static struct platform_device rtc_device = {
  167. .name = "rtc-bfin",
  168. .id = -1,
  169. };
  170. #endif
  171. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  172. #ifdef CONFIG_SERIAL_BFIN_UART0
  173. static struct resource bfin_uart0_resources[] = {
  174. {
  175. .start = UART0_REVID,
  176. .end = UART0_RXDIV+4,
  177. .flags = IORESOURCE_MEM,
  178. },
  179. {
  180. .start = IRQ_UART0_TX,
  181. .end = IRQ_UART0_TX,
  182. .flags = IORESOURCE_IRQ,
  183. },
  184. {
  185. .start = IRQ_UART0_RX,
  186. .end = IRQ_UART0_RX,
  187. .flags = IORESOURCE_IRQ,
  188. },
  189. {
  190. .start = IRQ_UART0_STAT,
  191. .end = IRQ_UART0_STAT,
  192. .flags = IORESOURCE_IRQ,
  193. },
  194. {
  195. .start = CH_UART0_TX,
  196. .end = CH_UART0_TX,
  197. .flags = IORESOURCE_DMA,
  198. },
  199. {
  200. .start = CH_UART0_RX,
  201. .end = CH_UART0_RX,
  202. .flags = IORESOURCE_DMA,
  203. },
  204. #ifdef CONFIG_BFIN_UART0_CTSRTS
  205. { /* CTS pin -- 0 means not supported */
  206. .start = GPIO_PD10,
  207. .end = GPIO_PD10,
  208. .flags = IORESOURCE_IO,
  209. },
  210. { /* RTS pin -- 0 means not supported */
  211. .start = GPIO_PD9,
  212. .end = GPIO_PD9,
  213. .flags = IORESOURCE_IO,
  214. },
  215. #endif
  216. };
  217. static unsigned short bfin_uart0_peripherals[] = {
  218. P_UART0_TX, P_UART0_RX,
  219. #ifdef CONFIG_BFIN_UART0_CTSRTS
  220. P_UART0_RTS, P_UART0_CTS,
  221. #endif
  222. 0
  223. };
  224. static struct platform_device bfin_uart0_device = {
  225. .name = "bfin-uart",
  226. .id = 0,
  227. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  228. .resource = bfin_uart0_resources,
  229. .dev = {
  230. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  231. },
  232. };
  233. #endif
  234. #ifdef CONFIG_SERIAL_BFIN_UART1
  235. static struct resource bfin_uart1_resources[] = {
  236. {
  237. .start = UART1_REVID,
  238. .end = UART1_RXDIV+4,
  239. .flags = IORESOURCE_MEM,
  240. },
  241. {
  242. .start = IRQ_UART1_TX,
  243. .end = IRQ_UART1_TX,
  244. .flags = IORESOURCE_IRQ,
  245. },
  246. {
  247. .start = IRQ_UART1_RX,
  248. .end = IRQ_UART1_RX,
  249. .flags = IORESOURCE_IRQ,
  250. },
  251. {
  252. .start = IRQ_UART1_STAT,
  253. .end = IRQ_UART1_STAT,
  254. .flags = IORESOURCE_IRQ,
  255. },
  256. {
  257. .start = CH_UART1_TX,
  258. .end = CH_UART1_TX,
  259. .flags = IORESOURCE_DMA,
  260. },
  261. {
  262. .start = CH_UART1_RX,
  263. .end = CH_UART1_RX,
  264. .flags = IORESOURCE_DMA,
  265. },
  266. #ifdef CONFIG_BFIN_UART1_CTSRTS
  267. { /* CTS pin -- 0 means not supported */
  268. .start = GPIO_PG13,
  269. .end = GPIO_PG13,
  270. .flags = IORESOURCE_IO,
  271. },
  272. { /* RTS pin -- 0 means not supported */
  273. .start = GPIO_PG10,
  274. .end = GPIO_PG10,
  275. .flags = IORESOURCE_IO,
  276. },
  277. #endif
  278. };
  279. static unsigned short bfin_uart1_peripherals[] = {
  280. P_UART1_TX, P_UART1_RX,
  281. #ifdef CONFIG_BFIN_UART1_CTSRTS
  282. P_UART1_RTS, P_UART1_CTS,
  283. #endif
  284. 0
  285. };
  286. static struct platform_device bfin_uart1_device = {
  287. .name = "bfin-uart",
  288. .id = 1,
  289. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  290. .resource = bfin_uart1_resources,
  291. .dev = {
  292. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  293. },
  294. };
  295. #endif
  296. #endif
  297. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  298. #ifdef CONFIG_BFIN_SIR0
  299. static struct resource bfin_sir0_resources[] = {
  300. {
  301. .start = 0xFFC00400,
  302. .end = 0xFFC004FF,
  303. .flags = IORESOURCE_MEM,
  304. },
  305. {
  306. .start = IRQ_UART0_TX,
  307. .end = IRQ_UART0_TX+1,
  308. .flags = IORESOURCE_IRQ,
  309. },
  310. {
  311. .start = CH_UART0_TX,
  312. .end = CH_UART0_TX+1,
  313. .flags = IORESOURCE_DMA,
  314. },
  315. };
  316. static struct platform_device bfin_sir0_device = {
  317. .name = "bfin_sir",
  318. .id = 0,
  319. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  320. .resource = bfin_sir0_resources,
  321. };
  322. #endif
  323. #ifdef CONFIG_BFIN_SIR1
  324. static struct resource bfin_sir1_resources[] = {
  325. {
  326. .start = 0xFFC02000,
  327. .end = 0xFFC020FF,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. {
  331. .start = IRQ_UART1_TX,
  332. .end = IRQ_UART1_TX+1,
  333. .flags = IORESOURCE_IRQ,
  334. },
  335. {
  336. .start = CH_UART1_TX,
  337. .end = CH_UART1_TX+1,
  338. .flags = IORESOURCE_DMA,
  339. },
  340. };
  341. static struct platform_device bfin_sir1_device = {
  342. .name = "bfin_sir",
  343. .id = 1,
  344. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  345. .resource = bfin_sir1_resources,
  346. };
  347. #endif
  348. #endif
  349. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  350. static struct resource musb_resources[] = {
  351. [0] = {
  352. .start = 0xFFCC1000,
  353. .end = 0xFFCC1398,
  354. .flags = IORESOURCE_MEM,
  355. },
  356. [1] = { /* general IRQ */
  357. .start = IRQ_USB_STAT,
  358. .end = IRQ_USB_STAT,
  359. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  360. .name = "mc"
  361. },
  362. [2] = { /* DMA IRQ */
  363. .start = IRQ_USB_DMA,
  364. .end = IRQ_USB_DMA,
  365. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  366. .name = "dma"
  367. },
  368. };
  369. static struct musb_hdrc_config musb_config = {
  370. .multipoint = 1,
  371. .dyn_fifo = 0,
  372. .dma = 1,
  373. .num_eps = 16,
  374. .dma_channels = 8,
  375. .clkin = 48, /* musb CLKIN in MHZ */
  376. };
  377. static struct musb_hdrc_platform_data musb_plat = {
  378. #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
  379. .mode = MUSB_OTG,
  380. #elif defined(CONFIG_USB_MUSB_HDRC)
  381. .mode = MUSB_HOST,
  382. #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  383. .mode = MUSB_PERIPHERAL,
  384. #endif
  385. .config = &musb_config,
  386. };
  387. static u64 musb_dmamask = ~(u32)0;
  388. static struct platform_device musb_device = {
  389. .name = "musb-blackfin",
  390. .id = 0,
  391. .dev = {
  392. .dma_mask = &musb_dmamask,
  393. .coherent_dma_mask = 0xffffffff,
  394. .platform_data = &musb_plat,
  395. },
  396. .num_resources = ARRAY_SIZE(musb_resources),
  397. .resource = musb_resources,
  398. };
  399. #endif
  400. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  401. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  402. static struct resource bfin_sport0_uart_resources[] = {
  403. {
  404. .start = SPORT0_TCR1,
  405. .end = SPORT0_MRCS3+4,
  406. .flags = IORESOURCE_MEM,
  407. },
  408. {
  409. .start = IRQ_SPORT0_RX,
  410. .end = IRQ_SPORT0_RX+1,
  411. .flags = IORESOURCE_IRQ,
  412. },
  413. {
  414. .start = IRQ_SPORT0_ERROR,
  415. .end = IRQ_SPORT0_ERROR,
  416. .flags = IORESOURCE_IRQ,
  417. },
  418. };
  419. static unsigned short bfin_sport0_peripherals[] = {
  420. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  421. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  422. };
  423. static struct platform_device bfin_sport0_uart_device = {
  424. .name = "bfin-sport-uart",
  425. .id = 0,
  426. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  427. .resource = bfin_sport0_uart_resources,
  428. .dev = {
  429. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  430. },
  431. };
  432. #endif
  433. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  434. static struct resource bfin_sport1_uart_resources[] = {
  435. {
  436. .start = SPORT1_TCR1,
  437. .end = SPORT1_MRCS3+4,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. {
  441. .start = IRQ_SPORT1_RX,
  442. .end = IRQ_SPORT1_RX+1,
  443. .flags = IORESOURCE_IRQ,
  444. },
  445. {
  446. .start = IRQ_SPORT1_ERROR,
  447. .end = IRQ_SPORT1_ERROR,
  448. .flags = IORESOURCE_IRQ,
  449. },
  450. };
  451. static unsigned short bfin_sport1_peripherals[] = {
  452. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  453. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  454. };
  455. static struct platform_device bfin_sport1_uart_device = {
  456. .name = "bfin-sport-uart",
  457. .id = 1,
  458. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  459. .resource = bfin_sport1_uart_resources,
  460. .dev = {
  461. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  462. },
  463. };
  464. #endif
  465. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  466. static struct resource bfin_sport2_uart_resources[] = {
  467. {
  468. .start = SPORT2_TCR1,
  469. .end = SPORT2_MRCS3+4,
  470. .flags = IORESOURCE_MEM,
  471. },
  472. {
  473. .start = IRQ_SPORT2_RX,
  474. .end = IRQ_SPORT2_RX+1,
  475. .flags = IORESOURCE_IRQ,
  476. },
  477. {
  478. .start = IRQ_SPORT2_ERROR,
  479. .end = IRQ_SPORT2_ERROR,
  480. .flags = IORESOURCE_IRQ,
  481. },
  482. };
  483. static unsigned short bfin_sport2_peripherals[] = {
  484. P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
  485. P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
  486. };
  487. static struct platform_device bfin_sport2_uart_device = {
  488. .name = "bfin-sport-uart",
  489. .id = 2,
  490. .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
  491. .resource = bfin_sport2_uart_resources,
  492. .dev = {
  493. .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
  494. },
  495. };
  496. #endif
  497. #endif
  498. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  499. static unsigned short bfin_can0_peripherals[] = {
  500. P_CAN0_RX, P_CAN0_TX, 0
  501. };
  502. static struct resource bfin_can0_resources[] = {
  503. {
  504. .start = 0xFFC00A00,
  505. .end = 0xFFC00FFF,
  506. .flags = IORESOURCE_MEM,
  507. },
  508. {
  509. .start = IRQ_CAN0_RX,
  510. .end = IRQ_CAN0_RX,
  511. .flags = IORESOURCE_IRQ,
  512. },
  513. {
  514. .start = IRQ_CAN0_TX,
  515. .end = IRQ_CAN0_TX,
  516. .flags = IORESOURCE_IRQ,
  517. },
  518. {
  519. .start = IRQ_CAN0_STAT,
  520. .end = IRQ_CAN0_STAT,
  521. .flags = IORESOURCE_IRQ,
  522. },
  523. };
  524. static struct platform_device bfin_can0_device = {
  525. .name = "bfin_can",
  526. .id = 0,
  527. .num_resources = ARRAY_SIZE(bfin_can0_resources),
  528. .resource = bfin_can0_resources,
  529. .dev = {
  530. .platform_data = &bfin_can0_peripherals, /* Passed to driver */
  531. },
  532. };
  533. #endif
  534. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  535. static struct mtd_partition partition_info[] = {
  536. {
  537. .name = "bootloader(nand)",
  538. .offset = 0,
  539. .size = 0x80000,
  540. }, {
  541. .name = "linux kernel(nand)",
  542. .offset = MTDPART_OFS_APPEND,
  543. .size = 4 * 1024 * 1024,
  544. },
  545. {
  546. .name = "file system(nand)",
  547. .offset = MTDPART_OFS_APPEND,
  548. .size = MTDPART_SIZ_FULL,
  549. },
  550. };
  551. static struct bf5xx_nand_platform bfin_nand_platform = {
  552. .data_width = NFC_NWIDTH_8,
  553. .partitions = partition_info,
  554. .nr_partitions = ARRAY_SIZE(partition_info),
  555. .rd_dly = 3,
  556. .wr_dly = 3,
  557. };
  558. static struct resource bfin_nand_resources[] = {
  559. {
  560. .start = 0xFFC03B00,
  561. .end = 0xFFC03B4F,
  562. .flags = IORESOURCE_MEM,
  563. },
  564. {
  565. .start = CH_NFC,
  566. .end = CH_NFC,
  567. .flags = IORESOURCE_IRQ,
  568. },
  569. };
  570. static struct platform_device bfin_nand_device = {
  571. .name = "bfin-nand",
  572. .id = 0,
  573. .num_resources = ARRAY_SIZE(bfin_nand_resources),
  574. .resource = bfin_nand_resources,
  575. .dev = {
  576. .platform_data = &bfin_nand_platform,
  577. },
  578. };
  579. #endif
  580. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  581. static struct bfin_sd_host bfin_sdh_data = {
  582. .dma_chan = CH_RSI,
  583. .irq_int0 = IRQ_RSI_INT0,
  584. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  585. };
  586. static struct platform_device bfin_sdh_device = {
  587. .name = "bfin-sdh",
  588. .id = 0,
  589. .dev = {
  590. .platform_data = &bfin_sdh_data,
  591. },
  592. };
  593. #endif
  594. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  595. static struct mtd_partition ezkit_partitions[] = {
  596. {
  597. .name = "bootloader(nor)",
  598. .size = 0x80000,
  599. .offset = 0,
  600. }, {
  601. .name = "linux kernel(nor)",
  602. .size = 0x400000,
  603. .offset = MTDPART_OFS_APPEND,
  604. }, {
  605. .name = "file system(nor)",
  606. .size = 0x1000000 - 0x80000 - 0x400000,
  607. .offset = MTDPART_OFS_APPEND,
  608. },
  609. };
  610. int bf609_nor_flash_init(struct platform_device *dev)
  611. {
  612. #define CONFIG_SMC_GCTL_VAL 0x00000010
  613. const unsigned short pins[] = {
  614. P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
  615. P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
  616. P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
  617. };
  618. peripheral_request_list(pins, "smc0");
  619. bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
  620. bfin_write32(SMC_B0CTL, 0x01002011);
  621. bfin_write32(SMC_B0TIM, 0x08170977);
  622. bfin_write32(SMC_B0ETIM, 0x00092231);
  623. return 0;
  624. }
  625. static struct physmap_flash_data ezkit_flash_data = {
  626. .width = 2,
  627. .parts = ezkit_partitions,
  628. .init = bf609_nor_flash_init,
  629. .nr_parts = ARRAY_SIZE(ezkit_partitions),
  630. };
  631. static struct resource ezkit_flash_resource = {
  632. .start = 0xb0000000,
  633. .end = 0xb0ffffff,
  634. .flags = IORESOURCE_MEM,
  635. };
  636. static struct platform_device ezkit_flash_device = {
  637. .name = "physmap-flash",
  638. .id = 0,
  639. .dev = {
  640. .platform_data = &ezkit_flash_data,
  641. },
  642. .num_resources = 1,
  643. .resource = &ezkit_flash_resource,
  644. };
  645. #endif
  646. #if defined(CONFIG_MTD_M25P80) \
  647. || defined(CONFIG_MTD_M25P80_MODULE)
  648. /* SPI flash chip (w25q32) */
  649. static struct mtd_partition bfin_spi_flash_partitions[] = {
  650. {
  651. .name = "bootloader(spi)",
  652. .size = 0x00080000,
  653. .offset = 0,
  654. .mask_flags = MTD_CAP_ROM
  655. }, {
  656. .name = "linux kernel(spi)",
  657. .size = 0x00180000,
  658. .offset = MTDPART_OFS_APPEND,
  659. }, {
  660. .name = "file system(spi)",
  661. .size = MTDPART_SIZ_FULL,
  662. .offset = MTDPART_OFS_APPEND,
  663. }
  664. };
  665. static struct flash_platform_data bfin_spi_flash_data = {
  666. .name = "m25p80",
  667. .parts = bfin_spi_flash_partitions,
  668. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  669. .type = "w25q32",
  670. };
  671. static struct bfin6xx_spi_chip spi_flash_chip_info = {
  672. .enable_dma = true, /* use dma transfer with this chip*/
  673. };
  674. #endif
  675. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  676. static struct bfin6xx_spi_chip spidev_chip_info = {
  677. .enable_dma = true,
  678. };
  679. #endif
  680. #if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
  681. static struct platform_device bfin_i2s_pcm = {
  682. .name = "bfin-i2s-pcm-audio",
  683. .id = -1,
  684. };
  685. #endif
  686. #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
  687. defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
  688. #include <asm/bfin_sport3.h>
  689. static struct resource bfin_snd_resources[] = {
  690. {
  691. .start = SPORT0_CTL_A,
  692. .end = SPORT0_CTL_A,
  693. .flags = IORESOURCE_MEM,
  694. },
  695. {
  696. .start = SPORT0_CTL_B,
  697. .end = SPORT0_CTL_B,
  698. .flags = IORESOURCE_MEM,
  699. },
  700. {
  701. .start = CH_SPORT0_TX,
  702. .end = CH_SPORT0_TX,
  703. .flags = IORESOURCE_DMA,
  704. },
  705. {
  706. .start = CH_SPORT0_RX,
  707. .end = CH_SPORT0_RX,
  708. .flags = IORESOURCE_DMA,
  709. },
  710. {
  711. .start = IRQ_SPORT0_TX_STAT,
  712. .end = IRQ_SPORT0_TX_STAT,
  713. .flags = IORESOURCE_IRQ,
  714. },
  715. {
  716. .start = IRQ_SPORT0_RX_STAT,
  717. .end = IRQ_SPORT0_RX_STAT,
  718. .flags = IORESOURCE_IRQ,
  719. },
  720. };
  721. static const unsigned short bfin_snd_pin[] = {
  722. P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
  723. P_SPORT0_BFS, P_SPORT0_BD0, 0,
  724. };
  725. static struct bfin_snd_platform_data bfin_snd_data = {
  726. .pin_req = bfin_snd_pin,
  727. };
  728. static struct platform_device bfin_i2s = {
  729. .name = "bfin-i2s",
  730. .num_resources = ARRAY_SIZE(bfin_snd_resources),
  731. .resource = bfin_snd_resources,
  732. .dev = {
  733. .platform_data = &bfin_snd_data,
  734. },
  735. };
  736. #endif
  737. #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
  738. defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
  739. static struct platform_device adau1761_device = {
  740. .name = "bfin-eval-adau1x61",
  741. };
  742. #endif
  743. #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
  744. #include <sound/adau17x1.h>
  745. static struct adau1761_platform_data adau1761_info = {
  746. .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
  747. .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
  748. };
  749. #endif
  750. #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
  751. || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
  752. #include <linux/videodev2.h>
  753. #include <media/blackfin/bfin_capture.h>
  754. #include <media/blackfin/ppi.h>
  755. static const unsigned short ppi_req[] = {
  756. P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
  757. P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
  758. P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
  759. 0,
  760. };
  761. static const struct ppi_info ppi_info = {
  762. .type = PPI_TYPE_EPPI3,
  763. .dma_ch = CH_EPPI0_CH0,
  764. .irq_err = IRQ_EPPI0_STAT,
  765. .base = (void __iomem *)EPPI0_STAT,
  766. .pin_req = ppi_req,
  767. };
  768. #if defined(CONFIG_VIDEO_VS6624) \
  769. || defined(CONFIG_VIDEO_VS6624_MODULE)
  770. static struct v4l2_input vs6624_inputs[] = {
  771. {
  772. .index = 0,
  773. .name = "Camera",
  774. .type = V4L2_INPUT_TYPE_CAMERA,
  775. .std = V4L2_STD_UNKNOWN,
  776. },
  777. };
  778. static struct bcap_route vs6624_routes[] = {
  779. {
  780. .input = 0,
  781. .output = 0,
  782. },
  783. };
  784. static const unsigned vs6624_ce_pin = GPIO_PD1;
  785. static struct bfin_capture_config bfin_capture_data = {
  786. .card_name = "BF609",
  787. .inputs = vs6624_inputs,
  788. .num_inputs = ARRAY_SIZE(vs6624_inputs),
  789. .routes = vs6624_routes,
  790. .i2c_adapter_id = 0,
  791. .board_info = {
  792. .type = "vs6624",
  793. .addr = 0x10,
  794. .platform_data = (void *)&vs6624_ce_pin,
  795. },
  796. .ppi_info = &ppi_info,
  797. .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
  798. | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
  799. .blank_clocks = 8,
  800. };
  801. #endif
  802. static struct platform_device bfin_capture_device = {
  803. .name = "bfin_capture",
  804. .dev = {
  805. .platform_data = &bfin_capture_data,
  806. },
  807. };
  808. #endif
  809. #if defined(CONFIG_BFIN_CRC)
  810. #define BFIN_CRC_NAME "bfin-crc"
  811. static struct resource bfin_crc0_resources[] = {
  812. {
  813. .start = REG_CRC0_CTL,
  814. .end = REG_CRC0_REVID+4,
  815. .flags = IORESOURCE_MEM,
  816. },
  817. {
  818. .start = IRQ_CRC0_DCNTEXP,
  819. .end = IRQ_CRC0_DCNTEXP,
  820. .flags = IORESOURCE_IRQ,
  821. },
  822. {
  823. .start = CH_MEM_STREAM0_SRC_CRC0,
  824. .end = CH_MEM_STREAM0_SRC_CRC0,
  825. .flags = IORESOURCE_DMA,
  826. },
  827. {
  828. .start = CH_MEM_STREAM0_DEST_CRC0,
  829. .end = CH_MEM_STREAM0_DEST_CRC0,
  830. .flags = IORESOURCE_DMA,
  831. },
  832. };
  833. static struct platform_device bfin_crc0_device = {
  834. .name = BFIN_CRC_NAME,
  835. .id = 0,
  836. .num_resources = ARRAY_SIZE(bfin_crc0_resources),
  837. .resource = bfin_crc0_resources,
  838. };
  839. static struct resource bfin_crc1_resources[] = {
  840. {
  841. .start = REG_CRC1_CTL,
  842. .end = REG_CRC1_REVID+4,
  843. .flags = IORESOURCE_MEM,
  844. },
  845. {
  846. .start = IRQ_CRC1_DCNTEXP,
  847. .end = IRQ_CRC1_DCNTEXP,
  848. .flags = IORESOURCE_IRQ,
  849. },
  850. {
  851. .start = CH_MEM_STREAM1_SRC_CRC1,
  852. .end = CH_MEM_STREAM1_SRC_CRC1,
  853. .flags = IORESOURCE_DMA,
  854. },
  855. {
  856. .start = CH_MEM_STREAM1_DEST_CRC1,
  857. .end = CH_MEM_STREAM1_DEST_CRC1,
  858. .flags = IORESOURCE_DMA,
  859. },
  860. };
  861. static struct platform_device bfin_crc1_device = {
  862. .name = BFIN_CRC_NAME,
  863. .id = 1,
  864. .num_resources = ARRAY_SIZE(bfin_crc1_resources),
  865. .resource = bfin_crc1_resources,
  866. };
  867. #endif
  868. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  869. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  870. .model = 7877,
  871. .vref_delay_usecs = 50, /* internal, no capacitor */
  872. .x_plate_ohms = 419,
  873. .y_plate_ohms = 486,
  874. .pressure_max = 1000,
  875. .pressure_min = 0,
  876. .stopacq_polarity = 1,
  877. .first_conversion_delay = 3,
  878. .acquisition_time = 1,
  879. .averaging = 1,
  880. .pen_down_acc_interval = 1,
  881. };
  882. #endif
  883. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  884. #if defined(CONFIG_MTD_M25P80) \
  885. || defined(CONFIG_MTD_M25P80_MODULE)
  886. {
  887. /* the modalias must be the same as spi device driver name */
  888. .modalias = "m25p80", /* Name of spi_driver for this device */
  889. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  890. .bus_num = 0, /* Framework bus number */
  891. .chip_select = 1, /* SPI_SSEL1*/
  892. .platform_data = &bfin_spi_flash_data,
  893. .controller_data = &spi_flash_chip_info,
  894. .mode = SPI_MODE_3,
  895. },
  896. #endif
  897. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  898. {
  899. .modalias = "ad7877",
  900. .platform_data = &bfin_ad7877_ts_info,
  901. .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
  902. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  903. .bus_num = 0,
  904. .chip_select = 2,
  905. },
  906. #endif
  907. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  908. {
  909. .modalias = "spidev",
  910. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  911. .bus_num = 0,
  912. .chip_select = 1,
  913. .controller_data = &spidev_chip_info,
  914. },
  915. #endif
  916. #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
  917. {
  918. .modalias = "adxl34x",
  919. .platform_data = &adxl34x_info,
  920. .irq = IRQ_PC5,
  921. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  922. .bus_num = 1,
  923. .chip_select = 2,
  924. .mode = SPI_MODE_3,
  925. },
  926. #endif
  927. };
  928. #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
  929. /* SPI (0) */
  930. static struct resource bfin_spi0_resource[] = {
  931. {
  932. .start = SPI0_REGBASE,
  933. .end = SPI0_REGBASE + 0xFF,
  934. .flags = IORESOURCE_MEM,
  935. },
  936. {
  937. .start = CH_SPI0_TX,
  938. .end = CH_SPI0_TX,
  939. .flags = IORESOURCE_DMA,
  940. },
  941. {
  942. .start = CH_SPI0_RX,
  943. .end = CH_SPI0_RX,
  944. .flags = IORESOURCE_DMA,
  945. },
  946. };
  947. /* SPI (1) */
  948. static struct resource bfin_spi1_resource[] = {
  949. {
  950. .start = SPI1_REGBASE,
  951. .end = SPI1_REGBASE + 0xFF,
  952. .flags = IORESOURCE_MEM,
  953. },
  954. {
  955. .start = CH_SPI1_TX,
  956. .end = CH_SPI1_TX,
  957. .flags = IORESOURCE_DMA,
  958. },
  959. {
  960. .start = CH_SPI1_RX,
  961. .end = CH_SPI1_RX,
  962. .flags = IORESOURCE_DMA,
  963. },
  964. };
  965. /* SPI controller data */
  966. static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
  967. .num_chipselect = 4,
  968. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  969. };
  970. static struct platform_device bf60x_spi_master0 = {
  971. .name = "bfin-spi",
  972. .id = 0, /* Bus number */
  973. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  974. .resource = bfin_spi0_resource,
  975. .dev = {
  976. .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
  977. },
  978. };
  979. static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
  980. .num_chipselect = 4,
  981. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  982. };
  983. static struct platform_device bf60x_spi_master1 = {
  984. .name = "bfin-spi",
  985. .id = 1, /* Bus number */
  986. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  987. .resource = bfin_spi1_resource,
  988. .dev = {
  989. .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
  990. },
  991. };
  992. #endif /* spi master and devices */
  993. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  994. static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
  995. static struct resource bfin_twi0_resource[] = {
  996. [0] = {
  997. .start = TWI0_CLKDIV,
  998. .end = TWI0_CLKDIV + 0xFF,
  999. .flags = IORESOURCE_MEM,
  1000. },
  1001. [1] = {
  1002. .start = IRQ_TWI0,
  1003. .end = IRQ_TWI0,
  1004. .flags = IORESOURCE_IRQ,
  1005. },
  1006. };
  1007. static struct platform_device i2c_bfin_twi0_device = {
  1008. .name = "i2c-bfin-twi",
  1009. .id = 0,
  1010. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  1011. .resource = bfin_twi0_resource,
  1012. .dev = {
  1013. .platform_data = &bfin_twi0_pins,
  1014. },
  1015. };
  1016. static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
  1017. static struct resource bfin_twi1_resource[] = {
  1018. [0] = {
  1019. .start = TWI1_CLKDIV,
  1020. .end = TWI1_CLKDIV + 0xFF,
  1021. .flags = IORESOURCE_MEM,
  1022. },
  1023. [1] = {
  1024. .start = IRQ_TWI1,
  1025. .end = IRQ_TWI1,
  1026. .flags = IORESOURCE_IRQ,
  1027. },
  1028. };
  1029. static struct platform_device i2c_bfin_twi1_device = {
  1030. .name = "i2c-bfin-twi",
  1031. .id = 1,
  1032. .num_resources = ARRAY_SIZE(bfin_twi1_resource),
  1033. .resource = bfin_twi1_resource,
  1034. .dev = {
  1035. .platform_data = &bfin_twi1_pins,
  1036. },
  1037. };
  1038. #endif
  1039. static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
  1040. #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
  1041. {
  1042. I2C_BOARD_INFO("adxl34x", 0x53),
  1043. .irq = IRQ_PC5,
  1044. .platform_data = (void *)&adxl34x_info,
  1045. },
  1046. #endif
  1047. #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
  1048. {
  1049. I2C_BOARD_INFO("adau1761", 0x38),
  1050. .platform_data = (void *)&adau1761_info
  1051. },
  1052. #endif
  1053. };
  1054. static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
  1055. };
  1056. static const unsigned int cclk_vlev_datasheet[] =
  1057. {
  1058. /*
  1059. * Internal VLEV BF54XSBBC1533
  1060. ****temporarily using these values until data sheet is updated
  1061. */
  1062. VRPAIR(VLEV_085, 150000000),
  1063. VRPAIR(VLEV_090, 250000000),
  1064. VRPAIR(VLEV_110, 276000000),
  1065. VRPAIR(VLEV_115, 301000000),
  1066. VRPAIR(VLEV_120, 525000000),
  1067. VRPAIR(VLEV_125, 550000000),
  1068. VRPAIR(VLEV_130, 600000000),
  1069. };
  1070. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  1071. .tuple_tab = cclk_vlev_datasheet,
  1072. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  1073. .vr_settling_time = 25 /* us */,
  1074. };
  1075. static struct platform_device bfin_dpmc = {
  1076. .name = "bfin dpmc",
  1077. .dev = {
  1078. .platform_data = &bfin_dmpc_vreg_data,
  1079. },
  1080. };
  1081. static struct platform_device *ezkit_devices[] __initdata = {
  1082. &bfin_dpmc,
  1083. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  1084. &rtc_device,
  1085. #endif
  1086. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  1087. #ifdef CONFIG_SERIAL_BFIN_UART0
  1088. &bfin_uart0_device,
  1089. #endif
  1090. #ifdef CONFIG_SERIAL_BFIN_UART1
  1091. &bfin_uart1_device,
  1092. #endif
  1093. #endif
  1094. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  1095. #ifdef CONFIG_BFIN_SIR0
  1096. &bfin_sir0_device,
  1097. #endif
  1098. #ifdef CONFIG_BFIN_SIR1
  1099. &bfin_sir1_device,
  1100. #endif
  1101. #endif
  1102. #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
  1103. &bfin_eth_device,
  1104. #endif
  1105. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  1106. &musb_device,
  1107. #endif
  1108. #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  1109. &bfin_isp1760_device,
  1110. #endif
  1111. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  1112. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  1113. &bfin_sport0_uart_device,
  1114. #endif
  1115. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  1116. &bfin_sport1_uart_device,
  1117. #endif
  1118. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  1119. &bfin_sport2_uart_device,
  1120. #endif
  1121. #endif
  1122. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  1123. &bfin_can0_device,
  1124. #endif
  1125. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  1126. &bfin_nand_device,
  1127. #endif
  1128. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  1129. &bfin_sdh_device,
  1130. #endif
  1131. #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
  1132. &bf60x_spi_master0,
  1133. &bf60x_spi_master1,
  1134. #endif
  1135. #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
  1136. &bfin_rotary_device,
  1137. #endif
  1138. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  1139. &i2c_bfin_twi0_device,
  1140. #if !defined(CONFIG_BF542)
  1141. &i2c_bfin_twi1_device,
  1142. #endif
  1143. #endif
  1144. #if defined(CONFIG_BFIN_CRC)
  1145. &bfin_crc0_device,
  1146. &bfin_crc1_device,
  1147. #endif
  1148. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  1149. &bfin_device_gpiokeys,
  1150. #endif
  1151. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  1152. &ezkit_flash_device,
  1153. #endif
  1154. #if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
  1155. &bfin_i2s_pcm,
  1156. #endif
  1157. #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
  1158. defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
  1159. &bfin_i2s,
  1160. #endif
  1161. #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
  1162. defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
  1163. &adau1761_device,
  1164. #endif
  1165. #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
  1166. || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
  1167. &bfin_capture_device,
  1168. #endif
  1169. };
  1170. static int __init ezkit_init(void)
  1171. {
  1172. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  1173. i2c_register_board_info(0, bfin_i2c_board_info0,
  1174. ARRAY_SIZE(bfin_i2c_board_info0));
  1175. i2c_register_board_info(1, bfin_i2c_board_info1,
  1176. ARRAY_SIZE(bfin_i2c_board_info1));
  1177. #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
  1178. if (!peripheral_request_list(pins, "emac0"))
  1179. printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
  1180. #endif
  1181. platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
  1182. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  1183. return 0;
  1184. }
  1185. arch_initcall(ezkit_init);
  1186. static struct platform_device *ezkit_early_devices[] __initdata = {
  1187. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  1188. #ifdef CONFIG_SERIAL_BFIN_UART0
  1189. &bfin_uart0_device,
  1190. #endif
  1191. #ifdef CONFIG_SERIAL_BFIN_UART1
  1192. &bfin_uart1_device,
  1193. #endif
  1194. #endif
  1195. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  1196. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  1197. &bfin_sport0_uart_device,
  1198. #endif
  1199. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  1200. &bfin_sport1_uart_device,
  1201. #endif
  1202. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  1203. &bfin_sport2_uart_device,
  1204. #endif
  1205. #endif
  1206. };
  1207. void __init native_machine_early_platform_add_devices(void)
  1208. {
  1209. printk(KERN_INFO "register early platform devices\n");
  1210. early_platform_add_devices(ezkit_early_devices,
  1211. ARRAY_SIZE(ezkit_early_devices));
  1212. }