dma.c 52 KB

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  1. /*
  2. * linux/arch/arm/plat-omap/dma.c
  3. *
  4. * Copyright (C) 2003 - 2008 Nokia Corporation
  5. * Author: Juha Yrjölä <juha.yrjola@nokia.com>
  6. * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
  7. * Graphics DMA and LCD DMA graphics tranformations
  8. * by Imre Deak <imre.deak@nokia.com>
  9. * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10. * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11. * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12. *
  13. * Copyright (C) 2009 Texas Instruments
  14. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15. *
  16. * Support functions for the OMAP internal DMA channels.
  17. *
  18. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  19. * Converted DMA library into DMA platform driver.
  20. * - G, Manjunath Kondaiah <manjugk@ti.com>
  21. *
  22. * This program is free software; you can redistribute it and/or modify
  23. * it under the terms of the GNU General Public License version 2 as
  24. * published by the Free Software Foundation.
  25. *
  26. */
  27. #include <linux/module.h>
  28. #include <linux/init.h>
  29. #include <linux/sched.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/errno.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/irq.h>
  34. #include <linux/io.h>
  35. #include <linux/slab.h>
  36. #include <linux/delay.h>
  37. #include <mach/hardware.h>
  38. #include <plat/dma.h>
  39. #include <plat/tc.h>
  40. /*
  41. * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
  42. * channels that an instance of the SDMA IP block can support. Used
  43. * to size arrays. (The actual maximum on a particular SoC may be less
  44. * than this -- for example, OMAP1 SDMA instances only support 17 logical
  45. * DMA channels.)
  46. */
  47. #define MAX_LOGICAL_DMA_CH_COUNT 32
  48. #undef DEBUG
  49. #ifndef CONFIG_ARCH_OMAP1
  50. enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  51. DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  52. };
  53. enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  54. #endif
  55. #define OMAP_DMA_ACTIVE 0x01
  56. #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
  57. #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
  58. static struct omap_system_dma_plat_info *p;
  59. static struct omap_dma_dev_attr *d;
  60. static int enable_1510_mode;
  61. static u32 errata;
  62. static struct omap_dma_global_context_registers {
  63. u32 dma_irqenable_l0;
  64. u32 dma_ocp_sysconfig;
  65. u32 dma_gcr;
  66. } omap_dma_global_context;
  67. struct dma_link_info {
  68. int *linked_dmach_q;
  69. int no_of_lchs_linked;
  70. int q_count;
  71. int q_tail;
  72. int q_head;
  73. int chain_state;
  74. int chain_mode;
  75. };
  76. static struct dma_link_info *dma_linked_lch;
  77. #ifndef CONFIG_ARCH_OMAP1
  78. /* Chain handling macros */
  79. #define OMAP_DMA_CHAIN_QINIT(chain_id) \
  80. do { \
  81. dma_linked_lch[chain_id].q_head = \
  82. dma_linked_lch[chain_id].q_tail = \
  83. dma_linked_lch[chain_id].q_count = 0; \
  84. } while (0)
  85. #define OMAP_DMA_CHAIN_QFULL(chain_id) \
  86. (dma_linked_lch[chain_id].no_of_lchs_linked == \
  87. dma_linked_lch[chain_id].q_count)
  88. #define OMAP_DMA_CHAIN_QLAST(chain_id) \
  89. do { \
  90. ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
  91. dma_linked_lch[chain_id].q_count) \
  92. } while (0)
  93. #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
  94. (0 == dma_linked_lch[chain_id].q_count)
  95. #define __OMAP_DMA_CHAIN_INCQ(end) \
  96. ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
  97. #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
  98. do { \
  99. __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
  100. dma_linked_lch[chain_id].q_count--; \
  101. } while (0)
  102. #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
  103. do { \
  104. __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
  105. dma_linked_lch[chain_id].q_count++; \
  106. } while (0)
  107. #endif
  108. static int dma_lch_count;
  109. static int dma_chan_count;
  110. static int omap_dma_reserve_channels;
  111. static spinlock_t dma_chan_lock;
  112. static struct omap_dma_lch *dma_chan;
  113. static inline void disable_lnk(int lch);
  114. static void omap_disable_channel_irq(int lch);
  115. static inline void omap_enable_channel_irq(int lch);
  116. #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
  117. __func__);
  118. #ifdef CONFIG_ARCH_OMAP15XX
  119. /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
  120. static int omap_dma_in_1510_mode(void)
  121. {
  122. return enable_1510_mode;
  123. }
  124. #else
  125. #define omap_dma_in_1510_mode() 0
  126. #endif
  127. #ifdef CONFIG_ARCH_OMAP1
  128. static inline int get_gdma_dev(int req)
  129. {
  130. u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  131. int shift = ((req - 1) % 5) * 6;
  132. return ((omap_readl(reg) >> shift) & 0x3f) + 1;
  133. }
  134. static inline void set_gdma_dev(int req, int dev)
  135. {
  136. u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  137. int shift = ((req - 1) % 5) * 6;
  138. u32 l;
  139. l = omap_readl(reg);
  140. l &= ~(0x3f << shift);
  141. l |= (dev - 1) << shift;
  142. omap_writel(l, reg);
  143. }
  144. #else
  145. #define set_gdma_dev(req, dev) do {} while (0)
  146. #define omap_readl(reg) 0
  147. #define omap_writel(val, reg) do {} while (0)
  148. #endif
  149. void omap_set_dma_priority(int lch, int dst_port, int priority)
  150. {
  151. unsigned long reg;
  152. u32 l;
  153. if (cpu_class_is_omap1()) {
  154. switch (dst_port) {
  155. case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
  156. reg = OMAP_TC_OCPT1_PRIOR;
  157. break;
  158. case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
  159. reg = OMAP_TC_OCPT2_PRIOR;
  160. break;
  161. case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
  162. reg = OMAP_TC_EMIFF_PRIOR;
  163. break;
  164. case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
  165. reg = OMAP_TC_EMIFS_PRIOR;
  166. break;
  167. default:
  168. BUG();
  169. return;
  170. }
  171. l = omap_readl(reg);
  172. l &= ~(0xf << 8);
  173. l |= (priority & 0xf) << 8;
  174. omap_writel(l, reg);
  175. }
  176. if (cpu_class_is_omap2()) {
  177. u32 ccr;
  178. ccr = p->dma_read(CCR, lch);
  179. if (priority)
  180. ccr |= (1 << 6);
  181. else
  182. ccr &= ~(1 << 6);
  183. p->dma_write(ccr, CCR, lch);
  184. }
  185. }
  186. EXPORT_SYMBOL(omap_set_dma_priority);
  187. void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
  188. int frame_count, int sync_mode,
  189. int dma_trigger, int src_or_dst_synch)
  190. {
  191. u32 l;
  192. l = p->dma_read(CSDP, lch);
  193. l &= ~0x03;
  194. l |= data_type;
  195. p->dma_write(l, CSDP, lch);
  196. if (cpu_class_is_omap1()) {
  197. u16 ccr;
  198. ccr = p->dma_read(CCR, lch);
  199. ccr &= ~(1 << 5);
  200. if (sync_mode == OMAP_DMA_SYNC_FRAME)
  201. ccr |= 1 << 5;
  202. p->dma_write(ccr, CCR, lch);
  203. ccr = p->dma_read(CCR2, lch);
  204. ccr &= ~(1 << 2);
  205. if (sync_mode == OMAP_DMA_SYNC_BLOCK)
  206. ccr |= 1 << 2;
  207. p->dma_write(ccr, CCR2, lch);
  208. }
  209. if (cpu_class_is_omap2() && dma_trigger) {
  210. u32 val;
  211. val = p->dma_read(CCR, lch);
  212. /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
  213. val &= ~((1 << 23) | (3 << 19) | 0x1f);
  214. val |= (dma_trigger & ~0x1f) << 14;
  215. val |= dma_trigger & 0x1f;
  216. if (sync_mode & OMAP_DMA_SYNC_FRAME)
  217. val |= 1 << 5;
  218. else
  219. val &= ~(1 << 5);
  220. if (sync_mode & OMAP_DMA_SYNC_BLOCK)
  221. val |= 1 << 18;
  222. else
  223. val &= ~(1 << 18);
  224. if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
  225. val &= ~(1 << 24); /* dest synch */
  226. val |= (1 << 23); /* Prefetch */
  227. } else if (src_or_dst_synch) {
  228. val |= 1 << 24; /* source synch */
  229. } else {
  230. val &= ~(1 << 24); /* dest synch */
  231. }
  232. p->dma_write(val, CCR, lch);
  233. }
  234. p->dma_write(elem_count, CEN, lch);
  235. p->dma_write(frame_count, CFN, lch);
  236. }
  237. EXPORT_SYMBOL(omap_set_dma_transfer_params);
  238. void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
  239. {
  240. BUG_ON(omap_dma_in_1510_mode());
  241. if (cpu_class_is_omap1()) {
  242. u16 w;
  243. w = p->dma_read(CCR2, lch);
  244. w &= ~0x03;
  245. switch (mode) {
  246. case OMAP_DMA_CONSTANT_FILL:
  247. w |= 0x01;
  248. break;
  249. case OMAP_DMA_TRANSPARENT_COPY:
  250. w |= 0x02;
  251. break;
  252. case OMAP_DMA_COLOR_DIS:
  253. break;
  254. default:
  255. BUG();
  256. }
  257. p->dma_write(w, CCR2, lch);
  258. w = p->dma_read(LCH_CTRL, lch);
  259. w &= ~0x0f;
  260. /* Default is channel type 2D */
  261. if (mode) {
  262. p->dma_write(color, COLOR, lch);
  263. w |= 1; /* Channel type G */
  264. }
  265. p->dma_write(w, LCH_CTRL, lch);
  266. }
  267. if (cpu_class_is_omap2()) {
  268. u32 val;
  269. val = p->dma_read(CCR, lch);
  270. val &= ~((1 << 17) | (1 << 16));
  271. switch (mode) {
  272. case OMAP_DMA_CONSTANT_FILL:
  273. val |= 1 << 16;
  274. break;
  275. case OMAP_DMA_TRANSPARENT_COPY:
  276. val |= 1 << 17;
  277. break;
  278. case OMAP_DMA_COLOR_DIS:
  279. break;
  280. default:
  281. BUG();
  282. }
  283. p->dma_write(val, CCR, lch);
  284. color &= 0xffffff;
  285. p->dma_write(color, COLOR, lch);
  286. }
  287. }
  288. EXPORT_SYMBOL(omap_set_dma_color_mode);
  289. void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
  290. {
  291. if (cpu_class_is_omap2()) {
  292. u32 csdp;
  293. csdp = p->dma_read(CSDP, lch);
  294. csdp &= ~(0x3 << 16);
  295. csdp |= (mode << 16);
  296. p->dma_write(csdp, CSDP, lch);
  297. }
  298. }
  299. EXPORT_SYMBOL(omap_set_dma_write_mode);
  300. void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
  301. {
  302. if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
  303. u32 l;
  304. l = p->dma_read(LCH_CTRL, lch);
  305. l &= ~0x7;
  306. l |= mode;
  307. p->dma_write(l, LCH_CTRL, lch);
  308. }
  309. }
  310. EXPORT_SYMBOL(omap_set_dma_channel_mode);
  311. /* Note that src_port is only for omap1 */
  312. void omap_set_dma_src_params(int lch, int src_port, int src_amode,
  313. unsigned long src_start,
  314. int src_ei, int src_fi)
  315. {
  316. u32 l;
  317. if (cpu_class_is_omap1()) {
  318. u16 w;
  319. w = p->dma_read(CSDP, lch);
  320. w &= ~(0x1f << 2);
  321. w |= src_port << 2;
  322. p->dma_write(w, CSDP, lch);
  323. }
  324. l = p->dma_read(CCR, lch);
  325. l &= ~(0x03 << 12);
  326. l |= src_amode << 12;
  327. p->dma_write(l, CCR, lch);
  328. p->dma_write(src_start, CSSA, lch);
  329. p->dma_write(src_ei, CSEI, lch);
  330. p->dma_write(src_fi, CSFI, lch);
  331. }
  332. EXPORT_SYMBOL(omap_set_dma_src_params);
  333. void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
  334. {
  335. omap_set_dma_transfer_params(lch, params->data_type,
  336. params->elem_count, params->frame_count,
  337. params->sync_mode, params->trigger,
  338. params->src_or_dst_synch);
  339. omap_set_dma_src_params(lch, params->src_port,
  340. params->src_amode, params->src_start,
  341. params->src_ei, params->src_fi);
  342. omap_set_dma_dest_params(lch, params->dst_port,
  343. params->dst_amode, params->dst_start,
  344. params->dst_ei, params->dst_fi);
  345. if (params->read_prio || params->write_prio)
  346. omap_dma_set_prio_lch(lch, params->read_prio,
  347. params->write_prio);
  348. }
  349. EXPORT_SYMBOL(omap_set_dma_params);
  350. void omap_set_dma_src_index(int lch, int eidx, int fidx)
  351. {
  352. if (cpu_class_is_omap2())
  353. return;
  354. p->dma_write(eidx, CSEI, lch);
  355. p->dma_write(fidx, CSFI, lch);
  356. }
  357. EXPORT_SYMBOL(omap_set_dma_src_index);
  358. void omap_set_dma_src_data_pack(int lch, int enable)
  359. {
  360. u32 l;
  361. l = p->dma_read(CSDP, lch);
  362. l &= ~(1 << 6);
  363. if (enable)
  364. l |= (1 << 6);
  365. p->dma_write(l, CSDP, lch);
  366. }
  367. EXPORT_SYMBOL(omap_set_dma_src_data_pack);
  368. void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
  369. {
  370. unsigned int burst = 0;
  371. u32 l;
  372. l = p->dma_read(CSDP, lch);
  373. l &= ~(0x03 << 7);
  374. switch (burst_mode) {
  375. case OMAP_DMA_DATA_BURST_DIS:
  376. break;
  377. case OMAP_DMA_DATA_BURST_4:
  378. if (cpu_class_is_omap2())
  379. burst = 0x1;
  380. else
  381. burst = 0x2;
  382. break;
  383. case OMAP_DMA_DATA_BURST_8:
  384. if (cpu_class_is_omap2()) {
  385. burst = 0x2;
  386. break;
  387. }
  388. /*
  389. * not supported by current hardware on OMAP1
  390. * w |= (0x03 << 7);
  391. * fall through
  392. */
  393. case OMAP_DMA_DATA_BURST_16:
  394. if (cpu_class_is_omap2()) {
  395. burst = 0x3;
  396. break;
  397. }
  398. /*
  399. * OMAP1 don't support burst 16
  400. * fall through
  401. */
  402. default:
  403. BUG();
  404. }
  405. l |= (burst << 7);
  406. p->dma_write(l, CSDP, lch);
  407. }
  408. EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
  409. /* Note that dest_port is only for OMAP1 */
  410. void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
  411. unsigned long dest_start,
  412. int dst_ei, int dst_fi)
  413. {
  414. u32 l;
  415. if (cpu_class_is_omap1()) {
  416. l = p->dma_read(CSDP, lch);
  417. l &= ~(0x1f << 9);
  418. l |= dest_port << 9;
  419. p->dma_write(l, CSDP, lch);
  420. }
  421. l = p->dma_read(CCR, lch);
  422. l &= ~(0x03 << 14);
  423. l |= dest_amode << 14;
  424. p->dma_write(l, CCR, lch);
  425. p->dma_write(dest_start, CDSA, lch);
  426. p->dma_write(dst_ei, CDEI, lch);
  427. p->dma_write(dst_fi, CDFI, lch);
  428. }
  429. EXPORT_SYMBOL(omap_set_dma_dest_params);
  430. void omap_set_dma_dest_index(int lch, int eidx, int fidx)
  431. {
  432. if (cpu_class_is_omap2())
  433. return;
  434. p->dma_write(eidx, CDEI, lch);
  435. p->dma_write(fidx, CDFI, lch);
  436. }
  437. EXPORT_SYMBOL(omap_set_dma_dest_index);
  438. void omap_set_dma_dest_data_pack(int lch, int enable)
  439. {
  440. u32 l;
  441. l = p->dma_read(CSDP, lch);
  442. l &= ~(1 << 13);
  443. if (enable)
  444. l |= 1 << 13;
  445. p->dma_write(l, CSDP, lch);
  446. }
  447. EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
  448. void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
  449. {
  450. unsigned int burst = 0;
  451. u32 l;
  452. l = p->dma_read(CSDP, lch);
  453. l &= ~(0x03 << 14);
  454. switch (burst_mode) {
  455. case OMAP_DMA_DATA_BURST_DIS:
  456. break;
  457. case OMAP_DMA_DATA_BURST_4:
  458. if (cpu_class_is_omap2())
  459. burst = 0x1;
  460. else
  461. burst = 0x2;
  462. break;
  463. case OMAP_DMA_DATA_BURST_8:
  464. if (cpu_class_is_omap2())
  465. burst = 0x2;
  466. else
  467. burst = 0x3;
  468. break;
  469. case OMAP_DMA_DATA_BURST_16:
  470. if (cpu_class_is_omap2()) {
  471. burst = 0x3;
  472. break;
  473. }
  474. /*
  475. * OMAP1 don't support burst 16
  476. * fall through
  477. */
  478. default:
  479. printk(KERN_ERR "Invalid DMA burst mode\n");
  480. BUG();
  481. return;
  482. }
  483. l |= (burst << 14);
  484. p->dma_write(l, CSDP, lch);
  485. }
  486. EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
  487. static inline void omap_enable_channel_irq(int lch)
  488. {
  489. u32 status;
  490. /* Clear CSR */
  491. if (cpu_class_is_omap1())
  492. status = p->dma_read(CSR, lch);
  493. else if (cpu_class_is_omap2())
  494. p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
  495. /* Enable some nice interrupts. */
  496. p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
  497. }
  498. static void omap_disable_channel_irq(int lch)
  499. {
  500. if (cpu_class_is_omap2())
  501. p->dma_write(0, CICR, lch);
  502. }
  503. void omap_enable_dma_irq(int lch, u16 bits)
  504. {
  505. dma_chan[lch].enabled_irqs |= bits;
  506. }
  507. EXPORT_SYMBOL(omap_enable_dma_irq);
  508. void omap_disable_dma_irq(int lch, u16 bits)
  509. {
  510. dma_chan[lch].enabled_irqs &= ~bits;
  511. }
  512. EXPORT_SYMBOL(omap_disable_dma_irq);
  513. static inline void enable_lnk(int lch)
  514. {
  515. u32 l;
  516. l = p->dma_read(CLNK_CTRL, lch);
  517. if (cpu_class_is_omap1())
  518. l &= ~(1 << 14);
  519. /* Set the ENABLE_LNK bits */
  520. if (dma_chan[lch].next_lch != -1)
  521. l = dma_chan[lch].next_lch | (1 << 15);
  522. #ifndef CONFIG_ARCH_OMAP1
  523. if (cpu_class_is_omap2())
  524. if (dma_chan[lch].next_linked_ch != -1)
  525. l = dma_chan[lch].next_linked_ch | (1 << 15);
  526. #endif
  527. p->dma_write(l, CLNK_CTRL, lch);
  528. }
  529. static inline void disable_lnk(int lch)
  530. {
  531. u32 l;
  532. l = p->dma_read(CLNK_CTRL, lch);
  533. /* Disable interrupts */
  534. if (cpu_class_is_omap1()) {
  535. p->dma_write(0, CICR, lch);
  536. /* Set the STOP_LNK bit */
  537. l |= 1 << 14;
  538. }
  539. if (cpu_class_is_omap2()) {
  540. omap_disable_channel_irq(lch);
  541. /* Clear the ENABLE_LNK bit */
  542. l &= ~(1 << 15);
  543. }
  544. p->dma_write(l, CLNK_CTRL, lch);
  545. dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
  546. }
  547. static inline void omap2_enable_irq_lch(int lch)
  548. {
  549. u32 val;
  550. unsigned long flags;
  551. if (!cpu_class_is_omap2())
  552. return;
  553. spin_lock_irqsave(&dma_chan_lock, flags);
  554. val = p->dma_read(IRQENABLE_L0, lch);
  555. val |= 1 << lch;
  556. p->dma_write(val, IRQENABLE_L0, lch);
  557. spin_unlock_irqrestore(&dma_chan_lock, flags);
  558. }
  559. static inline void omap2_disable_irq_lch(int lch)
  560. {
  561. u32 val;
  562. unsigned long flags;
  563. if (!cpu_class_is_omap2())
  564. return;
  565. spin_lock_irqsave(&dma_chan_lock, flags);
  566. val = p->dma_read(IRQENABLE_L0, lch);
  567. val &= ~(1 << lch);
  568. p->dma_write(val, IRQENABLE_L0, lch);
  569. spin_unlock_irqrestore(&dma_chan_lock, flags);
  570. }
  571. int omap_request_dma(int dev_id, const char *dev_name,
  572. void (*callback)(int lch, u16 ch_status, void *data),
  573. void *data, int *dma_ch_out)
  574. {
  575. int ch, free_ch = -1;
  576. unsigned long flags;
  577. struct omap_dma_lch *chan;
  578. spin_lock_irqsave(&dma_chan_lock, flags);
  579. for (ch = 0; ch < dma_chan_count; ch++) {
  580. if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
  581. free_ch = ch;
  582. if (dev_id == 0)
  583. break;
  584. }
  585. }
  586. if (free_ch == -1) {
  587. spin_unlock_irqrestore(&dma_chan_lock, flags);
  588. return -EBUSY;
  589. }
  590. chan = dma_chan + free_ch;
  591. chan->dev_id = dev_id;
  592. if (p->clear_lch_regs)
  593. p->clear_lch_regs(free_ch);
  594. if (cpu_class_is_omap2())
  595. omap_clear_dma(free_ch);
  596. spin_unlock_irqrestore(&dma_chan_lock, flags);
  597. chan->dev_name = dev_name;
  598. chan->callback = callback;
  599. chan->data = data;
  600. chan->flags = 0;
  601. #ifndef CONFIG_ARCH_OMAP1
  602. if (cpu_class_is_omap2()) {
  603. chan->chain_id = -1;
  604. chan->next_linked_ch = -1;
  605. }
  606. #endif
  607. chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
  608. if (cpu_class_is_omap1())
  609. chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
  610. else if (cpu_class_is_omap2())
  611. chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
  612. OMAP2_DMA_TRANS_ERR_IRQ;
  613. if (cpu_is_omap16xx()) {
  614. /* If the sync device is set, configure it dynamically. */
  615. if (dev_id != 0) {
  616. set_gdma_dev(free_ch + 1, dev_id);
  617. dev_id = free_ch + 1;
  618. }
  619. /*
  620. * Disable the 1510 compatibility mode and set the sync device
  621. * id.
  622. */
  623. p->dma_write(dev_id | (1 << 10), CCR, free_ch);
  624. } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
  625. p->dma_write(dev_id, CCR, free_ch);
  626. }
  627. if (cpu_class_is_omap2()) {
  628. omap2_enable_irq_lch(free_ch);
  629. omap_enable_channel_irq(free_ch);
  630. /* Clear the CSR register and IRQ status register */
  631. p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
  632. p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
  633. }
  634. *dma_ch_out = free_ch;
  635. return 0;
  636. }
  637. EXPORT_SYMBOL(omap_request_dma);
  638. void omap_free_dma(int lch)
  639. {
  640. unsigned long flags;
  641. if (dma_chan[lch].dev_id == -1) {
  642. pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
  643. lch);
  644. return;
  645. }
  646. if (cpu_class_is_omap1()) {
  647. /* Disable all DMA interrupts for the channel. */
  648. p->dma_write(0, CICR, lch);
  649. /* Make sure the DMA transfer is stopped. */
  650. p->dma_write(0, CCR, lch);
  651. }
  652. if (cpu_class_is_omap2()) {
  653. omap2_disable_irq_lch(lch);
  654. /* Clear the CSR register and IRQ status register */
  655. p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
  656. p->dma_write(1 << lch, IRQSTATUS_L0, lch);
  657. /* Disable all DMA interrupts for the channel. */
  658. p->dma_write(0, CICR, lch);
  659. /* Make sure the DMA transfer is stopped. */
  660. p->dma_write(0, CCR, lch);
  661. omap_clear_dma(lch);
  662. }
  663. spin_lock_irqsave(&dma_chan_lock, flags);
  664. dma_chan[lch].dev_id = -1;
  665. dma_chan[lch].next_lch = -1;
  666. dma_chan[lch].callback = NULL;
  667. spin_unlock_irqrestore(&dma_chan_lock, flags);
  668. }
  669. EXPORT_SYMBOL(omap_free_dma);
  670. /**
  671. * @brief omap_dma_set_global_params : Set global priority settings for dma
  672. *
  673. * @param arb_rate
  674. * @param max_fifo_depth
  675. * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
  676. * DMA_THREAD_RESERVE_ONET
  677. * DMA_THREAD_RESERVE_TWOT
  678. * DMA_THREAD_RESERVE_THREET
  679. */
  680. void
  681. omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
  682. {
  683. u32 reg;
  684. if (!cpu_class_is_omap2()) {
  685. printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
  686. return;
  687. }
  688. if (max_fifo_depth == 0)
  689. max_fifo_depth = 1;
  690. if (arb_rate == 0)
  691. arb_rate = 1;
  692. reg = 0xff & max_fifo_depth;
  693. reg |= (0x3 & tparams) << 12;
  694. reg |= (arb_rate & 0xff) << 16;
  695. p->dma_write(reg, GCR, 0);
  696. }
  697. EXPORT_SYMBOL(omap_dma_set_global_params);
  698. /**
  699. * @brief omap_dma_set_prio_lch : Set channel wise priority settings
  700. *
  701. * @param lch
  702. * @param read_prio - Read priority
  703. * @param write_prio - Write priority
  704. * Both of the above can be set with one of the following values :
  705. * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
  706. */
  707. int
  708. omap_dma_set_prio_lch(int lch, unsigned char read_prio,
  709. unsigned char write_prio)
  710. {
  711. u32 l;
  712. if (unlikely((lch < 0 || lch >= dma_lch_count))) {
  713. printk(KERN_ERR "Invalid channel id\n");
  714. return -EINVAL;
  715. }
  716. l = p->dma_read(CCR, lch);
  717. l &= ~((1 << 6) | (1 << 26));
  718. if (cpu_class_is_omap2() && !cpu_is_omap242x())
  719. l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
  720. else
  721. l |= ((read_prio & 0x1) << 6);
  722. p->dma_write(l, CCR, lch);
  723. return 0;
  724. }
  725. EXPORT_SYMBOL(omap_dma_set_prio_lch);
  726. /*
  727. * Clears any DMA state so the DMA engine is ready to restart with new buffers
  728. * through omap_start_dma(). Any buffers in flight are discarded.
  729. */
  730. void omap_clear_dma(int lch)
  731. {
  732. unsigned long flags;
  733. local_irq_save(flags);
  734. p->clear_dma(lch);
  735. local_irq_restore(flags);
  736. }
  737. EXPORT_SYMBOL(omap_clear_dma);
  738. void omap_start_dma(int lch)
  739. {
  740. u32 l;
  741. /*
  742. * The CPC/CDAC register needs to be initialized to zero
  743. * before starting dma transfer.
  744. */
  745. if (cpu_is_omap15xx())
  746. p->dma_write(0, CPC, lch);
  747. else
  748. p->dma_write(0, CDAC, lch);
  749. if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
  750. int next_lch, cur_lch;
  751. char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
  752. dma_chan_link_map[lch] = 1;
  753. /* Set the link register of the first channel */
  754. enable_lnk(lch);
  755. memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
  756. cur_lch = dma_chan[lch].next_lch;
  757. do {
  758. next_lch = dma_chan[cur_lch].next_lch;
  759. /* The loop case: we've been here already */
  760. if (dma_chan_link_map[cur_lch])
  761. break;
  762. /* Mark the current channel */
  763. dma_chan_link_map[cur_lch] = 1;
  764. enable_lnk(cur_lch);
  765. omap_enable_channel_irq(cur_lch);
  766. cur_lch = next_lch;
  767. } while (next_lch != -1);
  768. } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
  769. p->dma_write(lch, CLNK_CTRL, lch);
  770. omap_enable_channel_irq(lch);
  771. l = p->dma_read(CCR, lch);
  772. if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
  773. l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
  774. l |= OMAP_DMA_CCR_EN;
  775. /*
  776. * As dma_write() uses IO accessors which are weakly ordered, there
  777. * is no guarantee that data in coherent DMA memory will be visible
  778. * to the DMA device. Add a memory barrier here to ensure that any
  779. * such data is visible prior to enabling DMA.
  780. */
  781. mb();
  782. p->dma_write(l, CCR, lch);
  783. dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
  784. }
  785. EXPORT_SYMBOL(omap_start_dma);
  786. void omap_stop_dma(int lch)
  787. {
  788. u32 l;
  789. /* Disable all interrupts on the channel */
  790. if (cpu_class_is_omap1())
  791. p->dma_write(0, CICR, lch);
  792. l = p->dma_read(CCR, lch);
  793. if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
  794. (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
  795. int i = 0;
  796. u32 sys_cf;
  797. /* Configure No-Standby */
  798. l = p->dma_read(OCP_SYSCONFIG, lch);
  799. sys_cf = l;
  800. l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
  801. l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
  802. p->dma_write(l , OCP_SYSCONFIG, 0);
  803. l = p->dma_read(CCR, lch);
  804. l &= ~OMAP_DMA_CCR_EN;
  805. p->dma_write(l, CCR, lch);
  806. /* Wait for sDMA FIFO drain */
  807. l = p->dma_read(CCR, lch);
  808. while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
  809. OMAP_DMA_CCR_WR_ACTIVE))) {
  810. udelay(5);
  811. i++;
  812. l = p->dma_read(CCR, lch);
  813. }
  814. if (i >= 100)
  815. printk(KERN_ERR "DMA drain did not complete on "
  816. "lch %d\n", lch);
  817. /* Restore OCP_SYSCONFIG */
  818. p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
  819. } else {
  820. l &= ~OMAP_DMA_CCR_EN;
  821. p->dma_write(l, CCR, lch);
  822. }
  823. /*
  824. * Ensure that data transferred by DMA is visible to any access
  825. * after DMA has been disabled. This is important for coherent
  826. * DMA regions.
  827. */
  828. mb();
  829. if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
  830. int next_lch, cur_lch = lch;
  831. char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
  832. memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
  833. do {
  834. /* The loop case: we've been here already */
  835. if (dma_chan_link_map[cur_lch])
  836. break;
  837. /* Mark the current channel */
  838. dma_chan_link_map[cur_lch] = 1;
  839. disable_lnk(cur_lch);
  840. next_lch = dma_chan[cur_lch].next_lch;
  841. cur_lch = next_lch;
  842. } while (next_lch != -1);
  843. }
  844. dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
  845. }
  846. EXPORT_SYMBOL(omap_stop_dma);
  847. /*
  848. * Allows changing the DMA callback function or data. This may be needed if
  849. * the driver shares a single DMA channel for multiple dma triggers.
  850. */
  851. int omap_set_dma_callback(int lch,
  852. void (*callback)(int lch, u16 ch_status, void *data),
  853. void *data)
  854. {
  855. unsigned long flags;
  856. if (lch < 0)
  857. return -ENODEV;
  858. spin_lock_irqsave(&dma_chan_lock, flags);
  859. if (dma_chan[lch].dev_id == -1) {
  860. printk(KERN_ERR "DMA callback for not set for free channel\n");
  861. spin_unlock_irqrestore(&dma_chan_lock, flags);
  862. return -EINVAL;
  863. }
  864. dma_chan[lch].callback = callback;
  865. dma_chan[lch].data = data;
  866. spin_unlock_irqrestore(&dma_chan_lock, flags);
  867. return 0;
  868. }
  869. EXPORT_SYMBOL(omap_set_dma_callback);
  870. /*
  871. * Returns current physical source address for the given DMA channel.
  872. * If the channel is running the caller must disable interrupts prior calling
  873. * this function and process the returned value before re-enabling interrupt to
  874. * prevent races with the interrupt handler. Note that in continuous mode there
  875. * is a chance for CSSA_L register overflow between the two reads resulting
  876. * in incorrect return value.
  877. */
  878. dma_addr_t omap_get_dma_src_pos(int lch)
  879. {
  880. dma_addr_t offset = 0;
  881. if (cpu_is_omap15xx())
  882. offset = p->dma_read(CPC, lch);
  883. else
  884. offset = p->dma_read(CSAC, lch);
  885. if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
  886. offset = p->dma_read(CSAC, lch);
  887. if (!cpu_is_omap15xx()) {
  888. /*
  889. * CDAC == 0 indicates that the DMA transfer on the channel has
  890. * not been started (no data has been transferred so far).
  891. * Return the programmed source start address in this case.
  892. */
  893. if (likely(p->dma_read(CDAC, lch)))
  894. offset = p->dma_read(CSAC, lch);
  895. else
  896. offset = p->dma_read(CSSA, lch);
  897. }
  898. if (cpu_class_is_omap1())
  899. offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
  900. return offset;
  901. }
  902. EXPORT_SYMBOL(omap_get_dma_src_pos);
  903. /*
  904. * Returns current physical destination address for the given DMA channel.
  905. * If the channel is running the caller must disable interrupts prior calling
  906. * this function and process the returned value before re-enabling interrupt to
  907. * prevent races with the interrupt handler. Note that in continuous mode there
  908. * is a chance for CDSA_L register overflow between the two reads resulting
  909. * in incorrect return value.
  910. */
  911. dma_addr_t omap_get_dma_dst_pos(int lch)
  912. {
  913. dma_addr_t offset = 0;
  914. if (cpu_is_omap15xx())
  915. offset = p->dma_read(CPC, lch);
  916. else
  917. offset = p->dma_read(CDAC, lch);
  918. /*
  919. * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
  920. * read before the DMA controller finished disabling the channel.
  921. */
  922. if (!cpu_is_omap15xx() && offset == 0) {
  923. offset = p->dma_read(CDAC, lch);
  924. /*
  925. * CDAC == 0 indicates that the DMA transfer on the channel has
  926. * not been started (no data has been transferred so far).
  927. * Return the programmed destination start address in this case.
  928. */
  929. if (unlikely(!offset))
  930. offset = p->dma_read(CDSA, lch);
  931. }
  932. if (cpu_class_is_omap1())
  933. offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
  934. return offset;
  935. }
  936. EXPORT_SYMBOL(omap_get_dma_dst_pos);
  937. int omap_get_dma_active_status(int lch)
  938. {
  939. return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
  940. }
  941. EXPORT_SYMBOL(omap_get_dma_active_status);
  942. int omap_dma_running(void)
  943. {
  944. int lch;
  945. if (cpu_class_is_omap1())
  946. if (omap_lcd_dma_running())
  947. return 1;
  948. for (lch = 0; lch < dma_chan_count; lch++)
  949. if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
  950. return 1;
  951. return 0;
  952. }
  953. /*
  954. * lch_queue DMA will start right after lch_head one is finished.
  955. * For this DMA link to start, you still need to start (see omap_start_dma)
  956. * the first one. That will fire up the entire queue.
  957. */
  958. void omap_dma_link_lch(int lch_head, int lch_queue)
  959. {
  960. if (omap_dma_in_1510_mode()) {
  961. if (lch_head == lch_queue) {
  962. p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
  963. CCR, lch_head);
  964. return;
  965. }
  966. printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
  967. BUG();
  968. return;
  969. }
  970. if ((dma_chan[lch_head].dev_id == -1) ||
  971. (dma_chan[lch_queue].dev_id == -1)) {
  972. printk(KERN_ERR "omap_dma: trying to link "
  973. "non requested channels\n");
  974. dump_stack();
  975. }
  976. dma_chan[lch_head].next_lch = lch_queue;
  977. }
  978. EXPORT_SYMBOL(omap_dma_link_lch);
  979. /*
  980. * Once the DMA queue is stopped, we can destroy it.
  981. */
  982. void omap_dma_unlink_lch(int lch_head, int lch_queue)
  983. {
  984. if (omap_dma_in_1510_mode()) {
  985. if (lch_head == lch_queue) {
  986. p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
  987. CCR, lch_head);
  988. return;
  989. }
  990. printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
  991. BUG();
  992. return;
  993. }
  994. if (dma_chan[lch_head].next_lch != lch_queue ||
  995. dma_chan[lch_head].next_lch == -1) {
  996. printk(KERN_ERR "omap_dma: trying to unlink "
  997. "non linked channels\n");
  998. dump_stack();
  999. }
  1000. if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
  1001. (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
  1002. printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
  1003. "before unlinking\n");
  1004. dump_stack();
  1005. }
  1006. dma_chan[lch_head].next_lch = -1;
  1007. }
  1008. EXPORT_SYMBOL(omap_dma_unlink_lch);
  1009. #ifndef CONFIG_ARCH_OMAP1
  1010. /* Create chain of DMA channesls */
  1011. static void create_dma_lch_chain(int lch_head, int lch_queue)
  1012. {
  1013. u32 l;
  1014. /* Check if this is the first link in chain */
  1015. if (dma_chan[lch_head].next_linked_ch == -1) {
  1016. dma_chan[lch_head].next_linked_ch = lch_queue;
  1017. dma_chan[lch_head].prev_linked_ch = lch_queue;
  1018. dma_chan[lch_queue].next_linked_ch = lch_head;
  1019. dma_chan[lch_queue].prev_linked_ch = lch_head;
  1020. }
  1021. /* a link exists, link the new channel in circular chain */
  1022. else {
  1023. dma_chan[lch_queue].next_linked_ch =
  1024. dma_chan[lch_head].next_linked_ch;
  1025. dma_chan[lch_queue].prev_linked_ch = lch_head;
  1026. dma_chan[lch_head].next_linked_ch = lch_queue;
  1027. dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
  1028. lch_queue;
  1029. }
  1030. l = p->dma_read(CLNK_CTRL, lch_head);
  1031. l &= ~(0x1f);
  1032. l |= lch_queue;
  1033. p->dma_write(l, CLNK_CTRL, lch_head);
  1034. l = p->dma_read(CLNK_CTRL, lch_queue);
  1035. l &= ~(0x1f);
  1036. l |= (dma_chan[lch_queue].next_linked_ch);
  1037. p->dma_write(l, CLNK_CTRL, lch_queue);
  1038. }
  1039. /**
  1040. * @brief omap_request_dma_chain : Request a chain of DMA channels
  1041. *
  1042. * @param dev_id - Device id using the dma channel
  1043. * @param dev_name - Device name
  1044. * @param callback - Call back function
  1045. * @chain_id -
  1046. * @no_of_chans - Number of channels requested
  1047. * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
  1048. * OMAP_DMA_DYNAMIC_CHAIN
  1049. * @params - Channel parameters
  1050. *
  1051. * @return - Success : 0
  1052. * Failure: -EINVAL/-ENOMEM
  1053. */
  1054. int omap_request_dma_chain(int dev_id, const char *dev_name,
  1055. void (*callback) (int lch, u16 ch_status,
  1056. void *data),
  1057. int *chain_id, int no_of_chans, int chain_mode,
  1058. struct omap_dma_channel_params params)
  1059. {
  1060. int *channels;
  1061. int i, err;
  1062. /* Is the chain mode valid ? */
  1063. if (chain_mode != OMAP_DMA_STATIC_CHAIN
  1064. && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
  1065. printk(KERN_ERR "Invalid chain mode requested\n");
  1066. return -EINVAL;
  1067. }
  1068. if (unlikely((no_of_chans < 1
  1069. || no_of_chans > dma_lch_count))) {
  1070. printk(KERN_ERR "Invalid Number of channels requested\n");
  1071. return -EINVAL;
  1072. }
  1073. /*
  1074. * Allocate a queue to maintain the status of the channels
  1075. * in the chain
  1076. */
  1077. channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
  1078. if (channels == NULL) {
  1079. printk(KERN_ERR "omap_dma: No memory for channel queue\n");
  1080. return -ENOMEM;
  1081. }
  1082. /* request and reserve DMA channels for the chain */
  1083. for (i = 0; i < no_of_chans; i++) {
  1084. err = omap_request_dma(dev_id, dev_name,
  1085. callback, NULL, &channels[i]);
  1086. if (err < 0) {
  1087. int j;
  1088. for (j = 0; j < i; j++)
  1089. omap_free_dma(channels[j]);
  1090. kfree(channels);
  1091. printk(KERN_ERR "omap_dma: Request failed %d\n", err);
  1092. return err;
  1093. }
  1094. dma_chan[channels[i]].prev_linked_ch = -1;
  1095. dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
  1096. /*
  1097. * Allowing client drivers to set common parameters now,
  1098. * so that later only relevant (src_start, dest_start
  1099. * and element count) can be set
  1100. */
  1101. omap_set_dma_params(channels[i], &params);
  1102. }
  1103. *chain_id = channels[0];
  1104. dma_linked_lch[*chain_id].linked_dmach_q = channels;
  1105. dma_linked_lch[*chain_id].chain_mode = chain_mode;
  1106. dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
  1107. dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
  1108. for (i = 0; i < no_of_chans; i++)
  1109. dma_chan[channels[i]].chain_id = *chain_id;
  1110. /* Reset the Queue pointers */
  1111. OMAP_DMA_CHAIN_QINIT(*chain_id);
  1112. /* Set up the chain */
  1113. if (no_of_chans == 1)
  1114. create_dma_lch_chain(channels[0], channels[0]);
  1115. else {
  1116. for (i = 0; i < (no_of_chans - 1); i++)
  1117. create_dma_lch_chain(channels[i], channels[i + 1]);
  1118. }
  1119. return 0;
  1120. }
  1121. EXPORT_SYMBOL(omap_request_dma_chain);
  1122. /**
  1123. * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
  1124. * params after setting it. Dont do this while dma is running!!
  1125. *
  1126. * @param chain_id - Chained logical channel id.
  1127. * @param params
  1128. *
  1129. * @return - Success : 0
  1130. * Failure : -EINVAL
  1131. */
  1132. int omap_modify_dma_chain_params(int chain_id,
  1133. struct omap_dma_channel_params params)
  1134. {
  1135. int *channels;
  1136. u32 i;
  1137. /* Check for input params */
  1138. if (unlikely((chain_id < 0
  1139. || chain_id >= dma_lch_count))) {
  1140. printk(KERN_ERR "Invalid chain id\n");
  1141. return -EINVAL;
  1142. }
  1143. /* Check if the chain exists */
  1144. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1145. printk(KERN_ERR "Chain doesn't exists\n");
  1146. return -EINVAL;
  1147. }
  1148. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1149. for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
  1150. /*
  1151. * Allowing client drivers to set common parameters now,
  1152. * so that later only relevant (src_start, dest_start
  1153. * and element count) can be set
  1154. */
  1155. omap_set_dma_params(channels[i], &params);
  1156. }
  1157. return 0;
  1158. }
  1159. EXPORT_SYMBOL(omap_modify_dma_chain_params);
  1160. /**
  1161. * @brief omap_free_dma_chain - Free all the logical channels in a chain.
  1162. *
  1163. * @param chain_id
  1164. *
  1165. * @return - Success : 0
  1166. * Failure : -EINVAL
  1167. */
  1168. int omap_free_dma_chain(int chain_id)
  1169. {
  1170. int *channels;
  1171. u32 i;
  1172. /* Check for input params */
  1173. if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
  1174. printk(KERN_ERR "Invalid chain id\n");
  1175. return -EINVAL;
  1176. }
  1177. /* Check if the chain exists */
  1178. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1179. printk(KERN_ERR "Chain doesn't exists\n");
  1180. return -EINVAL;
  1181. }
  1182. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1183. for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
  1184. dma_chan[channels[i]].next_linked_ch = -1;
  1185. dma_chan[channels[i]].prev_linked_ch = -1;
  1186. dma_chan[channels[i]].chain_id = -1;
  1187. dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
  1188. omap_free_dma(channels[i]);
  1189. }
  1190. kfree(channels);
  1191. dma_linked_lch[chain_id].linked_dmach_q = NULL;
  1192. dma_linked_lch[chain_id].chain_mode = -1;
  1193. dma_linked_lch[chain_id].chain_state = -1;
  1194. return (0);
  1195. }
  1196. EXPORT_SYMBOL(omap_free_dma_chain);
  1197. /**
  1198. * @brief omap_dma_chain_status - Check if the chain is in
  1199. * active / inactive state.
  1200. * @param chain_id
  1201. *
  1202. * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
  1203. * Failure : -EINVAL
  1204. */
  1205. int omap_dma_chain_status(int chain_id)
  1206. {
  1207. /* Check for input params */
  1208. if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
  1209. printk(KERN_ERR "Invalid chain id\n");
  1210. return -EINVAL;
  1211. }
  1212. /* Check if the chain exists */
  1213. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1214. printk(KERN_ERR "Chain doesn't exists\n");
  1215. return -EINVAL;
  1216. }
  1217. pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
  1218. dma_linked_lch[chain_id].q_count);
  1219. if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
  1220. return OMAP_DMA_CHAIN_INACTIVE;
  1221. return OMAP_DMA_CHAIN_ACTIVE;
  1222. }
  1223. EXPORT_SYMBOL(omap_dma_chain_status);
  1224. /**
  1225. * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
  1226. * set the params and start the transfer.
  1227. *
  1228. * @param chain_id
  1229. * @param src_start - buffer start address
  1230. * @param dest_start - Dest address
  1231. * @param elem_count
  1232. * @param frame_count
  1233. * @param callbk_data - channel callback parameter data.
  1234. *
  1235. * @return - Success : 0
  1236. * Failure: -EINVAL/-EBUSY
  1237. */
  1238. int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
  1239. int elem_count, int frame_count, void *callbk_data)
  1240. {
  1241. int *channels;
  1242. u32 l, lch;
  1243. int start_dma = 0;
  1244. /*
  1245. * if buffer size is less than 1 then there is
  1246. * no use of starting the chain
  1247. */
  1248. if (elem_count < 1) {
  1249. printk(KERN_ERR "Invalid buffer size\n");
  1250. return -EINVAL;
  1251. }
  1252. /* Check for input params */
  1253. if (unlikely((chain_id < 0
  1254. || chain_id >= dma_lch_count))) {
  1255. printk(KERN_ERR "Invalid chain id\n");
  1256. return -EINVAL;
  1257. }
  1258. /* Check if the chain exists */
  1259. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1260. printk(KERN_ERR "Chain doesn't exist\n");
  1261. return -EINVAL;
  1262. }
  1263. /* Check if all the channels in chain are in use */
  1264. if (OMAP_DMA_CHAIN_QFULL(chain_id))
  1265. return -EBUSY;
  1266. /* Frame count may be negative in case of indexed transfers */
  1267. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1268. /* Get a free channel */
  1269. lch = channels[dma_linked_lch[chain_id].q_tail];
  1270. /* Store the callback data */
  1271. dma_chan[lch].data = callbk_data;
  1272. /* Increment the q_tail */
  1273. OMAP_DMA_CHAIN_INCQTAIL(chain_id);
  1274. /* Set the params to the free channel */
  1275. if (src_start != 0)
  1276. p->dma_write(src_start, CSSA, lch);
  1277. if (dest_start != 0)
  1278. p->dma_write(dest_start, CDSA, lch);
  1279. /* Write the buffer size */
  1280. p->dma_write(elem_count, CEN, lch);
  1281. p->dma_write(frame_count, CFN, lch);
  1282. /*
  1283. * If the chain is dynamically linked,
  1284. * then we may have to start the chain if its not active
  1285. */
  1286. if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
  1287. /*
  1288. * In Dynamic chain, if the chain is not started,
  1289. * queue the channel
  1290. */
  1291. if (dma_linked_lch[chain_id].chain_state ==
  1292. DMA_CHAIN_NOTSTARTED) {
  1293. /* Enable the link in previous channel */
  1294. if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
  1295. DMA_CH_QUEUED)
  1296. enable_lnk(dma_chan[lch].prev_linked_ch);
  1297. dma_chan[lch].state = DMA_CH_QUEUED;
  1298. }
  1299. /*
  1300. * Chain is already started, make sure its active,
  1301. * if not then start the chain
  1302. */
  1303. else {
  1304. start_dma = 1;
  1305. if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
  1306. DMA_CH_STARTED) {
  1307. enable_lnk(dma_chan[lch].prev_linked_ch);
  1308. dma_chan[lch].state = DMA_CH_QUEUED;
  1309. start_dma = 0;
  1310. if (0 == ((1 << 7) & p->dma_read(
  1311. CCR, dma_chan[lch].prev_linked_ch))) {
  1312. disable_lnk(dma_chan[lch].
  1313. prev_linked_ch);
  1314. pr_debug("\n prev ch is stopped\n");
  1315. start_dma = 1;
  1316. }
  1317. }
  1318. else if (dma_chan[dma_chan[lch].prev_linked_ch].state
  1319. == DMA_CH_QUEUED) {
  1320. enable_lnk(dma_chan[lch].prev_linked_ch);
  1321. dma_chan[lch].state = DMA_CH_QUEUED;
  1322. start_dma = 0;
  1323. }
  1324. omap_enable_channel_irq(lch);
  1325. l = p->dma_read(CCR, lch);
  1326. if ((0 == (l & (1 << 24))))
  1327. l &= ~(1 << 25);
  1328. else
  1329. l |= (1 << 25);
  1330. if (start_dma == 1) {
  1331. if (0 == (l & (1 << 7))) {
  1332. l |= (1 << 7);
  1333. dma_chan[lch].state = DMA_CH_STARTED;
  1334. pr_debug("starting %d\n", lch);
  1335. p->dma_write(l, CCR, lch);
  1336. } else
  1337. start_dma = 0;
  1338. } else {
  1339. if (0 == (l & (1 << 7)))
  1340. p->dma_write(l, CCR, lch);
  1341. }
  1342. dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
  1343. }
  1344. }
  1345. return 0;
  1346. }
  1347. EXPORT_SYMBOL(omap_dma_chain_a_transfer);
  1348. /**
  1349. * @brief omap_start_dma_chain_transfers - Start the chain
  1350. *
  1351. * @param chain_id
  1352. *
  1353. * @return - Success : 0
  1354. * Failure : -EINVAL/-EBUSY
  1355. */
  1356. int omap_start_dma_chain_transfers(int chain_id)
  1357. {
  1358. int *channels;
  1359. u32 l, i;
  1360. if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
  1361. printk(KERN_ERR "Invalid chain id\n");
  1362. return -EINVAL;
  1363. }
  1364. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1365. if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
  1366. printk(KERN_ERR "Chain is already started\n");
  1367. return -EBUSY;
  1368. }
  1369. if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
  1370. for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
  1371. i++) {
  1372. enable_lnk(channels[i]);
  1373. omap_enable_channel_irq(channels[i]);
  1374. }
  1375. } else {
  1376. omap_enable_channel_irq(channels[0]);
  1377. }
  1378. l = p->dma_read(CCR, channels[0]);
  1379. l |= (1 << 7);
  1380. dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
  1381. dma_chan[channels[0]].state = DMA_CH_STARTED;
  1382. if ((0 == (l & (1 << 24))))
  1383. l &= ~(1 << 25);
  1384. else
  1385. l |= (1 << 25);
  1386. p->dma_write(l, CCR, channels[0]);
  1387. dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
  1388. return 0;
  1389. }
  1390. EXPORT_SYMBOL(omap_start_dma_chain_transfers);
  1391. /**
  1392. * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
  1393. *
  1394. * @param chain_id
  1395. *
  1396. * @return - Success : 0
  1397. * Failure : EINVAL
  1398. */
  1399. int omap_stop_dma_chain_transfers(int chain_id)
  1400. {
  1401. int *channels;
  1402. u32 l, i;
  1403. u32 sys_cf = 0;
  1404. /* Check for input params */
  1405. if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
  1406. printk(KERN_ERR "Invalid chain id\n");
  1407. return -EINVAL;
  1408. }
  1409. /* Check if the chain exists */
  1410. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1411. printk(KERN_ERR "Chain doesn't exists\n");
  1412. return -EINVAL;
  1413. }
  1414. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1415. if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
  1416. sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
  1417. l = sys_cf;
  1418. /* Middle mode reg set no Standby */
  1419. l &= ~((1 << 12)|(1 << 13));
  1420. p->dma_write(l, OCP_SYSCONFIG, 0);
  1421. }
  1422. for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
  1423. /* Stop the Channel transmission */
  1424. l = p->dma_read(CCR, channels[i]);
  1425. l &= ~(1 << 7);
  1426. p->dma_write(l, CCR, channels[i]);
  1427. /* Disable the link in all the channels */
  1428. disable_lnk(channels[i]);
  1429. dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
  1430. }
  1431. dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
  1432. /* Reset the Queue pointers */
  1433. OMAP_DMA_CHAIN_QINIT(chain_id);
  1434. if (IS_DMA_ERRATA(DMA_ERRATA_i88))
  1435. p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
  1436. return 0;
  1437. }
  1438. EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
  1439. /* Get the index of the ongoing DMA in chain */
  1440. /**
  1441. * @brief omap_get_dma_chain_index - Get the element and frame index
  1442. * of the ongoing DMA in chain
  1443. *
  1444. * @param chain_id
  1445. * @param ei - Element index
  1446. * @param fi - Frame index
  1447. *
  1448. * @return - Success : 0
  1449. * Failure : -EINVAL
  1450. */
  1451. int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
  1452. {
  1453. int lch;
  1454. int *channels;
  1455. /* Check for input params */
  1456. if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
  1457. printk(KERN_ERR "Invalid chain id\n");
  1458. return -EINVAL;
  1459. }
  1460. /* Check if the chain exists */
  1461. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1462. printk(KERN_ERR "Chain doesn't exists\n");
  1463. return -EINVAL;
  1464. }
  1465. if ((!ei) || (!fi))
  1466. return -EINVAL;
  1467. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1468. /* Get the current channel */
  1469. lch = channels[dma_linked_lch[chain_id].q_head];
  1470. *ei = p->dma_read(CCEN, lch);
  1471. *fi = p->dma_read(CCFN, lch);
  1472. return 0;
  1473. }
  1474. EXPORT_SYMBOL(omap_get_dma_chain_index);
  1475. /**
  1476. * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
  1477. * ongoing DMA in chain
  1478. *
  1479. * @param chain_id
  1480. *
  1481. * @return - Success : Destination position
  1482. * Failure : -EINVAL
  1483. */
  1484. int omap_get_dma_chain_dst_pos(int chain_id)
  1485. {
  1486. int lch;
  1487. int *channels;
  1488. /* Check for input params */
  1489. if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
  1490. printk(KERN_ERR "Invalid chain id\n");
  1491. return -EINVAL;
  1492. }
  1493. /* Check if the chain exists */
  1494. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1495. printk(KERN_ERR "Chain doesn't exists\n");
  1496. return -EINVAL;
  1497. }
  1498. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1499. /* Get the current channel */
  1500. lch = channels[dma_linked_lch[chain_id].q_head];
  1501. return p->dma_read(CDAC, lch);
  1502. }
  1503. EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
  1504. /**
  1505. * @brief omap_get_dma_chain_src_pos - Get the source position
  1506. * of the ongoing DMA in chain
  1507. * @param chain_id
  1508. *
  1509. * @return - Success : Destination position
  1510. * Failure : -EINVAL
  1511. */
  1512. int omap_get_dma_chain_src_pos(int chain_id)
  1513. {
  1514. int lch;
  1515. int *channels;
  1516. /* Check for input params */
  1517. if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
  1518. printk(KERN_ERR "Invalid chain id\n");
  1519. return -EINVAL;
  1520. }
  1521. /* Check if the chain exists */
  1522. if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
  1523. printk(KERN_ERR "Chain doesn't exists\n");
  1524. return -EINVAL;
  1525. }
  1526. channels = dma_linked_lch[chain_id].linked_dmach_q;
  1527. /* Get the current channel */
  1528. lch = channels[dma_linked_lch[chain_id].q_head];
  1529. return p->dma_read(CSAC, lch);
  1530. }
  1531. EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
  1532. #endif /* ifndef CONFIG_ARCH_OMAP1 */
  1533. /*----------------------------------------------------------------------------*/
  1534. #ifdef CONFIG_ARCH_OMAP1
  1535. static int omap1_dma_handle_ch(int ch)
  1536. {
  1537. u32 csr;
  1538. if (enable_1510_mode && ch >= 6) {
  1539. csr = dma_chan[ch].saved_csr;
  1540. dma_chan[ch].saved_csr = 0;
  1541. } else
  1542. csr = p->dma_read(CSR, ch);
  1543. if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
  1544. dma_chan[ch + 6].saved_csr = csr >> 7;
  1545. csr &= 0x7f;
  1546. }
  1547. if ((csr & 0x3f) == 0)
  1548. return 0;
  1549. if (unlikely(dma_chan[ch].dev_id == -1)) {
  1550. printk(KERN_WARNING "Spurious interrupt from DMA channel "
  1551. "%d (CSR %04x)\n", ch, csr);
  1552. return 0;
  1553. }
  1554. if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
  1555. printk(KERN_WARNING "DMA timeout with device %d\n",
  1556. dma_chan[ch].dev_id);
  1557. if (unlikely(csr & OMAP_DMA_DROP_IRQ))
  1558. printk(KERN_WARNING "DMA synchronization event drop occurred "
  1559. "with device %d\n", dma_chan[ch].dev_id);
  1560. if (likely(csr & OMAP_DMA_BLOCK_IRQ))
  1561. dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
  1562. if (likely(dma_chan[ch].callback != NULL))
  1563. dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
  1564. return 1;
  1565. }
  1566. static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
  1567. {
  1568. int ch = ((int) dev_id) - 1;
  1569. int handled = 0;
  1570. for (;;) {
  1571. int handled_now = 0;
  1572. handled_now += omap1_dma_handle_ch(ch);
  1573. if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
  1574. handled_now += omap1_dma_handle_ch(ch + 6);
  1575. if (!handled_now)
  1576. break;
  1577. handled += handled_now;
  1578. }
  1579. return handled ? IRQ_HANDLED : IRQ_NONE;
  1580. }
  1581. #else
  1582. #define omap1_dma_irq_handler NULL
  1583. #endif
  1584. #ifdef CONFIG_ARCH_OMAP2PLUS
  1585. static int omap2_dma_handle_ch(int ch)
  1586. {
  1587. u32 status = p->dma_read(CSR, ch);
  1588. if (!status) {
  1589. if (printk_ratelimit())
  1590. printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
  1591. ch);
  1592. p->dma_write(1 << ch, IRQSTATUS_L0, ch);
  1593. return 0;
  1594. }
  1595. if (unlikely(dma_chan[ch].dev_id == -1)) {
  1596. if (printk_ratelimit())
  1597. printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
  1598. "channel %d\n", status, ch);
  1599. return 0;
  1600. }
  1601. if (unlikely(status & OMAP_DMA_DROP_IRQ))
  1602. printk(KERN_INFO
  1603. "DMA synchronization event drop occurred with device "
  1604. "%d\n", dma_chan[ch].dev_id);
  1605. if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
  1606. printk(KERN_INFO "DMA transaction error with device %d\n",
  1607. dma_chan[ch].dev_id);
  1608. if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
  1609. u32 ccr;
  1610. ccr = p->dma_read(CCR, ch);
  1611. ccr &= ~OMAP_DMA_CCR_EN;
  1612. p->dma_write(ccr, CCR, ch);
  1613. dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
  1614. }
  1615. }
  1616. if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
  1617. printk(KERN_INFO "DMA secure error with device %d\n",
  1618. dma_chan[ch].dev_id);
  1619. if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
  1620. printk(KERN_INFO "DMA misaligned error with device %d\n",
  1621. dma_chan[ch].dev_id);
  1622. p->dma_write(status, CSR, ch);
  1623. p->dma_write(1 << ch, IRQSTATUS_L0, ch);
  1624. /* read back the register to flush the write */
  1625. p->dma_read(IRQSTATUS_L0, ch);
  1626. /* If the ch is not chained then chain_id will be -1 */
  1627. if (dma_chan[ch].chain_id != -1) {
  1628. int chain_id = dma_chan[ch].chain_id;
  1629. dma_chan[ch].state = DMA_CH_NOTSTARTED;
  1630. if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
  1631. dma_chan[dma_chan[ch].next_linked_ch].state =
  1632. DMA_CH_STARTED;
  1633. if (dma_linked_lch[chain_id].chain_mode ==
  1634. OMAP_DMA_DYNAMIC_CHAIN)
  1635. disable_lnk(ch);
  1636. if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
  1637. OMAP_DMA_CHAIN_INCQHEAD(chain_id);
  1638. status = p->dma_read(CSR, ch);
  1639. p->dma_write(status, CSR, ch);
  1640. }
  1641. if (likely(dma_chan[ch].callback != NULL))
  1642. dma_chan[ch].callback(ch, status, dma_chan[ch].data);
  1643. return 0;
  1644. }
  1645. /* STATUS register count is from 1-32 while our is 0-31 */
  1646. static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
  1647. {
  1648. u32 val, enable_reg;
  1649. int i;
  1650. val = p->dma_read(IRQSTATUS_L0, 0);
  1651. if (val == 0) {
  1652. if (printk_ratelimit())
  1653. printk(KERN_WARNING "Spurious DMA IRQ\n");
  1654. return IRQ_HANDLED;
  1655. }
  1656. enable_reg = p->dma_read(IRQENABLE_L0, 0);
  1657. val &= enable_reg; /* Dispatch only relevant interrupts */
  1658. for (i = 0; i < dma_lch_count && val != 0; i++) {
  1659. if (val & 1)
  1660. omap2_dma_handle_ch(i);
  1661. val >>= 1;
  1662. }
  1663. return IRQ_HANDLED;
  1664. }
  1665. static struct irqaction omap24xx_dma_irq = {
  1666. .name = "DMA",
  1667. .handler = omap2_dma_irq_handler,
  1668. .flags = IRQF_DISABLED
  1669. };
  1670. #else
  1671. static struct irqaction omap24xx_dma_irq;
  1672. #endif
  1673. /*----------------------------------------------------------------------------*/
  1674. void omap_dma_global_context_save(void)
  1675. {
  1676. omap_dma_global_context.dma_irqenable_l0 =
  1677. p->dma_read(IRQENABLE_L0, 0);
  1678. omap_dma_global_context.dma_ocp_sysconfig =
  1679. p->dma_read(OCP_SYSCONFIG, 0);
  1680. omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
  1681. }
  1682. void omap_dma_global_context_restore(void)
  1683. {
  1684. int ch;
  1685. p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
  1686. p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
  1687. OCP_SYSCONFIG, 0);
  1688. p->dma_write(omap_dma_global_context.dma_irqenable_l0,
  1689. IRQENABLE_L0, 0);
  1690. if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
  1691. p->dma_write(0x3 , IRQSTATUS_L0, 0);
  1692. for (ch = 0; ch < dma_chan_count; ch++)
  1693. if (dma_chan[ch].dev_id != -1)
  1694. omap_clear_dma(ch);
  1695. }
  1696. static int __devinit omap_system_dma_probe(struct platform_device *pdev)
  1697. {
  1698. int ch, ret = 0;
  1699. int dma_irq;
  1700. char irq_name[4];
  1701. int irq_rel;
  1702. p = pdev->dev.platform_data;
  1703. if (!p) {
  1704. dev_err(&pdev->dev, "%s: System DMA initialized without"
  1705. "platform data\n", __func__);
  1706. return -EINVAL;
  1707. }
  1708. d = p->dma_attr;
  1709. errata = p->errata;
  1710. if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
  1711. && (omap_dma_reserve_channels <= dma_lch_count))
  1712. d->lch_count = omap_dma_reserve_channels;
  1713. dma_lch_count = d->lch_count;
  1714. dma_chan_count = dma_lch_count;
  1715. dma_chan = d->chan;
  1716. enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
  1717. if (cpu_class_is_omap2()) {
  1718. dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
  1719. dma_lch_count, GFP_KERNEL);
  1720. if (!dma_linked_lch) {
  1721. ret = -ENOMEM;
  1722. goto exit_dma_lch_fail;
  1723. }
  1724. }
  1725. spin_lock_init(&dma_chan_lock);
  1726. for (ch = 0; ch < dma_chan_count; ch++) {
  1727. omap_clear_dma(ch);
  1728. if (cpu_class_is_omap2())
  1729. omap2_disable_irq_lch(ch);
  1730. dma_chan[ch].dev_id = -1;
  1731. dma_chan[ch].next_lch = -1;
  1732. if (ch >= 6 && enable_1510_mode)
  1733. continue;
  1734. if (cpu_class_is_omap1()) {
  1735. /*
  1736. * request_irq() doesn't like dev_id (ie. ch) being
  1737. * zero, so we have to kludge around this.
  1738. */
  1739. sprintf(&irq_name[0], "%d", ch);
  1740. dma_irq = platform_get_irq_byname(pdev, irq_name);
  1741. if (dma_irq < 0) {
  1742. ret = dma_irq;
  1743. goto exit_dma_irq_fail;
  1744. }
  1745. /* INT_DMA_LCD is handled in lcd_dma.c */
  1746. if (dma_irq == INT_DMA_LCD)
  1747. continue;
  1748. ret = request_irq(dma_irq,
  1749. omap1_dma_irq_handler, 0, "DMA",
  1750. (void *) (ch + 1));
  1751. if (ret != 0)
  1752. goto exit_dma_irq_fail;
  1753. }
  1754. }
  1755. if (cpu_class_is_omap2() && !cpu_is_omap242x())
  1756. omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
  1757. DMA_DEFAULT_FIFO_DEPTH, 0);
  1758. if (cpu_class_is_omap2()) {
  1759. strcpy(irq_name, "0");
  1760. dma_irq = platform_get_irq_byname(pdev, irq_name);
  1761. if (dma_irq < 0) {
  1762. dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
  1763. goto exit_dma_lch_fail;
  1764. }
  1765. ret = setup_irq(dma_irq, &omap24xx_dma_irq);
  1766. if (ret) {
  1767. dev_err(&pdev->dev, "set_up failed for IRQ %d"
  1768. "for DMA (error %d)\n", dma_irq, ret);
  1769. goto exit_dma_lch_fail;
  1770. }
  1771. }
  1772. /* reserve dma channels 0 and 1 in high security devices */
  1773. if (cpu_is_omap34xx() &&
  1774. (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
  1775. printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
  1776. "HS ROM code\n");
  1777. dma_chan[0].dev_id = 0;
  1778. dma_chan[1].dev_id = 1;
  1779. }
  1780. p->show_dma_caps();
  1781. return 0;
  1782. exit_dma_irq_fail:
  1783. dev_err(&pdev->dev, "unable to request IRQ %d"
  1784. "for DMA (error %d)\n", dma_irq, ret);
  1785. for (irq_rel = 0; irq_rel < ch; irq_rel++) {
  1786. dma_irq = platform_get_irq(pdev, irq_rel);
  1787. free_irq(dma_irq, (void *)(irq_rel + 1));
  1788. }
  1789. exit_dma_lch_fail:
  1790. kfree(p);
  1791. kfree(d);
  1792. kfree(dma_chan);
  1793. return ret;
  1794. }
  1795. static int __devexit omap_system_dma_remove(struct platform_device *pdev)
  1796. {
  1797. int dma_irq;
  1798. if (cpu_class_is_omap2()) {
  1799. char irq_name[4];
  1800. strcpy(irq_name, "0");
  1801. dma_irq = platform_get_irq_byname(pdev, irq_name);
  1802. remove_irq(dma_irq, &omap24xx_dma_irq);
  1803. } else {
  1804. int irq_rel = 0;
  1805. for ( ; irq_rel < dma_chan_count; irq_rel++) {
  1806. dma_irq = platform_get_irq(pdev, irq_rel);
  1807. free_irq(dma_irq, (void *)(irq_rel + 1));
  1808. }
  1809. }
  1810. kfree(p);
  1811. kfree(d);
  1812. kfree(dma_chan);
  1813. return 0;
  1814. }
  1815. static struct platform_driver omap_system_dma_driver = {
  1816. .probe = omap_system_dma_probe,
  1817. .remove = __devexit_p(omap_system_dma_remove),
  1818. .driver = {
  1819. .name = "omap_dma_system"
  1820. },
  1821. };
  1822. static int __init omap_system_dma_init(void)
  1823. {
  1824. return platform_driver_register(&omap_system_dma_driver);
  1825. }
  1826. arch_initcall(omap_system_dma_init);
  1827. static void __exit omap_system_dma_exit(void)
  1828. {
  1829. platform_driver_unregister(&omap_system_dma_driver);
  1830. }
  1831. MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
  1832. MODULE_LICENSE("GPL");
  1833. MODULE_ALIAS("platform:" DRIVER_NAME);
  1834. MODULE_AUTHOR("Texas Instruments Inc");
  1835. /*
  1836. * Reserve the omap SDMA channels using cmdline bootarg
  1837. * "omap_dma_reserve_ch=". The valid range is 1 to 32
  1838. */
  1839. static int __init omap_dma_cmdline_reserve_ch(char *str)
  1840. {
  1841. if (get_option(&str, &omap_dma_reserve_channels) != 1)
  1842. omap_dma_reserve_channels = 0;
  1843. return 1;
  1844. }
  1845. __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);