core.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827
  1. /*
  2. * linux/arch/arm/mach-versatile/core.c
  3. *
  4. * Copyright (C) 1999 - 2003 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/device.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/of_address.h>
  28. #include <linux/of_platform.h>
  29. #include <linux/amba/bus.h>
  30. #include <linux/amba/clcd.h>
  31. #include <linux/amba/pl061.h>
  32. #include <linux/amba/mmci.h>
  33. #include <linux/amba/pl022.h>
  34. #include <linux/io.h>
  35. #include <linux/gfp.h>
  36. #include <linux/clkdev.h>
  37. #include <linux/mtd/physmap.h>
  38. #include <asm/irq.h>
  39. #include <asm/leds.h>
  40. #include <asm/hardware/arm_timer.h>
  41. #include <asm/hardware/icst.h>
  42. #include <asm/hardware/vic.h>
  43. #include <asm/mach-types.h>
  44. #include <asm/mach/arch.h>
  45. #include <asm/mach/irq.h>
  46. #include <asm/mach/time.h>
  47. #include <asm/mach/map.h>
  48. #include <mach/hardware.h>
  49. #include <mach/platform.h>
  50. #include <asm/hardware/timer-sp.h>
  51. #include <plat/clcd.h>
  52. #include <plat/fpga-irq.h>
  53. #include <plat/sched_clock.h>
  54. #include "core.h"
  55. /*
  56. * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  57. * is the (PA >> 12).
  58. *
  59. * Setup a VA for the Versatile Vectored Interrupt Controller.
  60. */
  61. #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
  62. #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
  63. #if 1
  64. #define IRQ_MMCI0A IRQ_VICSOURCE22
  65. #define IRQ_AACI IRQ_VICSOURCE24
  66. #define IRQ_ETH IRQ_VICSOURCE25
  67. #define PIC_MASK 0xFFD00000
  68. #else
  69. #define IRQ_MMCI0A IRQ_SIC_MMCI0A
  70. #define IRQ_AACI IRQ_SIC_AACI
  71. #define IRQ_ETH IRQ_SIC_ETH
  72. #define PIC_MASK 0
  73. #endif
  74. /* Lookup table for finding a DT node that represents the vic instance */
  75. static const struct of_device_id vic_of_match[] __initconst = {
  76. { .compatible = "arm,versatile-vic", },
  77. {}
  78. };
  79. static const struct of_device_id sic_of_match[] __initconst = {
  80. { .compatible = "arm,versatile-sic", },
  81. {}
  82. };
  83. void __init versatile_init_irq(void)
  84. {
  85. struct device_node *np;
  86. np = of_find_matching_node_by_address(NULL, vic_of_match,
  87. VERSATILE_VIC_BASE);
  88. __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
  89. writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  90. np = of_find_matching_node_by_address(NULL, sic_of_match,
  91. VERSATILE_SIC_BASE);
  92. fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
  93. IRQ_VICSOURCE31, ~PIC_MASK, np);
  94. /*
  95. * Interrupts on secondary controller from 0 to 8 are routed to
  96. * source 31 on PIC.
  97. * Interrupts from 21 to 31 are routed directly to the VIC on
  98. * the corresponding number on primary controller. This is controlled
  99. * by setting PIC_ENABLEx.
  100. */
  101. writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
  102. }
  103. static struct map_desc versatile_io_desc[] __initdata = {
  104. {
  105. .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
  106. .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
  107. .length = SZ_4K,
  108. .type = MT_DEVICE
  109. }, {
  110. .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
  111. .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
  112. .length = SZ_4K,
  113. .type = MT_DEVICE
  114. }, {
  115. .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
  116. .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
  117. .length = SZ_4K,
  118. .type = MT_DEVICE
  119. }, {
  120. .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
  121. .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
  122. .length = SZ_4K * 9,
  123. .type = MT_DEVICE
  124. },
  125. #ifdef CONFIG_MACH_VERSATILE_AB
  126. {
  127. .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
  128. .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
  129. .length = SZ_64M,
  130. .type = MT_DEVICE
  131. },
  132. #endif
  133. #ifdef CONFIG_DEBUG_LL
  134. {
  135. .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
  136. .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
  137. .length = SZ_4K,
  138. .type = MT_DEVICE
  139. },
  140. #endif
  141. #ifdef CONFIG_PCI
  142. {
  143. .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
  144. .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
  145. .length = SZ_4K,
  146. .type = MT_DEVICE
  147. }, {
  148. .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
  149. .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
  150. .length = VERSATILE_PCI_BASE_SIZE,
  151. .type = MT_DEVICE
  152. }, {
  153. .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
  154. .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
  155. .length = VERSATILE_PCI_CFG_BASE_SIZE,
  156. .type = MT_DEVICE
  157. },
  158. #if 0
  159. {
  160. .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
  161. .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
  162. .length = SZ_16M,
  163. .type = MT_DEVICE
  164. }, {
  165. .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
  166. .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
  167. .length = SZ_16M,
  168. .type = MT_DEVICE
  169. }, {
  170. .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
  171. .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
  172. .length = SZ_16M,
  173. .type = MT_DEVICE
  174. },
  175. #endif
  176. #endif
  177. };
  178. void __init versatile_map_io(void)
  179. {
  180. iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
  181. }
  182. #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
  183. static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
  184. {
  185. u32 val;
  186. val = __raw_readl(VERSATILE_FLASHCTRL);
  187. if (on)
  188. val |= VERSATILE_FLASHPROG_FLVPPEN;
  189. else
  190. val &= ~VERSATILE_FLASHPROG_FLVPPEN;
  191. __raw_writel(val, VERSATILE_FLASHCTRL);
  192. }
  193. static struct physmap_flash_data versatile_flash_data = {
  194. .width = 4,
  195. .set_vpp = versatile_flash_set_vpp,
  196. };
  197. static struct resource versatile_flash_resource = {
  198. .start = VERSATILE_FLASH_BASE,
  199. .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
  200. .flags = IORESOURCE_MEM,
  201. };
  202. static struct platform_device versatile_flash_device = {
  203. .name = "physmap-flash",
  204. .id = 0,
  205. .dev = {
  206. .platform_data = &versatile_flash_data,
  207. },
  208. .num_resources = 1,
  209. .resource = &versatile_flash_resource,
  210. };
  211. static struct resource smc91x_resources[] = {
  212. [0] = {
  213. .start = VERSATILE_ETH_BASE,
  214. .end = VERSATILE_ETH_BASE + SZ_64K - 1,
  215. .flags = IORESOURCE_MEM,
  216. },
  217. [1] = {
  218. .start = IRQ_ETH,
  219. .end = IRQ_ETH,
  220. .flags = IORESOURCE_IRQ,
  221. },
  222. };
  223. static struct platform_device smc91x_device = {
  224. .name = "smc91x",
  225. .id = 0,
  226. .num_resources = ARRAY_SIZE(smc91x_resources),
  227. .resource = smc91x_resources,
  228. };
  229. static struct resource versatile_i2c_resource = {
  230. .start = VERSATILE_I2C_BASE,
  231. .end = VERSATILE_I2C_BASE + SZ_4K - 1,
  232. .flags = IORESOURCE_MEM,
  233. };
  234. static struct platform_device versatile_i2c_device = {
  235. .name = "versatile-i2c",
  236. .id = 0,
  237. .num_resources = 1,
  238. .resource = &versatile_i2c_resource,
  239. };
  240. static struct i2c_board_info versatile_i2c_board_info[] = {
  241. {
  242. I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
  243. },
  244. };
  245. static int __init versatile_i2c_init(void)
  246. {
  247. return i2c_register_board_info(0, versatile_i2c_board_info,
  248. ARRAY_SIZE(versatile_i2c_board_info));
  249. }
  250. arch_initcall(versatile_i2c_init);
  251. #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
  252. unsigned int mmc_status(struct device *dev)
  253. {
  254. struct amba_device *adev = container_of(dev, struct amba_device, dev);
  255. u32 mask;
  256. if (adev->res.start == VERSATILE_MMCI0_BASE)
  257. mask = 1;
  258. else
  259. mask = 2;
  260. return readl(VERSATILE_SYSMCI) & mask;
  261. }
  262. static struct mmci_platform_data mmc0_plat_data = {
  263. .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
  264. .status = mmc_status,
  265. .gpio_wp = -1,
  266. .gpio_cd = -1,
  267. };
  268. static struct resource char_lcd_resources[] = {
  269. {
  270. .start = VERSATILE_CHAR_LCD_BASE,
  271. .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
  272. .flags = IORESOURCE_MEM,
  273. },
  274. };
  275. static struct platform_device char_lcd_device = {
  276. .name = "arm-charlcd",
  277. .id = -1,
  278. .num_resources = ARRAY_SIZE(char_lcd_resources),
  279. .resource = char_lcd_resources,
  280. };
  281. /*
  282. * Clock handling
  283. */
  284. static const struct icst_params versatile_oscvco_params = {
  285. .ref = 24000000,
  286. .vco_max = ICST307_VCO_MAX,
  287. .vco_min = ICST307_VCO_MIN,
  288. .vd_min = 4 + 8,
  289. .vd_max = 511 + 8,
  290. .rd_min = 1 + 2,
  291. .rd_max = 127 + 2,
  292. .s2div = icst307_s2div,
  293. .idx2s = icst307_idx2s,
  294. };
  295. static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
  296. {
  297. void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
  298. u32 val;
  299. val = readl(clk->vcoreg) & ~0x7ffff;
  300. val |= vco.v | (vco.r << 9) | (vco.s << 16);
  301. writel(0xa05f, sys_lock);
  302. writel(val, clk->vcoreg);
  303. writel(0, sys_lock);
  304. }
  305. static const struct clk_ops osc4_clk_ops = {
  306. .round = icst_clk_round,
  307. .set = icst_clk_set,
  308. .setvco = versatile_oscvco_set,
  309. };
  310. static struct clk osc4_clk = {
  311. .ops = &osc4_clk_ops,
  312. .params = &versatile_oscvco_params,
  313. };
  314. /*
  315. * These are fixed clocks.
  316. */
  317. static struct clk ref24_clk = {
  318. .rate = 24000000,
  319. };
  320. static struct clk sp804_clk = {
  321. .rate = 1000000,
  322. };
  323. static struct clk dummy_apb_pclk;
  324. static struct clk_lookup lookups[] = {
  325. { /* AMBA bus clock */
  326. .con_id = "apb_pclk",
  327. .clk = &dummy_apb_pclk,
  328. }, { /* UART0 */
  329. .dev_id = "dev:f1",
  330. .clk = &ref24_clk,
  331. }, { /* UART1 */
  332. .dev_id = "dev:f2",
  333. .clk = &ref24_clk,
  334. }, { /* UART2 */
  335. .dev_id = "dev:f3",
  336. .clk = &ref24_clk,
  337. }, { /* UART3 */
  338. .dev_id = "fpga:09",
  339. .clk = &ref24_clk,
  340. }, { /* KMI0 */
  341. .dev_id = "fpga:06",
  342. .clk = &ref24_clk,
  343. }, { /* KMI1 */
  344. .dev_id = "fpga:07",
  345. .clk = &ref24_clk,
  346. }, { /* MMC0 */
  347. .dev_id = "fpga:05",
  348. .clk = &ref24_clk,
  349. }, { /* MMC1 */
  350. .dev_id = "fpga:0b",
  351. .clk = &ref24_clk,
  352. }, { /* SSP */
  353. .dev_id = "dev:f4",
  354. .clk = &ref24_clk,
  355. }, { /* CLCD */
  356. .dev_id = "dev:20",
  357. .clk = &osc4_clk,
  358. }, { /* SP804 timers */
  359. .dev_id = "sp804",
  360. .clk = &sp804_clk,
  361. },
  362. };
  363. /*
  364. * CLCD support.
  365. */
  366. #define SYS_CLCD_MODE_MASK (3 << 0)
  367. #define SYS_CLCD_MODE_888 (0 << 0)
  368. #define SYS_CLCD_MODE_5551 (1 << 0)
  369. #define SYS_CLCD_MODE_565_RLSB (2 << 0)
  370. #define SYS_CLCD_MODE_565_BLSB (3 << 0)
  371. #define SYS_CLCD_NLCDIOON (1 << 2)
  372. #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
  373. #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
  374. #define SYS_CLCD_ID_MASK (0x1f << 8)
  375. #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
  376. #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
  377. #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
  378. #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
  379. #define SYS_CLCD_ID_VGA (0x1f << 8)
  380. static bool is_sanyo_2_5_lcd;
  381. /*
  382. * Disable all display connectors on the interface module.
  383. */
  384. static void versatile_clcd_disable(struct clcd_fb *fb)
  385. {
  386. void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
  387. u32 val;
  388. val = readl(sys_clcd);
  389. val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
  390. writel(val, sys_clcd);
  391. #ifdef CONFIG_MACH_VERSATILE_AB
  392. /*
  393. * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
  394. */
  395. if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
  396. void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
  397. unsigned long ctrl;
  398. ctrl = readl(versatile_ib2_ctrl);
  399. ctrl &= ~0x01;
  400. writel(ctrl, versatile_ib2_ctrl);
  401. }
  402. #endif
  403. }
  404. /*
  405. * Enable the relevant connector on the interface module.
  406. */
  407. static void versatile_clcd_enable(struct clcd_fb *fb)
  408. {
  409. struct fb_var_screeninfo *var = &fb->fb.var;
  410. void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
  411. u32 val;
  412. val = readl(sys_clcd);
  413. val &= ~SYS_CLCD_MODE_MASK;
  414. switch (var->green.length) {
  415. case 5:
  416. val |= SYS_CLCD_MODE_5551;
  417. break;
  418. case 6:
  419. if (var->red.offset == 0)
  420. val |= SYS_CLCD_MODE_565_RLSB;
  421. else
  422. val |= SYS_CLCD_MODE_565_BLSB;
  423. break;
  424. case 8:
  425. val |= SYS_CLCD_MODE_888;
  426. break;
  427. }
  428. /*
  429. * Set the MUX
  430. */
  431. writel(val, sys_clcd);
  432. /*
  433. * And now enable the PSUs
  434. */
  435. val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
  436. writel(val, sys_clcd);
  437. #ifdef CONFIG_MACH_VERSATILE_AB
  438. /*
  439. * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
  440. */
  441. if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
  442. void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
  443. unsigned long ctrl;
  444. ctrl = readl(versatile_ib2_ctrl);
  445. ctrl |= 0x01;
  446. writel(ctrl, versatile_ib2_ctrl);
  447. }
  448. #endif
  449. }
  450. /*
  451. * Detect which LCD panel is connected, and return the appropriate
  452. * clcd_panel structure. Note: we do not have any information on
  453. * the required timings for the 8.4in panel, so we presently assume
  454. * VGA timings.
  455. */
  456. static int versatile_clcd_setup(struct clcd_fb *fb)
  457. {
  458. void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
  459. const char *panel_name;
  460. u32 val;
  461. is_sanyo_2_5_lcd = false;
  462. val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
  463. if (val == SYS_CLCD_ID_SANYO_3_8)
  464. panel_name = "Sanyo TM38QV67A02A";
  465. else if (val == SYS_CLCD_ID_SANYO_2_5) {
  466. panel_name = "Sanyo QVGA Portrait";
  467. is_sanyo_2_5_lcd = true;
  468. } else if (val == SYS_CLCD_ID_EPSON_2_2)
  469. panel_name = "Epson L2F50113T00";
  470. else if (val == SYS_CLCD_ID_VGA)
  471. panel_name = "VGA";
  472. else {
  473. printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
  474. val);
  475. panel_name = "VGA";
  476. }
  477. fb->panel = versatile_clcd_get_panel(panel_name);
  478. if (!fb->panel)
  479. return -EINVAL;
  480. return versatile_clcd_setup_dma(fb, SZ_1M);
  481. }
  482. static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
  483. {
  484. clcdfb_decode(fb, regs);
  485. /* Always clear BGR for RGB565: we do the routing externally */
  486. if (fb->fb.var.green.length == 6)
  487. regs->cntl &= ~CNTL_BGR;
  488. }
  489. static struct clcd_board clcd_plat_data = {
  490. .name = "Versatile",
  491. .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
  492. .check = clcdfb_check,
  493. .decode = versatile_clcd_decode,
  494. .disable = versatile_clcd_disable,
  495. .enable = versatile_clcd_enable,
  496. .setup = versatile_clcd_setup,
  497. .mmap = versatile_clcd_mmap_dma,
  498. .remove = versatile_clcd_remove_dma,
  499. };
  500. static struct pl061_platform_data gpio0_plat_data = {
  501. .gpio_base = 0,
  502. .irq_base = IRQ_GPIO0_START,
  503. };
  504. static struct pl061_platform_data gpio1_plat_data = {
  505. .gpio_base = 8,
  506. .irq_base = IRQ_GPIO1_START,
  507. };
  508. static struct pl022_ssp_controller ssp0_plat_data = {
  509. .bus_id = 0,
  510. .enable_dma = 0,
  511. .num_chipselect = 1,
  512. };
  513. #define AACI_IRQ { IRQ_AACI }
  514. #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
  515. #define KMI0_IRQ { IRQ_SIC_KMI0 }
  516. #define KMI1_IRQ { IRQ_SIC_KMI1 }
  517. /*
  518. * These devices are connected directly to the multi-layer AHB switch
  519. */
  520. #define SMC_IRQ { }
  521. #define MPMC_IRQ { }
  522. #define CLCD_IRQ { IRQ_CLCDINT }
  523. #define DMAC_IRQ { IRQ_DMAINT }
  524. /*
  525. * These devices are connected via the core APB bridge
  526. */
  527. #define SCTL_IRQ { }
  528. #define WATCHDOG_IRQ { IRQ_WDOGINT }
  529. #define GPIO0_IRQ { IRQ_GPIOINT0 }
  530. #define GPIO1_IRQ { IRQ_GPIOINT1 }
  531. #define RTC_IRQ { IRQ_RTCINT }
  532. /*
  533. * These devices are connected via the DMA APB bridge
  534. */
  535. #define SCI_IRQ { IRQ_SCIINT }
  536. #define UART0_IRQ { IRQ_UARTINT0 }
  537. #define UART1_IRQ { IRQ_UARTINT1 }
  538. #define UART2_IRQ { IRQ_UARTINT2 }
  539. #define SSP_IRQ { IRQ_SSPINT }
  540. /* FPGA Primecells */
  541. APB_DEVICE(aaci, "fpga:04", AACI, NULL);
  542. APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
  543. APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
  544. APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
  545. /* DevChip Primecells */
  546. AHB_DEVICE(smc, "dev:00", SMC, NULL);
  547. AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
  548. AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
  549. AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
  550. APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
  551. APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
  552. APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
  553. APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
  554. APB_DEVICE(rtc, "dev:e8", RTC, NULL);
  555. APB_DEVICE(sci0, "dev:f0", SCI, NULL);
  556. APB_DEVICE(uart0, "dev:f1", UART0, NULL);
  557. APB_DEVICE(uart1, "dev:f2", UART1, NULL);
  558. APB_DEVICE(uart2, "dev:f3", UART2, NULL);
  559. APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
  560. static struct amba_device *amba_devs[] __initdata = {
  561. &dmac_device,
  562. &uart0_device,
  563. &uart1_device,
  564. &uart2_device,
  565. &smc_device,
  566. &mpmc_device,
  567. &clcd_device,
  568. &sctl_device,
  569. &wdog_device,
  570. &gpio0_device,
  571. &gpio1_device,
  572. &rtc_device,
  573. &sci0_device,
  574. &ssp0_device,
  575. &aaci_device,
  576. &mmc0_device,
  577. &kmi0_device,
  578. &kmi1_device,
  579. };
  580. #ifdef CONFIG_OF
  581. /*
  582. * Lookup table for attaching a specific name and platform_data pointer to
  583. * devices as they get created by of_platform_populate(). Ideally this table
  584. * would not exist, but the current clock implementation depends on some devices
  585. * having a specific name.
  586. */
  587. struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
  588. OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
  589. OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
  590. OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
  591. OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
  592. /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
  593. OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
  594. OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
  595. OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
  596. OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
  597. OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
  598. OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
  599. #if 0
  600. /*
  601. * These entries are unnecessary because no clocks referencing
  602. * them. I've left them in for now as place holders in case
  603. * any of them need to be added back, but they should be
  604. * removed before actually committing this patch. --gcl
  605. */
  606. OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
  607. OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
  608. OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
  609. OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
  610. OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
  611. OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
  612. OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
  613. OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
  614. OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
  615. OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
  616. OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
  617. OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
  618. OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
  619. #endif
  620. {}
  621. };
  622. #endif
  623. #ifdef CONFIG_LEDS
  624. #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
  625. static void versatile_leds_event(led_event_t ledevt)
  626. {
  627. unsigned long flags;
  628. u32 val;
  629. local_irq_save(flags);
  630. val = readl(VA_LEDS_BASE);
  631. switch (ledevt) {
  632. case led_idle_start:
  633. val = val & ~VERSATILE_SYS_LED0;
  634. break;
  635. case led_idle_end:
  636. val = val | VERSATILE_SYS_LED0;
  637. break;
  638. case led_timer:
  639. val = val ^ VERSATILE_SYS_LED1;
  640. break;
  641. case led_halted:
  642. val = 0;
  643. break;
  644. default:
  645. break;
  646. }
  647. writel(val, VA_LEDS_BASE);
  648. local_irq_restore(flags);
  649. }
  650. #endif /* CONFIG_LEDS */
  651. void versatile_restart(char mode, const char *cmd)
  652. {
  653. void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
  654. u32 val;
  655. val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
  656. val |= 0x105;
  657. __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
  658. __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
  659. __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
  660. }
  661. /* Early initializations */
  662. void __init versatile_init_early(void)
  663. {
  664. void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
  665. osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
  666. clkdev_add_table(lookups, ARRAY_SIZE(lookups));
  667. versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
  668. }
  669. void __init versatile_init(void)
  670. {
  671. int i;
  672. platform_device_register(&versatile_flash_device);
  673. platform_device_register(&versatile_i2c_device);
  674. platform_device_register(&smc91x_device);
  675. platform_device_register(&char_lcd_device);
  676. for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
  677. struct amba_device *d = amba_devs[i];
  678. amba_device_register(d, &iomem_resource);
  679. }
  680. #ifdef CONFIG_LEDS
  681. leds_event = versatile_leds_event;
  682. #endif
  683. }
  684. /*
  685. * Where is the timer (VA)?
  686. */
  687. #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
  688. #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
  689. #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
  690. #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
  691. /*
  692. * Set up timer interrupt, and return the current time in seconds.
  693. */
  694. static void __init versatile_timer_init(void)
  695. {
  696. u32 val;
  697. /*
  698. * set clock frequency:
  699. * VERSATILE_REFCLK is 32KHz
  700. * VERSATILE_TIMCLK is 1MHz
  701. */
  702. val = readl(__io_address(VERSATILE_SCTL_BASE));
  703. writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
  704. (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
  705. (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
  706. (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
  707. __io_address(VERSATILE_SCTL_BASE));
  708. /*
  709. * Initialise to a known state (all timers off)
  710. */
  711. writel(0, TIMER0_VA_BASE + TIMER_CTRL);
  712. writel(0, TIMER1_VA_BASE + TIMER_CTRL);
  713. writel(0, TIMER2_VA_BASE + TIMER_CTRL);
  714. writel(0, TIMER3_VA_BASE + TIMER_CTRL);
  715. sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
  716. sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
  717. }
  718. struct sys_timer versatile_timer = {
  719. .init = versatile_timer_init,
  720. };