spear300.c 8.0 KB

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  1. /*
  2. * arch/arm/mach-spear3xx/spear300.c
  3. *
  4. * SPEAr300 machine source file
  5. *
  6. * Copyright (C) 2009-2012 ST Microelectronics
  7. * Viresh Kumar <viresh.kumar@st.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #define pr_fmt(fmt) "SPEAr300: " fmt
  14. #include <linux/amba/pl08x.h>
  15. #include <linux/of_platform.h>
  16. #include <asm/hardware/vic.h>
  17. #include <asm/mach/arch.h>
  18. #include <plat/shirq.h>
  19. #include <mach/generic.h>
  20. #include <mach/spear.h>
  21. /* Base address of various IPs */
  22. #define SPEAR300_TELECOM_BASE UL(0x50000000)
  23. /* Interrupt registers offsets and masks */
  24. #define SPEAR300_INT_ENB_MASK_REG 0x54
  25. #define SPEAR300_INT_STS_MASK_REG 0x58
  26. #define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
  27. #define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
  28. #define SPEAR300_I2S_IRQ_MASK (1 << 2)
  29. #define SPEAR300_TDM_IRQ_MASK (1 << 3)
  30. #define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
  31. #define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
  32. #define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
  33. #define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
  34. #define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
  35. #define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
  36. #define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
  37. /* SPEAr300 Virtual irq definitions */
  38. /* IRQs sharing IRQ_GEN_RAS_1 */
  39. #define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
  40. #define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
  41. #define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
  42. #define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
  43. #define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
  44. #define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
  45. #define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
  46. #define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
  47. #define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
  48. /* IRQs sharing IRQ_GEN_RAS_3 */
  49. #define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
  50. /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
  51. #define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
  52. /* spear3xx shared irq */
  53. static struct shirq_dev_config shirq_ras1_config[] = {
  54. {
  55. .virq = SPEAR300_VIRQ_IT_PERS_S,
  56. .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
  57. .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
  58. }, {
  59. .virq = SPEAR300_VIRQ_IT_CHANGE_S,
  60. .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
  61. .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
  62. }, {
  63. .virq = SPEAR300_VIRQ_I2S,
  64. .enb_mask = SPEAR300_I2S_IRQ_MASK,
  65. .status_mask = SPEAR300_I2S_IRQ_MASK,
  66. }, {
  67. .virq = SPEAR300_VIRQ_TDM,
  68. .enb_mask = SPEAR300_TDM_IRQ_MASK,
  69. .status_mask = SPEAR300_TDM_IRQ_MASK,
  70. }, {
  71. .virq = SPEAR300_VIRQ_CAMERA_L,
  72. .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
  73. .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
  74. }, {
  75. .virq = SPEAR300_VIRQ_CAMERA_F,
  76. .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
  77. .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
  78. }, {
  79. .virq = SPEAR300_VIRQ_CAMERA_V,
  80. .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
  81. .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
  82. }, {
  83. .virq = SPEAR300_VIRQ_KEYBOARD,
  84. .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
  85. .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
  86. }, {
  87. .virq = SPEAR300_VIRQ_GPIO1,
  88. .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
  89. .status_mask = SPEAR300_GPIO1_IRQ_MASK,
  90. },
  91. };
  92. static struct spear_shirq shirq_ras1 = {
  93. .irq = SPEAR3XX_IRQ_GEN_RAS_1,
  94. .dev_config = shirq_ras1_config,
  95. .dev_count = ARRAY_SIZE(shirq_ras1_config),
  96. .regs = {
  97. .enb_reg = SPEAR300_INT_ENB_MASK_REG,
  98. .status_reg = SPEAR300_INT_STS_MASK_REG,
  99. .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
  100. .clear_reg = -1,
  101. },
  102. };
  103. /* DMAC platform data's slave info */
  104. struct pl08x_channel_data spear300_dma_info[] = {
  105. {
  106. .bus_id = "uart0_rx",
  107. .min_signal = 2,
  108. .max_signal = 2,
  109. .muxval = 0,
  110. .cctl = 0,
  111. .periph_buses = PL08X_AHB1,
  112. }, {
  113. .bus_id = "uart0_tx",
  114. .min_signal = 3,
  115. .max_signal = 3,
  116. .muxval = 0,
  117. .cctl = 0,
  118. .periph_buses = PL08X_AHB1,
  119. }, {
  120. .bus_id = "ssp0_rx",
  121. .min_signal = 8,
  122. .max_signal = 8,
  123. .muxval = 0,
  124. .cctl = 0,
  125. .periph_buses = PL08X_AHB1,
  126. }, {
  127. .bus_id = "ssp0_tx",
  128. .min_signal = 9,
  129. .max_signal = 9,
  130. .muxval = 0,
  131. .cctl = 0,
  132. .periph_buses = PL08X_AHB1,
  133. }, {
  134. .bus_id = "i2c_rx",
  135. .min_signal = 10,
  136. .max_signal = 10,
  137. .muxval = 0,
  138. .cctl = 0,
  139. .periph_buses = PL08X_AHB1,
  140. }, {
  141. .bus_id = "i2c_tx",
  142. .min_signal = 11,
  143. .max_signal = 11,
  144. .muxval = 0,
  145. .cctl = 0,
  146. .periph_buses = PL08X_AHB1,
  147. }, {
  148. .bus_id = "irda",
  149. .min_signal = 12,
  150. .max_signal = 12,
  151. .muxval = 0,
  152. .cctl = 0,
  153. .periph_buses = PL08X_AHB1,
  154. }, {
  155. .bus_id = "adc",
  156. .min_signal = 13,
  157. .max_signal = 13,
  158. .muxval = 0,
  159. .cctl = 0,
  160. .periph_buses = PL08X_AHB1,
  161. }, {
  162. .bus_id = "to_jpeg",
  163. .min_signal = 14,
  164. .max_signal = 14,
  165. .muxval = 0,
  166. .cctl = 0,
  167. .periph_buses = PL08X_AHB1,
  168. }, {
  169. .bus_id = "from_jpeg",
  170. .min_signal = 15,
  171. .max_signal = 15,
  172. .muxval = 0,
  173. .cctl = 0,
  174. .periph_buses = PL08X_AHB1,
  175. }, {
  176. .bus_id = "ras0_rx",
  177. .min_signal = 0,
  178. .max_signal = 0,
  179. .muxval = 1,
  180. .cctl = 0,
  181. .periph_buses = PL08X_AHB1,
  182. }, {
  183. .bus_id = "ras0_tx",
  184. .min_signal = 1,
  185. .max_signal = 1,
  186. .muxval = 1,
  187. .cctl = 0,
  188. .periph_buses = PL08X_AHB1,
  189. }, {
  190. .bus_id = "ras1_rx",
  191. .min_signal = 2,
  192. .max_signal = 2,
  193. .muxval = 1,
  194. .cctl = 0,
  195. .periph_buses = PL08X_AHB1,
  196. }, {
  197. .bus_id = "ras1_tx",
  198. .min_signal = 3,
  199. .max_signal = 3,
  200. .muxval = 1,
  201. .cctl = 0,
  202. .periph_buses = PL08X_AHB1,
  203. }, {
  204. .bus_id = "ras2_rx",
  205. .min_signal = 4,
  206. .max_signal = 4,
  207. .muxval = 1,
  208. .cctl = 0,
  209. .periph_buses = PL08X_AHB1,
  210. }, {
  211. .bus_id = "ras2_tx",
  212. .min_signal = 5,
  213. .max_signal = 5,
  214. .muxval = 1,
  215. .cctl = 0,
  216. .periph_buses = PL08X_AHB1,
  217. }, {
  218. .bus_id = "ras3_rx",
  219. .min_signal = 6,
  220. .max_signal = 6,
  221. .muxval = 1,
  222. .cctl = 0,
  223. .periph_buses = PL08X_AHB1,
  224. }, {
  225. .bus_id = "ras3_tx",
  226. .min_signal = 7,
  227. .max_signal = 7,
  228. .muxval = 1,
  229. .cctl = 0,
  230. .periph_buses = PL08X_AHB1,
  231. }, {
  232. .bus_id = "ras4_rx",
  233. .min_signal = 8,
  234. .max_signal = 8,
  235. .muxval = 1,
  236. .cctl = 0,
  237. .periph_buses = PL08X_AHB1,
  238. }, {
  239. .bus_id = "ras4_tx",
  240. .min_signal = 9,
  241. .max_signal = 9,
  242. .muxval = 1,
  243. .cctl = 0,
  244. .periph_buses = PL08X_AHB1,
  245. }, {
  246. .bus_id = "ras5_rx",
  247. .min_signal = 10,
  248. .max_signal = 10,
  249. .muxval = 1,
  250. .cctl = 0,
  251. .periph_buses = PL08X_AHB1,
  252. }, {
  253. .bus_id = "ras5_tx",
  254. .min_signal = 11,
  255. .max_signal = 11,
  256. .muxval = 1,
  257. .cctl = 0,
  258. .periph_buses = PL08X_AHB1,
  259. }, {
  260. .bus_id = "ras6_rx",
  261. .min_signal = 12,
  262. .max_signal = 12,
  263. .muxval = 1,
  264. .cctl = 0,
  265. .periph_buses = PL08X_AHB1,
  266. }, {
  267. .bus_id = "ras6_tx",
  268. .min_signal = 13,
  269. .max_signal = 13,
  270. .muxval = 1,
  271. .cctl = 0,
  272. .periph_buses = PL08X_AHB1,
  273. }, {
  274. .bus_id = "ras7_rx",
  275. .min_signal = 14,
  276. .max_signal = 14,
  277. .muxval = 1,
  278. .cctl = 0,
  279. .periph_buses = PL08X_AHB1,
  280. }, {
  281. .bus_id = "ras7_tx",
  282. .min_signal = 15,
  283. .max_signal = 15,
  284. .muxval = 1,
  285. .cctl = 0,
  286. .periph_buses = PL08X_AHB1,
  287. },
  288. };
  289. /* Add SPEAr300 auxdata to pass platform data */
  290. static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
  291. OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
  292. &pl022_plat_data),
  293. OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
  294. &pl080_plat_data),
  295. {}
  296. };
  297. static void __init spear300_dt_init(void)
  298. {
  299. int ret;
  300. pl080_plat_data.slave_channels = spear300_dma_info;
  301. pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
  302. of_platform_populate(NULL, of_default_bus_match_table,
  303. spear300_auxdata_lookup, NULL);
  304. /* shared irq registration */
  305. shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
  306. if (shirq_ras1.regs.base) {
  307. ret = spear_shirq_register(&shirq_ras1);
  308. if (ret)
  309. pr_err("Error registering Shared IRQ\n");
  310. }
  311. }
  312. static const char * const spear300_dt_board_compat[] = {
  313. "st,spear300",
  314. "st,spear300-evb",
  315. NULL,
  316. };
  317. static void __init spear300_map_io(void)
  318. {
  319. spear3xx_map_io();
  320. }
  321. DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
  322. .map_io = spear300_map_io,
  323. .init_irq = spear3xx_dt_init_irq,
  324. .handle_irq = vic_handle_irq,
  325. .timer = &spear3xx_timer,
  326. .init_machine = spear300_dt_init,
  327. .restart = spear_restart,
  328. .dt_compat = spear300_dt_board_compat,
  329. MACHINE_END