omap_hwmod_2xxx_ipblock_data.c 17 KB

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  1. /*
  2. * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
  3. *
  4. * Copyright (C) 2011 Nokia Corporation
  5. * Paul Walmsley
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <plat/omap_hwmod.h>
  12. #include <plat/serial.h>
  13. #include <plat/gpio.h>
  14. #include <plat/dma.h>
  15. #include <plat/dmtimer.h>
  16. #include <plat/mcspi.h>
  17. #include <mach/irqs.h>
  18. #include "omap_hwmod_common_data.h"
  19. #include "cm-regbits-24xx.h"
  20. #include "prm-regbits-24xx.h"
  21. #include "wd_timer.h"
  22. struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
  23. { .irq = 48, },
  24. { .irq = -1 }
  25. };
  26. struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
  27. { .name = "dispc", .dma_req = 5 },
  28. { .dma_req = -1 }
  29. };
  30. /*
  31. * 'dispc' class
  32. * display controller
  33. */
  34. static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  35. .rev_offs = 0x0000,
  36. .sysc_offs = 0x0010,
  37. .syss_offs = 0x0014,
  38. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  39. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  40. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  41. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  42. .sysc_fields = &omap_hwmod_sysc_type1,
  43. };
  44. struct omap_hwmod_class omap2_dispc_hwmod_class = {
  45. .name = "dispc",
  46. .sysc = &omap2_dispc_sysc,
  47. };
  48. /* OMAP2xxx Timer Common */
  49. static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  50. .rev_offs = 0x0000,
  51. .sysc_offs = 0x0010,
  52. .syss_offs = 0x0014,
  53. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  54. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  55. SYSC_HAS_AUTOIDLE),
  56. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  57. .sysc_fields = &omap_hwmod_sysc_type1,
  58. };
  59. struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  60. .name = "timer",
  61. .sysc = &omap2xxx_timer_sysc,
  62. .rev = OMAP_TIMER_IP_VERSION_1,
  63. };
  64. /*
  65. * 'wd_timer' class
  66. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  67. * overflow condition
  68. */
  69. static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  70. .rev_offs = 0x0000,
  71. .sysc_offs = 0x0010,
  72. .syss_offs = 0x0014,
  73. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  74. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  75. .sysc_fields = &omap_hwmod_sysc_type1,
  76. };
  77. struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  78. .name = "wd_timer",
  79. .sysc = &omap2xxx_wd_timer_sysc,
  80. .pre_shutdown = &omap2_wd_timer_disable,
  81. .reset = &omap2_wd_timer_reset,
  82. };
  83. /*
  84. * 'gpio' class
  85. * general purpose io module
  86. */
  87. static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  88. .rev_offs = 0x0000,
  89. .sysc_offs = 0x0010,
  90. .syss_offs = 0x0014,
  91. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  92. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  93. SYSS_HAS_RESET_STATUS),
  94. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  95. .sysc_fields = &omap_hwmod_sysc_type1,
  96. };
  97. struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
  98. .name = "gpio",
  99. .sysc = &omap2xxx_gpio_sysc,
  100. .rev = 0,
  101. };
  102. /* system dma */
  103. static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
  104. .rev_offs = 0x0000,
  105. .sysc_offs = 0x002c,
  106. .syss_offs = 0x0028,
  107. .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
  108. SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
  109. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  110. .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  111. .sysc_fields = &omap_hwmod_sysc_type1,
  112. };
  113. struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
  114. .name = "dma",
  115. .sysc = &omap2xxx_dma_sysc,
  116. };
  117. /*
  118. * 'mailbox' class
  119. * mailbox module allowing communication between the on-chip processors
  120. * using a queued mailbox-interrupt mechanism.
  121. */
  122. static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
  123. .rev_offs = 0x000,
  124. .sysc_offs = 0x010,
  125. .syss_offs = 0x014,
  126. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  127. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  128. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  129. .sysc_fields = &omap_hwmod_sysc_type1,
  130. };
  131. struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
  132. .name = "mailbox",
  133. .sysc = &omap2xxx_mailbox_sysc,
  134. };
  135. /*
  136. * 'mcspi' class
  137. * multichannel serial port interface (mcspi) / master/slave synchronous serial
  138. * bus
  139. */
  140. static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
  141. .rev_offs = 0x0000,
  142. .sysc_offs = 0x0010,
  143. .syss_offs = 0x0014,
  144. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  145. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  146. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  147. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  148. .sysc_fields = &omap_hwmod_sysc_type1,
  149. };
  150. struct omap_hwmod_class omap2xxx_mcspi_class = {
  151. .name = "mcspi",
  152. .sysc = &omap2xxx_mcspi_sysc,
  153. .rev = OMAP2_MCSPI_REV,
  154. };
  155. /*
  156. * IP blocks
  157. */
  158. /* L3 */
  159. struct omap_hwmod omap2xxx_l3_main_hwmod = {
  160. .name = "l3_main",
  161. .class = &l3_hwmod_class,
  162. .flags = HWMOD_NO_IDLEST,
  163. };
  164. /* L4 CORE */
  165. struct omap_hwmod omap2xxx_l4_core_hwmod = {
  166. .name = "l4_core",
  167. .class = &l4_hwmod_class,
  168. .flags = HWMOD_NO_IDLEST,
  169. };
  170. /* L4 WKUP */
  171. struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
  172. .name = "l4_wkup",
  173. .class = &l4_hwmod_class,
  174. .flags = HWMOD_NO_IDLEST,
  175. };
  176. /* MPU */
  177. struct omap_hwmod omap2xxx_mpu_hwmod = {
  178. .name = "mpu",
  179. .class = &mpu_hwmod_class,
  180. .main_clk = "mpu_ck",
  181. };
  182. /* IVA2 */
  183. struct omap_hwmod omap2xxx_iva_hwmod = {
  184. .name = "iva",
  185. .class = &iva_hwmod_class,
  186. };
  187. /* always-on timers dev attribute */
  188. static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
  189. .timer_capability = OMAP_TIMER_ALWON,
  190. };
  191. /* pwm timers dev attribute */
  192. static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
  193. .timer_capability = OMAP_TIMER_HAS_PWM,
  194. };
  195. /* timer1 */
  196. struct omap_hwmod omap2xxx_timer1_hwmod = {
  197. .name = "timer1",
  198. .mpu_irqs = omap2_timer1_mpu_irqs,
  199. .main_clk = "gpt1_fck",
  200. .prcm = {
  201. .omap2 = {
  202. .prcm_reg_id = 1,
  203. .module_bit = OMAP24XX_EN_GPT1_SHIFT,
  204. .module_offs = WKUP_MOD,
  205. .idlest_reg_id = 1,
  206. .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
  207. },
  208. },
  209. .dev_attr = &capability_alwon_dev_attr,
  210. .class = &omap2xxx_timer_hwmod_class,
  211. };
  212. /* timer2 */
  213. struct omap_hwmod omap2xxx_timer2_hwmod = {
  214. .name = "timer2",
  215. .mpu_irqs = omap2_timer2_mpu_irqs,
  216. .main_clk = "gpt2_fck",
  217. .prcm = {
  218. .omap2 = {
  219. .prcm_reg_id = 1,
  220. .module_bit = OMAP24XX_EN_GPT2_SHIFT,
  221. .module_offs = CORE_MOD,
  222. .idlest_reg_id = 1,
  223. .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
  224. },
  225. },
  226. .dev_attr = &capability_alwon_dev_attr,
  227. .class = &omap2xxx_timer_hwmod_class,
  228. };
  229. /* timer3 */
  230. struct omap_hwmod omap2xxx_timer3_hwmod = {
  231. .name = "timer3",
  232. .mpu_irqs = omap2_timer3_mpu_irqs,
  233. .main_clk = "gpt3_fck",
  234. .prcm = {
  235. .omap2 = {
  236. .prcm_reg_id = 1,
  237. .module_bit = OMAP24XX_EN_GPT3_SHIFT,
  238. .module_offs = CORE_MOD,
  239. .idlest_reg_id = 1,
  240. .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
  241. },
  242. },
  243. .dev_attr = &capability_alwon_dev_attr,
  244. .class = &omap2xxx_timer_hwmod_class,
  245. };
  246. /* timer4 */
  247. struct omap_hwmod omap2xxx_timer4_hwmod = {
  248. .name = "timer4",
  249. .mpu_irqs = omap2_timer4_mpu_irqs,
  250. .main_clk = "gpt4_fck",
  251. .prcm = {
  252. .omap2 = {
  253. .prcm_reg_id = 1,
  254. .module_bit = OMAP24XX_EN_GPT4_SHIFT,
  255. .module_offs = CORE_MOD,
  256. .idlest_reg_id = 1,
  257. .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
  258. },
  259. },
  260. .dev_attr = &capability_alwon_dev_attr,
  261. .class = &omap2xxx_timer_hwmod_class,
  262. };
  263. /* timer5 */
  264. struct omap_hwmod omap2xxx_timer5_hwmod = {
  265. .name = "timer5",
  266. .mpu_irqs = omap2_timer5_mpu_irqs,
  267. .main_clk = "gpt5_fck",
  268. .prcm = {
  269. .omap2 = {
  270. .prcm_reg_id = 1,
  271. .module_bit = OMAP24XX_EN_GPT5_SHIFT,
  272. .module_offs = CORE_MOD,
  273. .idlest_reg_id = 1,
  274. .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
  275. },
  276. },
  277. .dev_attr = &capability_alwon_dev_attr,
  278. .class = &omap2xxx_timer_hwmod_class,
  279. };
  280. /* timer6 */
  281. struct omap_hwmod omap2xxx_timer6_hwmod = {
  282. .name = "timer6",
  283. .mpu_irqs = omap2_timer6_mpu_irqs,
  284. .main_clk = "gpt6_fck",
  285. .prcm = {
  286. .omap2 = {
  287. .prcm_reg_id = 1,
  288. .module_bit = OMAP24XX_EN_GPT6_SHIFT,
  289. .module_offs = CORE_MOD,
  290. .idlest_reg_id = 1,
  291. .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
  292. },
  293. },
  294. .dev_attr = &capability_alwon_dev_attr,
  295. .class = &omap2xxx_timer_hwmod_class,
  296. };
  297. /* timer7 */
  298. struct omap_hwmod omap2xxx_timer7_hwmod = {
  299. .name = "timer7",
  300. .mpu_irqs = omap2_timer7_mpu_irqs,
  301. .main_clk = "gpt7_fck",
  302. .prcm = {
  303. .omap2 = {
  304. .prcm_reg_id = 1,
  305. .module_bit = OMAP24XX_EN_GPT7_SHIFT,
  306. .module_offs = CORE_MOD,
  307. .idlest_reg_id = 1,
  308. .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
  309. },
  310. },
  311. .dev_attr = &capability_alwon_dev_attr,
  312. .class = &omap2xxx_timer_hwmod_class,
  313. };
  314. /* timer8 */
  315. struct omap_hwmod omap2xxx_timer8_hwmod = {
  316. .name = "timer8",
  317. .mpu_irqs = omap2_timer8_mpu_irqs,
  318. .main_clk = "gpt8_fck",
  319. .prcm = {
  320. .omap2 = {
  321. .prcm_reg_id = 1,
  322. .module_bit = OMAP24XX_EN_GPT8_SHIFT,
  323. .module_offs = CORE_MOD,
  324. .idlest_reg_id = 1,
  325. .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
  326. },
  327. },
  328. .dev_attr = &capability_alwon_dev_attr,
  329. .class = &omap2xxx_timer_hwmod_class,
  330. };
  331. /* timer9 */
  332. struct omap_hwmod omap2xxx_timer9_hwmod = {
  333. .name = "timer9",
  334. .mpu_irqs = omap2_timer9_mpu_irqs,
  335. .main_clk = "gpt9_fck",
  336. .prcm = {
  337. .omap2 = {
  338. .prcm_reg_id = 1,
  339. .module_bit = OMAP24XX_EN_GPT9_SHIFT,
  340. .module_offs = CORE_MOD,
  341. .idlest_reg_id = 1,
  342. .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
  343. },
  344. },
  345. .dev_attr = &capability_pwm_dev_attr,
  346. .class = &omap2xxx_timer_hwmod_class,
  347. };
  348. /* timer10 */
  349. struct omap_hwmod omap2xxx_timer10_hwmod = {
  350. .name = "timer10",
  351. .mpu_irqs = omap2_timer10_mpu_irqs,
  352. .main_clk = "gpt10_fck",
  353. .prcm = {
  354. .omap2 = {
  355. .prcm_reg_id = 1,
  356. .module_bit = OMAP24XX_EN_GPT10_SHIFT,
  357. .module_offs = CORE_MOD,
  358. .idlest_reg_id = 1,
  359. .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
  360. },
  361. },
  362. .dev_attr = &capability_pwm_dev_attr,
  363. .class = &omap2xxx_timer_hwmod_class,
  364. };
  365. /* timer11 */
  366. struct omap_hwmod omap2xxx_timer11_hwmod = {
  367. .name = "timer11",
  368. .mpu_irqs = omap2_timer11_mpu_irqs,
  369. .main_clk = "gpt11_fck",
  370. .prcm = {
  371. .omap2 = {
  372. .prcm_reg_id = 1,
  373. .module_bit = OMAP24XX_EN_GPT11_SHIFT,
  374. .module_offs = CORE_MOD,
  375. .idlest_reg_id = 1,
  376. .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
  377. },
  378. },
  379. .dev_attr = &capability_pwm_dev_attr,
  380. .class = &omap2xxx_timer_hwmod_class,
  381. };
  382. /* timer12 */
  383. struct omap_hwmod omap2xxx_timer12_hwmod = {
  384. .name = "timer12",
  385. .mpu_irqs = omap2xxx_timer12_mpu_irqs,
  386. .main_clk = "gpt12_fck",
  387. .prcm = {
  388. .omap2 = {
  389. .prcm_reg_id = 1,
  390. .module_bit = OMAP24XX_EN_GPT12_SHIFT,
  391. .module_offs = CORE_MOD,
  392. .idlest_reg_id = 1,
  393. .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
  394. },
  395. },
  396. .dev_attr = &capability_pwm_dev_attr,
  397. .class = &omap2xxx_timer_hwmod_class,
  398. };
  399. /* wd_timer2 */
  400. struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
  401. .name = "wd_timer2",
  402. .class = &omap2xxx_wd_timer_hwmod_class,
  403. .main_clk = "mpu_wdt_fck",
  404. .prcm = {
  405. .omap2 = {
  406. .prcm_reg_id = 1,
  407. .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
  408. .module_offs = WKUP_MOD,
  409. .idlest_reg_id = 1,
  410. .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
  411. },
  412. },
  413. };
  414. /* UART1 */
  415. struct omap_hwmod omap2xxx_uart1_hwmod = {
  416. .name = "uart1",
  417. .mpu_irqs = omap2_uart1_mpu_irqs,
  418. .sdma_reqs = omap2_uart1_sdma_reqs,
  419. .main_clk = "uart1_fck",
  420. .prcm = {
  421. .omap2 = {
  422. .module_offs = CORE_MOD,
  423. .prcm_reg_id = 1,
  424. .module_bit = OMAP24XX_EN_UART1_SHIFT,
  425. .idlest_reg_id = 1,
  426. .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
  427. },
  428. },
  429. .class = &omap2_uart_class,
  430. };
  431. /* UART2 */
  432. struct omap_hwmod omap2xxx_uart2_hwmod = {
  433. .name = "uart2",
  434. .mpu_irqs = omap2_uart2_mpu_irqs,
  435. .sdma_reqs = omap2_uart2_sdma_reqs,
  436. .main_clk = "uart2_fck",
  437. .prcm = {
  438. .omap2 = {
  439. .module_offs = CORE_MOD,
  440. .prcm_reg_id = 1,
  441. .module_bit = OMAP24XX_EN_UART2_SHIFT,
  442. .idlest_reg_id = 1,
  443. .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
  444. },
  445. },
  446. .class = &omap2_uart_class,
  447. };
  448. /* UART3 */
  449. struct omap_hwmod omap2xxx_uart3_hwmod = {
  450. .name = "uart3",
  451. .mpu_irqs = omap2_uart3_mpu_irqs,
  452. .sdma_reqs = omap2_uart3_sdma_reqs,
  453. .main_clk = "uart3_fck",
  454. .prcm = {
  455. .omap2 = {
  456. .module_offs = CORE_MOD,
  457. .prcm_reg_id = 2,
  458. .module_bit = OMAP24XX_EN_UART3_SHIFT,
  459. .idlest_reg_id = 2,
  460. .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
  461. },
  462. },
  463. .class = &omap2_uart_class,
  464. };
  465. /* dss */
  466. static struct omap_hwmod_opt_clk dss_opt_clks[] = {
  467. /*
  468. * The DSS HW needs all DSS clocks enabled during reset. The dss_core
  469. * driver does not use these clocks.
  470. */
  471. { .role = "tv_clk", .clk = "dss_54m_fck" },
  472. { .role = "sys_clk", .clk = "dss2_fck" },
  473. };
  474. struct omap_hwmod omap2xxx_dss_core_hwmod = {
  475. .name = "dss_core",
  476. .class = &omap2_dss_hwmod_class,
  477. .main_clk = "dss1_fck", /* instead of dss_fck */
  478. .sdma_reqs = omap2xxx_dss_sdma_chs,
  479. .prcm = {
  480. .omap2 = {
  481. .prcm_reg_id = 1,
  482. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  483. .module_offs = CORE_MOD,
  484. .idlest_reg_id = 1,
  485. .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
  486. },
  487. },
  488. .opt_clks = dss_opt_clks,
  489. .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
  490. .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  491. };
  492. struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
  493. .name = "dss_dispc",
  494. .class = &omap2_dispc_hwmod_class,
  495. .mpu_irqs = omap2_dispc_irqs,
  496. .main_clk = "dss1_fck",
  497. .prcm = {
  498. .omap2 = {
  499. .prcm_reg_id = 1,
  500. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  501. .module_offs = CORE_MOD,
  502. .idlest_reg_id = 1,
  503. .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
  504. },
  505. },
  506. .flags = HWMOD_NO_IDLEST,
  507. .dev_attr = &omap2_3_dss_dispc_dev_attr
  508. };
  509. static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
  510. { .role = "ick", .clk = "dss_ick" },
  511. };
  512. struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
  513. .name = "dss_rfbi",
  514. .class = &omap2_rfbi_hwmod_class,
  515. .main_clk = "dss1_fck",
  516. .prcm = {
  517. .omap2 = {
  518. .prcm_reg_id = 1,
  519. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  520. .module_offs = CORE_MOD,
  521. },
  522. },
  523. .opt_clks = dss_rfbi_opt_clks,
  524. .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
  525. .flags = HWMOD_NO_IDLEST,
  526. };
  527. struct omap_hwmod omap2xxx_dss_venc_hwmod = {
  528. .name = "dss_venc",
  529. .class = &omap2_venc_hwmod_class,
  530. .main_clk = "dss_54m_fck",
  531. .prcm = {
  532. .omap2 = {
  533. .prcm_reg_id = 1,
  534. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  535. .module_offs = CORE_MOD,
  536. },
  537. },
  538. .flags = HWMOD_NO_IDLEST,
  539. };
  540. /* gpio dev_attr */
  541. struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
  542. .bank_width = 32,
  543. .dbck_flag = false,
  544. };
  545. /* gpio1 */
  546. struct omap_hwmod omap2xxx_gpio1_hwmod = {
  547. .name = "gpio1",
  548. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  549. .mpu_irqs = omap2_gpio1_irqs,
  550. .main_clk = "gpios_fck",
  551. .prcm = {
  552. .omap2 = {
  553. .prcm_reg_id = 1,
  554. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  555. .module_offs = WKUP_MOD,
  556. .idlest_reg_id = 1,
  557. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  558. },
  559. },
  560. .class = &omap2xxx_gpio_hwmod_class,
  561. .dev_attr = &omap2xxx_gpio_dev_attr,
  562. };
  563. /* gpio2 */
  564. struct omap_hwmod omap2xxx_gpio2_hwmod = {
  565. .name = "gpio2",
  566. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  567. .mpu_irqs = omap2_gpio2_irqs,
  568. .main_clk = "gpios_fck",
  569. .prcm = {
  570. .omap2 = {
  571. .prcm_reg_id = 1,
  572. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  573. .module_offs = WKUP_MOD,
  574. .idlest_reg_id = 1,
  575. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  576. },
  577. },
  578. .class = &omap2xxx_gpio_hwmod_class,
  579. .dev_attr = &omap2xxx_gpio_dev_attr,
  580. };
  581. /* gpio3 */
  582. struct omap_hwmod omap2xxx_gpio3_hwmod = {
  583. .name = "gpio3",
  584. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  585. .mpu_irqs = omap2_gpio3_irqs,
  586. .main_clk = "gpios_fck",
  587. .prcm = {
  588. .omap2 = {
  589. .prcm_reg_id = 1,
  590. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  591. .module_offs = WKUP_MOD,
  592. .idlest_reg_id = 1,
  593. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  594. },
  595. },
  596. .class = &omap2xxx_gpio_hwmod_class,
  597. .dev_attr = &omap2xxx_gpio_dev_attr,
  598. };
  599. /* gpio4 */
  600. struct omap_hwmod omap2xxx_gpio4_hwmod = {
  601. .name = "gpio4",
  602. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  603. .mpu_irqs = omap2_gpio4_irqs,
  604. .main_clk = "gpios_fck",
  605. .prcm = {
  606. .omap2 = {
  607. .prcm_reg_id = 1,
  608. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  609. .module_offs = WKUP_MOD,
  610. .idlest_reg_id = 1,
  611. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  612. },
  613. },
  614. .class = &omap2xxx_gpio_hwmod_class,
  615. .dev_attr = &omap2xxx_gpio_dev_attr,
  616. };
  617. /* mcspi1 */
  618. static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
  619. .num_chipselect = 4,
  620. };
  621. struct omap_hwmod omap2xxx_mcspi1_hwmod = {
  622. .name = "mcspi1",
  623. .mpu_irqs = omap2_mcspi1_mpu_irqs,
  624. .sdma_reqs = omap2_mcspi1_sdma_reqs,
  625. .main_clk = "mcspi1_fck",
  626. .prcm = {
  627. .omap2 = {
  628. .module_offs = CORE_MOD,
  629. .prcm_reg_id = 1,
  630. .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
  631. .idlest_reg_id = 1,
  632. .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
  633. },
  634. },
  635. .class = &omap2xxx_mcspi_class,
  636. .dev_attr = &omap_mcspi1_dev_attr,
  637. };
  638. /* mcspi2 */
  639. static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
  640. .num_chipselect = 2,
  641. };
  642. struct omap_hwmod omap2xxx_mcspi2_hwmod = {
  643. .name = "mcspi2",
  644. .mpu_irqs = omap2_mcspi2_mpu_irqs,
  645. .sdma_reqs = omap2_mcspi2_sdma_reqs,
  646. .main_clk = "mcspi2_fck",
  647. .prcm = {
  648. .omap2 = {
  649. .module_offs = CORE_MOD,
  650. .prcm_reg_id = 1,
  651. .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
  652. .idlest_reg_id = 1,
  653. .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
  654. },
  655. },
  656. .class = &omap2xxx_mcspi_class,
  657. .dev_attr = &omap_mcspi2_dev_attr,
  658. };
  659. static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
  660. .name = "counter",
  661. };
  662. struct omap_hwmod omap2xxx_counter_32k_hwmod = {
  663. .name = "counter_32k",
  664. .main_clk = "func_32k_ck",
  665. .prcm = {
  666. .omap2 = {
  667. .module_offs = WKUP_MOD,
  668. .prcm_reg_id = 1,
  669. .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
  670. .idlest_reg_id = 1,
  671. .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
  672. },
  673. },
  674. .class = &omap2xxx_counter_hwmod_class,
  675. };