hdq1w.c 2.3 KB

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  1. /*
  2. * IP block integration code for the HDQ1W/1-wire IP block
  3. *
  4. * Copyright (C) 2012 Texas Instruments, Inc.
  5. * Paul Walmsley
  6. *
  7. * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
  8. * Avinash.H.M <avinashhm@ti.com>
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * version 2 as published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  22. * 02110-1301 USA
  23. */
  24. #include <plat/omap_hwmod.h>
  25. #include <plat/hdq1w.h>
  26. #include "common.h"
  27. /* Maximum microseconds to wait for OMAP module to softreset */
  28. #define MAX_MODULE_SOFTRESET_WAIT 10000
  29. /**
  30. * omap_hdq1w_reset - reset the OMAP HDQ1W module
  31. * @oh: struct omap_hwmod *
  32. *
  33. * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
  34. * Software Reset" of the OMAP34xx Technical Reference Manual Revision
  35. * ZR (SWPU223R) does not include the rather important fact that, for
  36. * the reset to succeed, the HDQ1W module's internal clock gate must be
  37. * programmed to allow the clock to propagate to the rest of the
  38. * module. In this sense, it's rather similar to the I2C custom reset
  39. * function. Returns 0.
  40. */
  41. int omap_hdq1w_reset(struct omap_hwmod *oh)
  42. {
  43. u32 v;
  44. int c = 0;
  45. /* Write to the SOFTRESET bit */
  46. omap_hwmod_softreset(oh);
  47. /* Enable the module's internal clocks */
  48. v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
  49. v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
  50. omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
  51. /* Poll on RESETDONE bit */
  52. omap_test_timeout((omap_hwmod_read(oh,
  53. oh->class->sysc->syss_offs)
  54. & SYSS_RESETDONE_MASK),
  55. MAX_MODULE_SOFTRESET_WAIT, c);
  56. if (c == MAX_MODULE_SOFTRESET_WAIT)
  57. pr_warning("%s: %s: softreset failed (waited %d usec)\n",
  58. __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
  59. else
  60. pr_debug("%s: %s: softreset in %d usec\n", __func__,
  61. oh->name, c);
  62. return 0;
  63. }