mm-imx5.c 7.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244
  1. /*
  2. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. *
  11. * Create static mapping between physical to virtual memory.
  12. */
  13. #include <linux/mm.h>
  14. #include <linux/init.h>
  15. #include <linux/clk.h>
  16. #include <linux/pinctrl/machine.h>
  17. #include <asm/system_misc.h>
  18. #include <asm/mach/map.h>
  19. #include <mach/hardware.h>
  20. #include <mach/common.h>
  21. #include <mach/devices-common.h>
  22. #include <mach/iomux-v3.h>
  23. static struct clk *gpc_dvfs_clk;
  24. static void imx5_idle(void)
  25. {
  26. /* gpc clock is needed for SRPG */
  27. if (gpc_dvfs_clk == NULL) {
  28. gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
  29. if (IS_ERR(gpc_dvfs_clk))
  30. return;
  31. clk_prepare(gpc_dvfs_clk);
  32. }
  33. clk_enable(gpc_dvfs_clk);
  34. mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
  35. if (!tzic_enable_wake())
  36. cpu_do_idle();
  37. clk_disable(gpc_dvfs_clk);
  38. }
  39. /*
  40. * Define the MX50 memory map.
  41. */
  42. static struct map_desc mx50_io_desc[] __initdata = {
  43. imx_map_entry(MX50, TZIC, MT_DEVICE),
  44. imx_map_entry(MX50, SPBA0, MT_DEVICE),
  45. imx_map_entry(MX50, AIPS1, MT_DEVICE),
  46. imx_map_entry(MX50, AIPS2, MT_DEVICE),
  47. };
  48. /*
  49. * Define the MX51 memory map.
  50. */
  51. static struct map_desc mx51_io_desc[] __initdata = {
  52. imx_map_entry(MX51, TZIC, MT_DEVICE),
  53. imx_map_entry(MX51, IRAM, MT_DEVICE),
  54. imx_map_entry(MX51, AIPS1, MT_DEVICE),
  55. imx_map_entry(MX51, SPBA0, MT_DEVICE),
  56. imx_map_entry(MX51, AIPS2, MT_DEVICE),
  57. };
  58. /*
  59. * Define the MX53 memory map.
  60. */
  61. static struct map_desc mx53_io_desc[] __initdata = {
  62. imx_map_entry(MX53, TZIC, MT_DEVICE),
  63. imx_map_entry(MX53, AIPS1, MT_DEVICE),
  64. imx_map_entry(MX53, SPBA0, MT_DEVICE),
  65. imx_map_entry(MX53, AIPS2, MT_DEVICE),
  66. };
  67. /*
  68. * This function initializes the memory map. It is called during the
  69. * system startup to create static physical to virtual memory mappings
  70. * for the IO modules.
  71. */
  72. void __init mx50_map_io(void)
  73. {
  74. iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
  75. }
  76. void __init mx51_map_io(void)
  77. {
  78. iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
  79. }
  80. void __init mx53_map_io(void)
  81. {
  82. iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
  83. }
  84. void __init imx50_init_early(void)
  85. {
  86. mxc_set_cpu_type(MXC_CPU_MX50);
  87. mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
  88. mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
  89. }
  90. void __init imx51_init_early(void)
  91. {
  92. mxc_set_cpu_type(MXC_CPU_MX51);
  93. mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
  94. mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
  95. arm_pm_idle = imx5_idle;
  96. }
  97. void __init imx53_init_early(void)
  98. {
  99. mxc_set_cpu_type(MXC_CPU_MX53);
  100. mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
  101. mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
  102. }
  103. void __init mx50_init_irq(void)
  104. {
  105. tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
  106. }
  107. void __init mx51_init_irq(void)
  108. {
  109. tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
  110. }
  111. void __init mx53_init_irq(void)
  112. {
  113. tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
  114. }
  115. static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
  116. .ap_2_ap_addr = 642,
  117. .uart_2_mcu_addr = 817,
  118. .mcu_2_app_addr = 747,
  119. .mcu_2_shp_addr = 961,
  120. .ata_2_mcu_addr = 1473,
  121. .mcu_2_ata_addr = 1392,
  122. .app_2_per_addr = 1033,
  123. .app_2_mcu_addr = 683,
  124. .shp_2_per_addr = 1251,
  125. .shp_2_mcu_addr = 892,
  126. };
  127. static struct sdma_platform_data imx51_sdma_pdata __initdata = {
  128. .fw_name = "sdma-imx51.bin",
  129. .script_addrs = &imx51_sdma_script,
  130. };
  131. static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
  132. .ap_2_ap_addr = 642,
  133. .app_2_mcu_addr = 683,
  134. .mcu_2_app_addr = 747,
  135. .uart_2_mcu_addr = 817,
  136. .shp_2_mcu_addr = 891,
  137. .mcu_2_shp_addr = 960,
  138. .uartsh_2_mcu_addr = 1032,
  139. .spdif_2_mcu_addr = 1100,
  140. .mcu_2_spdif_addr = 1134,
  141. .firi_2_mcu_addr = 1193,
  142. .mcu_2_firi_addr = 1290,
  143. };
  144. static struct sdma_platform_data imx53_sdma_pdata __initdata = {
  145. .fw_name = "sdma-imx53.bin",
  146. .script_addrs = &imx53_sdma_script,
  147. };
  148. static const struct resource imx50_audmux_res[] __initconst = {
  149. DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
  150. };
  151. static const struct resource imx51_audmux_res[] __initconst = {
  152. DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
  153. };
  154. static const struct resource imx53_audmux_res[] __initconst = {
  155. DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
  156. };
  157. void __init imx50_soc_init(void)
  158. {
  159. /* i.mx50 has the i.mx31 type gpio */
  160. mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
  161. mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
  162. mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
  163. mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
  164. mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
  165. mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
  166. /* i.mx50 has the i.mx31 type audmux */
  167. platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
  168. ARRAY_SIZE(imx50_audmux_res));
  169. }
  170. void __init imx51_soc_init(void)
  171. {
  172. /* i.mx51 has the i.mx31 type gpio */
  173. mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
  174. mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
  175. mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
  176. mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
  177. /* i.mx51 has the i.mx35 type sdma */
  178. imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
  179. /* Setup AIPS registers */
  180. imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
  181. imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
  182. /* i.mx51 has the i.mx31 type audmux */
  183. platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
  184. ARRAY_SIZE(imx51_audmux_res));
  185. }
  186. void __init imx53_soc_init(void)
  187. {
  188. /* i.mx53 has the i.mx31 type gpio */
  189. mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
  190. mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
  191. mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
  192. mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
  193. mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
  194. mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
  195. mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
  196. pinctrl_provide_dummies();
  197. /* i.mx53 has the i.mx35 type sdma */
  198. imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
  199. /* Setup AIPS registers */
  200. imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
  201. imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
  202. /* i.mx53 has the i.mx31 type audmux */
  203. platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
  204. ARRAY_SIZE(imx53_audmux_res));
  205. }
  206. void __init imx51_init_late(void)
  207. {
  208. mx51_neon_fixup();
  209. }