mach-mx31_3ds.c 20 KB

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  1. /*
  2. * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/types.h>
  17. #include <linux/init.h>
  18. #include <linux/clk.h>
  19. #include <linux/irq.h>
  20. #include <linux/gpio.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/mfd/mc13783.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/spi/l4f00242t03.h>
  25. #include <linux/regulator/machine.h>
  26. #include <linux/usb/otg.h>
  27. #include <linux/usb/ulpi.h>
  28. #include <linux/memblock.h>
  29. #include <media/soc_camera.h>
  30. #include <mach/hardware.h>
  31. #include <asm/mach-types.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/time.h>
  34. #include <asm/memory.h>
  35. #include <asm/mach/map.h>
  36. #include <asm/memblock.h>
  37. #include <mach/common.h>
  38. #include <mach/iomux-mx3.h>
  39. #include <mach/3ds_debugboard.h>
  40. #include <mach/ulpi.h>
  41. #include "devices-imx31.h"
  42. /* CPLD IRQ line for external uart, external ethernet etc */
  43. #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
  44. static int mx31_3ds_pins[] = {
  45. /* UART1 */
  46. MX31_PIN_CTS1__CTS1,
  47. MX31_PIN_RTS1__RTS1,
  48. MX31_PIN_TXD1__TXD1,
  49. MX31_PIN_RXD1__RXD1,
  50. IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
  51. /*SPI0*/
  52. IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
  53. IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
  54. /* SPI 1 */
  55. MX31_PIN_CSPI2_SCLK__SCLK,
  56. MX31_PIN_CSPI2_MOSI__MOSI,
  57. MX31_PIN_CSPI2_MISO__MISO,
  58. MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
  59. MX31_PIN_CSPI2_SS0__SS0,
  60. MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
  61. /* MC13783 IRQ */
  62. IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
  63. /* USB OTG reset */
  64. IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
  65. /* USB OTG */
  66. MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
  67. MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
  68. MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
  69. MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
  70. MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
  71. MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
  72. MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
  73. MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
  74. MX31_PIN_USBOTG_CLK__USBOTG_CLK,
  75. MX31_PIN_USBOTG_DIR__USBOTG_DIR,
  76. MX31_PIN_USBOTG_NXT__USBOTG_NXT,
  77. MX31_PIN_USBOTG_STP__USBOTG_STP,
  78. /*Keyboard*/
  79. MX31_PIN_KEY_ROW0_KEY_ROW0,
  80. MX31_PIN_KEY_ROW1_KEY_ROW1,
  81. MX31_PIN_KEY_ROW2_KEY_ROW2,
  82. MX31_PIN_KEY_COL0_KEY_COL0,
  83. MX31_PIN_KEY_COL1_KEY_COL1,
  84. MX31_PIN_KEY_COL2_KEY_COL2,
  85. MX31_PIN_KEY_COL3_KEY_COL3,
  86. /* USB Host 2 */
  87. IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
  88. IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
  89. IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
  90. IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
  91. IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
  92. IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
  93. IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
  94. IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
  95. IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
  96. IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
  97. IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
  98. IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
  99. /* USB Host2 reset */
  100. IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
  101. /* I2C1 */
  102. MX31_PIN_I2C_CLK__I2C1_SCL,
  103. MX31_PIN_I2C_DAT__I2C1_SDA,
  104. /* SDHC1 */
  105. MX31_PIN_SD1_DATA3__SD1_DATA3,
  106. MX31_PIN_SD1_DATA2__SD1_DATA2,
  107. MX31_PIN_SD1_DATA1__SD1_DATA1,
  108. MX31_PIN_SD1_DATA0__SD1_DATA0,
  109. MX31_PIN_SD1_CLK__SD1_CLK,
  110. MX31_PIN_SD1_CMD__SD1_CMD,
  111. MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
  112. MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
  113. /* Framebuffer */
  114. MX31_PIN_LD0__LD0,
  115. MX31_PIN_LD1__LD1,
  116. MX31_PIN_LD2__LD2,
  117. MX31_PIN_LD3__LD3,
  118. MX31_PIN_LD4__LD4,
  119. MX31_PIN_LD5__LD5,
  120. MX31_PIN_LD6__LD6,
  121. MX31_PIN_LD7__LD7,
  122. MX31_PIN_LD8__LD8,
  123. MX31_PIN_LD9__LD9,
  124. MX31_PIN_LD10__LD10,
  125. MX31_PIN_LD11__LD11,
  126. MX31_PIN_LD12__LD12,
  127. MX31_PIN_LD13__LD13,
  128. MX31_PIN_LD14__LD14,
  129. MX31_PIN_LD15__LD15,
  130. MX31_PIN_LD16__LD16,
  131. MX31_PIN_LD17__LD17,
  132. MX31_PIN_VSYNC3__VSYNC3,
  133. MX31_PIN_HSYNC__HSYNC,
  134. MX31_PIN_FPSHIFT__FPSHIFT,
  135. MX31_PIN_CONTRAST__CONTRAST,
  136. /* CSI */
  137. MX31_PIN_CSI_D6__CSI_D6,
  138. MX31_PIN_CSI_D7__CSI_D7,
  139. MX31_PIN_CSI_D8__CSI_D8,
  140. MX31_PIN_CSI_D9__CSI_D9,
  141. MX31_PIN_CSI_D10__CSI_D10,
  142. MX31_PIN_CSI_D11__CSI_D11,
  143. MX31_PIN_CSI_D12__CSI_D12,
  144. MX31_PIN_CSI_D13__CSI_D13,
  145. MX31_PIN_CSI_D14__CSI_D14,
  146. MX31_PIN_CSI_D15__CSI_D15,
  147. MX31_PIN_CSI_HSYNC__CSI_HSYNC,
  148. MX31_PIN_CSI_MCLK__CSI_MCLK,
  149. MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
  150. MX31_PIN_CSI_VSYNC__CSI_VSYNC,
  151. MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
  152. IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
  153. /* SSI */
  154. MX31_PIN_STXD4__STXD4,
  155. MX31_PIN_SRXD4__SRXD4,
  156. MX31_PIN_SCK4__SCK4,
  157. MX31_PIN_SFS4__SFS4,
  158. };
  159. /*
  160. * Camera support
  161. */
  162. static phys_addr_t mx3_camera_base __initdata;
  163. #define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
  164. #define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
  165. #define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
  166. static struct gpio mx31_3ds_camera_gpios[] = {
  167. { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
  168. { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
  169. };
  170. static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
  171. .flags = MX3_CAMERA_DATAWIDTH_10,
  172. .mclk_10khz = 2600,
  173. };
  174. static int __init mx31_3ds_init_camera(void)
  175. {
  176. int dma, ret = -ENOMEM;
  177. struct platform_device *pdev =
  178. imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
  179. if (IS_ERR(pdev))
  180. return PTR_ERR(pdev);
  181. if (!mx3_camera_base)
  182. goto err;
  183. dma = dma_declare_coherent_memory(&pdev->dev,
  184. mx3_camera_base, mx3_camera_base,
  185. MX31_3DS_CAMERA_BUF_SIZE,
  186. DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
  187. if (!(dma & DMA_MEMORY_MAP))
  188. goto err;
  189. ret = platform_device_add(pdev);
  190. if (ret)
  191. err:
  192. platform_device_put(pdev);
  193. return ret;
  194. }
  195. static int mx31_3ds_camera_power(struct device *dev, int on)
  196. {
  197. /* enable or disable the camera */
  198. pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
  199. gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
  200. if (!on)
  201. goto out;
  202. /* If enabled, give a reset impulse */
  203. gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
  204. msleep(20);
  205. gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
  206. msleep(100);
  207. out:
  208. return 0;
  209. }
  210. static struct i2c_board_info mx31_3ds_i2c_camera = {
  211. I2C_BOARD_INFO("ov2640", 0x30),
  212. };
  213. static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
  214. { .supply = "cmos_vcore" },
  215. { .supply = "cmos_2v8" },
  216. };
  217. static struct soc_camera_link iclink_ov2640 = {
  218. .bus_id = 0,
  219. .board_info = &mx31_3ds_i2c_camera,
  220. .i2c_adapter_id = 0,
  221. .power = mx31_3ds_camera_power,
  222. .regulators = mx31_3ds_camera_regs,
  223. .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
  224. };
  225. static struct platform_device mx31_3ds_ov2640 = {
  226. .name = "soc-camera-pdrv",
  227. .id = 0,
  228. .dev = {
  229. .platform_data = &iclink_ov2640,
  230. },
  231. };
  232. /*
  233. * FB support
  234. */
  235. static const struct fb_videomode fb_modedb[] = {
  236. { /* 480x640 @ 60 Hz */
  237. .name = "Epson-VGA",
  238. .refresh = 60,
  239. .xres = 480,
  240. .yres = 640,
  241. .pixclock = 41701,
  242. .left_margin = 20,
  243. .right_margin = 41,
  244. .upper_margin = 10,
  245. .lower_margin = 5,
  246. .hsync_len = 20,
  247. .vsync_len = 10,
  248. .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
  249. .vmode = FB_VMODE_NONINTERLACED,
  250. .flag = 0,
  251. },
  252. };
  253. static struct ipu_platform_data mx3_ipu_data = {
  254. .irq_base = MXC_IPU_IRQ_START,
  255. };
  256. static struct mx3fb_platform_data mx3fb_pdata __initdata = {
  257. .name = "Epson-VGA",
  258. .mode = fb_modedb,
  259. .num_modes = ARRAY_SIZE(fb_modedb),
  260. };
  261. /* LCD */
  262. static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
  263. .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
  264. .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
  265. };
  266. /*
  267. * Support for SD card slot in personality board
  268. */
  269. #define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
  270. #define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
  271. static struct gpio mx31_3ds_sdhc1_gpios[] = {
  272. { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
  273. { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
  274. };
  275. static int mx31_3ds_sdhc1_init(struct device *dev,
  276. irq_handler_t detect_irq,
  277. void *data)
  278. {
  279. int ret;
  280. ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
  281. ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
  282. if (ret) {
  283. pr_warning("Unable to request the SD/MMC GPIOs.\n");
  284. return ret;
  285. }
  286. ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
  287. detect_irq, IRQF_DISABLED |
  288. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  289. "sdhc1-detect", data);
  290. if (ret) {
  291. pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
  292. goto gpio_free;
  293. }
  294. return 0;
  295. gpio_free:
  296. gpio_free_array(mx31_3ds_sdhc1_gpios,
  297. ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
  298. return ret;
  299. }
  300. static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
  301. {
  302. free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
  303. gpio_free_array(mx31_3ds_sdhc1_gpios,
  304. ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
  305. }
  306. static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
  307. {
  308. /*
  309. * While the voltage stuff is done by the driver, activate the
  310. * Buffer Enable Pin only if there is a card in slot to fix the card
  311. * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
  312. * Done here because at this stage we have for sure a debounced value
  313. * of the presence of the card, showed by the value of vdd.
  314. * 7 == ilog2(MMC_VDD_165_195)
  315. */
  316. if (vdd > 7)
  317. gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
  318. else
  319. gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
  320. }
  321. static struct imxmmc_platform_data sdhc1_pdata = {
  322. .init = mx31_3ds_sdhc1_init,
  323. .exit = mx31_3ds_sdhc1_exit,
  324. .setpower = mx31_3ds_sdhc1_setpower,
  325. };
  326. /*
  327. * Matrix keyboard
  328. */
  329. static const uint32_t mx31_3ds_keymap[] = {
  330. KEY(0, 0, KEY_UP),
  331. KEY(0, 1, KEY_DOWN),
  332. KEY(1, 0, KEY_RIGHT),
  333. KEY(1, 1, KEY_LEFT),
  334. KEY(1, 2, KEY_ENTER),
  335. KEY(2, 0, KEY_F6),
  336. KEY(2, 1, KEY_F8),
  337. KEY(2, 2, KEY_F9),
  338. KEY(2, 3, KEY_F10),
  339. };
  340. static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
  341. .keymap = mx31_3ds_keymap,
  342. .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
  343. };
  344. /* Regulators */
  345. static struct regulator_init_data pwgtx_init = {
  346. .constraints = {
  347. .boot_on = 1,
  348. .always_on = 1,
  349. },
  350. };
  351. static struct regulator_init_data gpo_init = {
  352. .constraints = {
  353. .boot_on = 1,
  354. .always_on = 1,
  355. }
  356. };
  357. static struct regulator_consumer_supply vmmc2_consumers[] = {
  358. REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
  359. };
  360. static struct regulator_init_data vmmc2_init = {
  361. .constraints = {
  362. .min_uV = 3000000,
  363. .max_uV = 3000000,
  364. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
  365. REGULATOR_CHANGE_STATUS,
  366. },
  367. .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
  368. .consumer_supplies = vmmc2_consumers,
  369. };
  370. static struct regulator_consumer_supply vmmc1_consumers[] = {
  371. REGULATOR_SUPPLY("vcore", "spi0.0"),
  372. REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
  373. };
  374. static struct regulator_init_data vmmc1_init = {
  375. .constraints = {
  376. .min_uV = 2800000,
  377. .max_uV = 2800000,
  378. .apply_uV = 1,
  379. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
  380. REGULATOR_CHANGE_STATUS,
  381. },
  382. .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
  383. .consumer_supplies = vmmc1_consumers,
  384. };
  385. static struct regulator_consumer_supply vgen_consumers[] = {
  386. REGULATOR_SUPPLY("vdd", "spi0.0"),
  387. };
  388. static struct regulator_init_data vgen_init = {
  389. .constraints = {
  390. .min_uV = 1800000,
  391. .max_uV = 1800000,
  392. .apply_uV = 1,
  393. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
  394. REGULATOR_CHANGE_STATUS,
  395. },
  396. .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
  397. .consumer_supplies = vgen_consumers,
  398. };
  399. static struct regulator_consumer_supply vvib_consumers[] = {
  400. REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
  401. };
  402. static struct regulator_init_data vvib_init = {
  403. .constraints = {
  404. .min_uV = 1300000,
  405. .max_uV = 1300000,
  406. .apply_uV = 1,
  407. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
  408. REGULATOR_CHANGE_STATUS,
  409. },
  410. .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
  411. .consumer_supplies = vvib_consumers,
  412. };
  413. static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
  414. {
  415. .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
  416. .init_data = &pwgtx_init,
  417. }, {
  418. .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
  419. .init_data = &pwgtx_init,
  420. }, {
  421. .id = MC13783_REG_GPO1, /* Turn on 1.8V */
  422. .init_data = &gpo_init,
  423. }, {
  424. .id = MC13783_REG_GPO3, /* Turn on 3.3V */
  425. .init_data = &gpo_init,
  426. }, {
  427. .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
  428. .init_data = &vmmc2_init,
  429. }, {
  430. .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
  431. .init_data = &vmmc1_init,
  432. }, {
  433. .id = MC13783_REG_VGEN, /* Power LCD */
  434. .init_data = &vgen_init,
  435. }, {
  436. .id = MC13783_REG_VVIB, /* Power CMOS */
  437. .init_data = &vvib_init,
  438. },
  439. };
  440. /* MC13783 */
  441. static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
  442. .dac_ssi_port = MC13783_SSI1_PORT,
  443. .adc_ssi_port = MC13783_SSI1_PORT,
  444. };
  445. static struct mc13xxx_platform_data mc13783_pdata = {
  446. .regulators = {
  447. .regulators = mx31_3ds_regulators,
  448. .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
  449. },
  450. .codec = &mx31_3ds_codec,
  451. .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
  452. };
  453. static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
  454. .flags = IMX_SSI_DMA | IMX_SSI_NET,
  455. };
  456. /* SPI */
  457. static int spi0_internal_chipselect[] = {
  458. MXC_SPI_CS(2),
  459. };
  460. static const struct spi_imx_master spi0_pdata __initconst = {
  461. .chipselect = spi0_internal_chipselect,
  462. .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
  463. };
  464. static int spi1_internal_chipselect[] = {
  465. MXC_SPI_CS(0),
  466. MXC_SPI_CS(2),
  467. };
  468. static const struct spi_imx_master spi1_pdata __initconst = {
  469. .chipselect = spi1_internal_chipselect,
  470. .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
  471. };
  472. static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
  473. {
  474. .modalias = "mc13783",
  475. .max_speed_hz = 1000000,
  476. .bus_num = 1,
  477. .chip_select = 1, /* SS2 */
  478. .platform_data = &mc13783_pdata,
  479. .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
  480. .mode = SPI_CS_HIGH,
  481. }, {
  482. .modalias = "l4f00242t03",
  483. .max_speed_hz = 5000000,
  484. .bus_num = 0,
  485. .chip_select = 0, /* SS2 */
  486. .platform_data = &mx31_3ds_l4f00242t03_pdata,
  487. },
  488. };
  489. /*
  490. * NAND Flash
  491. */
  492. static const struct mxc_nand_platform_data
  493. mx31_3ds_nand_board_info __initconst = {
  494. .width = 1,
  495. .hw_ecc = 1,
  496. #ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
  497. .flash_bbt = 1,
  498. #endif
  499. };
  500. /*
  501. * USB OTG
  502. */
  503. #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
  504. PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
  505. #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
  506. #define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
  507. static int mx31_3ds_usbotg_init(void)
  508. {
  509. int err;
  510. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
  511. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
  512. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
  513. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
  514. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
  515. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
  516. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
  517. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
  518. mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
  519. mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
  520. mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
  521. mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
  522. err = gpio_request(USBOTG_RST_B, "otgusb-reset");
  523. if (err) {
  524. pr_err("Failed to request the USB OTG reset gpio\n");
  525. return err;
  526. }
  527. err = gpio_direction_output(USBOTG_RST_B, 0);
  528. if (err) {
  529. pr_err("Failed to drive the USB OTG reset gpio\n");
  530. goto usbotg_free_reset;
  531. }
  532. mdelay(1);
  533. gpio_set_value(USBOTG_RST_B, 1);
  534. return 0;
  535. usbotg_free_reset:
  536. gpio_free(USBOTG_RST_B);
  537. return err;
  538. }
  539. static int mx31_3ds_otg_init(struct platform_device *pdev)
  540. {
  541. return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
  542. }
  543. static int mx31_3ds_host2_init(struct platform_device *pdev)
  544. {
  545. int err;
  546. mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
  547. mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
  548. mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
  549. mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
  550. mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
  551. mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
  552. mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
  553. mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
  554. mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
  555. mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
  556. mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
  557. mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
  558. err = gpio_request(USBH2_RST_B, "usbh2-reset");
  559. if (err) {
  560. pr_err("Failed to request the USB Host 2 reset gpio\n");
  561. return err;
  562. }
  563. err = gpio_direction_output(USBH2_RST_B, 0);
  564. if (err) {
  565. pr_err("Failed to drive the USB Host 2 reset gpio\n");
  566. goto usbotg_free_reset;
  567. }
  568. mdelay(1);
  569. gpio_set_value(USBH2_RST_B, 1);
  570. mdelay(10);
  571. return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
  572. usbotg_free_reset:
  573. gpio_free(USBH2_RST_B);
  574. return err;
  575. }
  576. static struct mxc_usbh_platform_data otg_pdata __initdata = {
  577. .init = mx31_3ds_otg_init,
  578. .portsc = MXC_EHCI_MODE_ULPI,
  579. };
  580. static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
  581. .init = mx31_3ds_host2_init,
  582. .portsc = MXC_EHCI_MODE_ULPI,
  583. };
  584. static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
  585. .operating_mode = FSL_USB2_DR_DEVICE,
  586. .phy_mode = FSL_USB2_PHY_ULPI,
  587. };
  588. static int otg_mode_host;
  589. static int __init mx31_3ds_otg_mode(char *options)
  590. {
  591. if (!strcmp(options, "host"))
  592. otg_mode_host = 1;
  593. else if (!strcmp(options, "device"))
  594. otg_mode_host = 0;
  595. else
  596. pr_info("otg_mode neither \"host\" nor \"device\". "
  597. "Defaulting to device\n");
  598. return 0;
  599. }
  600. __setup("otg_mode=", mx31_3ds_otg_mode);
  601. static const struct imxuart_platform_data uart_pdata __initconst = {
  602. .flags = IMXUART_HAVE_RTSCTS,
  603. };
  604. static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
  605. .bitrate = 100000,
  606. };
  607. static struct platform_device *devices[] __initdata = {
  608. &mx31_3ds_ov2640,
  609. };
  610. static void __init mx31_3ds_init(void)
  611. {
  612. int ret;
  613. imx31_soc_init();
  614. /* Configure SPI1 IOMUX */
  615. mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
  616. mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
  617. "mx31_3ds");
  618. imx31_add_imx_uart0(&uart_pdata);
  619. imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
  620. imx31_add_spi_imx1(&spi1_pdata);
  621. spi_register_board_info(mx31_3ds_spi_devs,
  622. ARRAY_SIZE(mx31_3ds_spi_devs));
  623. platform_add_devices(devices, ARRAY_SIZE(devices));
  624. imx31_add_imx_keypad(&mx31_3ds_keymap_data);
  625. mx31_3ds_usbotg_init();
  626. if (otg_mode_host) {
  627. otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
  628. ULPI_OTG_DRVVBUS_EXT);
  629. if (otg_pdata.otg)
  630. imx31_add_mxc_ehci_otg(&otg_pdata);
  631. }
  632. usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
  633. ULPI_OTG_DRVVBUS_EXT);
  634. if (usbh2_pdata.otg)
  635. imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
  636. if (!otg_mode_host)
  637. imx31_add_fsl_usb2_udc(&usbotg_pdata);
  638. if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
  639. printk(KERN_WARNING "Init of the debug board failed, all "
  640. "devices on the debug board are unusable.\n");
  641. imx31_add_imx2_wdt(NULL);
  642. imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
  643. imx31_add_mxc_mmc(0, &sdhc1_pdata);
  644. imx31_add_spi_imx0(&spi0_pdata);
  645. imx31_add_ipu_core(&mx3_ipu_data);
  646. imx31_add_mx3_sdc_fb(&mx3fb_pdata);
  647. /* CSI */
  648. /* Camera power: default - off */
  649. ret = gpio_request_array(mx31_3ds_camera_gpios,
  650. ARRAY_SIZE(mx31_3ds_camera_gpios));
  651. if (ret) {
  652. pr_err("Failed to request camera gpios");
  653. iclink_ov2640.power = NULL;
  654. }
  655. mx31_3ds_init_camera();
  656. imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
  657. imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
  658. }
  659. static void __init mx31_3ds_timer_init(void)
  660. {
  661. mx31_clocks_init(26000000);
  662. }
  663. static struct sys_timer mx31_3ds_timer = {
  664. .init = mx31_3ds_timer_init,
  665. };
  666. static void __init mx31_3ds_reserve(void)
  667. {
  668. /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
  669. mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
  670. MX31_3DS_CAMERA_BUF_SIZE);
  671. }
  672. MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
  673. /* Maintainer: Freescale Semiconductor, Inc. */
  674. .atag_offset = 0x100,
  675. .map_io = mx31_map_io,
  676. .init_early = imx31_init_early,
  677. .init_irq = mx31_init_irq,
  678. .handle_irq = imx31_handle_irq,
  679. .timer = &mx31_3ds_timer,
  680. .init_machine = mx31_3ds_init,
  681. .reserve = mx31_3ds_reserve,
  682. .restart = mxc_restart,
  683. MACHINE_END