tegra-seaboard.dts 9.7 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Seaboard";
  5. compatible = "nvidia,seaboard", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata";
  15. nvidia,function = "ide";
  16. };
  17. atb {
  18. nvidia,pins = "atb", "gma", "gme";
  19. nvidia,function = "sdio4";
  20. };
  21. atc {
  22. nvidia,pins = "atc";
  23. nvidia,function = "nand";
  24. };
  25. atd {
  26. nvidia,pins = "atd", "ate", "gmb", "spia",
  27. "spib", "spic";
  28. nvidia,function = "gmi";
  29. };
  30. cdev1 {
  31. nvidia,pins = "cdev1";
  32. nvidia,function = "plla_out";
  33. };
  34. cdev2 {
  35. nvidia,pins = "cdev2";
  36. nvidia,function = "pllp_out4";
  37. };
  38. crtp {
  39. nvidia,pins = "crtp", "lm1";
  40. nvidia,function = "crt";
  41. };
  42. csus {
  43. nvidia,pins = "csus";
  44. nvidia,function = "vi_sensor_clk";
  45. };
  46. dap1 {
  47. nvidia,pins = "dap1";
  48. nvidia,function = "dap1";
  49. };
  50. dap2 {
  51. nvidia,pins = "dap2";
  52. nvidia,function = "dap2";
  53. };
  54. dap3 {
  55. nvidia,pins = "dap3";
  56. nvidia,function = "dap3";
  57. };
  58. dap4 {
  59. nvidia,pins = "dap4";
  60. nvidia,function = "dap4";
  61. };
  62. ddc {
  63. nvidia,pins = "ddc", "owc", "spdi", "spdo",
  64. "uac";
  65. nvidia,function = "rsvd2";
  66. };
  67. dta {
  68. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  69. nvidia,function = "vi";
  70. };
  71. dtf {
  72. nvidia,pins = "dtf";
  73. nvidia,function = "i2c3";
  74. };
  75. gmc {
  76. nvidia,pins = "gmc";
  77. nvidia,function = "uartd";
  78. };
  79. gmd {
  80. nvidia,pins = "gmd";
  81. nvidia,function = "sflash";
  82. };
  83. gpu {
  84. nvidia,pins = "gpu";
  85. nvidia,function = "pwm";
  86. };
  87. gpu7 {
  88. nvidia,pins = "gpu7";
  89. nvidia,function = "rtck";
  90. };
  91. gpv {
  92. nvidia,pins = "gpv", "slxa", "slxk";
  93. nvidia,function = "pcie";
  94. };
  95. hdint {
  96. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  97. "lsck", "lsda";
  98. nvidia,function = "hdmi";
  99. };
  100. i2cp {
  101. nvidia,pins = "i2cp";
  102. nvidia,function = "i2cp";
  103. };
  104. irrx {
  105. nvidia,pins = "irrx", "irtx";
  106. nvidia,function = "uartb";
  107. };
  108. kbca {
  109. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  110. "kbce", "kbcf";
  111. nvidia,function = "kbc";
  112. };
  113. lcsn {
  114. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  115. "lsdi", "lvp0";
  116. nvidia,function = "rsvd4";
  117. };
  118. ld0 {
  119. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  120. "ld5", "ld6", "ld7", "ld8", "ld9",
  121. "ld10", "ld11", "ld12", "ld13", "ld14",
  122. "ld15", "ld16", "ld17", "ldi", "lhp0",
  123. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  124. "lspi", "lvp1", "lvs";
  125. nvidia,function = "displaya";
  126. };
  127. pmc {
  128. nvidia,pins = "pmc";
  129. nvidia,function = "pwr_on";
  130. };
  131. pta {
  132. nvidia,pins = "pta";
  133. nvidia,function = "i2c2";
  134. };
  135. rm {
  136. nvidia,pins = "rm";
  137. nvidia,function = "i2c1";
  138. };
  139. sdb {
  140. nvidia,pins = "sdb", "sdc", "sdd";
  141. nvidia,function = "sdio3";
  142. };
  143. sdio1 {
  144. nvidia,pins = "sdio1";
  145. nvidia,function = "sdio1";
  146. };
  147. slxc {
  148. nvidia,pins = "slxc", "slxd";
  149. nvidia,function = "spdif";
  150. };
  151. spid {
  152. nvidia,pins = "spid", "spie", "spif";
  153. nvidia,function = "spi1";
  154. };
  155. spig {
  156. nvidia,pins = "spig", "spih";
  157. nvidia,function = "spi2_alt";
  158. };
  159. uaa {
  160. nvidia,pins = "uaa", "uab", "uda";
  161. nvidia,function = "ulpi";
  162. };
  163. uad {
  164. nvidia,pins = "uad";
  165. nvidia,function = "irda";
  166. };
  167. uca {
  168. nvidia,pins = "uca", "ucb";
  169. nvidia,function = "uartc";
  170. };
  171. conf_ata {
  172. nvidia,pins = "ata", "atb", "atc", "atd",
  173. "cdev1", "cdev2", "dap1", "dap2",
  174. "dap4", "dtf", "gma", "gmc", "gmd",
  175. "gme", "gpu", "gpu7", "i2cp", "irrx",
  176. "irtx", "pta", "rm", "sdc", "sdd",
  177. "slxd", "slxk", "spdi", "spdo", "uac",
  178. "uad", "uca", "ucb", "uda";
  179. nvidia,pull = <0>;
  180. nvidia,tristate = <0>;
  181. };
  182. conf_ate {
  183. nvidia,pins = "ate", "csus", "dap3", "ddc",
  184. "gpv", "owc", "slxc", "spib", "spid",
  185. "spie";
  186. nvidia,pull = <0>;
  187. nvidia,tristate = <1>;
  188. };
  189. conf_ck32 {
  190. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  191. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  192. nvidia,pull = <0>;
  193. };
  194. conf_crtp {
  195. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  196. "spig", "spih";
  197. nvidia,pull = <2>;
  198. nvidia,tristate = <1>;
  199. };
  200. conf_dta {
  201. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  202. nvidia,pull = <1>;
  203. nvidia,tristate = <0>;
  204. };
  205. conf_dte {
  206. nvidia,pins = "dte", "spif";
  207. nvidia,pull = <1>;
  208. nvidia,tristate = <1>;
  209. };
  210. conf_hdint {
  211. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  212. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  213. "lvp0";
  214. nvidia,tristate = <1>;
  215. };
  216. conf_kbca {
  217. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  218. "kbce", "kbcf", "sdio1", "spic", "uaa",
  219. "uab";
  220. nvidia,pull = <2>;
  221. nvidia,tristate = <0>;
  222. };
  223. conf_lc {
  224. nvidia,pins = "lc", "ls";
  225. nvidia,pull = <2>;
  226. };
  227. conf_ld0 {
  228. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  229. "ld5", "ld6", "ld7", "ld8", "ld9",
  230. "ld10", "ld11", "ld12", "ld13", "ld14",
  231. "ld15", "ld16", "ld17", "ldi", "lhp0",
  232. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  233. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  234. "lvs", "pmc", "sdb";
  235. nvidia,tristate = <0>;
  236. };
  237. conf_ld17_0 {
  238. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  239. "ld23_22";
  240. nvidia,pull = <1>;
  241. };
  242. drive_sdio1 {
  243. nvidia,pins = "drive_sdio1";
  244. nvidia,high-speed-mode = <0>;
  245. nvidia,schmitt = <0>;
  246. nvidia,low-power-mode = <3>;
  247. nvidia,pull-down-strength = <31>;
  248. nvidia,pull-up-strength = <31>;
  249. nvidia,slew-rate-rising = <3>;
  250. nvidia,slew-rate-falling = <3>;
  251. };
  252. };
  253. };
  254. i2s@70002800 {
  255. status = "okay";
  256. };
  257. serial@70006300 {
  258. status = "okay";
  259. clock-frequency = <216000000>;
  260. };
  261. i2c@7000c000 {
  262. status = "okay";
  263. clock-frequency = <400000>;
  264. wm8903: wm8903@1a {
  265. compatible = "wlf,wm8903";
  266. reg = <0x1a>;
  267. interrupt-parent = <&gpio>;
  268. interrupts = <187 0x04>;
  269. gpio-controller;
  270. #gpio-cells = <2>;
  271. micdet-cfg = <0>;
  272. micdet-delay = <100>;
  273. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  274. };
  275. /* ALS and proximity sensor */
  276. isl29018@44 {
  277. compatible = "isil,isl29018";
  278. reg = <0x44>;
  279. interrupt-parent = <&gpio>;
  280. interrupts = <202 0x04>; /* GPIO PZ2 */
  281. };
  282. gyrometer@68 {
  283. compatible = "invn,mpu3050";
  284. reg = <0x68>;
  285. interrupt-parent = <&gpio>;
  286. interrupts = <204 0x04>; /* gpio PZ4 */
  287. };
  288. };
  289. i2c@7000c400 {
  290. status = "okay";
  291. clock-frequency = <100000>;
  292. smart-battery@b {
  293. compatible = "ti,bq20z75", "smart-battery-1.1";
  294. reg = <0xb>;
  295. ti,i2c-retry-count = <2>;
  296. ti,poll-retry-count = <10>;
  297. };
  298. };
  299. i2c@7000c500 {
  300. status = "okay";
  301. clock-frequency = <400000>;
  302. };
  303. i2c@7000d000 {
  304. status = "okay";
  305. clock-frequency = <400000>;
  306. temperature-sensor@4c {
  307. compatible = "nct1008";
  308. reg = <0x4c>;
  309. };
  310. magnetometer@c {
  311. compatible = "ak8975";
  312. reg = <0xc>;
  313. interrupt-parent = <&gpio>;
  314. interrupts = <109 0x04>; /* gpio PN5 */
  315. };
  316. };
  317. emc {
  318. emc-table@190000 {
  319. reg = <190000>;
  320. compatible = "nvidia,tegra20-emc-table";
  321. clock-frequency = <190000>;
  322. nvidia,emc-registers = <0x0000000c 0x00000026
  323. 0x00000009 0x00000003 0x00000004 0x00000004
  324. 0x00000002 0x0000000c 0x00000003 0x00000003
  325. 0x00000002 0x00000001 0x00000004 0x00000005
  326. 0x00000004 0x00000009 0x0000000d 0x0000059f
  327. 0x00000000 0x00000003 0x00000003 0x00000003
  328. 0x00000003 0x00000001 0x0000000b 0x000000c8
  329. 0x00000003 0x00000007 0x00000004 0x0000000f
  330. 0x00000002 0x00000000 0x00000000 0x00000002
  331. 0x00000000 0x00000000 0x00000083 0xa06204ae
  332. 0x007dc010 0x00000000 0x00000000 0x00000000
  333. 0x00000000 0x00000000 0x00000000 0x00000000>;
  334. };
  335. emc-table@380000 {
  336. reg = <380000>;
  337. compatible = "nvidia,tegra20-emc-table";
  338. clock-frequency = <380000>;
  339. nvidia,emc-registers = <0x00000017 0x0000004b
  340. 0x00000012 0x00000006 0x00000004 0x00000005
  341. 0x00000003 0x0000000c 0x00000006 0x00000006
  342. 0x00000003 0x00000001 0x00000004 0x00000005
  343. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  344. 0x00000000 0x00000003 0x00000003 0x00000006
  345. 0x00000006 0x00000001 0x00000011 0x000000c8
  346. 0x00000003 0x0000000e 0x00000007 0x0000000f
  347. 0x00000002 0x00000000 0x00000000 0x00000002
  348. 0x00000000 0x00000000 0x00000083 0xe044048b
  349. 0x007d8010 0x00000000 0x00000000 0x00000000
  350. 0x00000000 0x00000000 0x00000000 0x00000000>;
  351. };
  352. };
  353. usb@c5000000 {
  354. status = "okay";
  355. nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
  356. dr_mode = "otg";
  357. };
  358. usb@c5004000 {
  359. status = "okay";
  360. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  361. };
  362. usb@c5008000 {
  363. status = "okay";
  364. };
  365. sdhci@c8000400 {
  366. status = "okay";
  367. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  368. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  369. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  370. bus-width = <4>;
  371. };
  372. sdhci@c8000600 {
  373. status = "okay";
  374. support-8bit;
  375. bus-width = <8>;
  376. };
  377. gpio-keys {
  378. compatible = "gpio-keys";
  379. power {
  380. label = "Power";
  381. gpios = <&gpio 170 1>; /* gpio PV2, active low */
  382. linux,code = <116>; /* KEY_POWER */
  383. gpio-key,wakeup;
  384. };
  385. lid {
  386. label = "Lid";
  387. gpios = <&gpio 23 0>; /* gpio PC7 */
  388. linux,input-type = <5>; /* EV_SW */
  389. linux,code = <0>; /* SW_LID */
  390. debounce-interval = <1>;
  391. gpio-key,wakeup;
  392. };
  393. };
  394. sound {
  395. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  396. "nvidia,tegra-audio-wm8903";
  397. nvidia,model = "NVIDIA Tegra Seaboard";
  398. nvidia,audio-routing =
  399. "Headphone Jack", "HPOUTR",
  400. "Headphone Jack", "HPOUTL",
  401. "Int Spk", "ROP",
  402. "Int Spk", "RON",
  403. "Int Spk", "LOP",
  404. "Int Spk", "LON",
  405. "Mic Jack", "MICBIAS",
  406. "IN1R", "Mic Jack";
  407. nvidia,i2s-controller = <&tegra_i2s1>;
  408. nvidia,audio-codec = <&wm8903>;
  409. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  410. nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
  411. };
  412. };