phy3250.dts 2.6 KB

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  1. /*
  2. * PHYTEC phyCORE-LPC3250 board
  3. *
  4. * Copyright 2012 Roland Stigge <stigge@antcom.de>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /dts-v1/;
  14. /include/ "lpc32xx.dtsi"
  15. / {
  16. model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
  17. compatible = "phytec,phy3250", "nxp,lpc3250";
  18. #address-cells = <1>;
  19. #size-cells = <1>;
  20. memory {
  21. device_type = "memory";
  22. reg = <0 0x4000000>;
  23. };
  24. ahb {
  25. mac: ethernet@31060000 {
  26. phy-mode = "rmii";
  27. use-iram;
  28. };
  29. /* Here, choose exactly one from: ohci, usbd */
  30. ohci@31020000 {
  31. transceiver = <&isp1301>;
  32. status = "okay";
  33. };
  34. /*
  35. usbd@31020000 {
  36. transceiver = <&isp1301>;
  37. status = "okay";
  38. };
  39. */
  40. clcd@31040000 {
  41. status = "okay";
  42. };
  43. /* 64MB Flash via SLC NAND controller */
  44. slc: flash@20020000 {
  45. status = "okay";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. mtd0@00000000 {
  49. label = "phy3250-boot";
  50. reg = <0x00000000 0x00064000>;
  51. read-only;
  52. };
  53. mtd1@00064000 {
  54. label = "phy3250-uboot";
  55. reg = <0x00064000 0x00190000>;
  56. read-only;
  57. };
  58. mtd2@001f4000 {
  59. label = "phy3250-ubt-prms";
  60. reg = <0x001f4000 0x00010000>;
  61. };
  62. mtd3@00204000 {
  63. label = "phy3250-kernel";
  64. reg = <0x00204000 0x00400000>;
  65. };
  66. mtd4@00604000 {
  67. label = "phy3250-rootfs";
  68. reg = <0x00604000 0x039fc000>;
  69. };
  70. };
  71. apb {
  72. i2c1: i2c@400A0000 {
  73. clock-frequency = <100000>;
  74. pcf8563: rtc@51 {
  75. compatible = "nxp,pcf8563";
  76. reg = <0x51>;
  77. };
  78. uda1380: uda1380@18 {
  79. compatible = "nxp,uda1380";
  80. reg = <0x18>;
  81. power-gpio = <&gpio 0x59 0>;
  82. reset-gpio = <&gpio 0x51 0>;
  83. dac-clk = "wspll";
  84. };
  85. };
  86. i2c2: i2c@400A8000 {
  87. clock-frequency = <100000>;
  88. };
  89. i2cusb: i2c@31020300 {
  90. clock-frequency = <100000>;
  91. isp1301: usb-transceiver@2c {
  92. compatible = "nxp,isp1301";
  93. reg = <0x2c>;
  94. };
  95. };
  96. ssp0: ssp@20084000 {
  97. eeprom: at25@0 {
  98. compatible = "atmel,at25";
  99. };
  100. };
  101. };
  102. fab {
  103. tsc@40048000 {
  104. status = "okay";
  105. };
  106. };
  107. };
  108. leds {
  109. compatible = "gpio-leds";
  110. led0 {
  111. gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
  112. linux,default-trigger = "heartbeat";
  113. default-state = "off";
  114. };
  115. led1 {
  116. gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
  117. linux,default-trigger = "timer";
  118. default-state = "off";
  119. };
  120. };
  121. };