imx28.dtsi 9.5 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. saif0 = &saif0;
  21. saif1 = &saif1;
  22. };
  23. cpus {
  24. cpu@0 {
  25. compatible = "arm,arm926ejs";
  26. };
  27. };
  28. apb@80000000 {
  29. compatible = "simple-bus";
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. reg = <0x80000000 0x80000>;
  33. ranges;
  34. apbh@80000000 {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. reg = <0x80000000 0x3c900>;
  39. ranges;
  40. icoll: interrupt-controller@80000000 {
  41. compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
  42. interrupt-controller;
  43. #interrupt-cells = <1>;
  44. reg = <0x80000000 0x2000>;
  45. };
  46. hsadc@80002000 {
  47. reg = <0x80002000 2000>;
  48. interrupts = <13 87>;
  49. status = "disabled";
  50. };
  51. dma-apbh@80004000 {
  52. compatible = "fsl,imx28-dma-apbh";
  53. reg = <0x80004000 2000>;
  54. };
  55. perfmon@80006000 {
  56. reg = <0x80006000 800>;
  57. interrupts = <27>;
  58. status = "disabled";
  59. };
  60. bch@8000a000 {
  61. reg = <0x8000a000 2000>;
  62. interrupts = <41>;
  63. status = "disabled";
  64. };
  65. gpmi@8000c000 {
  66. reg = <0x8000c000 2000>;
  67. interrupts = <42 88>;
  68. status = "disabled";
  69. };
  70. ssp0: ssp@80010000 {
  71. reg = <0x80010000 2000>;
  72. interrupts = <96 82>;
  73. fsl,ssp-dma-channel = <0>;
  74. status = "disabled";
  75. };
  76. ssp1: ssp@80012000 {
  77. reg = <0x80012000 2000>;
  78. interrupts = <97 83>;
  79. fsl,ssp-dma-channel = <1>;
  80. status = "disabled";
  81. };
  82. ssp2: ssp@80014000 {
  83. reg = <0x80014000 2000>;
  84. interrupts = <98 84>;
  85. fsl,ssp-dma-channel = <2>;
  86. status = "disabled";
  87. };
  88. ssp3: ssp@80016000 {
  89. reg = <0x80016000 2000>;
  90. interrupts = <99 85>;
  91. fsl,ssp-dma-channel = <3>;
  92. status = "disabled";
  93. };
  94. pinctrl@80018000 {
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. compatible = "fsl,imx28-pinctrl", "simple-bus";
  98. reg = <0x80018000 2000>;
  99. gpio0: gpio@0 {
  100. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  101. interrupts = <127>;
  102. gpio-controller;
  103. #gpio-cells = <2>;
  104. interrupt-controller;
  105. #interrupt-cells = <2>;
  106. };
  107. gpio1: gpio@1 {
  108. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  109. interrupts = <126>;
  110. gpio-controller;
  111. #gpio-cells = <2>;
  112. interrupt-controller;
  113. #interrupt-cells = <2>;
  114. };
  115. gpio2: gpio@2 {
  116. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  117. interrupts = <125>;
  118. gpio-controller;
  119. #gpio-cells = <2>;
  120. interrupt-controller;
  121. #interrupt-cells = <2>;
  122. };
  123. gpio3: gpio@3 {
  124. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  125. interrupts = <124>;
  126. gpio-controller;
  127. #gpio-cells = <2>;
  128. interrupt-controller;
  129. #interrupt-cells = <2>;
  130. };
  131. gpio4: gpio@4 {
  132. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  133. interrupts = <123>;
  134. gpio-controller;
  135. #gpio-cells = <2>;
  136. interrupt-controller;
  137. #interrupt-cells = <2>;
  138. };
  139. duart_pins_a: duart@0 {
  140. reg = <0>;
  141. fsl,pinmux-ids = <0x3102 0x3112>;
  142. fsl,drive-strength = <0>;
  143. fsl,voltage = <1>;
  144. fsl,pull-up = <0>;
  145. };
  146. mac0_pins_a: mac0@0 {
  147. reg = <0>;
  148. fsl,pinmux-ids = <0x4000 0x4010 0x4020
  149. 0x4030 0x4040 0x4060 0x4070
  150. 0x4080 0x4100>;
  151. fsl,drive-strength = <1>;
  152. fsl,voltage = <1>;
  153. fsl,pull-up = <1>;
  154. };
  155. mac1_pins_a: mac1@0 {
  156. reg = <0>;
  157. fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
  158. 0x40e1 0x40b1 0x40c1>;
  159. fsl,drive-strength = <1>;
  160. fsl,voltage = <1>;
  161. fsl,pull-up = <1>;
  162. };
  163. mmc0_8bit_pins_a: mmc0-8bit@0 {
  164. reg = <0>;
  165. fsl,pinmux-ids = <0x2000 0x2010 0x2020
  166. 0x2030 0x2040 0x2050 0x2060
  167. 0x2070 0x2080 0x2090 0x20a0>;
  168. fsl,drive-strength = <1>;
  169. fsl,voltage = <1>;
  170. fsl,pull-up = <1>;
  171. };
  172. mmc0_cd_cfg: mmc0-cd-cfg {
  173. fsl,pinmux-ids = <0x2090>;
  174. fsl,pull-up = <0>;
  175. };
  176. mmc0_sck_cfg: mmc0-sck-cfg {
  177. fsl,pinmux-ids = <0x20a0>;
  178. fsl,drive-strength = <2>;
  179. fsl,pull-up = <0>;
  180. };
  181. i2c0_pins_a: i2c0@0 {
  182. reg = <0>;
  183. fsl,pinmux-ids = <0x3180 0x3190>;
  184. fsl,drive-strength = <1>;
  185. fsl,voltage = <1>;
  186. fsl,pull-up = <1>;
  187. };
  188. saif0_pins_a: saif0@0 {
  189. reg = <0>;
  190. fsl,pinmux-ids =
  191. <0x3140 0x3150 0x3160 0x3170>;
  192. fsl,drive-strength = <2>;
  193. fsl,voltage = <1>;
  194. fsl,pull-up = <1>;
  195. };
  196. saif1_pins_a: saif1@0 {
  197. reg = <0>;
  198. fsl,pinmux-ids = <0x31a0>;
  199. fsl,drive-strength = <2>;
  200. fsl,voltage = <1>;
  201. fsl,pull-up = <1>;
  202. };
  203. };
  204. digctl@8001c000 {
  205. reg = <0x8001c000 2000>;
  206. interrupts = <89>;
  207. status = "disabled";
  208. };
  209. etm@80022000 {
  210. reg = <0x80022000 2000>;
  211. status = "disabled";
  212. };
  213. dma-apbx@80024000 {
  214. compatible = "fsl,imx28-dma-apbx";
  215. reg = <0x80024000 2000>;
  216. };
  217. dcp@80028000 {
  218. reg = <0x80028000 2000>;
  219. interrupts = <52 53 54>;
  220. status = "disabled";
  221. };
  222. pxp@8002a000 {
  223. reg = <0x8002a000 2000>;
  224. interrupts = <39>;
  225. status = "disabled";
  226. };
  227. ocotp@8002c000 {
  228. reg = <0x8002c000 2000>;
  229. status = "disabled";
  230. };
  231. axi-ahb@8002e000 {
  232. reg = <0x8002e000 2000>;
  233. status = "disabled";
  234. };
  235. lcdif@80030000 {
  236. reg = <0x80030000 2000>;
  237. interrupts = <38 86>;
  238. status = "disabled";
  239. };
  240. can0: can@80032000 {
  241. reg = <0x80032000 2000>;
  242. interrupts = <8>;
  243. status = "disabled";
  244. };
  245. can1: can@80034000 {
  246. reg = <0x80034000 2000>;
  247. interrupts = <9>;
  248. status = "disabled";
  249. };
  250. simdbg@8003c000 {
  251. reg = <0x8003c000 200>;
  252. status = "disabled";
  253. };
  254. simgpmisel@8003c200 {
  255. reg = <0x8003c200 100>;
  256. status = "disabled";
  257. };
  258. simsspsel@8003c300 {
  259. reg = <0x8003c300 100>;
  260. status = "disabled";
  261. };
  262. simmemsel@8003c400 {
  263. reg = <0x8003c400 100>;
  264. status = "disabled";
  265. };
  266. gpiomon@8003c500 {
  267. reg = <0x8003c500 100>;
  268. status = "disabled";
  269. };
  270. simenet@8003c700 {
  271. reg = <0x8003c700 100>;
  272. status = "disabled";
  273. };
  274. armjtag@8003c800 {
  275. reg = <0x8003c800 100>;
  276. status = "disabled";
  277. };
  278. };
  279. apbx@80040000 {
  280. compatible = "simple-bus";
  281. #address-cells = <1>;
  282. #size-cells = <1>;
  283. reg = <0x80040000 0x40000>;
  284. ranges;
  285. clkctl@80040000 {
  286. reg = <0x80040000 2000>;
  287. status = "disabled";
  288. };
  289. saif0: saif@80042000 {
  290. compatible = "fsl,imx28-saif";
  291. reg = <0x80042000 2000>;
  292. interrupts = <59 80>;
  293. fsl,saif-dma-channel = <4>;
  294. status = "disabled";
  295. };
  296. power@80044000 {
  297. reg = <0x80044000 2000>;
  298. status = "disabled";
  299. };
  300. saif1: saif@80046000 {
  301. compatible = "fsl,imx28-saif";
  302. reg = <0x80046000 2000>;
  303. interrupts = <58 81>;
  304. fsl,saif-dma-channel = <5>;
  305. status = "disabled";
  306. };
  307. lradc@80050000 {
  308. reg = <0x80050000 2000>;
  309. status = "disabled";
  310. };
  311. spdif@80054000 {
  312. reg = <0x80054000 2000>;
  313. interrupts = <45 66>;
  314. status = "disabled";
  315. };
  316. rtc@80056000 {
  317. reg = <0x80056000 2000>;
  318. interrupts = <28 29>;
  319. status = "disabled";
  320. };
  321. i2c0: i2c@80058000 {
  322. #address-cells = <1>;
  323. #size-cells = <0>;
  324. compatible = "fsl,imx28-i2c";
  325. reg = <0x80058000 2000>;
  326. interrupts = <111 68>;
  327. status = "disabled";
  328. };
  329. i2c1: i2c@8005a000 {
  330. #address-cells = <1>;
  331. #size-cells = <0>;
  332. compatible = "fsl,imx28-i2c";
  333. reg = <0x8005a000 2000>;
  334. interrupts = <110 69>;
  335. status = "disabled";
  336. };
  337. pwm@80064000 {
  338. reg = <0x80064000 2000>;
  339. status = "disabled";
  340. };
  341. timrot@80068000 {
  342. reg = <0x80068000 2000>;
  343. status = "disabled";
  344. };
  345. auart0: serial@8006a000 {
  346. reg = <0x8006a000 0x2000>;
  347. interrupts = <112 70 71>;
  348. status = "disabled";
  349. };
  350. auart1: serial@8006c000 {
  351. reg = <0x8006c000 0x2000>;
  352. interrupts = <113 72 73>;
  353. status = "disabled";
  354. };
  355. auart2: serial@8006e000 {
  356. reg = <0x8006e000 0x2000>;
  357. interrupts = <114 74 75>;
  358. status = "disabled";
  359. };
  360. auart3: serial@80070000 {
  361. reg = <0x80070000 0x2000>;
  362. interrupts = <115 76 77>;
  363. status = "disabled";
  364. };
  365. auart4: serial@80072000 {
  366. reg = <0x80072000 0x2000>;
  367. interrupts = <116 78 79>;
  368. status = "disabled";
  369. };
  370. duart: serial@80074000 {
  371. compatible = "arm,pl011", "arm,primecell";
  372. reg = <0x80074000 0x1000>;
  373. interrupts = <47>;
  374. status = "disabled";
  375. };
  376. usbphy0: usbphy@8007c000 {
  377. reg = <0x8007c000 0x2000>;
  378. status = "disabled";
  379. };
  380. usbphy1: usbphy@8007e000 {
  381. reg = <0x8007e000 0x2000>;
  382. status = "disabled";
  383. };
  384. };
  385. };
  386. ahb@80080000 {
  387. compatible = "simple-bus";
  388. #address-cells = <1>;
  389. #size-cells = <1>;
  390. reg = <0x80080000 0x80000>;
  391. ranges;
  392. usbctrl0: usbctrl@80080000 {
  393. reg = <0x80080000 0x10000>;
  394. status = "disabled";
  395. };
  396. usbctrl1: usbctrl@80090000 {
  397. reg = <0x80090000 0x10000>;
  398. status = "disabled";
  399. };
  400. dflpt@800c0000 {
  401. reg = <0x800c0000 0x10000>;
  402. status = "disabled";
  403. };
  404. mac0: ethernet@800f0000 {
  405. compatible = "fsl,imx28-fec";
  406. reg = <0x800f0000 0x4000>;
  407. interrupts = <101>;
  408. status = "disabled";
  409. };
  410. mac1: ethernet@800f4000 {
  411. compatible = "fsl,imx28-fec";
  412. reg = <0x800f4000 0x4000>;
  413. interrupts = <102>;
  414. status = "disabled";
  415. };
  416. switch@800f8000 {
  417. reg = <0x800f8000 0x8000>;
  418. status = "disabled";
  419. };
  420. };
  421. };