at91sam9x5.dtsi 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301
  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. memory {
  34. reg = <0x20000000 0x10000000>;
  35. };
  36. ahb {
  37. compatible = "simple-bus";
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. ranges;
  41. apb {
  42. compatible = "simple-bus";
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. aic: interrupt-controller@fffff000 {
  47. #interrupt-cells = <2>;
  48. compatible = "atmel,at91rm9200-aic";
  49. interrupt-controller;
  50. reg = <0xfffff000 0x200>;
  51. };
  52. ramc0: ramc@ffffe800 {
  53. compatible = "atmel,at91sam9g45-ddramc";
  54. reg = <0xffffe800 0x200>;
  55. };
  56. pmc: pmc@fffffc00 {
  57. compatible = "atmel,at91rm9200-pmc";
  58. reg = <0xfffffc00 0x100>;
  59. };
  60. rstc@fffffe00 {
  61. compatible = "atmel,at91sam9g45-rstc";
  62. reg = <0xfffffe00 0x10>;
  63. };
  64. shdwc@fffffe10 {
  65. compatible = "atmel,at91sam9x5-shdwc";
  66. reg = <0xfffffe10 0x10>;
  67. };
  68. pit: timer@fffffe30 {
  69. compatible = "atmel,at91sam9260-pit";
  70. reg = <0xfffffe30 0xf>;
  71. interrupts = <1 4>;
  72. };
  73. tcb0: timer@f8008000 {
  74. compatible = "atmel,at91sam9x5-tcb";
  75. reg = <0xf8008000 0x100>;
  76. interrupts = <17 4>;
  77. };
  78. tcb1: timer@f800c000 {
  79. compatible = "atmel,at91sam9x5-tcb";
  80. reg = <0xf800c000 0x100>;
  81. interrupts = <17 4>;
  82. };
  83. dma0: dma-controller@ffffec00 {
  84. compatible = "atmel,at91sam9g45-dma";
  85. reg = <0xffffec00 0x200>;
  86. interrupts = <20 4>;
  87. };
  88. dma1: dma-controller@ffffee00 {
  89. compatible = "atmel,at91sam9g45-dma";
  90. reg = <0xffffee00 0x200>;
  91. interrupts = <21 4>;
  92. };
  93. pioA: gpio@fffff400 {
  94. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  95. reg = <0xfffff400 0x100>;
  96. interrupts = <2 4>;
  97. #gpio-cells = <2>;
  98. gpio-controller;
  99. interrupt-controller;
  100. };
  101. pioB: gpio@fffff600 {
  102. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  103. reg = <0xfffff600 0x100>;
  104. interrupts = <2 4>;
  105. #gpio-cells = <2>;
  106. gpio-controller;
  107. interrupt-controller;
  108. };
  109. pioC: gpio@fffff800 {
  110. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  111. reg = <0xfffff800 0x100>;
  112. interrupts = <3 4>;
  113. #gpio-cells = <2>;
  114. gpio-controller;
  115. interrupt-controller;
  116. };
  117. pioD: gpio@fffffa00 {
  118. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  119. reg = <0xfffffa00 0x100>;
  120. interrupts = <3 4>;
  121. #gpio-cells = <2>;
  122. gpio-controller;
  123. interrupt-controller;
  124. };
  125. dbgu: serial@fffff200 {
  126. compatible = "atmel,at91sam9260-usart";
  127. reg = <0xfffff200 0x200>;
  128. interrupts = <1 4>;
  129. status = "disabled";
  130. };
  131. usart0: serial@f801c000 {
  132. compatible = "atmel,at91sam9260-usart";
  133. reg = <0xf801c000 0x200>;
  134. interrupts = <5 4>;
  135. atmel,use-dma-rx;
  136. atmel,use-dma-tx;
  137. status = "disabled";
  138. };
  139. usart1: serial@f8020000 {
  140. compatible = "atmel,at91sam9260-usart";
  141. reg = <0xf8020000 0x200>;
  142. interrupts = <6 4>;
  143. atmel,use-dma-rx;
  144. atmel,use-dma-tx;
  145. status = "disabled";
  146. };
  147. usart2: serial@f8024000 {
  148. compatible = "atmel,at91sam9260-usart";
  149. reg = <0xf8024000 0x200>;
  150. interrupts = <7 4>;
  151. atmel,use-dma-rx;
  152. atmel,use-dma-tx;
  153. status = "disabled";
  154. };
  155. macb0: ethernet@f802c000 {
  156. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  157. reg = <0xf802c000 0x100>;
  158. interrupts = <24 4>;
  159. status = "disabled";
  160. };
  161. macb1: ethernet@f8030000 {
  162. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  163. reg = <0xf8030000 0x100>;
  164. interrupts = <27 4>;
  165. status = "disabled";
  166. };
  167. adc0: adc@f804c000 {
  168. compatible = "atmel,at91sam9260-adc";
  169. reg = <0xf804c000 0x100>;
  170. interrupts = <19 4>;
  171. atmel,adc-use-external;
  172. atmel,adc-channels-used = <0xffff>;
  173. atmel,adc-vref = <3300>;
  174. atmel,adc-num-channels = <12>;
  175. atmel,adc-startup-time = <40>;
  176. atmel,adc-channel-base = <0x50>;
  177. atmel,adc-drdy-mask = <0x1000000>;
  178. atmel,adc-status-register = <0x30>;
  179. atmel,adc-trigger-register = <0xc0>;
  180. trigger@0 {
  181. trigger-name = "external-rising";
  182. trigger-value = <0x1>;
  183. trigger-external;
  184. };
  185. trigger@1 {
  186. trigger-name = "external-falling";
  187. trigger-value = <0x2>;
  188. trigger-external;
  189. };
  190. trigger@2 {
  191. trigger-name = "external-any";
  192. trigger-value = <0x3>;
  193. trigger-external;
  194. };
  195. trigger@3 {
  196. trigger-name = "continuous";
  197. trigger-value = <0x6>;
  198. };
  199. };
  200. };
  201. nand0: nand@40000000 {
  202. compatible = "atmel,at91rm9200-nand";
  203. #address-cells = <1>;
  204. #size-cells = <1>;
  205. reg = <0x40000000 0x10000000
  206. >;
  207. atmel,nand-addr-offset = <21>;
  208. atmel,nand-cmd-offset = <22>;
  209. gpios = <&pioD 5 0
  210. &pioD 4 0
  211. 0
  212. >;
  213. status = "disabled";
  214. };
  215. usb0: ohci@00600000 {
  216. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  217. reg = <0x00600000 0x100000>;
  218. interrupts = <22 4>;
  219. status = "disabled";
  220. };
  221. usb1: ehci@00700000 {
  222. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  223. reg = <0x00700000 0x100000>;
  224. interrupts = <22 4>;
  225. status = "disabled";
  226. };
  227. };
  228. i2c@0 {
  229. compatible = "i2c-gpio";
  230. gpios = <&pioA 30 0 /* sda */
  231. &pioA 31 0 /* scl */
  232. >;
  233. i2c-gpio,sda-open-drain;
  234. i2c-gpio,scl-open-drain;
  235. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. status = "disabled";
  239. };
  240. i2c@1 {
  241. compatible = "i2c-gpio";
  242. gpios = <&pioC 0 0 /* sda */
  243. &pioC 1 0 /* scl */
  244. >;
  245. i2c-gpio,sda-open-drain;
  246. i2c-gpio,scl-open-drain;
  247. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  248. #address-cells = <1>;
  249. #size-cells = <0>;
  250. status = "disabled";
  251. };
  252. i2c@2 {
  253. compatible = "i2c-gpio";
  254. gpios = <&pioB 4 0 /* sda */
  255. &pioB 5 0 /* scl */
  256. >;
  257. i2c-gpio,sda-open-drain;
  258. i2c-gpio,scl-open-drain;
  259. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  260. #address-cells = <1>;
  261. #size-cells = <0>;
  262. status = "disabled";
  263. };
  264. };