main.c 61 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
  151. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  152. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  153. ath_start_rx_poll(sc, 3);
  154. ath_start_ani(sc);
  155. }
  156. static bool ath_prepare_reset(struct ath_softc *sc)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. bool ret = true;
  160. ieee80211_stop_queues(sc->hw);
  161. sc->hw_busy_count = 0;
  162. ath_stop_ani(sc);
  163. del_timer_sync(&sc->rx_poll_timer);
  164. ath9k_hw_disable_interrupts(ah);
  165. if (!ath_drain_all_txq(sc))
  166. ret = false;
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. return ret;
  170. }
  171. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  172. {
  173. struct ath_hw *ah = sc->sc_ah;
  174. struct ath_common *common = ath9k_hw_common(ah);
  175. unsigned long flags;
  176. if (ath_startrecv(sc) != 0) {
  177. ath_err(common, "Unable to restart recv logic\n");
  178. return false;
  179. }
  180. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  181. sc->config.txpowlimit, &sc->curtxpow);
  182. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  183. ath9k_hw_set_interrupts(ah);
  184. ath9k_hw_enable_interrupts(ah);
  185. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  186. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  187. goto work;
  188. if (ah->opmode == NL80211_IFTYPE_STATION &&
  189. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  190. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  191. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  192. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  193. } else {
  194. ath9k_set_beacon(sc);
  195. }
  196. work:
  197. ath_restart_work(sc);
  198. }
  199. ieee80211_wake_queues(sc->hw);
  200. return true;
  201. }
  202. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  203. {
  204. struct ath_hw *ah = sc->sc_ah;
  205. struct ath_common *common = ath9k_hw_common(ah);
  206. struct ath9k_hw_cal_data *caldata = NULL;
  207. bool fastcc = true;
  208. int r;
  209. __ath_cancel_work(sc);
  210. tasklet_disable(&sc->intr_tq);
  211. spin_lock_bh(&sc->sc_pcu_lock);
  212. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  213. fastcc = false;
  214. caldata = &sc->caldata;
  215. }
  216. if (!hchan) {
  217. fastcc = false;
  218. hchan = ah->curchan;
  219. }
  220. if (!ath_prepare_reset(sc))
  221. fastcc = false;
  222. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  223. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  224. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  225. if (r) {
  226. ath_err(common,
  227. "Unable to reset channel, reset status %d\n", r);
  228. ath9k_hw_enable_interrupts(ah);
  229. ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
  230. goto out;
  231. }
  232. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  233. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  234. ath9k_mci_set_txpower(sc, true, false);
  235. if (!ath_complete_reset(sc, true))
  236. r = -EIO;
  237. out:
  238. spin_unlock_bh(&sc->sc_pcu_lock);
  239. tasklet_enable(&sc->intr_tq);
  240. return r;
  241. }
  242. /*
  243. * Set/change channels. If the channel is really being changed, it's done
  244. * by reseting the chip. To accomplish this we must first cleanup any pending
  245. * DMA, then restart stuff.
  246. */
  247. static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chandef)
  248. {
  249. struct ath_hw *ah = sc->sc_ah;
  250. struct ath_common *common = ath9k_hw_common(ah);
  251. struct ieee80211_hw *hw = sc->hw;
  252. struct ath9k_channel *hchan;
  253. struct ieee80211_channel *chan = chandef->chan;
  254. unsigned long flags;
  255. bool offchannel;
  256. int pos = chan->hw_value;
  257. int old_pos = -1;
  258. int r;
  259. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  260. return -EIO;
  261. offchannel = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
  262. if (ah->curchan)
  263. old_pos = ah->curchan - &ah->channels[0];
  264. ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n",
  265. chan->center_freq, chandef->width);
  266. /* update survey stats for the old channel before switching */
  267. spin_lock_irqsave(&common->cc_lock, flags);
  268. ath_update_survey_stats(sc);
  269. spin_unlock_irqrestore(&common->cc_lock, flags);
  270. ath9k_cmn_get_channel(hw, ah, chandef);
  271. /*
  272. * If the operating channel changes, change the survey in-use flags
  273. * along with it.
  274. * Reset the survey data for the new channel, unless we're switching
  275. * back to the operating channel from an off-channel operation.
  276. */
  277. if (!offchannel && sc->cur_survey != &sc->survey[pos]) {
  278. if (sc->cur_survey)
  279. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  280. sc->cur_survey = &sc->survey[pos];
  281. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  282. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  283. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  284. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  285. }
  286. hchan = &sc->sc_ah->channels[pos];
  287. r = ath_reset_internal(sc, hchan);
  288. if (r)
  289. return r;
  290. /*
  291. * The most recent snapshot of channel->noisefloor for the old
  292. * channel is only available after the hardware reset. Copy it to
  293. * the survey stats now.
  294. */
  295. if (old_pos >= 0)
  296. ath_update_survey_nf(sc, old_pos);
  297. /*
  298. * Enable radar pulse detection if on a DFS channel. Spectral
  299. * scanning and radar detection can not be used concurrently.
  300. */
  301. if (hw->conf.radar_enabled) {
  302. u32 rxfilter;
  303. /* set HW specific DFS configuration */
  304. ath9k_hw_set_radar_params(ah);
  305. rxfilter = ath9k_hw_getrxfilter(ah);
  306. rxfilter |= ATH9K_RX_FILTER_PHYRADAR |
  307. ATH9K_RX_FILTER_PHYERR;
  308. ath9k_hw_setrxfilter(ah, rxfilter);
  309. ath_dbg(common, DFS, "DFS enabled at freq %d\n",
  310. chan->center_freq);
  311. } else {
  312. /* perform spectral scan if requested. */
  313. if (test_bit(SC_OP_SCANNING, &sc->sc_flags) &&
  314. sc->spectral_mode == SPECTRAL_CHANSCAN)
  315. ath9k_spectral_scan_trigger(hw);
  316. }
  317. return 0;
  318. }
  319. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  320. struct ieee80211_vif *vif)
  321. {
  322. struct ath_node *an;
  323. an = (struct ath_node *)sta->drv_priv;
  324. an->sc = sc;
  325. an->sta = sta;
  326. an->vif = vif;
  327. ath_tx_node_init(sc, an);
  328. if (sta->ht_cap.ht_supported) {
  329. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  330. sta->ht_cap.ampdu_factor);
  331. an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  332. }
  333. }
  334. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  335. {
  336. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  337. ath_tx_node_cleanup(sc, an);
  338. }
  339. void ath9k_tasklet(unsigned long data)
  340. {
  341. struct ath_softc *sc = (struct ath_softc *)data;
  342. struct ath_hw *ah = sc->sc_ah;
  343. struct ath_common *common = ath9k_hw_common(ah);
  344. enum ath_reset_type type;
  345. unsigned long flags;
  346. u32 status = sc->intrstatus;
  347. u32 rxmask;
  348. ath9k_ps_wakeup(sc);
  349. spin_lock(&sc->sc_pcu_lock);
  350. if ((status & ATH9K_INT_FATAL) ||
  351. (status & ATH9K_INT_BB_WATCHDOG)) {
  352. if (status & ATH9K_INT_FATAL)
  353. type = RESET_TYPE_FATAL_INT;
  354. else
  355. type = RESET_TYPE_BB_WATCHDOG;
  356. ath9k_queue_reset(sc, type);
  357. /*
  358. * Increment the ref. counter here so that
  359. * interrupts are enabled in the reset routine.
  360. */
  361. atomic_inc(&ah->intr_ref_cnt);
  362. ath_dbg(common, ANY, "FATAL: Skipping interrupts\n");
  363. goto out;
  364. }
  365. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  366. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  367. /*
  368. * TSF sync does not look correct; remain awake to sync with
  369. * the next Beacon.
  370. */
  371. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  372. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  373. }
  374. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  375. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  376. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  377. ATH9K_INT_RXORN);
  378. else
  379. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  380. if (status & rxmask) {
  381. /* Check for high priority Rx first */
  382. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  383. (status & ATH9K_INT_RXHP))
  384. ath_rx_tasklet(sc, 0, true);
  385. ath_rx_tasklet(sc, 0, false);
  386. }
  387. if (status & ATH9K_INT_TX) {
  388. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  389. ath_tx_edma_tasklet(sc);
  390. else
  391. ath_tx_tasklet(sc);
  392. }
  393. ath9k_btcoex_handle_interrupt(sc, status);
  394. /* re-enable hardware interrupt */
  395. ath9k_hw_enable_interrupts(ah);
  396. out:
  397. spin_unlock(&sc->sc_pcu_lock);
  398. ath9k_ps_restore(sc);
  399. }
  400. irqreturn_t ath_isr(int irq, void *dev)
  401. {
  402. #define SCHED_INTR ( \
  403. ATH9K_INT_FATAL | \
  404. ATH9K_INT_BB_WATCHDOG | \
  405. ATH9K_INT_RXORN | \
  406. ATH9K_INT_RXEOL | \
  407. ATH9K_INT_RX | \
  408. ATH9K_INT_RXLP | \
  409. ATH9K_INT_RXHP | \
  410. ATH9K_INT_TX | \
  411. ATH9K_INT_BMISS | \
  412. ATH9K_INT_CST | \
  413. ATH9K_INT_TSFOOR | \
  414. ATH9K_INT_GENTIMER | \
  415. ATH9K_INT_MCI)
  416. struct ath_softc *sc = dev;
  417. struct ath_hw *ah = sc->sc_ah;
  418. struct ath_common *common = ath9k_hw_common(ah);
  419. enum ath9k_int status;
  420. bool sched = false;
  421. /*
  422. * The hardware is not ready/present, don't
  423. * touch anything. Note this can happen early
  424. * on if the IRQ is shared.
  425. */
  426. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  427. return IRQ_NONE;
  428. /* shared irq, not for us */
  429. if (!ath9k_hw_intrpend(ah))
  430. return IRQ_NONE;
  431. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  432. ath9k_hw_kill_interrupts(ah);
  433. return IRQ_HANDLED;
  434. }
  435. /*
  436. * Figure out the reason(s) for the interrupt. Note
  437. * that the hal returns a pseudo-ISR that may include
  438. * bits we haven't explicitly enabled so we mask the
  439. * value to insure we only process bits we requested.
  440. */
  441. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  442. status &= ah->imask; /* discard unasked-for bits */
  443. /*
  444. * If there are no status bits set, then this interrupt was not
  445. * for me (should have been caught above).
  446. */
  447. if (!status)
  448. return IRQ_NONE;
  449. /* Cache the status */
  450. sc->intrstatus = status;
  451. if (status & SCHED_INTR)
  452. sched = true;
  453. /*
  454. * If a FATAL or RXORN interrupt is received, we have to reset the
  455. * chip immediately.
  456. */
  457. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  458. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  459. goto chip_reset;
  460. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  461. (status & ATH9K_INT_BB_WATCHDOG)) {
  462. spin_lock(&common->cc_lock);
  463. ath_hw_cycle_counters_update(common);
  464. ar9003_hw_bb_watchdog_dbg_info(ah);
  465. spin_unlock(&common->cc_lock);
  466. goto chip_reset;
  467. }
  468. #ifdef CONFIG_PM_SLEEP
  469. if (status & ATH9K_INT_BMISS) {
  470. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  471. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  472. atomic_inc(&sc->wow_got_bmiss_intr);
  473. atomic_dec(&sc->wow_sleep_proc_intr);
  474. }
  475. }
  476. #endif
  477. if (status & ATH9K_INT_SWBA)
  478. tasklet_schedule(&sc->bcon_tasklet);
  479. if (status & ATH9K_INT_TXURN)
  480. ath9k_hw_updatetxtriglevel(ah, true);
  481. if (status & ATH9K_INT_RXEOL) {
  482. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  483. ath9k_hw_set_interrupts(ah);
  484. }
  485. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  486. if (status & ATH9K_INT_TIM_TIMER) {
  487. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  488. goto chip_reset;
  489. /* Clear RxAbort bit so that we can
  490. * receive frames */
  491. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  492. spin_lock(&sc->sc_pm_lock);
  493. ath9k_hw_setrxabort(sc->sc_ah, 0);
  494. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  495. spin_unlock(&sc->sc_pm_lock);
  496. }
  497. chip_reset:
  498. ath_debug_stat_interrupt(sc, status);
  499. if (sched) {
  500. /* turn off every interrupt */
  501. ath9k_hw_disable_interrupts(ah);
  502. tasklet_schedule(&sc->intr_tq);
  503. }
  504. return IRQ_HANDLED;
  505. #undef SCHED_INTR
  506. }
  507. static int ath_reset(struct ath_softc *sc)
  508. {
  509. int i, r;
  510. ath9k_ps_wakeup(sc);
  511. r = ath_reset_internal(sc, NULL);
  512. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  513. if (!ATH_TXQ_SETUP(sc, i))
  514. continue;
  515. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  516. ath_txq_schedule(sc, &sc->tx.txq[i]);
  517. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  518. }
  519. ath9k_ps_restore(sc);
  520. return r;
  521. }
  522. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  523. {
  524. #ifdef CONFIG_ATH9K_DEBUGFS
  525. RESET_STAT_INC(sc, type);
  526. #endif
  527. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  528. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  529. }
  530. void ath_reset_work(struct work_struct *work)
  531. {
  532. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  533. ath_reset(sc);
  534. }
  535. /**********************/
  536. /* mac80211 callbacks */
  537. /**********************/
  538. static int ath9k_start(struct ieee80211_hw *hw)
  539. {
  540. struct ath_softc *sc = hw->priv;
  541. struct ath_hw *ah = sc->sc_ah;
  542. struct ath_common *common = ath9k_hw_common(ah);
  543. struct ieee80211_channel *curchan = hw->conf.chandef.chan;
  544. struct ath9k_channel *init_channel;
  545. int r;
  546. ath_dbg(common, CONFIG,
  547. "Starting driver with initial channel: %d MHz\n",
  548. curchan->center_freq);
  549. ath9k_ps_wakeup(sc);
  550. mutex_lock(&sc->mutex);
  551. init_channel = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef);
  552. /* Reset SERDES registers */
  553. ath9k_hw_configpcipowersave(ah, false);
  554. /*
  555. * The basic interface to setting the hardware in a good
  556. * state is ``reset''. On return the hardware is known to
  557. * be powered up and with interrupts disabled. This must
  558. * be followed by initialization of the appropriate bits
  559. * and then setup of the interrupt mask.
  560. */
  561. spin_lock_bh(&sc->sc_pcu_lock);
  562. atomic_set(&ah->intr_ref_cnt, -1);
  563. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  564. if (r) {
  565. ath_err(common,
  566. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  567. r, curchan->center_freq);
  568. ah->reset_power_on = false;
  569. }
  570. /* Setup our intr mask. */
  571. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  572. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  573. ATH9K_INT_GLOBAL;
  574. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  575. ah->imask |= ATH9K_INT_RXHP |
  576. ATH9K_INT_RXLP |
  577. ATH9K_INT_BB_WATCHDOG;
  578. else
  579. ah->imask |= ATH9K_INT_RX;
  580. ah->imask |= ATH9K_INT_GTT;
  581. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  582. ah->imask |= ATH9K_INT_CST;
  583. ath_mci_enable(sc);
  584. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  585. sc->sc_ah->is_monitoring = false;
  586. if (!ath_complete_reset(sc, false))
  587. ah->reset_power_on = false;
  588. if (ah->led_pin >= 0) {
  589. ath9k_hw_cfg_output(ah, ah->led_pin,
  590. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  591. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  592. }
  593. /*
  594. * Reset key cache to sane defaults (all entries cleared) instead of
  595. * semi-random values after suspend/resume.
  596. */
  597. ath9k_cmn_init_crypto(sc->sc_ah);
  598. spin_unlock_bh(&sc->sc_pcu_lock);
  599. mutex_unlock(&sc->mutex);
  600. ath9k_ps_restore(sc);
  601. return 0;
  602. }
  603. static void ath9k_tx(struct ieee80211_hw *hw,
  604. struct ieee80211_tx_control *control,
  605. struct sk_buff *skb)
  606. {
  607. struct ath_softc *sc = hw->priv;
  608. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  609. struct ath_tx_control txctl;
  610. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  611. unsigned long flags;
  612. if (sc->ps_enabled) {
  613. /*
  614. * mac80211 does not set PM field for normal data frames, so we
  615. * need to update that based on the current PS mode.
  616. */
  617. if (ieee80211_is_data(hdr->frame_control) &&
  618. !ieee80211_is_nullfunc(hdr->frame_control) &&
  619. !ieee80211_has_pm(hdr->frame_control)) {
  620. ath_dbg(common, PS,
  621. "Add PM=1 for a TX frame while in PS mode\n");
  622. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  623. }
  624. }
  625. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  626. /*
  627. * We are using PS-Poll and mac80211 can request TX while in
  628. * power save mode. Need to wake up hardware for the TX to be
  629. * completed and if needed, also for RX of buffered frames.
  630. */
  631. ath9k_ps_wakeup(sc);
  632. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  633. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  634. ath9k_hw_setrxabort(sc->sc_ah, 0);
  635. if (ieee80211_is_pspoll(hdr->frame_control)) {
  636. ath_dbg(common, PS,
  637. "Sending PS-Poll to pick a buffered frame\n");
  638. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  639. } else {
  640. ath_dbg(common, PS, "Wake up to complete TX\n");
  641. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  642. }
  643. /*
  644. * The actual restore operation will happen only after
  645. * the ps_flags bit is cleared. We are just dropping
  646. * the ps_usecount here.
  647. */
  648. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  649. ath9k_ps_restore(sc);
  650. }
  651. /*
  652. * Cannot tx while the hardware is in full sleep, it first needs a full
  653. * chip reset to recover from that
  654. */
  655. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  656. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  657. goto exit;
  658. }
  659. memset(&txctl, 0, sizeof(struct ath_tx_control));
  660. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  661. txctl.sta = control->sta;
  662. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  663. if (ath_tx_start(hw, skb, &txctl) != 0) {
  664. ath_dbg(common, XMIT, "TX failed\n");
  665. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  666. goto exit;
  667. }
  668. return;
  669. exit:
  670. ieee80211_free_txskb(hw, skb);
  671. }
  672. static void ath9k_stop(struct ieee80211_hw *hw)
  673. {
  674. struct ath_softc *sc = hw->priv;
  675. struct ath_hw *ah = sc->sc_ah;
  676. struct ath_common *common = ath9k_hw_common(ah);
  677. bool prev_idle;
  678. mutex_lock(&sc->mutex);
  679. ath_cancel_work(sc);
  680. del_timer_sync(&sc->rx_poll_timer);
  681. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  682. ath_dbg(common, ANY, "Device not present\n");
  683. mutex_unlock(&sc->mutex);
  684. return;
  685. }
  686. /* Ensure HW is awake when we try to shut it down. */
  687. ath9k_ps_wakeup(sc);
  688. spin_lock_bh(&sc->sc_pcu_lock);
  689. /* prevent tasklets to enable interrupts once we disable them */
  690. ah->imask &= ~ATH9K_INT_GLOBAL;
  691. /* make sure h/w will not generate any interrupt
  692. * before setting the invalid flag. */
  693. ath9k_hw_disable_interrupts(ah);
  694. spin_unlock_bh(&sc->sc_pcu_lock);
  695. /* we can now sync irq and kill any running tasklets, since we already
  696. * disabled interrupts and not holding a spin lock */
  697. synchronize_irq(sc->irq);
  698. tasklet_kill(&sc->intr_tq);
  699. tasklet_kill(&sc->bcon_tasklet);
  700. prev_idle = sc->ps_idle;
  701. sc->ps_idle = true;
  702. spin_lock_bh(&sc->sc_pcu_lock);
  703. if (ah->led_pin >= 0) {
  704. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  705. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  706. }
  707. ath_prepare_reset(sc);
  708. if (sc->rx.frag) {
  709. dev_kfree_skb_any(sc->rx.frag);
  710. sc->rx.frag = NULL;
  711. }
  712. if (!ah->curchan)
  713. ah->curchan = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef);
  714. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  715. ath9k_hw_phy_disable(ah);
  716. ath9k_hw_configpcipowersave(ah, true);
  717. spin_unlock_bh(&sc->sc_pcu_lock);
  718. ath9k_ps_restore(sc);
  719. set_bit(SC_OP_INVALID, &sc->sc_flags);
  720. sc->ps_idle = prev_idle;
  721. mutex_unlock(&sc->mutex);
  722. ath_dbg(common, CONFIG, "Driver halt\n");
  723. }
  724. static bool ath9k_uses_beacons(int type)
  725. {
  726. switch (type) {
  727. case NL80211_IFTYPE_AP:
  728. case NL80211_IFTYPE_ADHOC:
  729. case NL80211_IFTYPE_MESH_POINT:
  730. return true;
  731. default:
  732. return false;
  733. }
  734. }
  735. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  736. {
  737. struct ath9k_vif_iter_data *iter_data = data;
  738. int i;
  739. if (iter_data->has_hw_macaddr) {
  740. for (i = 0; i < ETH_ALEN; i++)
  741. iter_data->mask[i] &=
  742. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  743. } else {
  744. memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
  745. iter_data->has_hw_macaddr = true;
  746. }
  747. switch (vif->type) {
  748. case NL80211_IFTYPE_AP:
  749. iter_data->naps++;
  750. break;
  751. case NL80211_IFTYPE_STATION:
  752. iter_data->nstations++;
  753. break;
  754. case NL80211_IFTYPE_ADHOC:
  755. iter_data->nadhocs++;
  756. break;
  757. case NL80211_IFTYPE_MESH_POINT:
  758. iter_data->nmeshes++;
  759. break;
  760. case NL80211_IFTYPE_WDS:
  761. iter_data->nwds++;
  762. break;
  763. default:
  764. break;
  765. }
  766. }
  767. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  768. {
  769. struct ath_softc *sc = data;
  770. struct ath_vif *avp = (void *)vif->drv_priv;
  771. if (vif->type != NL80211_IFTYPE_STATION)
  772. return;
  773. if (avp->primary_sta_vif)
  774. ath9k_set_assoc_state(sc, vif);
  775. }
  776. /* Called with sc->mutex held. */
  777. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  778. struct ieee80211_vif *vif,
  779. struct ath9k_vif_iter_data *iter_data)
  780. {
  781. struct ath_softc *sc = hw->priv;
  782. struct ath_hw *ah = sc->sc_ah;
  783. struct ath_common *common = ath9k_hw_common(ah);
  784. /*
  785. * Use the hardware MAC address as reference, the hardware uses it
  786. * together with the BSSID mask when matching addresses.
  787. */
  788. memset(iter_data, 0, sizeof(*iter_data));
  789. memset(&iter_data->mask, 0xff, ETH_ALEN);
  790. if (vif)
  791. ath9k_vif_iter(iter_data, vif->addr, vif);
  792. /* Get list of all active MAC addresses */
  793. ieee80211_iterate_active_interfaces_atomic(
  794. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  795. ath9k_vif_iter, iter_data);
  796. memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN);
  797. }
  798. /* Called with sc->mutex held. */
  799. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  800. struct ieee80211_vif *vif)
  801. {
  802. struct ath_softc *sc = hw->priv;
  803. struct ath_hw *ah = sc->sc_ah;
  804. struct ath_common *common = ath9k_hw_common(ah);
  805. struct ath9k_vif_iter_data iter_data;
  806. enum nl80211_iftype old_opmode = ah->opmode;
  807. ath9k_calculate_iter_data(hw, vif, &iter_data);
  808. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  809. ath_hw_setbssidmask(common);
  810. if (iter_data.naps > 0) {
  811. ath9k_hw_set_tsfadjust(ah, true);
  812. ah->opmode = NL80211_IFTYPE_AP;
  813. } else {
  814. ath9k_hw_set_tsfadjust(ah, false);
  815. if (iter_data.nmeshes)
  816. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  817. else if (iter_data.nwds)
  818. ah->opmode = NL80211_IFTYPE_AP;
  819. else if (iter_data.nadhocs)
  820. ah->opmode = NL80211_IFTYPE_ADHOC;
  821. else
  822. ah->opmode = NL80211_IFTYPE_STATION;
  823. }
  824. ath9k_hw_setopmode(ah);
  825. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  826. ah->imask |= ATH9K_INT_TSFOOR;
  827. else
  828. ah->imask &= ~ATH9K_INT_TSFOOR;
  829. ath9k_hw_set_interrupts(ah);
  830. /*
  831. * If we are changing the opmode to STATION,
  832. * a beacon sync needs to be done.
  833. */
  834. if (ah->opmode == NL80211_IFTYPE_STATION &&
  835. old_opmode == NL80211_IFTYPE_AP &&
  836. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  837. ieee80211_iterate_active_interfaces_atomic(
  838. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  839. ath9k_sta_vif_iter, sc);
  840. }
  841. }
  842. static int ath9k_add_interface(struct ieee80211_hw *hw,
  843. struct ieee80211_vif *vif)
  844. {
  845. struct ath_softc *sc = hw->priv;
  846. struct ath_hw *ah = sc->sc_ah;
  847. struct ath_common *common = ath9k_hw_common(ah);
  848. struct ath_vif *avp = (void *)vif->drv_priv;
  849. struct ath_node *an = &avp->mcast_node;
  850. mutex_lock(&sc->mutex);
  851. if (config_enabled(CONFIG_ATH9K_TX99)) {
  852. if (sc->nvifs >= 1) {
  853. mutex_unlock(&sc->mutex);
  854. return -EOPNOTSUPP;
  855. }
  856. sc->tx99_vif = vif;
  857. }
  858. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  859. sc->nvifs++;
  860. ath9k_ps_wakeup(sc);
  861. ath9k_calculate_summary_state(hw, vif);
  862. ath9k_ps_restore(sc);
  863. if (ath9k_uses_beacons(vif->type))
  864. ath9k_beacon_assign_slot(sc, vif);
  865. an->sc = sc;
  866. an->sta = NULL;
  867. an->vif = vif;
  868. an->no_ps_filter = true;
  869. ath_tx_node_init(sc, an);
  870. mutex_unlock(&sc->mutex);
  871. return 0;
  872. }
  873. static int ath9k_change_interface(struct ieee80211_hw *hw,
  874. struct ieee80211_vif *vif,
  875. enum nl80211_iftype new_type,
  876. bool p2p)
  877. {
  878. struct ath_softc *sc = hw->priv;
  879. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  880. mutex_lock(&sc->mutex);
  881. if (config_enabled(CONFIG_ATH9K_TX99)) {
  882. mutex_unlock(&sc->mutex);
  883. return -EOPNOTSUPP;
  884. }
  885. ath_dbg(common, CONFIG, "Change Interface\n");
  886. if (ath9k_uses_beacons(vif->type))
  887. ath9k_beacon_remove_slot(sc, vif);
  888. vif->type = new_type;
  889. vif->p2p = p2p;
  890. ath9k_ps_wakeup(sc);
  891. ath9k_calculate_summary_state(hw, vif);
  892. ath9k_ps_restore(sc);
  893. if (ath9k_uses_beacons(vif->type))
  894. ath9k_beacon_assign_slot(sc, vif);
  895. mutex_unlock(&sc->mutex);
  896. return 0;
  897. }
  898. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  899. struct ieee80211_vif *vif)
  900. {
  901. struct ath_softc *sc = hw->priv;
  902. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  903. struct ath_vif *avp = (void *)vif->drv_priv;
  904. ath_dbg(common, CONFIG, "Detach Interface\n");
  905. mutex_lock(&sc->mutex);
  906. sc->nvifs--;
  907. sc->tx99_vif = NULL;
  908. if (ath9k_uses_beacons(vif->type))
  909. ath9k_beacon_remove_slot(sc, vif);
  910. if (sc->csa_vif == vif)
  911. sc->csa_vif = NULL;
  912. ath9k_ps_wakeup(sc);
  913. ath9k_calculate_summary_state(hw, NULL);
  914. ath9k_ps_restore(sc);
  915. ath_tx_node_cleanup(sc, &avp->mcast_node);
  916. mutex_unlock(&sc->mutex);
  917. }
  918. static void ath9k_enable_ps(struct ath_softc *sc)
  919. {
  920. struct ath_hw *ah = sc->sc_ah;
  921. struct ath_common *common = ath9k_hw_common(ah);
  922. if (config_enabled(CONFIG_ATH9K_TX99))
  923. return;
  924. sc->ps_enabled = true;
  925. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  926. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  927. ah->imask |= ATH9K_INT_TIM_TIMER;
  928. ath9k_hw_set_interrupts(ah);
  929. }
  930. ath9k_hw_setrxabort(ah, 1);
  931. }
  932. ath_dbg(common, PS, "PowerSave enabled\n");
  933. }
  934. static void ath9k_disable_ps(struct ath_softc *sc)
  935. {
  936. struct ath_hw *ah = sc->sc_ah;
  937. struct ath_common *common = ath9k_hw_common(ah);
  938. if (config_enabled(CONFIG_ATH9K_TX99))
  939. return;
  940. sc->ps_enabled = false;
  941. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  942. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  943. ath9k_hw_setrxabort(ah, 0);
  944. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  945. PS_WAIT_FOR_CAB |
  946. PS_WAIT_FOR_PSPOLL_DATA |
  947. PS_WAIT_FOR_TX_ACK);
  948. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  949. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  950. ath9k_hw_set_interrupts(ah);
  951. }
  952. }
  953. ath_dbg(common, PS, "PowerSave disabled\n");
  954. }
  955. void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
  956. {
  957. struct ath_softc *sc = hw->priv;
  958. struct ath_hw *ah = sc->sc_ah;
  959. struct ath_common *common = ath9k_hw_common(ah);
  960. u32 rxfilter;
  961. if (config_enabled(CONFIG_ATH9K_TX99))
  962. return;
  963. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  964. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  965. return;
  966. }
  967. ath9k_ps_wakeup(sc);
  968. rxfilter = ath9k_hw_getrxfilter(ah);
  969. ath9k_hw_setrxfilter(ah, rxfilter |
  970. ATH9K_RX_FILTER_PHYRADAR |
  971. ATH9K_RX_FILTER_PHYERR);
  972. /* TODO: usually this should not be neccesary, but for some reason
  973. * (or in some mode?) the trigger must be called after the
  974. * configuration, otherwise the register will have its values reset
  975. * (on my ar9220 to value 0x01002310)
  976. */
  977. ath9k_spectral_scan_config(hw, sc->spectral_mode);
  978. ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
  979. ath9k_ps_restore(sc);
  980. }
  981. int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
  982. enum spectral_mode spectral_mode)
  983. {
  984. struct ath_softc *sc = hw->priv;
  985. struct ath_hw *ah = sc->sc_ah;
  986. struct ath_common *common = ath9k_hw_common(ah);
  987. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  988. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  989. return -1;
  990. }
  991. switch (spectral_mode) {
  992. case SPECTRAL_DISABLED:
  993. sc->spec_config.enabled = 0;
  994. break;
  995. case SPECTRAL_BACKGROUND:
  996. /* send endless samples.
  997. * TODO: is this really useful for "background"?
  998. */
  999. sc->spec_config.endless = 1;
  1000. sc->spec_config.enabled = 1;
  1001. break;
  1002. case SPECTRAL_CHANSCAN:
  1003. case SPECTRAL_MANUAL:
  1004. sc->spec_config.endless = 0;
  1005. sc->spec_config.enabled = 1;
  1006. break;
  1007. default:
  1008. return -1;
  1009. }
  1010. ath9k_ps_wakeup(sc);
  1011. ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
  1012. ath9k_ps_restore(sc);
  1013. sc->spectral_mode = spectral_mode;
  1014. return 0;
  1015. }
  1016. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1017. {
  1018. struct ath_softc *sc = hw->priv;
  1019. struct ath_hw *ah = sc->sc_ah;
  1020. struct ath_common *common = ath9k_hw_common(ah);
  1021. struct ieee80211_conf *conf = &hw->conf;
  1022. bool reset_channel = false;
  1023. ath9k_ps_wakeup(sc);
  1024. mutex_lock(&sc->mutex);
  1025. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1026. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1027. if (sc->ps_idle) {
  1028. ath_cancel_work(sc);
  1029. ath9k_stop_btcoex(sc);
  1030. } else {
  1031. ath9k_start_btcoex(sc);
  1032. /*
  1033. * The chip needs a reset to properly wake up from
  1034. * full sleep
  1035. */
  1036. reset_channel = ah->chip_fullsleep;
  1037. }
  1038. }
  1039. /*
  1040. * We just prepare to enable PS. We have to wait until our AP has
  1041. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1042. * those ACKs and end up retransmitting the same null data frames.
  1043. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1044. */
  1045. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1046. unsigned long flags;
  1047. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1048. if (conf->flags & IEEE80211_CONF_PS)
  1049. ath9k_enable_ps(sc);
  1050. else
  1051. ath9k_disable_ps(sc);
  1052. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1053. }
  1054. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1055. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1056. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1057. sc->sc_ah->is_monitoring = true;
  1058. } else {
  1059. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1060. sc->sc_ah->is_monitoring = false;
  1061. }
  1062. }
  1063. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  1064. if (ath_set_channel(sc, &hw->conf.chandef) < 0) {
  1065. ath_err(common, "Unable to set channel\n");
  1066. mutex_unlock(&sc->mutex);
  1067. ath9k_ps_restore(sc);
  1068. return -EINVAL;
  1069. }
  1070. }
  1071. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1072. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1073. sc->config.txpowlimit = 2 * conf->power_level;
  1074. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1075. sc->config.txpowlimit, &sc->curtxpow);
  1076. }
  1077. mutex_unlock(&sc->mutex);
  1078. ath9k_ps_restore(sc);
  1079. return 0;
  1080. }
  1081. #define SUPPORTED_FILTERS \
  1082. (FIF_PROMISC_IN_BSS | \
  1083. FIF_ALLMULTI | \
  1084. FIF_CONTROL | \
  1085. FIF_PSPOLL | \
  1086. FIF_OTHER_BSS | \
  1087. FIF_BCN_PRBRESP_PROMISC | \
  1088. FIF_PROBE_REQ | \
  1089. FIF_FCSFAIL)
  1090. /* FIXME: sc->sc_full_reset ? */
  1091. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1092. unsigned int changed_flags,
  1093. unsigned int *total_flags,
  1094. u64 multicast)
  1095. {
  1096. struct ath_softc *sc = hw->priv;
  1097. u32 rfilt;
  1098. changed_flags &= SUPPORTED_FILTERS;
  1099. *total_flags &= SUPPORTED_FILTERS;
  1100. sc->rx.rxfilter = *total_flags;
  1101. ath9k_ps_wakeup(sc);
  1102. rfilt = ath_calcrxfilter(sc);
  1103. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1104. ath9k_ps_restore(sc);
  1105. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1106. rfilt);
  1107. }
  1108. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1109. struct ieee80211_vif *vif,
  1110. struct ieee80211_sta *sta)
  1111. {
  1112. struct ath_softc *sc = hw->priv;
  1113. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1114. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1115. struct ieee80211_key_conf ps_key = { };
  1116. int key;
  1117. ath_node_attach(sc, sta, vif);
  1118. if (vif->type != NL80211_IFTYPE_AP &&
  1119. vif->type != NL80211_IFTYPE_AP_VLAN)
  1120. return 0;
  1121. key = ath_key_config(common, vif, sta, &ps_key);
  1122. if (key > 0)
  1123. an->ps_key = key;
  1124. return 0;
  1125. }
  1126. static void ath9k_del_ps_key(struct ath_softc *sc,
  1127. struct ieee80211_vif *vif,
  1128. struct ieee80211_sta *sta)
  1129. {
  1130. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1131. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1132. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1133. if (!an->ps_key)
  1134. return;
  1135. ath_key_delete(common, &ps_key);
  1136. an->ps_key = 0;
  1137. }
  1138. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1139. struct ieee80211_vif *vif,
  1140. struct ieee80211_sta *sta)
  1141. {
  1142. struct ath_softc *sc = hw->priv;
  1143. ath9k_del_ps_key(sc, vif, sta);
  1144. ath_node_detach(sc, sta);
  1145. return 0;
  1146. }
  1147. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1148. struct ieee80211_vif *vif,
  1149. enum sta_notify_cmd cmd,
  1150. struct ieee80211_sta *sta)
  1151. {
  1152. struct ath_softc *sc = hw->priv;
  1153. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1154. switch (cmd) {
  1155. case STA_NOTIFY_SLEEP:
  1156. an->sleeping = true;
  1157. ath_tx_aggr_sleep(sta, sc, an);
  1158. break;
  1159. case STA_NOTIFY_AWAKE:
  1160. an->sleeping = false;
  1161. ath_tx_aggr_wakeup(sc, an);
  1162. break;
  1163. }
  1164. }
  1165. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1166. struct ieee80211_vif *vif, u16 queue,
  1167. const struct ieee80211_tx_queue_params *params)
  1168. {
  1169. struct ath_softc *sc = hw->priv;
  1170. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1171. struct ath_txq *txq;
  1172. struct ath9k_tx_queue_info qi;
  1173. int ret = 0;
  1174. if (queue >= IEEE80211_NUM_ACS)
  1175. return 0;
  1176. txq = sc->tx.txq_map[queue];
  1177. ath9k_ps_wakeup(sc);
  1178. mutex_lock(&sc->mutex);
  1179. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1180. qi.tqi_aifs = params->aifs;
  1181. qi.tqi_cwmin = params->cw_min;
  1182. qi.tqi_cwmax = params->cw_max;
  1183. qi.tqi_burstTime = params->txop * 32;
  1184. ath_dbg(common, CONFIG,
  1185. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1186. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1187. params->cw_max, params->txop);
  1188. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1189. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1190. if (ret)
  1191. ath_err(common, "TXQ Update failed\n");
  1192. mutex_unlock(&sc->mutex);
  1193. ath9k_ps_restore(sc);
  1194. return ret;
  1195. }
  1196. static int ath9k_set_key(struct ieee80211_hw *hw,
  1197. enum set_key_cmd cmd,
  1198. struct ieee80211_vif *vif,
  1199. struct ieee80211_sta *sta,
  1200. struct ieee80211_key_conf *key)
  1201. {
  1202. struct ath_softc *sc = hw->priv;
  1203. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1204. int ret = 0;
  1205. if (ath9k_modparam_nohwcrypt)
  1206. return -ENOSPC;
  1207. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1208. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1209. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1210. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1211. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1212. /*
  1213. * For now, disable hw crypto for the RSN IBSS group keys. This
  1214. * could be optimized in the future to use a modified key cache
  1215. * design to support per-STA RX GTK, but until that gets
  1216. * implemented, use of software crypto for group addressed
  1217. * frames is a acceptable to allow RSN IBSS to be used.
  1218. */
  1219. return -EOPNOTSUPP;
  1220. }
  1221. mutex_lock(&sc->mutex);
  1222. ath9k_ps_wakeup(sc);
  1223. ath_dbg(common, CONFIG, "Set HW Key\n");
  1224. switch (cmd) {
  1225. case SET_KEY:
  1226. if (sta)
  1227. ath9k_del_ps_key(sc, vif, sta);
  1228. ret = ath_key_config(common, vif, sta, key);
  1229. if (ret >= 0) {
  1230. key->hw_key_idx = ret;
  1231. /* push IV and Michael MIC generation to stack */
  1232. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1233. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1234. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1235. if (sc->sc_ah->sw_mgmt_crypto &&
  1236. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1237. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1238. ret = 0;
  1239. }
  1240. break;
  1241. case DISABLE_KEY:
  1242. ath_key_delete(common, key);
  1243. break;
  1244. default:
  1245. ret = -EINVAL;
  1246. }
  1247. ath9k_ps_restore(sc);
  1248. mutex_unlock(&sc->mutex);
  1249. return ret;
  1250. }
  1251. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1252. struct ieee80211_vif *vif)
  1253. {
  1254. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1255. struct ath_vif *avp = (void *)vif->drv_priv;
  1256. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1257. unsigned long flags;
  1258. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1259. avp->primary_sta_vif = true;
  1260. /*
  1261. * Set the AID, BSSID and do beacon-sync only when
  1262. * the HW opmode is STATION.
  1263. *
  1264. * But the primary bit is set above in any case.
  1265. */
  1266. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1267. return;
  1268. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1269. common->curaid = bss_conf->aid;
  1270. ath9k_hw_write_associd(sc->sc_ah);
  1271. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1272. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1273. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1274. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1275. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1276. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1277. ath9k_mci_update_wlan_channels(sc, false);
  1278. ath_dbg(common, CONFIG,
  1279. "Primary Station interface: %pM, BSSID: %pM\n",
  1280. vif->addr, common->curbssid);
  1281. }
  1282. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1283. {
  1284. struct ath_softc *sc = data;
  1285. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1286. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1287. return;
  1288. if (bss_conf->assoc)
  1289. ath9k_set_assoc_state(sc, vif);
  1290. }
  1291. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1292. struct ieee80211_vif *vif,
  1293. struct ieee80211_bss_conf *bss_conf,
  1294. u32 changed)
  1295. {
  1296. #define CHECK_ANI \
  1297. (BSS_CHANGED_ASSOC | \
  1298. BSS_CHANGED_IBSS | \
  1299. BSS_CHANGED_BEACON_ENABLED)
  1300. struct ath_softc *sc = hw->priv;
  1301. struct ath_hw *ah = sc->sc_ah;
  1302. struct ath_common *common = ath9k_hw_common(ah);
  1303. struct ath_vif *avp = (void *)vif->drv_priv;
  1304. int slottime;
  1305. ath9k_ps_wakeup(sc);
  1306. mutex_lock(&sc->mutex);
  1307. if (changed & BSS_CHANGED_ASSOC) {
  1308. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1309. bss_conf->bssid, bss_conf->assoc);
  1310. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1311. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1312. avp->primary_sta_vif = false;
  1313. if (ah->opmode == NL80211_IFTYPE_STATION)
  1314. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1315. }
  1316. ieee80211_iterate_active_interfaces_atomic(
  1317. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1318. ath9k_bss_assoc_iter, sc);
  1319. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1320. ah->opmode == NL80211_IFTYPE_STATION) {
  1321. memset(common->curbssid, 0, ETH_ALEN);
  1322. common->curaid = 0;
  1323. ath9k_hw_write_associd(sc->sc_ah);
  1324. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1325. ath9k_mci_update_wlan_channels(sc, true);
  1326. }
  1327. }
  1328. if (changed & BSS_CHANGED_IBSS) {
  1329. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1330. common->curaid = bss_conf->aid;
  1331. ath9k_hw_write_associd(sc->sc_ah);
  1332. }
  1333. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1334. (changed & BSS_CHANGED_BEACON_INT)) {
  1335. if (ah->opmode == NL80211_IFTYPE_AP &&
  1336. bss_conf->enable_beacon)
  1337. ath9k_set_tsfadjust(sc, vif);
  1338. if (ath9k_allow_beacon_config(sc, vif))
  1339. ath9k_beacon_config(sc, vif, changed);
  1340. }
  1341. if (changed & BSS_CHANGED_ERP_SLOT) {
  1342. if (bss_conf->use_short_slot)
  1343. slottime = 9;
  1344. else
  1345. slottime = 20;
  1346. if (vif->type == NL80211_IFTYPE_AP) {
  1347. /*
  1348. * Defer update, so that connected stations can adjust
  1349. * their settings at the same time.
  1350. * See beacon.c for more details
  1351. */
  1352. sc->beacon.slottime = slottime;
  1353. sc->beacon.updateslot = UPDATE;
  1354. } else {
  1355. ah->slottime = slottime;
  1356. ath9k_hw_init_global_settings(ah);
  1357. }
  1358. }
  1359. if (changed & CHECK_ANI)
  1360. ath_check_ani(sc);
  1361. mutex_unlock(&sc->mutex);
  1362. ath9k_ps_restore(sc);
  1363. #undef CHECK_ANI
  1364. }
  1365. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1366. {
  1367. struct ath_softc *sc = hw->priv;
  1368. u64 tsf;
  1369. mutex_lock(&sc->mutex);
  1370. ath9k_ps_wakeup(sc);
  1371. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1372. ath9k_ps_restore(sc);
  1373. mutex_unlock(&sc->mutex);
  1374. return tsf;
  1375. }
  1376. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1377. struct ieee80211_vif *vif,
  1378. u64 tsf)
  1379. {
  1380. struct ath_softc *sc = hw->priv;
  1381. mutex_lock(&sc->mutex);
  1382. ath9k_ps_wakeup(sc);
  1383. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1384. ath9k_ps_restore(sc);
  1385. mutex_unlock(&sc->mutex);
  1386. }
  1387. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1388. {
  1389. struct ath_softc *sc = hw->priv;
  1390. mutex_lock(&sc->mutex);
  1391. ath9k_ps_wakeup(sc);
  1392. ath9k_hw_reset_tsf(sc->sc_ah);
  1393. ath9k_ps_restore(sc);
  1394. mutex_unlock(&sc->mutex);
  1395. }
  1396. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1397. struct ieee80211_vif *vif,
  1398. enum ieee80211_ampdu_mlme_action action,
  1399. struct ieee80211_sta *sta,
  1400. u16 tid, u16 *ssn, u8 buf_size)
  1401. {
  1402. struct ath_softc *sc = hw->priv;
  1403. bool flush = false;
  1404. int ret = 0;
  1405. mutex_lock(&sc->mutex);
  1406. switch (action) {
  1407. case IEEE80211_AMPDU_RX_START:
  1408. break;
  1409. case IEEE80211_AMPDU_RX_STOP:
  1410. break;
  1411. case IEEE80211_AMPDU_TX_START:
  1412. ath9k_ps_wakeup(sc);
  1413. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1414. if (!ret)
  1415. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1416. ath9k_ps_restore(sc);
  1417. break;
  1418. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1419. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1420. flush = true;
  1421. case IEEE80211_AMPDU_TX_STOP_CONT:
  1422. ath9k_ps_wakeup(sc);
  1423. ath_tx_aggr_stop(sc, sta, tid);
  1424. if (!flush)
  1425. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1426. ath9k_ps_restore(sc);
  1427. break;
  1428. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1429. ath9k_ps_wakeup(sc);
  1430. ath_tx_aggr_resume(sc, sta, tid);
  1431. ath9k_ps_restore(sc);
  1432. break;
  1433. default:
  1434. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1435. }
  1436. mutex_unlock(&sc->mutex);
  1437. return ret;
  1438. }
  1439. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1440. struct survey_info *survey)
  1441. {
  1442. struct ath_softc *sc = hw->priv;
  1443. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1444. struct ieee80211_supported_band *sband;
  1445. struct ieee80211_channel *chan;
  1446. unsigned long flags;
  1447. int pos;
  1448. if (config_enabled(CONFIG_ATH9K_TX99))
  1449. return -EOPNOTSUPP;
  1450. spin_lock_irqsave(&common->cc_lock, flags);
  1451. if (idx == 0)
  1452. ath_update_survey_stats(sc);
  1453. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1454. if (sband && idx >= sband->n_channels) {
  1455. idx -= sband->n_channels;
  1456. sband = NULL;
  1457. }
  1458. if (!sband)
  1459. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1460. if (!sband || idx >= sband->n_channels) {
  1461. spin_unlock_irqrestore(&common->cc_lock, flags);
  1462. return -ENOENT;
  1463. }
  1464. chan = &sband->channels[idx];
  1465. pos = chan->hw_value;
  1466. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1467. survey->channel = chan;
  1468. spin_unlock_irqrestore(&common->cc_lock, flags);
  1469. return 0;
  1470. }
  1471. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1472. {
  1473. struct ath_softc *sc = hw->priv;
  1474. struct ath_hw *ah = sc->sc_ah;
  1475. if (config_enabled(CONFIG_ATH9K_TX99))
  1476. return;
  1477. mutex_lock(&sc->mutex);
  1478. ah->coverage_class = coverage_class;
  1479. ath9k_ps_wakeup(sc);
  1480. ath9k_hw_init_global_settings(ah);
  1481. ath9k_ps_restore(sc);
  1482. mutex_unlock(&sc->mutex);
  1483. }
  1484. static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
  1485. {
  1486. struct ath_softc *sc = hw->priv;
  1487. struct ath_hw *ah = sc->sc_ah;
  1488. struct ath_common *common = ath9k_hw_common(ah);
  1489. int timeout = 200; /* ms */
  1490. int i, j;
  1491. bool drain_txq;
  1492. mutex_lock(&sc->mutex);
  1493. cancel_delayed_work_sync(&sc->tx_complete_work);
  1494. if (ah->ah_flags & AH_UNPLUGGED) {
  1495. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1496. mutex_unlock(&sc->mutex);
  1497. return;
  1498. }
  1499. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1500. ath_dbg(common, ANY, "Device not present\n");
  1501. mutex_unlock(&sc->mutex);
  1502. return;
  1503. }
  1504. for (j = 0; j < timeout; j++) {
  1505. bool npend = false;
  1506. if (j)
  1507. usleep_range(1000, 2000);
  1508. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1509. if (!ATH_TXQ_SETUP(sc, i))
  1510. continue;
  1511. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1512. if (npend)
  1513. break;
  1514. }
  1515. if (!npend)
  1516. break;
  1517. }
  1518. if (drop) {
  1519. ath9k_ps_wakeup(sc);
  1520. spin_lock_bh(&sc->sc_pcu_lock);
  1521. drain_txq = ath_drain_all_txq(sc);
  1522. spin_unlock_bh(&sc->sc_pcu_lock);
  1523. if (!drain_txq)
  1524. ath_reset(sc);
  1525. ath9k_ps_restore(sc);
  1526. ieee80211_wake_queues(hw);
  1527. }
  1528. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1529. mutex_unlock(&sc->mutex);
  1530. }
  1531. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1532. {
  1533. struct ath_softc *sc = hw->priv;
  1534. int i;
  1535. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1536. if (!ATH_TXQ_SETUP(sc, i))
  1537. continue;
  1538. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1539. return true;
  1540. }
  1541. return false;
  1542. }
  1543. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1544. {
  1545. struct ath_softc *sc = hw->priv;
  1546. struct ath_hw *ah = sc->sc_ah;
  1547. struct ieee80211_vif *vif;
  1548. struct ath_vif *avp;
  1549. struct ath_buf *bf;
  1550. struct ath_tx_status ts;
  1551. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1552. int status;
  1553. vif = sc->beacon.bslot[0];
  1554. if (!vif)
  1555. return 0;
  1556. if (!vif->bss_conf.enable_beacon)
  1557. return 0;
  1558. avp = (void *)vif->drv_priv;
  1559. if (!sc->beacon.tx_processed && !edma) {
  1560. tasklet_disable(&sc->bcon_tasklet);
  1561. bf = avp->av_bcbuf;
  1562. if (!bf || !bf->bf_mpdu)
  1563. goto skip;
  1564. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1565. if (status == -EINPROGRESS)
  1566. goto skip;
  1567. sc->beacon.tx_processed = true;
  1568. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1569. skip:
  1570. tasklet_enable(&sc->bcon_tasklet);
  1571. }
  1572. return sc->beacon.tx_last;
  1573. }
  1574. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1575. struct ieee80211_low_level_stats *stats)
  1576. {
  1577. struct ath_softc *sc = hw->priv;
  1578. struct ath_hw *ah = sc->sc_ah;
  1579. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1580. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1581. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1582. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1583. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1584. return 0;
  1585. }
  1586. static u32 fill_chainmask(u32 cap, u32 new)
  1587. {
  1588. u32 filled = 0;
  1589. int i;
  1590. for (i = 0; cap && new; i++, cap >>= 1) {
  1591. if (!(cap & BIT(0)))
  1592. continue;
  1593. if (new & BIT(0))
  1594. filled |= BIT(i);
  1595. new >>= 1;
  1596. }
  1597. return filled;
  1598. }
  1599. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1600. {
  1601. if (AR_SREV_9300_20_OR_LATER(ah))
  1602. return true;
  1603. switch (val & 0x7) {
  1604. case 0x1:
  1605. case 0x3:
  1606. case 0x7:
  1607. return true;
  1608. case 0x2:
  1609. return (ah->caps.rx_chainmask == 1);
  1610. default:
  1611. return false;
  1612. }
  1613. }
  1614. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1615. {
  1616. struct ath_softc *sc = hw->priv;
  1617. struct ath_hw *ah = sc->sc_ah;
  1618. if (ah->caps.rx_chainmask != 1)
  1619. rx_ant |= tx_ant;
  1620. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1621. return -EINVAL;
  1622. sc->ant_rx = rx_ant;
  1623. sc->ant_tx = tx_ant;
  1624. if (ah->caps.rx_chainmask == 1)
  1625. return 0;
  1626. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1627. if (AR_SREV_9100(ah))
  1628. ah->rxchainmask = 0x7;
  1629. else
  1630. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1631. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1632. ath9k_reload_chainmask_settings(sc);
  1633. return 0;
  1634. }
  1635. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1636. {
  1637. struct ath_softc *sc = hw->priv;
  1638. *tx_ant = sc->ant_tx;
  1639. *rx_ant = sc->ant_rx;
  1640. return 0;
  1641. }
  1642. #ifdef CONFIG_PM_SLEEP
  1643. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1644. struct cfg80211_wowlan *wowlan,
  1645. u32 *wow_triggers)
  1646. {
  1647. if (wowlan->disconnect)
  1648. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1649. AH_WOW_BEACON_MISS;
  1650. if (wowlan->magic_pkt)
  1651. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1652. if (wowlan->n_patterns)
  1653. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1654. sc->wow_enabled = *wow_triggers;
  1655. }
  1656. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1657. {
  1658. struct ath_hw *ah = sc->sc_ah;
  1659. struct ath_common *common = ath9k_hw_common(ah);
  1660. int pattern_count = 0;
  1661. int i, byte_cnt;
  1662. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1663. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1664. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1665. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1666. /*
  1667. * Create Dissassociate / Deauthenticate packet filter
  1668. *
  1669. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1670. * +--------------+----------+---------+--------+--------+----
  1671. * + Frame Control+ Duration + DA + SA + BSSID +
  1672. * +--------------+----------+---------+--------+--------+----
  1673. *
  1674. * The above is the management frame format for disassociate/
  1675. * deauthenticate pattern, from this we need to match the first byte
  1676. * of 'Frame Control' and DA, SA, and BSSID fields
  1677. * (skipping 2nd byte of FC and Duration feild.
  1678. *
  1679. * Disassociate pattern
  1680. * --------------------
  1681. * Frame control = 00 00 1010
  1682. * DA, SA, BSSID = x:x:x:x:x:x
  1683. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1684. * | x:x:x:x:x:x -- 22 bytes
  1685. *
  1686. * Deauthenticate pattern
  1687. * ----------------------
  1688. * Frame control = 00 00 1100
  1689. * DA, SA, BSSID = x:x:x:x:x:x
  1690. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1691. * | x:x:x:x:x:x -- 22 bytes
  1692. */
  1693. /* Create Disassociate Pattern first */
  1694. byte_cnt = 0;
  1695. /* Fill out the mask with all FF's */
  1696. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1697. dis_deauth_mask[i] = 0xff;
  1698. /* copy the first byte of frame control field */
  1699. dis_deauth_pattern[byte_cnt] = 0xa0;
  1700. byte_cnt++;
  1701. /* skip 2nd byte of frame control and Duration field */
  1702. byte_cnt += 3;
  1703. /*
  1704. * need not match the destination mac address, it can be a broadcast
  1705. * mac address or an unicast to this station
  1706. */
  1707. byte_cnt += 6;
  1708. /* copy the source mac address */
  1709. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1710. byte_cnt += 6;
  1711. /* copy the bssid, its same as the source mac address */
  1712. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1713. /* Create Disassociate pattern mask */
  1714. dis_deauth_mask[0] = 0xfe;
  1715. dis_deauth_mask[1] = 0x03;
  1716. dis_deauth_mask[2] = 0xc0;
  1717. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1718. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1719. pattern_count, byte_cnt);
  1720. pattern_count++;
  1721. /*
  1722. * for de-authenticate pattern, only the first byte of the frame
  1723. * control field gets changed from 0xA0 to 0xC0
  1724. */
  1725. dis_deauth_pattern[0] = 0xC0;
  1726. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1727. pattern_count, byte_cnt);
  1728. }
  1729. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1730. struct cfg80211_wowlan *wowlan)
  1731. {
  1732. struct ath_hw *ah = sc->sc_ah;
  1733. struct ath9k_wow_pattern *wow_pattern = NULL;
  1734. struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
  1735. int mask_len;
  1736. s8 i = 0;
  1737. if (!wowlan->n_patterns)
  1738. return;
  1739. /*
  1740. * Add the new user configured patterns
  1741. */
  1742. for (i = 0; i < wowlan->n_patterns; i++) {
  1743. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1744. if (!wow_pattern)
  1745. return;
  1746. /*
  1747. * TODO: convert the generic user space pattern to
  1748. * appropriate chip specific/802.11 pattern.
  1749. */
  1750. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1751. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1752. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1753. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1754. patterns[i].pattern_len);
  1755. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1756. wow_pattern->pattern_len = patterns[i].pattern_len;
  1757. /*
  1758. * just need to take care of deauth and disssoc pattern,
  1759. * make sure we don't overwrite them.
  1760. */
  1761. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1762. wow_pattern->mask_bytes,
  1763. i + 2,
  1764. wow_pattern->pattern_len);
  1765. kfree(wow_pattern);
  1766. }
  1767. }
  1768. static int ath9k_suspend(struct ieee80211_hw *hw,
  1769. struct cfg80211_wowlan *wowlan)
  1770. {
  1771. struct ath_softc *sc = hw->priv;
  1772. struct ath_hw *ah = sc->sc_ah;
  1773. struct ath_common *common = ath9k_hw_common(ah);
  1774. u32 wow_triggers_enabled = 0;
  1775. int ret = 0;
  1776. mutex_lock(&sc->mutex);
  1777. ath_cancel_work(sc);
  1778. ath_stop_ani(sc);
  1779. del_timer_sync(&sc->rx_poll_timer);
  1780. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1781. ath_dbg(common, ANY, "Device not present\n");
  1782. ret = -EINVAL;
  1783. goto fail_wow;
  1784. }
  1785. if (WARN_ON(!wowlan)) {
  1786. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1787. ret = -EINVAL;
  1788. goto fail_wow;
  1789. }
  1790. if (!device_can_wakeup(sc->dev)) {
  1791. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1792. ret = 1;
  1793. goto fail_wow;
  1794. }
  1795. /*
  1796. * none of the sta vifs are associated
  1797. * and we are not currently handling multivif
  1798. * cases, for instance we have to seperately
  1799. * configure 'keep alive frame' for each
  1800. * STA.
  1801. */
  1802. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1803. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1804. ret = 1;
  1805. goto fail_wow;
  1806. }
  1807. if (sc->nvifs > 1) {
  1808. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1809. ret = 1;
  1810. goto fail_wow;
  1811. }
  1812. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1813. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1814. wow_triggers_enabled);
  1815. ath9k_ps_wakeup(sc);
  1816. ath9k_stop_btcoex(sc);
  1817. /*
  1818. * Enable wake up on recieving disassoc/deauth
  1819. * frame by default.
  1820. */
  1821. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1822. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1823. ath9k_wow_add_pattern(sc, wowlan);
  1824. spin_lock_bh(&sc->sc_pcu_lock);
  1825. /*
  1826. * To avoid false wake, we enable beacon miss interrupt only
  1827. * when we go to sleep. We save the current interrupt mask
  1828. * so we can restore it after the system wakes up
  1829. */
  1830. sc->wow_intr_before_sleep = ah->imask;
  1831. ah->imask &= ~ATH9K_INT_GLOBAL;
  1832. ath9k_hw_disable_interrupts(ah);
  1833. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1834. ath9k_hw_set_interrupts(ah);
  1835. ath9k_hw_enable_interrupts(ah);
  1836. spin_unlock_bh(&sc->sc_pcu_lock);
  1837. /*
  1838. * we can now sync irq and kill any running tasklets, since we already
  1839. * disabled interrupts and not holding a spin lock
  1840. */
  1841. synchronize_irq(sc->irq);
  1842. tasklet_kill(&sc->intr_tq);
  1843. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1844. ath9k_ps_restore(sc);
  1845. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1846. atomic_inc(&sc->wow_sleep_proc_intr);
  1847. fail_wow:
  1848. mutex_unlock(&sc->mutex);
  1849. return ret;
  1850. }
  1851. static int ath9k_resume(struct ieee80211_hw *hw)
  1852. {
  1853. struct ath_softc *sc = hw->priv;
  1854. struct ath_hw *ah = sc->sc_ah;
  1855. struct ath_common *common = ath9k_hw_common(ah);
  1856. u32 wow_status;
  1857. mutex_lock(&sc->mutex);
  1858. ath9k_ps_wakeup(sc);
  1859. spin_lock_bh(&sc->sc_pcu_lock);
  1860. ath9k_hw_disable_interrupts(ah);
  1861. ah->imask = sc->wow_intr_before_sleep;
  1862. ath9k_hw_set_interrupts(ah);
  1863. ath9k_hw_enable_interrupts(ah);
  1864. spin_unlock_bh(&sc->sc_pcu_lock);
  1865. wow_status = ath9k_hw_wow_wakeup(ah);
  1866. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1867. /*
  1868. * some devices may not pick beacon miss
  1869. * as the reason they woke up so we add
  1870. * that here for that shortcoming.
  1871. */
  1872. wow_status |= AH_WOW_BEACON_MISS;
  1873. atomic_dec(&sc->wow_got_bmiss_intr);
  1874. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1875. }
  1876. atomic_dec(&sc->wow_sleep_proc_intr);
  1877. if (wow_status) {
  1878. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1879. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1880. }
  1881. ath_restart_work(sc);
  1882. ath9k_start_btcoex(sc);
  1883. ath9k_ps_restore(sc);
  1884. mutex_unlock(&sc->mutex);
  1885. return 0;
  1886. }
  1887. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1888. {
  1889. struct ath_softc *sc = hw->priv;
  1890. mutex_lock(&sc->mutex);
  1891. device_init_wakeup(sc->dev, 1);
  1892. device_set_wakeup_enable(sc->dev, enabled);
  1893. mutex_unlock(&sc->mutex);
  1894. }
  1895. #endif
  1896. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1897. {
  1898. struct ath_softc *sc = hw->priv;
  1899. set_bit(SC_OP_SCANNING, &sc->sc_flags);
  1900. }
  1901. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1902. {
  1903. struct ath_softc *sc = hw->priv;
  1904. clear_bit(SC_OP_SCANNING, &sc->sc_flags);
  1905. }
  1906. static void ath9k_channel_switch_beacon(struct ieee80211_hw *hw,
  1907. struct ieee80211_vif *vif,
  1908. struct cfg80211_chan_def *chandef)
  1909. {
  1910. struct ath_softc *sc = hw->priv;
  1911. /* mac80211 does not support CSA in multi-if cases (yet) */
  1912. if (WARN_ON(sc->csa_vif))
  1913. return;
  1914. sc->csa_vif = vif;
  1915. }
  1916. static void ath9k_tx99_stop(struct ath_softc *sc)
  1917. {
  1918. struct ath_hw *ah = sc->sc_ah;
  1919. struct ath_common *common = ath9k_hw_common(ah);
  1920. ath_drain_all_txq(sc);
  1921. ath_startrecv(sc);
  1922. ath9k_hw_set_interrupts(ah);
  1923. ath9k_hw_enable_interrupts(ah);
  1924. ieee80211_wake_queues(sc->hw);
  1925. kfree_skb(sc->tx99_skb);
  1926. sc->tx99_skb = NULL;
  1927. sc->tx99_state = false;
  1928. ath9k_hw_tx99_stop(sc->sc_ah);
  1929. ath_dbg(common, XMIT, "TX99 stopped\n");
  1930. }
  1931. static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
  1932. {
  1933. static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
  1934. 0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
  1935. 0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
  1936. 0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
  1937. 0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
  1938. 0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
  1939. 0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
  1940. 0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
  1941. u32 len = 1200;
  1942. struct ieee80211_hw *hw = sc->hw;
  1943. struct ieee80211_hdr *hdr;
  1944. struct ieee80211_tx_info *tx_info;
  1945. struct sk_buff *skb;
  1946. skb = alloc_skb(len, GFP_KERNEL);
  1947. if (!skb)
  1948. return NULL;
  1949. skb_put(skb, len);
  1950. memset(skb->data, 0, len);
  1951. hdr = (struct ieee80211_hdr *)skb->data;
  1952. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
  1953. hdr->duration_id = 0;
  1954. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  1955. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  1956. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  1957. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1958. tx_info = IEEE80211_SKB_CB(skb);
  1959. memset(tx_info, 0, sizeof(*tx_info));
  1960. tx_info->band = hw->conf.chandef.chan->band;
  1961. tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
  1962. tx_info->control.vif = sc->tx99_vif;
  1963. memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
  1964. return skb;
  1965. }
  1966. void ath9k_tx99_deinit(struct ath_softc *sc)
  1967. {
  1968. ath_reset(sc);
  1969. ath9k_ps_wakeup(sc);
  1970. ath9k_tx99_stop(sc);
  1971. ath9k_ps_restore(sc);
  1972. }
  1973. int ath9k_tx99_init(struct ath_softc *sc)
  1974. {
  1975. struct ieee80211_hw *hw = sc->hw;
  1976. struct ath_hw *ah = sc->sc_ah;
  1977. struct ath_common *common = ath9k_hw_common(ah);
  1978. struct ath_tx_control txctl;
  1979. int r;
  1980. if (sc->sc_flags & SC_OP_INVALID) {
  1981. ath_err(common,
  1982. "driver is in invalid state unable to use TX99");
  1983. return -EINVAL;
  1984. }
  1985. sc->tx99_skb = ath9k_build_tx99_skb(sc);
  1986. if (!sc->tx99_skb)
  1987. return -ENOMEM;
  1988. memset(&txctl, 0, sizeof(txctl));
  1989. txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
  1990. ath_reset(sc);
  1991. ath9k_ps_wakeup(sc);
  1992. ath9k_hw_disable_interrupts(ah);
  1993. atomic_set(&ah->intr_ref_cnt, -1);
  1994. ath_drain_all_txq(sc);
  1995. ath_stoprecv(sc);
  1996. sc->tx99_state = true;
  1997. ieee80211_stop_queues(hw);
  1998. if (sc->tx99_power == MAX_RATE_POWER + 1)
  1999. sc->tx99_power = MAX_RATE_POWER;
  2000. ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
  2001. r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
  2002. if (r) {
  2003. ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
  2004. return r;
  2005. }
  2006. ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
  2007. sc->tx99_power,
  2008. sc->tx99_power / 2);
  2009. /* We leave the harware awake as it will be chugging on */
  2010. return 0;
  2011. }
  2012. struct ieee80211_ops ath9k_ops = {
  2013. .tx = ath9k_tx,
  2014. .start = ath9k_start,
  2015. .stop = ath9k_stop,
  2016. .add_interface = ath9k_add_interface,
  2017. .change_interface = ath9k_change_interface,
  2018. .remove_interface = ath9k_remove_interface,
  2019. .config = ath9k_config,
  2020. .configure_filter = ath9k_configure_filter,
  2021. .sta_add = ath9k_sta_add,
  2022. .sta_remove = ath9k_sta_remove,
  2023. .sta_notify = ath9k_sta_notify,
  2024. .conf_tx = ath9k_conf_tx,
  2025. .bss_info_changed = ath9k_bss_info_changed,
  2026. .set_key = ath9k_set_key,
  2027. .get_tsf = ath9k_get_tsf,
  2028. .set_tsf = ath9k_set_tsf,
  2029. .reset_tsf = ath9k_reset_tsf,
  2030. .ampdu_action = ath9k_ampdu_action,
  2031. .get_survey = ath9k_get_survey,
  2032. .rfkill_poll = ath9k_rfkill_poll_state,
  2033. .set_coverage_class = ath9k_set_coverage_class,
  2034. .flush = ath9k_flush,
  2035. .tx_frames_pending = ath9k_tx_frames_pending,
  2036. .tx_last_beacon = ath9k_tx_last_beacon,
  2037. .release_buffered_frames = ath9k_release_buffered_frames,
  2038. .get_stats = ath9k_get_stats,
  2039. .set_antenna = ath9k_set_antenna,
  2040. .get_antenna = ath9k_get_antenna,
  2041. #ifdef CONFIG_PM_SLEEP
  2042. .suspend = ath9k_suspend,
  2043. .resume = ath9k_resume,
  2044. .set_wakeup = ath9k_set_wakeup,
  2045. #endif
  2046. #ifdef CONFIG_ATH9K_DEBUGFS
  2047. .get_et_sset_count = ath9k_get_et_sset_count,
  2048. .get_et_stats = ath9k_get_et_stats,
  2049. .get_et_strings = ath9k_get_et_strings,
  2050. #endif
  2051. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
  2052. .sta_add_debugfs = ath9k_sta_add_debugfs,
  2053. #endif
  2054. .sw_scan_start = ath9k_sw_scan_start,
  2055. .sw_scan_complete = ath9k_sw_scan_complete,
  2056. .channel_switch_beacon = ath9k_channel_switch_beacon,
  2057. };