sdhci.c 33 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/highmem.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mmc/protocol.h>
  16. #include <asm/scatterlist.h>
  17. #include "sdhci.h"
  18. #define DRIVER_NAME "sdhci"
  19. #define DRIVER_VERSION "0.11"
  20. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  21. #define DBG(f, x...) \
  22. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  23. static const struct pci_device_id pci_ids[] __devinitdata = {
  24. /* handle any SD host controller */
  25. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  26. { /* end: all zeroes */ },
  27. };
  28. MODULE_DEVICE_TABLE(pci, pci_ids);
  29. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  30. static void sdhci_finish_data(struct sdhci_host *);
  31. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  32. static void sdhci_finish_command(struct sdhci_host *);
  33. static void sdhci_dumpregs(struct sdhci_host *host)
  34. {
  35. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  36. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  37. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  38. readw(host->ioaddr + SDHCI_HOST_VERSION));
  39. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  40. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  41. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  42. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  43. readl(host->ioaddr + SDHCI_ARGUMENT),
  44. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  45. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  46. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  47. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  48. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  49. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  50. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  51. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  52. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  53. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  54. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  55. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  56. readl(host->ioaddr + SDHCI_INT_STATUS));
  57. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  58. readl(host->ioaddr + SDHCI_INT_ENABLE),
  59. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  60. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  61. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  62. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  63. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  64. readl(host->ioaddr + SDHCI_CAPABILITIES),
  65. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  66. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  67. }
  68. /*****************************************************************************\
  69. * *
  70. * Low level functions *
  71. * *
  72. \*****************************************************************************/
  73. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  74. {
  75. unsigned long timeout;
  76. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  77. if (mask & SDHCI_RESET_ALL)
  78. host->clock = 0;
  79. /* Wait max 100 ms */
  80. timeout = 100;
  81. /* hw clears the bit when it's done */
  82. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  83. if (timeout == 0) {
  84. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  85. "Please report this to " BUGMAIL ".\n",
  86. mmc_hostname(host->mmc), (int)mask);
  87. sdhci_dumpregs(host);
  88. return;
  89. }
  90. timeout--;
  91. mdelay(1);
  92. }
  93. }
  94. static void sdhci_init(struct sdhci_host *host)
  95. {
  96. u32 intmask;
  97. sdhci_reset(host, SDHCI_RESET_ALL);
  98. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  99. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  100. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  101. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  102. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  103. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  104. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  105. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  106. }
  107. static void sdhci_activate_led(struct sdhci_host *host)
  108. {
  109. u8 ctrl;
  110. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  111. ctrl |= SDHCI_CTRL_LED;
  112. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  113. }
  114. static void sdhci_deactivate_led(struct sdhci_host *host)
  115. {
  116. u8 ctrl;
  117. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  118. ctrl &= ~SDHCI_CTRL_LED;
  119. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  120. }
  121. /*****************************************************************************\
  122. * *
  123. * Core functions *
  124. * *
  125. \*****************************************************************************/
  126. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  127. {
  128. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  129. return host->mapped_sg + host->cur_sg->offset;
  130. }
  131. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  132. {
  133. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  134. }
  135. static inline int sdhci_next_sg(struct sdhci_host* host)
  136. {
  137. /*
  138. * Skip to next SG entry.
  139. */
  140. host->cur_sg++;
  141. host->num_sg--;
  142. /*
  143. * Any entries left?
  144. */
  145. if (host->num_sg > 0) {
  146. host->offset = 0;
  147. host->remain = host->cur_sg->length;
  148. }
  149. return host->num_sg;
  150. }
  151. static void sdhci_read_block_pio(struct sdhci_host *host)
  152. {
  153. int blksize, chunk_remain;
  154. u32 data;
  155. char *buffer;
  156. int size;
  157. DBG("PIO reading\n");
  158. blksize = host->data->blksz;
  159. chunk_remain = 0;
  160. data = 0;
  161. buffer = sdhci_kmap_sg(host) + host->offset;
  162. while (blksize) {
  163. if (chunk_remain == 0) {
  164. data = readl(host->ioaddr + SDHCI_BUFFER);
  165. chunk_remain = min(blksize, 4);
  166. }
  167. size = min(host->size, host->remain);
  168. size = min(size, chunk_remain);
  169. chunk_remain -= size;
  170. blksize -= size;
  171. host->offset += size;
  172. host->remain -= size;
  173. host->size -= size;
  174. while (size) {
  175. *buffer = data & 0xFF;
  176. buffer++;
  177. data >>= 8;
  178. size--;
  179. }
  180. if (host->remain == 0) {
  181. sdhci_kunmap_sg(host);
  182. if (sdhci_next_sg(host) == 0) {
  183. BUG_ON(blksize != 0);
  184. return;
  185. }
  186. buffer = sdhci_kmap_sg(host);
  187. }
  188. }
  189. sdhci_kunmap_sg(host);
  190. }
  191. static void sdhci_write_block_pio(struct sdhci_host *host)
  192. {
  193. int blksize, chunk_remain;
  194. u32 data;
  195. char *buffer;
  196. int bytes, size;
  197. DBG("PIO writing\n");
  198. blksize = host->data->blksz;
  199. chunk_remain = 4;
  200. data = 0;
  201. bytes = 0;
  202. buffer = sdhci_kmap_sg(host) + host->offset;
  203. while (blksize) {
  204. size = min(host->size, host->remain);
  205. size = min(size, chunk_remain);
  206. chunk_remain -= size;
  207. blksize -= size;
  208. host->offset += size;
  209. host->remain -= size;
  210. host->size -= size;
  211. while (size) {
  212. data >>= 8;
  213. data |= (u32)*buffer << 24;
  214. buffer++;
  215. size--;
  216. }
  217. if (chunk_remain == 0) {
  218. writel(data, host->ioaddr + SDHCI_BUFFER);
  219. chunk_remain = min(blksize, 4);
  220. }
  221. if (host->remain == 0) {
  222. sdhci_kunmap_sg(host);
  223. if (sdhci_next_sg(host) == 0) {
  224. BUG_ON(blksize != 0);
  225. return;
  226. }
  227. buffer = sdhci_kmap_sg(host);
  228. }
  229. }
  230. sdhci_kunmap_sg(host);
  231. }
  232. static void sdhci_transfer_pio(struct sdhci_host *host)
  233. {
  234. u32 mask;
  235. BUG_ON(!host->data);
  236. if (host->size == 0)
  237. return;
  238. if (host->data->flags & MMC_DATA_READ)
  239. mask = SDHCI_DATA_AVAILABLE;
  240. else
  241. mask = SDHCI_SPACE_AVAILABLE;
  242. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  243. if (host->data->flags & MMC_DATA_READ)
  244. sdhci_read_block_pio(host);
  245. else
  246. sdhci_write_block_pio(host);
  247. if (host->size == 0)
  248. break;
  249. BUG_ON(host->num_sg == 0);
  250. }
  251. DBG("PIO transfer complete.\n");
  252. }
  253. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  254. {
  255. u8 count;
  256. unsigned target_timeout, current_timeout;
  257. WARN_ON(host->data);
  258. if (data == NULL)
  259. return;
  260. DBG("blksz %04x blks %04x flags %08x\n",
  261. data->blksz, data->blocks, data->flags);
  262. DBG("tsac %d ms nsac %d clk\n",
  263. data->timeout_ns / 1000000, data->timeout_clks);
  264. /* timeout in us */
  265. target_timeout = data->timeout_ns / 1000 +
  266. data->timeout_clks / host->clock;
  267. /*
  268. * Figure out needed cycles.
  269. * We do this in steps in order to fit inside a 32 bit int.
  270. * The first step is the minimum timeout, which will have a
  271. * minimum resolution of 6 bits:
  272. * (1) 2^13*1000 > 2^22,
  273. * (2) host->timeout_clk < 2^16
  274. * =>
  275. * (1) / (2) > 2^6
  276. */
  277. count = 0;
  278. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  279. while (current_timeout < target_timeout) {
  280. count++;
  281. current_timeout <<= 1;
  282. if (count >= 0xF)
  283. break;
  284. }
  285. if (count >= 0xF) {
  286. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  287. mmc_hostname(host->mmc));
  288. count = 0xE;
  289. }
  290. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  291. if (host->flags & SDHCI_USE_DMA) {
  292. int count;
  293. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  294. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  295. BUG_ON(count != 1);
  296. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  297. } else {
  298. host->size = data->blksz * data->blocks;
  299. host->cur_sg = data->sg;
  300. host->num_sg = data->sg_len;
  301. host->offset = 0;
  302. host->remain = host->cur_sg->length;
  303. }
  304. writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
  305. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  306. }
  307. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  308. struct mmc_data *data)
  309. {
  310. u16 mode;
  311. WARN_ON(host->data);
  312. if (data == NULL)
  313. return;
  314. mode = SDHCI_TRNS_BLK_CNT_EN;
  315. if (data->blocks > 1)
  316. mode |= SDHCI_TRNS_MULTI;
  317. if (data->flags & MMC_DATA_READ)
  318. mode |= SDHCI_TRNS_READ;
  319. if (host->flags & SDHCI_USE_DMA)
  320. mode |= SDHCI_TRNS_DMA;
  321. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  322. }
  323. static void sdhci_finish_data(struct sdhci_host *host)
  324. {
  325. struct mmc_data *data;
  326. u16 blocks;
  327. BUG_ON(!host->data);
  328. data = host->data;
  329. host->data = NULL;
  330. if (host->flags & SDHCI_USE_DMA) {
  331. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  332. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  333. }
  334. /*
  335. * Controller doesn't count down when in single block mode.
  336. */
  337. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  338. blocks = 0;
  339. else
  340. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  341. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  342. if ((data->error == MMC_ERR_NONE) && blocks) {
  343. printk(KERN_ERR "%s: Controller signalled completion even "
  344. "though there were blocks left. Please report this "
  345. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  346. data->error = MMC_ERR_FAILED;
  347. }
  348. if (host->size != 0) {
  349. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  350. "Please report this to " BUGMAIL ".\n",
  351. mmc_hostname(host->mmc), host->size);
  352. data->error = MMC_ERR_FAILED;
  353. }
  354. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  355. if (data->stop) {
  356. /*
  357. * The controller needs a reset of internal state machines
  358. * upon error conditions.
  359. */
  360. if (data->error != MMC_ERR_NONE) {
  361. sdhci_reset(host, SDHCI_RESET_CMD);
  362. sdhci_reset(host, SDHCI_RESET_DATA);
  363. }
  364. sdhci_send_command(host, data->stop);
  365. } else
  366. tasklet_schedule(&host->finish_tasklet);
  367. }
  368. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  369. {
  370. int flags;
  371. unsigned long timeout;
  372. WARN_ON(host->cmd);
  373. DBG("Sending cmd (%x)\n", cmd->opcode);
  374. /* Wait max 10 ms */
  375. timeout = 10;
  376. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  377. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  378. if (timeout == 0) {
  379. printk(KERN_ERR "%s: Controller never released "
  380. "inhibit bits. Please report this to "
  381. BUGMAIL ".\n", mmc_hostname(host->mmc));
  382. sdhci_dumpregs(host);
  383. cmd->error = MMC_ERR_FAILED;
  384. tasklet_schedule(&host->finish_tasklet);
  385. return;
  386. }
  387. timeout--;
  388. mdelay(1);
  389. }
  390. mod_timer(&host->timer, jiffies + 10 * HZ);
  391. host->cmd = cmd;
  392. sdhci_prepare_data(host, cmd->data);
  393. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  394. sdhci_set_transfer_mode(host, cmd->data);
  395. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  396. printk(KERN_ERR "%s: Unsupported response type! "
  397. "Please report this to " BUGMAIL ".\n",
  398. mmc_hostname(host->mmc));
  399. cmd->error = MMC_ERR_INVALID;
  400. tasklet_schedule(&host->finish_tasklet);
  401. return;
  402. }
  403. if (!(cmd->flags & MMC_RSP_PRESENT))
  404. flags = SDHCI_CMD_RESP_NONE;
  405. else if (cmd->flags & MMC_RSP_136)
  406. flags = SDHCI_CMD_RESP_LONG;
  407. else if (cmd->flags & MMC_RSP_BUSY)
  408. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  409. else
  410. flags = SDHCI_CMD_RESP_SHORT;
  411. if (cmd->flags & MMC_RSP_CRC)
  412. flags |= SDHCI_CMD_CRC;
  413. if (cmd->flags & MMC_RSP_OPCODE)
  414. flags |= SDHCI_CMD_INDEX;
  415. if (cmd->data)
  416. flags |= SDHCI_CMD_DATA;
  417. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  418. host->ioaddr + SDHCI_COMMAND);
  419. }
  420. static void sdhci_finish_command(struct sdhci_host *host)
  421. {
  422. int i;
  423. BUG_ON(host->cmd == NULL);
  424. if (host->cmd->flags & MMC_RSP_PRESENT) {
  425. if (host->cmd->flags & MMC_RSP_136) {
  426. /* CRC is stripped so we need to do some shifting. */
  427. for (i = 0;i < 4;i++) {
  428. host->cmd->resp[i] = readl(host->ioaddr +
  429. SDHCI_RESPONSE + (3-i)*4) << 8;
  430. if (i != 3)
  431. host->cmd->resp[i] |=
  432. readb(host->ioaddr +
  433. SDHCI_RESPONSE + (3-i)*4-1);
  434. }
  435. } else {
  436. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  437. }
  438. }
  439. host->cmd->error = MMC_ERR_NONE;
  440. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  441. if (host->cmd->data)
  442. host->data = host->cmd->data;
  443. else
  444. tasklet_schedule(&host->finish_tasklet);
  445. host->cmd = NULL;
  446. }
  447. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  448. {
  449. int div;
  450. u16 clk;
  451. unsigned long timeout;
  452. if (clock == host->clock)
  453. return;
  454. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  455. if (clock == 0)
  456. goto out;
  457. for (div = 1;div < 256;div *= 2) {
  458. if ((host->max_clk / div) <= clock)
  459. break;
  460. }
  461. div >>= 1;
  462. clk = div << SDHCI_DIVIDER_SHIFT;
  463. clk |= SDHCI_CLOCK_INT_EN;
  464. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  465. /* Wait max 10 ms */
  466. timeout = 10;
  467. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  468. & SDHCI_CLOCK_INT_STABLE)) {
  469. if (timeout == 0) {
  470. printk(KERN_ERR "%s: Internal clock never stabilised. "
  471. "Please report this to " BUGMAIL ".\n",
  472. mmc_hostname(host->mmc));
  473. sdhci_dumpregs(host);
  474. return;
  475. }
  476. timeout--;
  477. mdelay(1);
  478. }
  479. clk |= SDHCI_CLOCK_CARD_EN;
  480. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  481. out:
  482. host->clock = clock;
  483. }
  484. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  485. {
  486. u8 pwr;
  487. if (host->power == power)
  488. return;
  489. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  490. if (power == (unsigned short)-1)
  491. goto out;
  492. pwr = SDHCI_POWER_ON;
  493. switch (power) {
  494. case MMC_VDD_170:
  495. case MMC_VDD_180:
  496. case MMC_VDD_190:
  497. pwr |= SDHCI_POWER_180;
  498. break;
  499. case MMC_VDD_290:
  500. case MMC_VDD_300:
  501. case MMC_VDD_310:
  502. pwr |= SDHCI_POWER_300;
  503. break;
  504. case MMC_VDD_320:
  505. case MMC_VDD_330:
  506. case MMC_VDD_340:
  507. pwr |= SDHCI_POWER_330;
  508. break;
  509. default:
  510. BUG();
  511. }
  512. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  513. out:
  514. host->power = power;
  515. }
  516. /*****************************************************************************\
  517. * *
  518. * MMC callbacks *
  519. * *
  520. \*****************************************************************************/
  521. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  522. {
  523. struct sdhci_host *host;
  524. unsigned long flags;
  525. host = mmc_priv(mmc);
  526. spin_lock_irqsave(&host->lock, flags);
  527. WARN_ON(host->mrq != NULL);
  528. sdhci_activate_led(host);
  529. host->mrq = mrq;
  530. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  531. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  532. tasklet_schedule(&host->finish_tasklet);
  533. } else
  534. sdhci_send_command(host, mrq->cmd);
  535. spin_unlock_irqrestore(&host->lock, flags);
  536. }
  537. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  538. {
  539. struct sdhci_host *host;
  540. unsigned long flags;
  541. u8 ctrl;
  542. host = mmc_priv(mmc);
  543. spin_lock_irqsave(&host->lock, flags);
  544. /*
  545. * Reset the chip on each power off.
  546. * Should clear out any weird states.
  547. */
  548. if (ios->power_mode == MMC_POWER_OFF) {
  549. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  550. sdhci_init(host);
  551. }
  552. sdhci_set_clock(host, ios->clock);
  553. if (ios->power_mode == MMC_POWER_OFF)
  554. sdhci_set_power(host, -1);
  555. else
  556. sdhci_set_power(host, ios->vdd);
  557. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  558. if (ios->bus_width == MMC_BUS_WIDTH_4)
  559. ctrl |= SDHCI_CTRL_4BITBUS;
  560. else
  561. ctrl &= ~SDHCI_CTRL_4BITBUS;
  562. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  563. spin_unlock_irqrestore(&host->lock, flags);
  564. }
  565. static int sdhci_get_ro(struct mmc_host *mmc)
  566. {
  567. struct sdhci_host *host;
  568. unsigned long flags;
  569. int present;
  570. host = mmc_priv(mmc);
  571. spin_lock_irqsave(&host->lock, flags);
  572. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  573. spin_unlock_irqrestore(&host->lock, flags);
  574. return !(present & SDHCI_WRITE_PROTECT);
  575. }
  576. static struct mmc_host_ops sdhci_ops = {
  577. .request = sdhci_request,
  578. .set_ios = sdhci_set_ios,
  579. .get_ro = sdhci_get_ro,
  580. };
  581. /*****************************************************************************\
  582. * *
  583. * Tasklets *
  584. * *
  585. \*****************************************************************************/
  586. static void sdhci_tasklet_card(unsigned long param)
  587. {
  588. struct sdhci_host *host;
  589. unsigned long flags;
  590. host = (struct sdhci_host*)param;
  591. spin_lock_irqsave(&host->lock, flags);
  592. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  593. if (host->mrq) {
  594. printk(KERN_ERR "%s: Card removed during transfer!\n",
  595. mmc_hostname(host->mmc));
  596. printk(KERN_ERR "%s: Resetting controller.\n",
  597. mmc_hostname(host->mmc));
  598. sdhci_reset(host, SDHCI_RESET_CMD);
  599. sdhci_reset(host, SDHCI_RESET_DATA);
  600. host->mrq->cmd->error = MMC_ERR_FAILED;
  601. tasklet_schedule(&host->finish_tasklet);
  602. }
  603. }
  604. spin_unlock_irqrestore(&host->lock, flags);
  605. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  606. }
  607. static void sdhci_tasklet_finish(unsigned long param)
  608. {
  609. struct sdhci_host *host;
  610. unsigned long flags;
  611. struct mmc_request *mrq;
  612. host = (struct sdhci_host*)param;
  613. spin_lock_irqsave(&host->lock, flags);
  614. del_timer(&host->timer);
  615. mrq = host->mrq;
  616. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  617. /*
  618. * The controller needs a reset of internal state machines
  619. * upon error conditions.
  620. */
  621. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  622. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  623. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  624. sdhci_reset(host, SDHCI_RESET_CMD);
  625. sdhci_reset(host, SDHCI_RESET_DATA);
  626. }
  627. host->mrq = NULL;
  628. host->cmd = NULL;
  629. host->data = NULL;
  630. sdhci_deactivate_led(host);
  631. spin_unlock_irqrestore(&host->lock, flags);
  632. mmc_request_done(host->mmc, mrq);
  633. }
  634. static void sdhci_timeout_timer(unsigned long data)
  635. {
  636. struct sdhci_host *host;
  637. unsigned long flags;
  638. host = (struct sdhci_host*)data;
  639. spin_lock_irqsave(&host->lock, flags);
  640. if (host->mrq) {
  641. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  642. "Please report this to " BUGMAIL ".\n",
  643. mmc_hostname(host->mmc));
  644. sdhci_dumpregs(host);
  645. if (host->data) {
  646. host->data->error = MMC_ERR_TIMEOUT;
  647. sdhci_finish_data(host);
  648. } else {
  649. if (host->cmd)
  650. host->cmd->error = MMC_ERR_TIMEOUT;
  651. else
  652. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  653. tasklet_schedule(&host->finish_tasklet);
  654. }
  655. }
  656. spin_unlock_irqrestore(&host->lock, flags);
  657. }
  658. /*****************************************************************************\
  659. * *
  660. * Interrupt handling *
  661. * *
  662. \*****************************************************************************/
  663. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  664. {
  665. BUG_ON(intmask == 0);
  666. if (!host->cmd) {
  667. printk(KERN_ERR "%s: Got command interrupt even though no "
  668. "command operation was in progress.\n",
  669. mmc_hostname(host->mmc));
  670. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  671. mmc_hostname(host->mmc));
  672. sdhci_dumpregs(host);
  673. return;
  674. }
  675. if (intmask & SDHCI_INT_RESPONSE)
  676. sdhci_finish_command(host);
  677. else {
  678. if (intmask & SDHCI_INT_TIMEOUT)
  679. host->cmd->error = MMC_ERR_TIMEOUT;
  680. else if (intmask & SDHCI_INT_CRC)
  681. host->cmd->error = MMC_ERR_BADCRC;
  682. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  683. host->cmd->error = MMC_ERR_FAILED;
  684. else
  685. host->cmd->error = MMC_ERR_INVALID;
  686. tasklet_schedule(&host->finish_tasklet);
  687. }
  688. }
  689. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  690. {
  691. BUG_ON(intmask == 0);
  692. if (!host->data) {
  693. /*
  694. * A data end interrupt is sent together with the response
  695. * for the stop command.
  696. */
  697. if (intmask & SDHCI_INT_DATA_END)
  698. return;
  699. printk(KERN_ERR "%s: Got data interrupt even though no "
  700. "data operation was in progress.\n",
  701. mmc_hostname(host->mmc));
  702. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  703. mmc_hostname(host->mmc));
  704. sdhci_dumpregs(host);
  705. return;
  706. }
  707. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  708. host->data->error = MMC_ERR_TIMEOUT;
  709. else if (intmask & SDHCI_INT_DATA_CRC)
  710. host->data->error = MMC_ERR_BADCRC;
  711. else if (intmask & SDHCI_INT_DATA_END_BIT)
  712. host->data->error = MMC_ERR_FAILED;
  713. if (host->data->error != MMC_ERR_NONE)
  714. sdhci_finish_data(host);
  715. else {
  716. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  717. sdhci_transfer_pio(host);
  718. if (intmask & SDHCI_INT_DATA_END)
  719. sdhci_finish_data(host);
  720. }
  721. }
  722. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  723. {
  724. irqreturn_t result;
  725. struct sdhci_host* host = dev_id;
  726. u32 intmask;
  727. spin_lock(&host->lock);
  728. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  729. if (!intmask) {
  730. result = IRQ_NONE;
  731. goto out;
  732. }
  733. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  734. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  735. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  736. host->ioaddr + SDHCI_INT_STATUS);
  737. tasklet_schedule(&host->card_tasklet);
  738. }
  739. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  740. if (intmask & SDHCI_INT_CMD_MASK) {
  741. writel(intmask & SDHCI_INT_CMD_MASK,
  742. host->ioaddr + SDHCI_INT_STATUS);
  743. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  744. }
  745. if (intmask & SDHCI_INT_DATA_MASK) {
  746. writel(intmask & SDHCI_INT_DATA_MASK,
  747. host->ioaddr + SDHCI_INT_STATUS);
  748. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  749. }
  750. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  751. if (intmask & SDHCI_INT_BUS_POWER) {
  752. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  753. mmc_hostname(host->mmc));
  754. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  755. }
  756. intmask &= SDHCI_INT_BUS_POWER;
  757. if (intmask) {
  758. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  759. "report this to " BUGMAIL ".\n",
  760. mmc_hostname(host->mmc), intmask);
  761. sdhci_dumpregs(host);
  762. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  763. }
  764. result = IRQ_HANDLED;
  765. out:
  766. spin_unlock(&host->lock);
  767. return result;
  768. }
  769. /*****************************************************************************\
  770. * *
  771. * Suspend/resume *
  772. * *
  773. \*****************************************************************************/
  774. #ifdef CONFIG_PM
  775. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  776. {
  777. struct sdhci_chip *chip;
  778. int i, ret;
  779. chip = pci_get_drvdata(pdev);
  780. if (!chip)
  781. return 0;
  782. DBG("Suspending...\n");
  783. for (i = 0;i < chip->num_slots;i++) {
  784. if (!chip->hosts[i])
  785. continue;
  786. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  787. if (ret) {
  788. for (i--;i >= 0;i--)
  789. mmc_resume_host(chip->hosts[i]->mmc);
  790. return ret;
  791. }
  792. }
  793. pci_save_state(pdev);
  794. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  795. pci_disable_device(pdev);
  796. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  797. return 0;
  798. }
  799. static int sdhci_resume (struct pci_dev *pdev)
  800. {
  801. struct sdhci_chip *chip;
  802. int i, ret;
  803. chip = pci_get_drvdata(pdev);
  804. if (!chip)
  805. return 0;
  806. DBG("Resuming...\n");
  807. pci_set_power_state(pdev, PCI_D0);
  808. pci_restore_state(pdev);
  809. pci_enable_device(pdev);
  810. for (i = 0;i < chip->num_slots;i++) {
  811. if (!chip->hosts[i])
  812. continue;
  813. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  814. pci_set_master(pdev);
  815. sdhci_init(chip->hosts[i]);
  816. ret = mmc_resume_host(chip->hosts[i]->mmc);
  817. if (ret)
  818. return ret;
  819. }
  820. return 0;
  821. }
  822. #else /* CONFIG_PM */
  823. #define sdhci_suspend NULL
  824. #define sdhci_resume NULL
  825. #endif /* CONFIG_PM */
  826. /*****************************************************************************\
  827. * *
  828. * Device probing/removal *
  829. * *
  830. \*****************************************************************************/
  831. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  832. {
  833. int ret;
  834. struct sdhci_chip *chip;
  835. struct mmc_host *mmc;
  836. struct sdhci_host *host;
  837. u8 first_bar;
  838. unsigned int caps;
  839. chip = pci_get_drvdata(pdev);
  840. BUG_ON(!chip);
  841. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  842. if (ret)
  843. return ret;
  844. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  845. if (first_bar > 5) {
  846. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  847. return -ENODEV;
  848. }
  849. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  850. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  851. return -ENODEV;
  852. }
  853. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  854. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  855. return -ENODEV;
  856. }
  857. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  858. if (!mmc)
  859. return -ENOMEM;
  860. host = mmc_priv(mmc);
  861. host->mmc = mmc;
  862. host->bar = first_bar + slot;
  863. host->addr = pci_resource_start(pdev, host->bar);
  864. host->irq = pdev->irq;
  865. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  866. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  867. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  868. if (ret)
  869. goto free;
  870. host->ioaddr = ioremap_nocache(host->addr,
  871. pci_resource_len(pdev, host->bar));
  872. if (!host->ioaddr) {
  873. ret = -ENOMEM;
  874. goto release;
  875. }
  876. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  877. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  878. host->flags |= SDHCI_USE_DMA;
  879. if (host->flags & SDHCI_USE_DMA) {
  880. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  881. printk(KERN_WARNING "%s: No suitable DMA available. "
  882. "Falling back to PIO.\n", host->slot_descr);
  883. host->flags &= ~SDHCI_USE_DMA;
  884. }
  885. }
  886. if (host->flags & SDHCI_USE_DMA)
  887. pci_set_master(pdev);
  888. else /* XXX: Hack to get MMC layer to avoid highmem */
  889. pdev->dma_mask = 0;
  890. host->max_clk =
  891. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  892. if (host->max_clk == 0) {
  893. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  894. "frequency.\n", host->slot_descr);
  895. ret = -ENODEV;
  896. goto unmap;
  897. }
  898. host->max_clk *= 1000000;
  899. host->timeout_clk =
  900. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  901. if (host->timeout_clk == 0) {
  902. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  903. "frequency.\n", host->slot_descr);
  904. ret = -ENODEV;
  905. goto unmap;
  906. }
  907. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  908. host->timeout_clk *= 1000;
  909. /*
  910. * Set host parameters.
  911. */
  912. mmc->ops = &sdhci_ops;
  913. mmc->f_min = host->max_clk / 256;
  914. mmc->f_max = host->max_clk;
  915. mmc->caps = MMC_CAP_4_BIT_DATA;
  916. mmc->ocr_avail = 0;
  917. if (caps & SDHCI_CAN_VDD_330)
  918. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  919. else if (caps & SDHCI_CAN_VDD_300)
  920. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  921. else if (caps & SDHCI_CAN_VDD_180)
  922. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  923. if (mmc->ocr_avail == 0) {
  924. printk(KERN_ERR "%s: Hardware doesn't report any "
  925. "support voltages.\n", host->slot_descr);
  926. ret = -ENODEV;
  927. goto unmap;
  928. }
  929. spin_lock_init(&host->lock);
  930. /*
  931. * Maximum number of segments. Hardware cannot do scatter lists.
  932. */
  933. if (host->flags & SDHCI_USE_DMA)
  934. mmc->max_hw_segs = 1;
  935. else
  936. mmc->max_hw_segs = 16;
  937. mmc->max_phys_segs = 16;
  938. /*
  939. * Maximum number of sectors in one transfer. Limited by sector
  940. * count register.
  941. */
  942. mmc->max_sectors = 0x3FFF;
  943. /*
  944. * Maximum segment size. Could be one segment with the maximum number
  945. * of sectors.
  946. */
  947. mmc->max_seg_size = mmc->max_sectors * 512;
  948. /*
  949. * Init tasklets.
  950. */
  951. tasklet_init(&host->card_tasklet,
  952. sdhci_tasklet_card, (unsigned long)host);
  953. tasklet_init(&host->finish_tasklet,
  954. sdhci_tasklet_finish, (unsigned long)host);
  955. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  956. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  957. host->slot_descr, host);
  958. if (ret)
  959. goto untasklet;
  960. sdhci_init(host);
  961. #ifdef CONFIG_MMC_DEBUG
  962. sdhci_dumpregs(host);
  963. #endif
  964. host->chip = chip;
  965. chip->hosts[slot] = host;
  966. mmc_add_host(mmc);
  967. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  968. host->addr, host->irq,
  969. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  970. return 0;
  971. untasklet:
  972. tasklet_kill(&host->card_tasklet);
  973. tasklet_kill(&host->finish_tasklet);
  974. unmap:
  975. iounmap(host->ioaddr);
  976. release:
  977. pci_release_region(pdev, host->bar);
  978. free:
  979. mmc_free_host(mmc);
  980. return ret;
  981. }
  982. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  983. {
  984. struct sdhci_chip *chip;
  985. struct mmc_host *mmc;
  986. struct sdhci_host *host;
  987. chip = pci_get_drvdata(pdev);
  988. host = chip->hosts[slot];
  989. mmc = host->mmc;
  990. chip->hosts[slot] = NULL;
  991. mmc_remove_host(mmc);
  992. sdhci_reset(host, SDHCI_RESET_ALL);
  993. free_irq(host->irq, host);
  994. del_timer_sync(&host->timer);
  995. tasklet_kill(&host->card_tasklet);
  996. tasklet_kill(&host->finish_tasklet);
  997. iounmap(host->ioaddr);
  998. pci_release_region(pdev, host->bar);
  999. mmc_free_host(mmc);
  1000. }
  1001. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1002. const struct pci_device_id *ent)
  1003. {
  1004. int ret, i;
  1005. u8 slots, rev;
  1006. struct sdhci_chip *chip;
  1007. BUG_ON(pdev == NULL);
  1008. BUG_ON(ent == NULL);
  1009. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1010. printk(KERN_INFO DRIVER_NAME
  1011. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1012. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1013. (int)rev);
  1014. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1015. if (ret)
  1016. return ret;
  1017. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1018. DBG("found %d slot(s)\n", slots);
  1019. if (slots == 0)
  1020. return -ENODEV;
  1021. ret = pci_enable_device(pdev);
  1022. if (ret)
  1023. return ret;
  1024. chip = kzalloc(sizeof(struct sdhci_chip) +
  1025. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1026. if (!chip) {
  1027. ret = -ENOMEM;
  1028. goto err;
  1029. }
  1030. chip->pdev = pdev;
  1031. chip->num_slots = slots;
  1032. pci_set_drvdata(pdev, chip);
  1033. for (i = 0;i < slots;i++) {
  1034. ret = sdhci_probe_slot(pdev, i);
  1035. if (ret) {
  1036. for (i--;i >= 0;i--)
  1037. sdhci_remove_slot(pdev, i);
  1038. goto free;
  1039. }
  1040. }
  1041. return 0;
  1042. free:
  1043. pci_set_drvdata(pdev, NULL);
  1044. kfree(chip);
  1045. err:
  1046. pci_disable_device(pdev);
  1047. return ret;
  1048. }
  1049. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1050. {
  1051. int i;
  1052. struct sdhci_chip *chip;
  1053. chip = pci_get_drvdata(pdev);
  1054. if (chip) {
  1055. for (i = 0;i < chip->num_slots;i++)
  1056. sdhci_remove_slot(pdev, i);
  1057. pci_set_drvdata(pdev, NULL);
  1058. kfree(chip);
  1059. }
  1060. pci_disable_device(pdev);
  1061. }
  1062. static struct pci_driver sdhci_driver = {
  1063. .name = DRIVER_NAME,
  1064. .id_table = pci_ids,
  1065. .probe = sdhci_probe,
  1066. .remove = __devexit_p(sdhci_remove),
  1067. .suspend = sdhci_suspend,
  1068. .resume = sdhci_resume,
  1069. };
  1070. /*****************************************************************************\
  1071. * *
  1072. * Driver init/exit *
  1073. * *
  1074. \*****************************************************************************/
  1075. static int __init sdhci_drv_init(void)
  1076. {
  1077. printk(KERN_INFO DRIVER_NAME
  1078. ": Secure Digital Host Controller Interface driver, "
  1079. DRIVER_VERSION "\n");
  1080. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1081. return pci_register_driver(&sdhci_driver);
  1082. }
  1083. static void __exit sdhci_drv_exit(void)
  1084. {
  1085. DBG("Exiting\n");
  1086. pci_unregister_driver(&sdhci_driver);
  1087. }
  1088. module_init(sdhci_drv_init);
  1089. module_exit(sdhci_drv_exit);
  1090. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1091. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1092. MODULE_VERSION(DRIVER_VERSION);
  1093. MODULE_LICENSE("GPL");