hash_low_32.S 16 KB

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  1. /*
  2. * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $
  3. *
  4. * PowerPC version
  5. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  6. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  7. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  8. * Adapted for Power Macintosh by Paul Mackerras.
  9. * Low-level exception handlers and MMU support
  10. * rewritten by Paul Mackerras.
  11. * Copyright (C) 1996 Paul Mackerras.
  12. *
  13. * This file contains low-level assembler routines for managing
  14. * the PowerPC MMU hash table. (PPC 8xx processors don't use a
  15. * hash table, so this file is not used on them.)
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License
  19. * as published by the Free Software Foundation; either version
  20. * 2 of the License, or (at your option) any later version.
  21. *
  22. */
  23. #include <linux/config.h>
  24. #include <asm/reg.h>
  25. #include <asm/page.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/cputable.h>
  28. #include <asm/ppc_asm.h>
  29. #include <asm/thread_info.h>
  30. #include <asm/asm-offsets.h>
  31. #ifdef CONFIG_SMP
  32. .comm mmu_hash_lock,4
  33. #endif /* CONFIG_SMP */
  34. /*
  35. * Sync CPUs with hash_page taking & releasing the hash
  36. * table lock
  37. */
  38. #ifdef CONFIG_SMP
  39. .text
  40. _GLOBAL(hash_page_sync)
  41. lis r8,mmu_hash_lock@h
  42. ori r8,r8,mmu_hash_lock@l
  43. lis r0,0x0fff
  44. b 10f
  45. 11: lwz r6,0(r8)
  46. cmpwi 0,r6,0
  47. bne 11b
  48. 10: lwarx r6,0,r8
  49. cmpwi 0,r6,0
  50. bne- 11b
  51. stwcx. r0,0,r8
  52. bne- 10b
  53. isync
  54. eieio
  55. li r0,0
  56. stw r0,0(r8)
  57. blr
  58. #endif
  59. /*
  60. * Load a PTE into the hash table, if possible.
  61. * The address is in r4, and r3 contains an access flag:
  62. * _PAGE_RW (0x400) if a write.
  63. * r9 contains the SRR1 value, from which we use the MSR_PR bit.
  64. * SPRG3 contains the physical address of the current task's thread.
  65. *
  66. * Returns to the caller if the access is illegal or there is no
  67. * mapping for the address. Otherwise it places an appropriate PTE
  68. * in the hash table and returns from the exception.
  69. * Uses r0, r3 - r8, ctr, lr.
  70. */
  71. .text
  72. _GLOBAL(hash_page)
  73. tophys(r7,0) /* gets -KERNELBASE into r7 */
  74. #ifdef CONFIG_SMP
  75. addis r8,r7,mmu_hash_lock@h
  76. ori r8,r8,mmu_hash_lock@l
  77. lis r0,0x0fff
  78. b 10f
  79. 11: lwz r6,0(r8)
  80. cmpwi 0,r6,0
  81. bne 11b
  82. 10: lwarx r6,0,r8
  83. cmpwi 0,r6,0
  84. bne- 11b
  85. stwcx. r0,0,r8
  86. bne- 10b
  87. isync
  88. #endif
  89. /* Get PTE (linux-style) and check access */
  90. lis r0,KERNELBASE@h /* check if kernel address */
  91. cmplw 0,r4,r0
  92. mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */
  93. ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
  94. lwz r5,PGDIR(r8) /* virt page-table root */
  95. blt+ 112f /* assume user more likely */
  96. lis r5,swapper_pg_dir@ha /* if kernel address, use */
  97. addi r5,r5,swapper_pg_dir@l /* kernel page table */
  98. rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
  99. 112: add r5,r5,r7 /* convert to phys addr */
  100. rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
  101. lwz r8,0(r5) /* get pmd entry */
  102. rlwinm. r8,r8,0,0,19 /* extract address of pte page */
  103. #ifdef CONFIG_SMP
  104. beq- hash_page_out /* return if no mapping */
  105. #else
  106. /* XXX it seems like the 601 will give a machine fault on the
  107. rfi if its alignment is wrong (bottom 4 bits of address are
  108. 8 or 0xc) and we have had a not-taken conditional branch
  109. to the address following the rfi. */
  110. beqlr-
  111. #endif
  112. rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
  113. rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
  114. ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
  115. /*
  116. * Update the linux PTE atomically. We do the lwarx up-front
  117. * because almost always, there won't be a permission violation
  118. * and there won't already be an HPTE, and thus we will have
  119. * to update the PTE to set _PAGE_HASHPTE. -- paulus.
  120. */
  121. retry:
  122. lwarx r6,0,r8 /* get linux-style pte */
  123. andc. r5,r3,r6 /* check access & ~permission */
  124. #ifdef CONFIG_SMP
  125. bne- hash_page_out /* return if access not permitted */
  126. #else
  127. bnelr-
  128. #endif
  129. or r5,r0,r6 /* set accessed/dirty bits */
  130. stwcx. r5,0,r8 /* attempt to update PTE */
  131. bne- retry /* retry if someone got there first */
  132. mfsrin r3,r4 /* get segment reg for segment */
  133. mfctr r0
  134. stw r0,_CTR(r11)
  135. bl create_hpte /* add the hash table entry */
  136. #ifdef CONFIG_SMP
  137. eieio
  138. addis r8,r7,mmu_hash_lock@ha
  139. li r0,0
  140. stw r0,mmu_hash_lock@l(r8)
  141. #endif
  142. /* Return from the exception */
  143. lwz r5,_CTR(r11)
  144. mtctr r5
  145. lwz r0,GPR0(r11)
  146. lwz r7,GPR7(r11)
  147. lwz r8,GPR8(r11)
  148. b fast_exception_return
  149. #ifdef CONFIG_SMP
  150. hash_page_out:
  151. eieio
  152. addis r8,r7,mmu_hash_lock@ha
  153. li r0,0
  154. stw r0,mmu_hash_lock@l(r8)
  155. blr
  156. #endif /* CONFIG_SMP */
  157. /*
  158. * Add an entry for a particular page to the hash table.
  159. *
  160. * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
  161. *
  162. * We assume any necessary modifications to the pte (e.g. setting
  163. * the accessed bit) have already been done and that there is actually
  164. * a hash table in use (i.e. we're not on a 603).
  165. */
  166. _GLOBAL(add_hash_page)
  167. mflr r0
  168. stw r0,4(r1)
  169. /* Convert context and va to VSID */
  170. mulli r3,r3,897*16 /* multiply context by context skew */
  171. rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
  172. mulli r0,r0,0x111 /* multiply by ESID skew */
  173. add r3,r3,r0 /* note create_hpte trims to 24 bits */
  174. #ifdef CONFIG_SMP
  175. rlwinm r8,r1,0,0,18 /* use cpu number to make tag */
  176. lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
  177. oris r8,r8,12
  178. #endif /* CONFIG_SMP */
  179. /*
  180. * We disable interrupts here, even on UP, because we don't
  181. * want to race with hash_page, and because we want the
  182. * _PAGE_HASHPTE bit to be a reliable indication of whether
  183. * the HPTE exists (or at least whether one did once).
  184. * We also turn off the MMU for data accesses so that we
  185. * we can't take a hash table miss (assuming the code is
  186. * covered by a BAT). -- paulus
  187. */
  188. mfmsr r10
  189. SYNC
  190. rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
  191. rlwinm r0,r0,0,28,26 /* clear MSR_DR */
  192. mtmsr r0
  193. SYNC_601
  194. isync
  195. tophys(r7,0)
  196. #ifdef CONFIG_SMP
  197. addis r9,r7,mmu_hash_lock@ha
  198. addi r9,r9,mmu_hash_lock@l
  199. 10: lwarx r0,0,r9 /* take the mmu_hash_lock */
  200. cmpi 0,r0,0
  201. bne- 11f
  202. stwcx. r8,0,r9
  203. beq+ 12f
  204. 11: lwz r0,0(r9)
  205. cmpi 0,r0,0
  206. beq 10b
  207. b 11b
  208. 12: isync
  209. #endif
  210. /*
  211. * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
  212. * If _PAGE_HASHPTE was already set, we don't replace the existing
  213. * HPTE, so we just unlock and return.
  214. */
  215. mr r8,r5
  216. rlwimi r8,r4,22,20,29
  217. 1: lwarx r6,0,r8
  218. andi. r0,r6,_PAGE_HASHPTE
  219. bne 9f /* if HASHPTE already set, done */
  220. ori r5,r6,_PAGE_HASHPTE
  221. stwcx. r5,0,r8
  222. bne- 1b
  223. bl create_hpte
  224. 9:
  225. #ifdef CONFIG_SMP
  226. eieio
  227. li r0,0
  228. stw r0,0(r9) /* clear mmu_hash_lock */
  229. #endif
  230. /* reenable interrupts and DR */
  231. mtmsr r10
  232. SYNC_601
  233. isync
  234. lwz r0,4(r1)
  235. mtlr r0
  236. blr
  237. /*
  238. * This routine adds a hardware PTE to the hash table.
  239. * It is designed to be called with the MMU either on or off.
  240. * r3 contains the VSID, r4 contains the virtual address,
  241. * r5 contains the linux PTE, r6 contains the old value of the
  242. * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
  243. * offset to be added to addresses (0 if the MMU is on,
  244. * -KERNELBASE if it is off).
  245. * On SMP, the caller should have the mmu_hash_lock held.
  246. * We assume that the caller has (or will) set the _PAGE_HASHPTE
  247. * bit in the linux PTE in memory. The value passed in r6 should
  248. * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
  249. * this routine will skip the search for an existing HPTE.
  250. * This procedure modifies r0, r3 - r6, r8, cr0.
  251. * -- paulus.
  252. *
  253. * For speed, 4 of the instructions get patched once the size and
  254. * physical address of the hash table are known. These definitions
  255. * of Hash_base and Hash_bits below are just an example.
  256. */
  257. Hash_base = 0xc0180000
  258. Hash_bits = 12 /* e.g. 256kB hash table */
  259. Hash_msk = (((1 << Hash_bits) - 1) * 64)
  260. /* defines for the PTE format for 32-bit PPCs */
  261. #define PTE_SIZE 8
  262. #define PTEG_SIZE 64
  263. #define LG_PTEG_SIZE 6
  264. #define LDPTEu lwzu
  265. #define STPTE stw
  266. #define CMPPTE cmpw
  267. #define PTE_H 0x40
  268. #define PTE_V 0x80000000
  269. #define TST_V(r) rlwinm. r,r,0,0,0
  270. #define SET_V(r) oris r,r,PTE_V@h
  271. #define CLR_V(r,t) rlwinm r,r,0,1,31
  272. #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
  273. #define HASH_RIGHT 31-LG_PTEG_SIZE
  274. _GLOBAL(create_hpte)
  275. /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
  276. rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
  277. rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
  278. and r8,r8,r0 /* writable if _RW & _DIRTY */
  279. rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
  280. rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
  281. ori r8,r8,0xe14 /* clear out reserved bits and M */
  282. andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
  283. BEGIN_FTR_SECTION
  284. ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
  285. END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
  286. /* Construct the high word of the PPC-style PTE (r5) */
  287. rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
  288. rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
  289. SET_V(r5) /* set V (valid) bit */
  290. /* Get the address of the primary PTE group in the hash table (r3) */
  291. _GLOBAL(hash_page_patch_A)
  292. addis r0,r7,Hash_base@h /* base address of hash table */
  293. rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
  294. rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
  295. xor r3,r3,r0 /* make primary hash */
  296. li r0,8 /* PTEs/group */
  297. /*
  298. * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
  299. * if it is clear, meaning that the HPTE isn't there already...
  300. */
  301. andi. r6,r6,_PAGE_HASHPTE
  302. beq+ 10f /* no PTE: go look for an empty slot */
  303. tlbie r4
  304. addis r4,r7,htab_hash_searches@ha
  305. lwz r6,htab_hash_searches@l(r4)
  306. addi r6,r6,1 /* count how many searches we do */
  307. stw r6,htab_hash_searches@l(r4)
  308. /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
  309. mtctr r0
  310. addi r4,r3,-PTE_SIZE
  311. 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
  312. CMPPTE 0,r6,r5
  313. bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
  314. beq+ found_slot
  315. /* Search the secondary PTEG for a matching PTE */
  316. ori r5,r5,PTE_H /* set H (secondary hash) bit */
  317. _GLOBAL(hash_page_patch_B)
  318. xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
  319. xori r4,r4,(-PTEG_SIZE & 0xffff)
  320. addi r4,r4,-PTE_SIZE
  321. mtctr r0
  322. 2: LDPTEu r6,PTE_SIZE(r4)
  323. CMPPTE 0,r6,r5
  324. bdnzf 2,2b
  325. beq+ found_slot
  326. xori r5,r5,PTE_H /* clear H bit again */
  327. /* Search the primary PTEG for an empty slot */
  328. 10: mtctr r0
  329. addi r4,r3,-PTE_SIZE /* search primary PTEG */
  330. 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
  331. TST_V(r6) /* test valid bit */
  332. bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
  333. beq+ found_empty
  334. /* update counter of times that the primary PTEG is full */
  335. addis r4,r7,primary_pteg_full@ha
  336. lwz r6,primary_pteg_full@l(r4)
  337. addi r6,r6,1
  338. stw r6,primary_pteg_full@l(r4)
  339. /* Search the secondary PTEG for an empty slot */
  340. ori r5,r5,PTE_H /* set H (secondary hash) bit */
  341. _GLOBAL(hash_page_patch_C)
  342. xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
  343. xori r4,r4,(-PTEG_SIZE & 0xffff)
  344. addi r4,r4,-PTE_SIZE
  345. mtctr r0
  346. 2: LDPTEu r6,PTE_SIZE(r4)
  347. TST_V(r6)
  348. bdnzf 2,2b
  349. beq+ found_empty
  350. xori r5,r5,PTE_H /* clear H bit again */
  351. /*
  352. * Choose an arbitrary slot in the primary PTEG to overwrite.
  353. * Since both the primary and secondary PTEGs are full, and we
  354. * have no information that the PTEs in the primary PTEG are
  355. * more important or useful than those in the secondary PTEG,
  356. * and we know there is a definite (although small) speed
  357. * advantage to putting the PTE in the primary PTEG, we always
  358. * put the PTE in the primary PTEG.
  359. */
  360. addis r4,r7,next_slot@ha
  361. lwz r6,next_slot@l(r4)
  362. addi r6,r6,PTE_SIZE
  363. andi. r6,r6,7*PTE_SIZE
  364. stw r6,next_slot@l(r4)
  365. add r4,r3,r6
  366. #ifndef CONFIG_SMP
  367. /* Store PTE in PTEG */
  368. found_empty:
  369. STPTE r5,0(r4)
  370. found_slot:
  371. STPTE r8,PTE_SIZE/2(r4)
  372. #else /* CONFIG_SMP */
  373. /*
  374. * Between the tlbie above and updating the hash table entry below,
  375. * another CPU could read the hash table entry and put it in its TLB.
  376. * There are 3 cases:
  377. * 1. using an empty slot
  378. * 2. updating an earlier entry to change permissions (i.e. enable write)
  379. * 3. taking over the PTE for an unrelated address
  380. *
  381. * In each case it doesn't really matter if the other CPUs have the old
  382. * PTE in their TLB. So we don't need to bother with another tlbie here,
  383. * which is convenient as we've overwritten the register that had the
  384. * address. :-) The tlbie above is mainly to make sure that this CPU comes
  385. * and gets the new PTE from the hash table.
  386. *
  387. * We do however have to make sure that the PTE is never in an invalid
  388. * state with the V bit set.
  389. */
  390. found_empty:
  391. found_slot:
  392. CLR_V(r5,r0) /* clear V (valid) bit in PTE */
  393. STPTE r5,0(r4)
  394. sync
  395. TLBSYNC
  396. STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
  397. sync
  398. SET_V(r5)
  399. STPTE r5,0(r4) /* finally set V bit in PTE */
  400. #endif /* CONFIG_SMP */
  401. sync /* make sure pte updates get to memory */
  402. blr
  403. .comm next_slot,4
  404. .comm primary_pteg_full,4
  405. .comm htab_hash_searches,4
  406. /*
  407. * Flush the entry for a particular page from the hash table.
  408. *
  409. * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
  410. * int count)
  411. *
  412. * We assume that there is a hash table in use (Hash != 0).
  413. */
  414. _GLOBAL(flush_hash_pages)
  415. tophys(r7,0)
  416. /*
  417. * We disable interrupts here, even on UP, because we want
  418. * the _PAGE_HASHPTE bit to be a reliable indication of
  419. * whether the HPTE exists (or at least whether one did once).
  420. * We also turn off the MMU for data accesses so that we
  421. * we can't take a hash table miss (assuming the code is
  422. * covered by a BAT). -- paulus
  423. */
  424. mfmsr r10
  425. SYNC
  426. rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
  427. rlwinm r0,r0,0,28,26 /* clear MSR_DR */
  428. mtmsr r0
  429. SYNC_601
  430. isync
  431. /* First find a PTE in the range that has _PAGE_HASHPTE set */
  432. rlwimi r5,r4,22,20,29
  433. 1: lwz r0,0(r5)
  434. cmpwi cr1,r6,1
  435. andi. r0,r0,_PAGE_HASHPTE
  436. bne 2f
  437. ble cr1,19f
  438. addi r4,r4,0x1000
  439. addi r5,r5,4
  440. addi r6,r6,-1
  441. b 1b
  442. /* Convert context and va to VSID */
  443. 2: mulli r3,r3,897*16 /* multiply context by context skew */
  444. rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
  445. mulli r0,r0,0x111 /* multiply by ESID skew */
  446. add r3,r3,r0 /* note code below trims to 24 bits */
  447. /* Construct the high word of the PPC-style PTE (r11) */
  448. rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
  449. rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
  450. SET_V(r11) /* set V (valid) bit */
  451. #ifdef CONFIG_SMP
  452. addis r9,r7,mmu_hash_lock@ha
  453. addi r9,r9,mmu_hash_lock@l
  454. rlwinm r8,r1,0,0,18
  455. add r8,r8,r7
  456. lwz r8,TI_CPU(r8)
  457. oris r8,r8,9
  458. 10: lwarx r0,0,r9
  459. cmpi 0,r0,0
  460. bne- 11f
  461. stwcx. r8,0,r9
  462. beq+ 12f
  463. 11: lwz r0,0(r9)
  464. cmpi 0,r0,0
  465. beq 10b
  466. b 11b
  467. 12: isync
  468. #endif
  469. /*
  470. * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
  471. * already clear, we're done (for this pte). If not,
  472. * clear it (atomically) and proceed. -- paulus.
  473. */
  474. 33: lwarx r8,0,r5 /* fetch the pte */
  475. andi. r0,r8,_PAGE_HASHPTE
  476. beq 8f /* done if HASHPTE is already clear */
  477. rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
  478. stwcx. r8,0,r5 /* update the pte */
  479. bne- 33b
  480. /* Get the address of the primary PTE group in the hash table (r3) */
  481. _GLOBAL(flush_hash_patch_A)
  482. addis r8,r7,Hash_base@h /* base address of hash table */
  483. rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
  484. rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
  485. xor r8,r0,r8 /* make primary hash */
  486. /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
  487. li r0,8 /* PTEs/group */
  488. mtctr r0
  489. addi r12,r8,-PTE_SIZE
  490. 1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */
  491. CMPPTE 0,r0,r11
  492. bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
  493. beq+ 3f
  494. /* Search the secondary PTEG for a matching PTE */
  495. ori r11,r11,PTE_H /* set H (secondary hash) bit */
  496. li r0,8 /* PTEs/group */
  497. _GLOBAL(flush_hash_patch_B)
  498. xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
  499. xori r12,r12,(-PTEG_SIZE & 0xffff)
  500. addi r12,r12,-PTE_SIZE
  501. mtctr r0
  502. 2: LDPTEu r0,PTE_SIZE(r12)
  503. CMPPTE 0,r0,r11
  504. bdnzf 2,2b
  505. xori r11,r11,PTE_H /* clear H again */
  506. bne- 4f /* should rarely fail to find it */
  507. 3: li r0,0
  508. STPTE r0,0(r12) /* invalidate entry */
  509. 4: sync
  510. tlbie r4 /* in hw tlb too */
  511. sync
  512. 8: ble cr1,9f /* if all ptes checked */
  513. 81: addi r6,r6,-1
  514. addi r5,r5,4 /* advance to next pte */
  515. addi r4,r4,0x1000
  516. lwz r0,0(r5) /* check next pte */
  517. cmpwi cr1,r6,1
  518. andi. r0,r0,_PAGE_HASHPTE
  519. bne 33b
  520. bgt cr1,81b
  521. 9:
  522. #ifdef CONFIG_SMP
  523. TLBSYNC
  524. li r0,0
  525. stw r0,0(r9) /* clear mmu_hash_lock */
  526. #endif
  527. 19: mtmsr r10
  528. SYNC_601
  529. isync
  530. blr