ti_am335x_tscadc.h 4.5 KB

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  1. #ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
  2. #define __LINUX_TI_AM335X_TSCADC_MFD_H
  3. /*
  4. * TI Touch Screen / ADC MFD driver
  5. *
  6. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/mfd/core.h>
  18. #define REG_RAWIRQSTATUS 0x024
  19. #define REG_IRQSTATUS 0x028
  20. #define REG_IRQENABLE 0x02C
  21. #define REG_IRQCLR 0x030
  22. #define REG_IRQWAKEUP 0x034
  23. #define REG_CTRL 0x040
  24. #define REG_ADCFSM 0x044
  25. #define REG_CLKDIV 0x04C
  26. #define REG_SE 0x054
  27. #define REG_IDLECONFIG 0x058
  28. #define REG_CHARGECONFIG 0x05C
  29. #define REG_CHARGEDELAY 0x060
  30. #define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8))
  31. #define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8))
  32. #define REG_FIFO0CNT 0xE4
  33. #define REG_FIFO0THR 0xE8
  34. #define REG_FIFO1CNT 0xF0
  35. #define REG_FIFO1THR 0xF4
  36. #define REG_FIFO0 0x100
  37. #define REG_FIFO1 0x200
  38. /* Register Bitfields */
  39. /* IRQ wakeup enable */
  40. #define IRQWKUP_ENB BIT(0)
  41. /* Step Enable */
  42. #define STEPENB_MASK (0x1FFFF << 0)
  43. #define STEPENB(val) ((val) << 0)
  44. /* IRQ enable */
  45. #define IRQENB_HW_PEN BIT(0)
  46. #define IRQENB_FIFO0THRES BIT(2)
  47. #define IRQENB_FIFO1THRES BIT(5)
  48. #define IRQENB_PENUP BIT(9)
  49. /* Step Configuration */
  50. #define STEPCONFIG_MODE_MASK (3 << 0)
  51. #define STEPCONFIG_MODE(val) ((val) << 0)
  52. #define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
  53. #define STEPCONFIG_AVG_MASK (7 << 2)
  54. #define STEPCONFIG_AVG(val) ((val) << 2)
  55. #define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
  56. #define STEPCONFIG_XPP BIT(5)
  57. #define STEPCONFIG_XNN BIT(6)
  58. #define STEPCONFIG_YPP BIT(7)
  59. #define STEPCONFIG_YNN BIT(8)
  60. #define STEPCONFIG_XNP BIT(9)
  61. #define STEPCONFIG_YPN BIT(10)
  62. #define STEPCONFIG_INM_MASK (0xF << 15)
  63. #define STEPCONFIG_INM(val) ((val) << 15)
  64. #define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
  65. #define STEPCONFIG_INP_MASK (0xF << 19)
  66. #define STEPCONFIG_INP(val) ((val) << 19)
  67. #define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
  68. #define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
  69. #define STEPCONFIG_FIFO1 BIT(26)
  70. /* Delay register */
  71. #define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
  72. #define STEPDELAY_OPEN(val) ((val) << 0)
  73. #define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
  74. #define STEPDELAY_SAMPLE_MASK (0xFF << 24)
  75. #define STEPDELAY_SAMPLE(val) ((val) << 24)
  76. #define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
  77. /* Charge Config */
  78. #define STEPCHARGE_RFP_MASK (7 << 12)
  79. #define STEPCHARGE_RFP(val) ((val) << 12)
  80. #define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
  81. #define STEPCHARGE_INM_MASK (0xF << 15)
  82. #define STEPCHARGE_INM(val) ((val) << 15)
  83. #define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
  84. #define STEPCHARGE_INP_MASK (0xF << 19)
  85. #define STEPCHARGE_INP(val) ((val) << 19)
  86. #define STEPCHARGE_RFM_MASK (3 << 23)
  87. #define STEPCHARGE_RFM(val) ((val) << 23)
  88. #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
  89. /* Charge delay */
  90. #define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
  91. #define CHARGEDLY_OPEN(val) ((val) << 0)
  92. #define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(1)
  93. /* Control register */
  94. #define CNTRLREG_TSCSSENB BIT(0)
  95. #define CNTRLREG_STEPID BIT(1)
  96. #define CNTRLREG_STEPCONFIGWRT BIT(2)
  97. #define CNTRLREG_POWERDOWN BIT(4)
  98. #define CNTRLREG_AFE_CTRL_MASK (3 << 5)
  99. #define CNTRLREG_AFE_CTRL(val) ((val) << 5)
  100. #define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
  101. #define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
  102. #define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
  103. #define CNTRLREG_TSCENB BIT(7)
  104. #define ADC_CLK 3000000
  105. #define MAX_CLK_DIV 7
  106. #define TOTAL_STEPS 16
  107. #define TOTAL_CHANNELS 8
  108. #define TSCADC_CELLS 2
  109. struct ti_tscadc_dev {
  110. struct device *dev;
  111. struct regmap *regmap_tscadc;
  112. void __iomem *tscadc_base;
  113. int irq;
  114. int used_cells; /* 1-2 */
  115. int tsc_cell; /* -1 if not used */
  116. int adc_cell; /* -1 if not used */
  117. struct mfd_cell cells[TSCADC_CELLS];
  118. u32 reg_se_cache;
  119. spinlock_t reg_lock;
  120. /* tsc device */
  121. struct titsc *tsc;
  122. /* adc device */
  123. struct adc_device *adc;
  124. };
  125. static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
  126. {
  127. struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
  128. return *tscadc_dev;
  129. }
  130. void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc);
  131. void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val);
  132. void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
  133. #endif