cnic.c 141 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "cnic.h"
  47. #include "cnic_defs.h"
  48. #define DRV_MODULE_NAME "cnic"
  49. static char version[] __devinitdata =
  50. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  51. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  52. "Chen (zongxi@broadcom.com");
  53. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  54. MODULE_LICENSE("GPL");
  55. MODULE_VERSION(CNIC_MODULE_VERSION);
  56. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  57. static LIST_HEAD(cnic_dev_list);
  58. static LIST_HEAD(cnic_udev_list);
  59. static DEFINE_RWLOCK(cnic_dev_lock);
  60. static DEFINE_MUTEX(cnic_lock);
  61. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  62. /* helper function, assuming cnic_lock is held */
  63. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  64. {
  65. return rcu_dereference_protected(cnic_ulp_tbl[type],
  66. lockdep_is_held(&cnic_lock));
  67. }
  68. static int cnic_service_bnx2(void *, void *);
  69. static int cnic_service_bnx2x(void *, void *);
  70. static int cnic_ctl(void *, struct cnic_ctl_info *);
  71. static struct cnic_ops cnic_bnx2_ops = {
  72. .cnic_owner = THIS_MODULE,
  73. .cnic_handler = cnic_service_bnx2,
  74. .cnic_ctl = cnic_ctl,
  75. };
  76. static struct cnic_ops cnic_bnx2x_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2x,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct workqueue_struct *cnic_wq;
  82. static void cnic_shutdown_rings(struct cnic_dev *);
  83. static void cnic_init_rings(struct cnic_dev *);
  84. static int cnic_cm_set_pg(struct cnic_sock *);
  85. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  86. {
  87. struct cnic_uio_dev *udev = uinfo->priv;
  88. struct cnic_dev *dev;
  89. if (!capable(CAP_NET_ADMIN))
  90. return -EPERM;
  91. if (udev->uio_dev != -1)
  92. return -EBUSY;
  93. rtnl_lock();
  94. dev = udev->dev;
  95. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  96. rtnl_unlock();
  97. return -ENODEV;
  98. }
  99. udev->uio_dev = iminor(inode);
  100. cnic_shutdown_rings(dev);
  101. cnic_init_rings(dev);
  102. rtnl_unlock();
  103. return 0;
  104. }
  105. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  106. {
  107. struct cnic_uio_dev *udev = uinfo->priv;
  108. udev->uio_dev = -1;
  109. return 0;
  110. }
  111. static inline void cnic_hold(struct cnic_dev *dev)
  112. {
  113. atomic_inc(&dev->ref_count);
  114. }
  115. static inline void cnic_put(struct cnic_dev *dev)
  116. {
  117. atomic_dec(&dev->ref_count);
  118. }
  119. static inline void csk_hold(struct cnic_sock *csk)
  120. {
  121. atomic_inc(&csk->ref_count);
  122. }
  123. static inline void csk_put(struct cnic_sock *csk)
  124. {
  125. atomic_dec(&csk->ref_count);
  126. }
  127. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  128. {
  129. struct cnic_dev *cdev;
  130. read_lock(&cnic_dev_lock);
  131. list_for_each_entry(cdev, &cnic_dev_list, list) {
  132. if (netdev == cdev->netdev) {
  133. cnic_hold(cdev);
  134. read_unlock(&cnic_dev_lock);
  135. return cdev;
  136. }
  137. }
  138. read_unlock(&cnic_dev_lock);
  139. return NULL;
  140. }
  141. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  142. {
  143. atomic_inc(&ulp_ops->ref_count);
  144. }
  145. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  146. {
  147. atomic_dec(&ulp_ops->ref_count);
  148. }
  149. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  150. {
  151. struct cnic_local *cp = dev->cnic_priv;
  152. struct cnic_eth_dev *ethdev = cp->ethdev;
  153. struct drv_ctl_info info;
  154. struct drv_ctl_io *io = &info.data.io;
  155. info.cmd = DRV_CTL_CTX_WR_CMD;
  156. io->cid_addr = cid_addr;
  157. io->offset = off;
  158. io->data = val;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_io *io = &info.data.io;
  167. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  168. io->offset = off;
  169. io->dma_addr = addr;
  170. ethdev->drv_ctl(dev->netdev, &info);
  171. }
  172. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  173. {
  174. struct cnic_local *cp = dev->cnic_priv;
  175. struct cnic_eth_dev *ethdev = cp->ethdev;
  176. struct drv_ctl_info info;
  177. struct drv_ctl_l2_ring *ring = &info.data.ring;
  178. if (start)
  179. info.cmd = DRV_CTL_START_L2_CMD;
  180. else
  181. info.cmd = DRV_CTL_STOP_L2_CMD;
  182. ring->cid = cid;
  183. ring->client_id = cl_id;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_WR_CMD;
  193. io->offset = off;
  194. io->data = val;
  195. ethdev->drv_ctl(dev->netdev, &info);
  196. }
  197. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  198. {
  199. struct cnic_local *cp = dev->cnic_priv;
  200. struct cnic_eth_dev *ethdev = cp->ethdev;
  201. struct drv_ctl_info info;
  202. struct drv_ctl_io *io = &info.data.io;
  203. info.cmd = DRV_CTL_IO_RD_CMD;
  204. io->offset = off;
  205. ethdev->drv_ctl(dev->netdev, &info);
  206. return io->data;
  207. }
  208. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  209. {
  210. struct cnic_local *cp = dev->cnic_priv;
  211. struct cnic_eth_dev *ethdev = cp->ethdev;
  212. struct drv_ctl_info info;
  213. if (reg)
  214. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  215. else
  216. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  217. info.data.ulp_type = ulp_type;
  218. ethdev->drv_ctl(dev->netdev, &info);
  219. }
  220. static int cnic_in_use(struct cnic_sock *csk)
  221. {
  222. return test_bit(SK_F_INUSE, &csk->flags);
  223. }
  224. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  225. {
  226. struct cnic_local *cp = dev->cnic_priv;
  227. struct cnic_eth_dev *ethdev = cp->ethdev;
  228. struct drv_ctl_info info;
  229. info.cmd = cmd;
  230. info.data.credit.credit_count = count;
  231. ethdev->drv_ctl(dev->netdev, &info);
  232. }
  233. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  234. {
  235. u32 i;
  236. for (i = 0; i < cp->max_cid_space; i++) {
  237. if (cp->ctx_tbl[i].cid == cid) {
  238. *l5_cid = i;
  239. return 0;
  240. }
  241. }
  242. return -EINVAL;
  243. }
  244. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  245. struct cnic_sock *csk)
  246. {
  247. struct iscsi_path path_req;
  248. char *buf = NULL;
  249. u16 len = 0;
  250. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  251. struct cnic_ulp_ops *ulp_ops;
  252. struct cnic_uio_dev *udev = cp->udev;
  253. int rc = 0, retry = 0;
  254. if (!udev || udev->uio_dev == -1)
  255. return -ENODEV;
  256. if (csk) {
  257. len = sizeof(path_req);
  258. buf = (char *) &path_req;
  259. memset(&path_req, 0, len);
  260. msg_type = ISCSI_KEVENT_PATH_REQ;
  261. path_req.handle = (u64) csk->l5_cid;
  262. if (test_bit(SK_F_IPV6, &csk->flags)) {
  263. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  264. sizeof(struct in6_addr));
  265. path_req.ip_addr_len = 16;
  266. } else {
  267. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  268. sizeof(struct in_addr));
  269. path_req.ip_addr_len = 4;
  270. }
  271. path_req.vlan_id = csk->vlan_id;
  272. path_req.pmtu = csk->mtu;
  273. }
  274. while (retry < 3) {
  275. rc = 0;
  276. rcu_read_lock();
  277. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  278. if (ulp_ops)
  279. rc = ulp_ops->iscsi_nl_send_msg(
  280. cp->ulp_handle[CNIC_ULP_ISCSI],
  281. msg_type, buf, len);
  282. rcu_read_unlock();
  283. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  284. break;
  285. msleep(100);
  286. retry++;
  287. }
  288. return rc;
  289. }
  290. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  291. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  292. char *buf, u16 len)
  293. {
  294. int rc = -EINVAL;
  295. switch (msg_type) {
  296. case ISCSI_UEVENT_PATH_UPDATE: {
  297. struct cnic_local *cp;
  298. u32 l5_cid;
  299. struct cnic_sock *csk;
  300. struct iscsi_path *path_resp;
  301. if (len < sizeof(*path_resp))
  302. break;
  303. path_resp = (struct iscsi_path *) buf;
  304. cp = dev->cnic_priv;
  305. l5_cid = (u32) path_resp->handle;
  306. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  307. break;
  308. rcu_read_lock();
  309. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  310. rc = -ENODEV;
  311. rcu_read_unlock();
  312. break;
  313. }
  314. csk = &cp->csk_tbl[l5_cid];
  315. csk_hold(csk);
  316. if (cnic_in_use(csk) &&
  317. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  318. memcpy(csk->ha, path_resp->mac_addr, 6);
  319. if (test_bit(SK_F_IPV6, &csk->flags))
  320. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  321. sizeof(struct in6_addr));
  322. else
  323. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  324. sizeof(struct in_addr));
  325. if (is_valid_ether_addr(csk->ha)) {
  326. cnic_cm_set_pg(csk);
  327. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  328. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  329. cnic_cm_upcall(cp, csk,
  330. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  331. clear_bit(SK_F_CONNECT_START, &csk->flags);
  332. }
  333. }
  334. csk_put(csk);
  335. rcu_read_unlock();
  336. rc = 0;
  337. }
  338. }
  339. return rc;
  340. }
  341. static int cnic_offld_prep(struct cnic_sock *csk)
  342. {
  343. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  344. return 0;
  345. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  346. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  347. return 0;
  348. }
  349. return 1;
  350. }
  351. static int cnic_close_prep(struct cnic_sock *csk)
  352. {
  353. clear_bit(SK_F_CONNECT_START, &csk->flags);
  354. smp_mb__after_clear_bit();
  355. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  356. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  357. msleep(1);
  358. return 1;
  359. }
  360. return 0;
  361. }
  362. static int cnic_abort_prep(struct cnic_sock *csk)
  363. {
  364. clear_bit(SK_F_CONNECT_START, &csk->flags);
  365. smp_mb__after_clear_bit();
  366. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  367. msleep(1);
  368. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  369. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  370. return 1;
  371. }
  372. return 0;
  373. }
  374. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  375. {
  376. struct cnic_dev *dev;
  377. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  378. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  379. return -EINVAL;
  380. }
  381. mutex_lock(&cnic_lock);
  382. if (cnic_ulp_tbl_prot(ulp_type)) {
  383. pr_err("%s: Type %d has already been registered\n",
  384. __func__, ulp_type);
  385. mutex_unlock(&cnic_lock);
  386. return -EBUSY;
  387. }
  388. read_lock(&cnic_dev_lock);
  389. list_for_each_entry(dev, &cnic_dev_list, list) {
  390. struct cnic_local *cp = dev->cnic_priv;
  391. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  392. }
  393. read_unlock(&cnic_dev_lock);
  394. atomic_set(&ulp_ops->ref_count, 0);
  395. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  396. mutex_unlock(&cnic_lock);
  397. /* Prevent race conditions with netdev_event */
  398. rtnl_lock();
  399. list_for_each_entry(dev, &cnic_dev_list, list) {
  400. struct cnic_local *cp = dev->cnic_priv;
  401. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  402. ulp_ops->cnic_init(dev);
  403. }
  404. rtnl_unlock();
  405. return 0;
  406. }
  407. int cnic_unregister_driver(int ulp_type)
  408. {
  409. struct cnic_dev *dev;
  410. struct cnic_ulp_ops *ulp_ops;
  411. int i = 0;
  412. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  413. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  414. return -EINVAL;
  415. }
  416. mutex_lock(&cnic_lock);
  417. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  418. if (!ulp_ops) {
  419. pr_err("%s: Type %d has not been registered\n",
  420. __func__, ulp_type);
  421. goto out_unlock;
  422. }
  423. read_lock(&cnic_dev_lock);
  424. list_for_each_entry(dev, &cnic_dev_list, list) {
  425. struct cnic_local *cp = dev->cnic_priv;
  426. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  427. pr_err("%s: Type %d still has devices registered\n",
  428. __func__, ulp_type);
  429. read_unlock(&cnic_dev_lock);
  430. goto out_unlock;
  431. }
  432. }
  433. read_unlock(&cnic_dev_lock);
  434. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  435. mutex_unlock(&cnic_lock);
  436. synchronize_rcu();
  437. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  438. msleep(100);
  439. i++;
  440. }
  441. if (atomic_read(&ulp_ops->ref_count) != 0)
  442. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  443. return 0;
  444. out_unlock:
  445. mutex_unlock(&cnic_lock);
  446. return -EINVAL;
  447. }
  448. static int cnic_start_hw(struct cnic_dev *);
  449. static void cnic_stop_hw(struct cnic_dev *);
  450. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  451. void *ulp_ctx)
  452. {
  453. struct cnic_local *cp = dev->cnic_priv;
  454. struct cnic_ulp_ops *ulp_ops;
  455. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  456. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  457. return -EINVAL;
  458. }
  459. mutex_lock(&cnic_lock);
  460. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  461. pr_err("%s: Driver with type %d has not been registered\n",
  462. __func__, ulp_type);
  463. mutex_unlock(&cnic_lock);
  464. return -EAGAIN;
  465. }
  466. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  467. pr_err("%s: Type %d has already been registered to this device\n",
  468. __func__, ulp_type);
  469. mutex_unlock(&cnic_lock);
  470. return -EBUSY;
  471. }
  472. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  473. cp->ulp_handle[ulp_type] = ulp_ctx;
  474. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  475. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  476. cnic_hold(dev);
  477. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  478. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  479. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  480. mutex_unlock(&cnic_lock);
  481. cnic_ulp_ctl(dev, ulp_type, true);
  482. return 0;
  483. }
  484. EXPORT_SYMBOL(cnic_register_driver);
  485. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  486. {
  487. struct cnic_local *cp = dev->cnic_priv;
  488. int i = 0;
  489. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  490. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  491. return -EINVAL;
  492. }
  493. mutex_lock(&cnic_lock);
  494. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  495. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  496. cnic_put(dev);
  497. } else {
  498. pr_err("%s: device not registered to this ulp type %d\n",
  499. __func__, ulp_type);
  500. mutex_unlock(&cnic_lock);
  501. return -EINVAL;
  502. }
  503. mutex_unlock(&cnic_lock);
  504. if (ulp_type == CNIC_ULP_ISCSI)
  505. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  506. synchronize_rcu();
  507. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  508. i < 20) {
  509. msleep(100);
  510. i++;
  511. }
  512. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  513. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  514. cnic_ulp_ctl(dev, ulp_type, false);
  515. return 0;
  516. }
  517. EXPORT_SYMBOL(cnic_unregister_driver);
  518. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  519. u32 next)
  520. {
  521. id_tbl->start = start_id;
  522. id_tbl->max = size;
  523. id_tbl->next = next;
  524. spin_lock_init(&id_tbl->lock);
  525. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  526. if (!id_tbl->table)
  527. return -ENOMEM;
  528. return 0;
  529. }
  530. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  531. {
  532. kfree(id_tbl->table);
  533. id_tbl->table = NULL;
  534. }
  535. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  536. {
  537. int ret = -1;
  538. id -= id_tbl->start;
  539. if (id >= id_tbl->max)
  540. return ret;
  541. spin_lock(&id_tbl->lock);
  542. if (!test_bit(id, id_tbl->table)) {
  543. set_bit(id, id_tbl->table);
  544. ret = 0;
  545. }
  546. spin_unlock(&id_tbl->lock);
  547. return ret;
  548. }
  549. /* Returns -1 if not successful */
  550. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  551. {
  552. u32 id;
  553. spin_lock(&id_tbl->lock);
  554. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  555. if (id >= id_tbl->max) {
  556. id = -1;
  557. if (id_tbl->next != 0) {
  558. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  559. if (id >= id_tbl->next)
  560. id = -1;
  561. }
  562. }
  563. if (id < id_tbl->max) {
  564. set_bit(id, id_tbl->table);
  565. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  566. id += id_tbl->start;
  567. }
  568. spin_unlock(&id_tbl->lock);
  569. return id;
  570. }
  571. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  572. {
  573. if (id == -1)
  574. return;
  575. id -= id_tbl->start;
  576. if (id >= id_tbl->max)
  577. return;
  578. clear_bit(id, id_tbl->table);
  579. }
  580. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  581. {
  582. int i;
  583. if (!dma->pg_arr)
  584. return;
  585. for (i = 0; i < dma->num_pages; i++) {
  586. if (dma->pg_arr[i]) {
  587. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  588. dma->pg_arr[i], dma->pg_map_arr[i]);
  589. dma->pg_arr[i] = NULL;
  590. }
  591. }
  592. if (dma->pgtbl) {
  593. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  594. dma->pgtbl, dma->pgtbl_map);
  595. dma->pgtbl = NULL;
  596. }
  597. kfree(dma->pg_arr);
  598. dma->pg_arr = NULL;
  599. dma->num_pages = 0;
  600. }
  601. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  602. {
  603. int i;
  604. __le32 *page_table = (__le32 *) dma->pgtbl;
  605. for (i = 0; i < dma->num_pages; i++) {
  606. /* Each entry needs to be in big endian format. */
  607. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  608. page_table++;
  609. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  610. page_table++;
  611. }
  612. }
  613. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  614. {
  615. int i;
  616. __le32 *page_table = (__le32 *) dma->pgtbl;
  617. for (i = 0; i < dma->num_pages; i++) {
  618. /* Each entry needs to be in little endian format. */
  619. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  620. page_table++;
  621. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  622. page_table++;
  623. }
  624. }
  625. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  626. int pages, int use_pg_tbl)
  627. {
  628. int i, size;
  629. struct cnic_local *cp = dev->cnic_priv;
  630. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  631. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  632. if (dma->pg_arr == NULL)
  633. return -ENOMEM;
  634. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  635. dma->num_pages = pages;
  636. for (i = 0; i < pages; i++) {
  637. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  638. BCM_PAGE_SIZE,
  639. &dma->pg_map_arr[i],
  640. GFP_ATOMIC);
  641. if (dma->pg_arr[i] == NULL)
  642. goto error;
  643. }
  644. if (!use_pg_tbl)
  645. return 0;
  646. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  647. ~(BCM_PAGE_SIZE - 1);
  648. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  649. &dma->pgtbl_map, GFP_ATOMIC);
  650. if (dma->pgtbl == NULL)
  651. goto error;
  652. cp->setup_pgtbl(dev, dma);
  653. return 0;
  654. error:
  655. cnic_free_dma(dev, dma);
  656. return -ENOMEM;
  657. }
  658. static void cnic_free_context(struct cnic_dev *dev)
  659. {
  660. struct cnic_local *cp = dev->cnic_priv;
  661. int i;
  662. for (i = 0; i < cp->ctx_blks; i++) {
  663. if (cp->ctx_arr[i].ctx) {
  664. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  665. cp->ctx_arr[i].ctx,
  666. cp->ctx_arr[i].mapping);
  667. cp->ctx_arr[i].ctx = NULL;
  668. }
  669. }
  670. }
  671. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  672. {
  673. uio_unregister_device(&udev->cnic_uinfo);
  674. if (udev->l2_buf) {
  675. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  676. udev->l2_buf, udev->l2_buf_map);
  677. udev->l2_buf = NULL;
  678. }
  679. if (udev->l2_ring) {
  680. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  681. udev->l2_ring, udev->l2_ring_map);
  682. udev->l2_ring = NULL;
  683. }
  684. pci_dev_put(udev->pdev);
  685. kfree(udev);
  686. }
  687. static void cnic_free_uio(struct cnic_uio_dev *udev)
  688. {
  689. if (!udev)
  690. return;
  691. write_lock(&cnic_dev_lock);
  692. list_del_init(&udev->list);
  693. write_unlock(&cnic_dev_lock);
  694. __cnic_free_uio(udev);
  695. }
  696. static void cnic_free_resc(struct cnic_dev *dev)
  697. {
  698. struct cnic_local *cp = dev->cnic_priv;
  699. struct cnic_uio_dev *udev = cp->udev;
  700. if (udev) {
  701. udev->dev = NULL;
  702. cp->udev = NULL;
  703. }
  704. cnic_free_context(dev);
  705. kfree(cp->ctx_arr);
  706. cp->ctx_arr = NULL;
  707. cp->ctx_blks = 0;
  708. cnic_free_dma(dev, &cp->gbl_buf_info);
  709. cnic_free_dma(dev, &cp->kwq_info);
  710. cnic_free_dma(dev, &cp->kwq_16_data_info);
  711. cnic_free_dma(dev, &cp->kcq2.dma);
  712. cnic_free_dma(dev, &cp->kcq1.dma);
  713. kfree(cp->iscsi_tbl);
  714. cp->iscsi_tbl = NULL;
  715. kfree(cp->ctx_tbl);
  716. cp->ctx_tbl = NULL;
  717. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  718. cnic_free_id_tbl(&cp->cid_tbl);
  719. }
  720. static int cnic_alloc_context(struct cnic_dev *dev)
  721. {
  722. struct cnic_local *cp = dev->cnic_priv;
  723. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  724. int i, k, arr_size;
  725. cp->ctx_blk_size = BCM_PAGE_SIZE;
  726. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  727. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  728. sizeof(struct cnic_ctx);
  729. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  730. if (cp->ctx_arr == NULL)
  731. return -ENOMEM;
  732. k = 0;
  733. for (i = 0; i < 2; i++) {
  734. u32 j, reg, off, lo, hi;
  735. if (i == 0)
  736. off = BNX2_PG_CTX_MAP;
  737. else
  738. off = BNX2_ISCSI_CTX_MAP;
  739. reg = cnic_reg_rd_ind(dev, off);
  740. lo = reg >> 16;
  741. hi = reg & 0xffff;
  742. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  743. cp->ctx_arr[k].cid = j;
  744. }
  745. cp->ctx_blks = k;
  746. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  747. cp->ctx_blks = 0;
  748. return -ENOMEM;
  749. }
  750. for (i = 0; i < cp->ctx_blks; i++) {
  751. cp->ctx_arr[i].ctx =
  752. dma_alloc_coherent(&dev->pcidev->dev,
  753. BCM_PAGE_SIZE,
  754. &cp->ctx_arr[i].mapping,
  755. GFP_KERNEL);
  756. if (cp->ctx_arr[i].ctx == NULL)
  757. return -ENOMEM;
  758. }
  759. }
  760. return 0;
  761. }
  762. static u16 cnic_bnx2_next_idx(u16 idx)
  763. {
  764. return idx + 1;
  765. }
  766. static u16 cnic_bnx2_hw_idx(u16 idx)
  767. {
  768. return idx;
  769. }
  770. static u16 cnic_bnx2x_next_idx(u16 idx)
  771. {
  772. idx++;
  773. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  774. idx++;
  775. return idx;
  776. }
  777. static u16 cnic_bnx2x_hw_idx(u16 idx)
  778. {
  779. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  780. idx++;
  781. return idx;
  782. }
  783. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  784. bool use_pg_tbl)
  785. {
  786. int err, i, use_page_tbl = 0;
  787. struct kcqe **kcq;
  788. if (use_pg_tbl)
  789. use_page_tbl = 1;
  790. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  791. if (err)
  792. return err;
  793. kcq = (struct kcqe **) info->dma.pg_arr;
  794. info->kcq = kcq;
  795. info->next_idx = cnic_bnx2_next_idx;
  796. info->hw_idx = cnic_bnx2_hw_idx;
  797. if (use_pg_tbl)
  798. return 0;
  799. info->next_idx = cnic_bnx2x_next_idx;
  800. info->hw_idx = cnic_bnx2x_hw_idx;
  801. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  802. struct bnx2x_bd_chain_next *next =
  803. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  804. int j = i + 1;
  805. if (j >= KCQ_PAGE_CNT)
  806. j = 0;
  807. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  808. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  809. }
  810. return 0;
  811. }
  812. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  813. {
  814. struct cnic_local *cp = dev->cnic_priv;
  815. struct cnic_uio_dev *udev;
  816. read_lock(&cnic_dev_lock);
  817. list_for_each_entry(udev, &cnic_udev_list, list) {
  818. if (udev->pdev == dev->pcidev) {
  819. udev->dev = dev;
  820. cp->udev = udev;
  821. read_unlock(&cnic_dev_lock);
  822. return 0;
  823. }
  824. }
  825. read_unlock(&cnic_dev_lock);
  826. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  827. if (!udev)
  828. return -ENOMEM;
  829. udev->uio_dev = -1;
  830. udev->dev = dev;
  831. udev->pdev = dev->pcidev;
  832. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  833. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  834. &udev->l2_ring_map,
  835. GFP_KERNEL | __GFP_COMP);
  836. if (!udev->l2_ring)
  837. goto err_udev;
  838. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  839. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  840. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  841. &udev->l2_buf_map,
  842. GFP_KERNEL | __GFP_COMP);
  843. if (!udev->l2_buf)
  844. goto err_dma;
  845. write_lock(&cnic_dev_lock);
  846. list_add(&udev->list, &cnic_udev_list);
  847. write_unlock(&cnic_dev_lock);
  848. pci_dev_get(udev->pdev);
  849. cp->udev = udev;
  850. return 0;
  851. err_dma:
  852. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  853. udev->l2_ring, udev->l2_ring_map);
  854. err_udev:
  855. kfree(udev);
  856. return -ENOMEM;
  857. }
  858. static int cnic_init_uio(struct cnic_dev *dev)
  859. {
  860. struct cnic_local *cp = dev->cnic_priv;
  861. struct cnic_uio_dev *udev = cp->udev;
  862. struct uio_info *uinfo;
  863. int ret = 0;
  864. if (!udev)
  865. return -ENOMEM;
  866. uinfo = &udev->cnic_uinfo;
  867. uinfo->mem[0].addr = dev->netdev->base_addr;
  868. uinfo->mem[0].internal_addr = dev->regview;
  869. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  870. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  871. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  872. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  873. PAGE_MASK;
  874. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  875. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  876. else
  877. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  878. uinfo->name = "bnx2_cnic";
  879. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  880. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  881. PAGE_MASK;
  882. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  883. uinfo->name = "bnx2x_cnic";
  884. }
  885. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  886. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  887. uinfo->mem[2].size = udev->l2_ring_size;
  888. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  889. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  890. uinfo->mem[3].size = udev->l2_buf_size;
  891. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  892. uinfo->version = CNIC_MODULE_VERSION;
  893. uinfo->irq = UIO_IRQ_CUSTOM;
  894. uinfo->open = cnic_uio_open;
  895. uinfo->release = cnic_uio_close;
  896. if (udev->uio_dev == -1) {
  897. if (!uinfo->priv) {
  898. uinfo->priv = udev;
  899. ret = uio_register_device(&udev->pdev->dev, uinfo);
  900. }
  901. } else {
  902. cnic_init_rings(dev);
  903. }
  904. return ret;
  905. }
  906. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  907. {
  908. struct cnic_local *cp = dev->cnic_priv;
  909. int ret;
  910. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  911. if (ret)
  912. goto error;
  913. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  914. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  915. if (ret)
  916. goto error;
  917. ret = cnic_alloc_context(dev);
  918. if (ret)
  919. goto error;
  920. ret = cnic_alloc_uio_rings(dev, 2);
  921. if (ret)
  922. goto error;
  923. ret = cnic_init_uio(dev);
  924. if (ret)
  925. goto error;
  926. return 0;
  927. error:
  928. cnic_free_resc(dev);
  929. return ret;
  930. }
  931. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  932. {
  933. struct cnic_local *cp = dev->cnic_priv;
  934. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  935. int total_mem, blks, i;
  936. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  937. blks = total_mem / ctx_blk_size;
  938. if (total_mem % ctx_blk_size)
  939. blks++;
  940. if (blks > cp->ethdev->ctx_tbl_len)
  941. return -ENOMEM;
  942. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  943. if (cp->ctx_arr == NULL)
  944. return -ENOMEM;
  945. cp->ctx_blks = blks;
  946. cp->ctx_blk_size = ctx_blk_size;
  947. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  948. cp->ctx_align = 0;
  949. else
  950. cp->ctx_align = ctx_blk_size;
  951. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  952. for (i = 0; i < blks; i++) {
  953. cp->ctx_arr[i].ctx =
  954. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  955. &cp->ctx_arr[i].mapping,
  956. GFP_KERNEL);
  957. if (cp->ctx_arr[i].ctx == NULL)
  958. return -ENOMEM;
  959. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  960. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  961. cnic_free_context(dev);
  962. cp->ctx_blk_size += cp->ctx_align;
  963. i = -1;
  964. continue;
  965. }
  966. }
  967. }
  968. return 0;
  969. }
  970. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  971. {
  972. struct cnic_local *cp = dev->cnic_priv;
  973. struct cnic_eth_dev *ethdev = cp->ethdev;
  974. u32 start_cid = ethdev->starting_cid;
  975. int i, j, n, ret, pages;
  976. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  977. cp->iro_arr = ethdev->iro_arr;
  978. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  979. cp->iscsi_start_cid = start_cid;
  980. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  981. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  982. cp->max_cid_space += dev->max_fcoe_conn;
  983. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  984. if (!cp->fcoe_init_cid)
  985. cp->fcoe_init_cid = 0x10;
  986. }
  987. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  988. GFP_KERNEL);
  989. if (!cp->iscsi_tbl)
  990. goto error;
  991. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  992. cp->max_cid_space, GFP_KERNEL);
  993. if (!cp->ctx_tbl)
  994. goto error;
  995. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  996. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  997. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  998. }
  999. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1000. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1001. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1002. PAGE_SIZE;
  1003. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1004. if (ret)
  1005. return -ENOMEM;
  1006. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1007. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1008. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1009. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1010. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1011. off;
  1012. if ((i % n) == (n - 1))
  1013. j++;
  1014. }
  1015. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1016. if (ret)
  1017. goto error;
  1018. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1019. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1020. if (ret)
  1021. goto error;
  1022. }
  1023. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1024. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1025. if (ret)
  1026. goto error;
  1027. ret = cnic_alloc_bnx2x_context(dev);
  1028. if (ret)
  1029. goto error;
  1030. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1031. cp->l2_rx_ring_size = 15;
  1032. ret = cnic_alloc_uio_rings(dev, 4);
  1033. if (ret)
  1034. goto error;
  1035. ret = cnic_init_uio(dev);
  1036. if (ret)
  1037. goto error;
  1038. return 0;
  1039. error:
  1040. cnic_free_resc(dev);
  1041. return -ENOMEM;
  1042. }
  1043. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1044. {
  1045. return cp->max_kwq_idx -
  1046. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1047. }
  1048. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1049. u32 num_wqes)
  1050. {
  1051. struct cnic_local *cp = dev->cnic_priv;
  1052. struct kwqe *prod_qe;
  1053. u16 prod, sw_prod, i;
  1054. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1055. return -EAGAIN; /* bnx2 is down */
  1056. spin_lock_bh(&cp->cnic_ulp_lock);
  1057. if (num_wqes > cnic_kwq_avail(cp) &&
  1058. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1059. spin_unlock_bh(&cp->cnic_ulp_lock);
  1060. return -EAGAIN;
  1061. }
  1062. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1063. prod = cp->kwq_prod_idx;
  1064. sw_prod = prod & MAX_KWQ_IDX;
  1065. for (i = 0; i < num_wqes; i++) {
  1066. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1067. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1068. prod++;
  1069. sw_prod = prod & MAX_KWQ_IDX;
  1070. }
  1071. cp->kwq_prod_idx = prod;
  1072. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1073. spin_unlock_bh(&cp->cnic_ulp_lock);
  1074. return 0;
  1075. }
  1076. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1077. union l5cm_specific_data *l5_data)
  1078. {
  1079. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1080. dma_addr_t map;
  1081. map = ctx->kwqe_data_mapping;
  1082. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1083. l5_data->phy_address.hi = (u64) map >> 32;
  1084. return ctx->kwqe_data;
  1085. }
  1086. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1087. u32 type, union l5cm_specific_data *l5_data)
  1088. {
  1089. struct cnic_local *cp = dev->cnic_priv;
  1090. struct l5cm_spe kwqe;
  1091. struct kwqe_16 *kwq[1];
  1092. u16 type_16;
  1093. int ret;
  1094. kwqe.hdr.conn_and_cmd_data =
  1095. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1096. BNX2X_HW_CID(cp, cid)));
  1097. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1098. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1099. SPE_HDR_FUNCTION_ID;
  1100. kwqe.hdr.type = cpu_to_le16(type_16);
  1101. kwqe.hdr.reserved1 = 0;
  1102. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1103. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1104. kwq[0] = (struct kwqe_16 *) &kwqe;
  1105. spin_lock_bh(&cp->cnic_ulp_lock);
  1106. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1107. spin_unlock_bh(&cp->cnic_ulp_lock);
  1108. if (ret == 1)
  1109. return 0;
  1110. return -EBUSY;
  1111. }
  1112. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1113. struct kcqe *cqes[], u32 num_cqes)
  1114. {
  1115. struct cnic_local *cp = dev->cnic_priv;
  1116. struct cnic_ulp_ops *ulp_ops;
  1117. rcu_read_lock();
  1118. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1119. if (likely(ulp_ops)) {
  1120. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1121. cqes, num_cqes);
  1122. }
  1123. rcu_read_unlock();
  1124. }
  1125. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1126. {
  1127. struct cnic_local *cp = dev->cnic_priv;
  1128. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1129. int hq_bds, pages;
  1130. u32 pfid = cp->pfid;
  1131. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1132. cp->num_ccells = req1->num_ccells_per_conn;
  1133. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1134. cp->num_iscsi_tasks;
  1135. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1136. BNX2X_ISCSI_R2TQE_SIZE;
  1137. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1138. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1139. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1140. cp->num_cqs = req1->num_cqs;
  1141. if (!dev->max_iscsi_conn)
  1142. return 0;
  1143. /* init Tstorm RAM */
  1144. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1145. req1->rq_num_wqes);
  1146. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1147. PAGE_SIZE);
  1148. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1149. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1150. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1151. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1152. req1->num_tasks_per_conn);
  1153. /* init Ustorm RAM */
  1154. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1155. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1156. req1->rq_buffer_size);
  1157. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1158. PAGE_SIZE);
  1159. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1160. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1161. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1162. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1163. req1->num_tasks_per_conn);
  1164. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1165. req1->rq_num_wqes);
  1166. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1167. req1->cq_num_wqes);
  1168. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1169. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1170. /* init Xstorm RAM */
  1171. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1172. PAGE_SIZE);
  1173. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1174. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1175. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1176. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1177. req1->num_tasks_per_conn);
  1178. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1179. hq_bds);
  1180. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1181. req1->num_tasks_per_conn);
  1182. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1183. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1184. /* init Cstorm RAM */
  1185. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1186. PAGE_SIZE);
  1187. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1188. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1189. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1190. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1191. req1->num_tasks_per_conn);
  1192. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1193. req1->cq_num_wqes);
  1194. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1195. hq_bds);
  1196. return 0;
  1197. }
  1198. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1199. {
  1200. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1201. struct cnic_local *cp = dev->cnic_priv;
  1202. u32 pfid = cp->pfid;
  1203. struct iscsi_kcqe kcqe;
  1204. struct kcqe *cqes[1];
  1205. memset(&kcqe, 0, sizeof(kcqe));
  1206. if (!dev->max_iscsi_conn) {
  1207. kcqe.completion_status =
  1208. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1209. goto done;
  1210. }
  1211. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1212. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1213. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1214. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1215. req2->error_bit_map[1]);
  1216. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1217. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1218. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1219. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1220. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1221. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1222. req2->error_bit_map[1]);
  1223. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1224. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1225. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1226. done:
  1227. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1228. cqes[0] = (struct kcqe *) &kcqe;
  1229. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1230. return 0;
  1231. }
  1232. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1233. {
  1234. struct cnic_local *cp = dev->cnic_priv;
  1235. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1236. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1237. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1238. cnic_free_dma(dev, &iscsi->hq_info);
  1239. cnic_free_dma(dev, &iscsi->r2tq_info);
  1240. cnic_free_dma(dev, &iscsi->task_array_info);
  1241. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1242. } else {
  1243. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1244. }
  1245. ctx->cid = 0;
  1246. }
  1247. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1248. {
  1249. u32 cid;
  1250. int ret, pages;
  1251. struct cnic_local *cp = dev->cnic_priv;
  1252. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1253. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1254. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1255. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1256. if (cid == -1) {
  1257. ret = -ENOMEM;
  1258. goto error;
  1259. }
  1260. ctx->cid = cid;
  1261. return 0;
  1262. }
  1263. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1264. if (cid == -1) {
  1265. ret = -ENOMEM;
  1266. goto error;
  1267. }
  1268. ctx->cid = cid;
  1269. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1270. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1271. if (ret)
  1272. goto error;
  1273. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1274. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1275. if (ret)
  1276. goto error;
  1277. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1278. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1279. if (ret)
  1280. goto error;
  1281. return 0;
  1282. error:
  1283. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1284. return ret;
  1285. }
  1286. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1287. struct regpair *ctx_addr)
  1288. {
  1289. struct cnic_local *cp = dev->cnic_priv;
  1290. struct cnic_eth_dev *ethdev = cp->ethdev;
  1291. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1292. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1293. unsigned long align_off = 0;
  1294. dma_addr_t ctx_map;
  1295. void *ctx;
  1296. if (cp->ctx_align) {
  1297. unsigned long mask = cp->ctx_align - 1;
  1298. if (cp->ctx_arr[blk].mapping & mask)
  1299. align_off = cp->ctx_align -
  1300. (cp->ctx_arr[blk].mapping & mask);
  1301. }
  1302. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1303. (off * BNX2X_CONTEXT_MEM_SIZE);
  1304. ctx = cp->ctx_arr[blk].ctx + align_off +
  1305. (off * BNX2X_CONTEXT_MEM_SIZE);
  1306. if (init)
  1307. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1308. ctx_addr->lo = ctx_map & 0xffffffff;
  1309. ctx_addr->hi = (u64) ctx_map >> 32;
  1310. return ctx;
  1311. }
  1312. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1313. u32 num)
  1314. {
  1315. struct cnic_local *cp = dev->cnic_priv;
  1316. struct iscsi_kwqe_conn_offload1 *req1 =
  1317. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1318. struct iscsi_kwqe_conn_offload2 *req2 =
  1319. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1320. struct iscsi_kwqe_conn_offload3 *req3;
  1321. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1322. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1323. u32 cid = ctx->cid;
  1324. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1325. struct iscsi_context *ictx;
  1326. struct regpair context_addr;
  1327. int i, j, n = 2, n_max;
  1328. u8 port = CNIC_PORT(cp);
  1329. ctx->ctx_flags = 0;
  1330. if (!req2->num_additional_wqes)
  1331. return -EINVAL;
  1332. n_max = req2->num_additional_wqes + 2;
  1333. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1334. if (ictx == NULL)
  1335. return -ENOMEM;
  1336. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1337. ictx->xstorm_ag_context.hq_prod = 1;
  1338. ictx->xstorm_st_context.iscsi.first_burst_length =
  1339. ISCSI_DEF_FIRST_BURST_LEN;
  1340. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1341. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1342. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1343. req1->sq_page_table_addr_lo;
  1344. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1345. req1->sq_page_table_addr_hi;
  1346. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1347. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1348. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1349. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1350. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1351. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1352. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1353. iscsi->hq_info.pgtbl[0];
  1354. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1355. iscsi->hq_info.pgtbl[1];
  1356. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1357. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1358. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1359. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1360. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1361. iscsi->r2tq_info.pgtbl[0];
  1362. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1363. iscsi->r2tq_info.pgtbl[1];
  1364. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1365. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1366. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1367. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1368. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1369. BNX2X_ISCSI_PBL_NOT_CACHED;
  1370. ictx->xstorm_st_context.iscsi.flags.flags |=
  1371. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1372. ictx->xstorm_st_context.iscsi.flags.flags |=
  1373. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1374. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1375. ETH_P_8021Q;
  1376. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1377. cp->port_mode == CHIP_2_PORT_MODE) {
  1378. port = 0;
  1379. }
  1380. ictx->xstorm_st_context.common.flags =
  1381. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1382. ictx->xstorm_st_context.common.flags =
  1383. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1384. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1385. /* TSTORM requires the base address of RQ DB & not PTE */
  1386. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1387. req2->rq_page_table_addr_lo & PAGE_MASK;
  1388. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1389. req2->rq_page_table_addr_hi;
  1390. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1391. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1392. ictx->tstorm_st_context.tcp.flags2 |=
  1393. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1394. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1395. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1396. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1397. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1398. req2->rq_page_table_addr_lo;
  1399. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1400. req2->rq_page_table_addr_hi;
  1401. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1402. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1403. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1404. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1405. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1406. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1407. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1408. iscsi->r2tq_info.pgtbl[0];
  1409. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1410. iscsi->r2tq_info.pgtbl[1];
  1411. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1412. req1->cq_page_table_addr_lo;
  1413. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1414. req1->cq_page_table_addr_hi;
  1415. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1416. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1417. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1418. ictx->ustorm_st_context.task_pbe_cache_index =
  1419. BNX2X_ISCSI_PBL_NOT_CACHED;
  1420. ictx->ustorm_st_context.task_pdu_cache_index =
  1421. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1422. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1423. if (j == 3) {
  1424. if (n >= n_max)
  1425. break;
  1426. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1427. j = 0;
  1428. }
  1429. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1430. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1431. req3->qp_first_pte[j].hi;
  1432. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1433. req3->qp_first_pte[j].lo;
  1434. }
  1435. ictx->ustorm_st_context.task_pbl_base.lo =
  1436. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1437. ictx->ustorm_st_context.task_pbl_base.hi =
  1438. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1439. ictx->ustorm_st_context.tce_phy_addr.lo =
  1440. iscsi->task_array_info.pgtbl[0];
  1441. ictx->ustorm_st_context.tce_phy_addr.hi =
  1442. iscsi->task_array_info.pgtbl[1];
  1443. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1444. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1445. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1446. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1447. ISCSI_DEF_MAX_BURST_LEN;
  1448. ictx->ustorm_st_context.negotiated_rx |=
  1449. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1450. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1451. ictx->cstorm_st_context.hq_pbl_base.lo =
  1452. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1453. ictx->cstorm_st_context.hq_pbl_base.hi =
  1454. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1455. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1456. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1457. ictx->cstorm_st_context.task_pbl_base.lo =
  1458. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1459. ictx->cstorm_st_context.task_pbl_base.hi =
  1460. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1461. /* CSTORM and USTORM initialization is different, CSTORM requires
  1462. * CQ DB base & not PTE addr */
  1463. ictx->cstorm_st_context.cq_db_base.lo =
  1464. req1->cq_page_table_addr_lo & PAGE_MASK;
  1465. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1466. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1467. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1468. for (i = 0; i < cp->num_cqs; i++) {
  1469. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1470. ISCSI_INITIAL_SN;
  1471. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1472. ISCSI_INITIAL_SN;
  1473. }
  1474. ictx->xstorm_ag_context.cdu_reserved =
  1475. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1476. ISCSI_CONNECTION_TYPE);
  1477. ictx->ustorm_ag_context.cdu_usage =
  1478. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1479. ISCSI_CONNECTION_TYPE);
  1480. return 0;
  1481. }
  1482. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1483. u32 num, int *work)
  1484. {
  1485. struct iscsi_kwqe_conn_offload1 *req1;
  1486. struct iscsi_kwqe_conn_offload2 *req2;
  1487. struct cnic_local *cp = dev->cnic_priv;
  1488. struct cnic_context *ctx;
  1489. struct iscsi_kcqe kcqe;
  1490. struct kcqe *cqes[1];
  1491. u32 l5_cid;
  1492. int ret = 0;
  1493. if (num < 2) {
  1494. *work = num;
  1495. return -EINVAL;
  1496. }
  1497. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1498. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1499. if ((num - 2) < req2->num_additional_wqes) {
  1500. *work = num;
  1501. return -EINVAL;
  1502. }
  1503. *work = 2 + req2->num_additional_wqes;
  1504. l5_cid = req1->iscsi_conn_id;
  1505. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1506. return -EINVAL;
  1507. memset(&kcqe, 0, sizeof(kcqe));
  1508. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1509. kcqe.iscsi_conn_id = l5_cid;
  1510. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1511. ctx = &cp->ctx_tbl[l5_cid];
  1512. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1513. kcqe.completion_status =
  1514. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1515. goto done;
  1516. }
  1517. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1518. atomic_dec(&cp->iscsi_conn);
  1519. goto done;
  1520. }
  1521. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1522. if (ret) {
  1523. atomic_dec(&cp->iscsi_conn);
  1524. ret = 0;
  1525. goto done;
  1526. }
  1527. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1528. if (ret < 0) {
  1529. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1530. atomic_dec(&cp->iscsi_conn);
  1531. goto done;
  1532. }
  1533. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1534. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1535. done:
  1536. cqes[0] = (struct kcqe *) &kcqe;
  1537. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1538. return ret;
  1539. }
  1540. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1541. {
  1542. struct cnic_local *cp = dev->cnic_priv;
  1543. struct iscsi_kwqe_conn_update *req =
  1544. (struct iscsi_kwqe_conn_update *) kwqe;
  1545. void *data;
  1546. union l5cm_specific_data l5_data;
  1547. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1548. int ret;
  1549. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1550. return -EINVAL;
  1551. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1552. if (!data)
  1553. return -ENOMEM;
  1554. memcpy(data, kwqe, sizeof(struct kwqe));
  1555. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1556. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1557. return ret;
  1558. }
  1559. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1560. {
  1561. struct cnic_local *cp = dev->cnic_priv;
  1562. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1563. union l5cm_specific_data l5_data;
  1564. int ret;
  1565. u32 hw_cid;
  1566. init_waitqueue_head(&ctx->waitq);
  1567. ctx->wait_cond = 0;
  1568. memset(&l5_data, 0, sizeof(l5_data));
  1569. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1570. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1571. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1572. if (ret == 0) {
  1573. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1574. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1575. return -EBUSY;
  1576. }
  1577. return 0;
  1578. }
  1579. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1580. {
  1581. struct cnic_local *cp = dev->cnic_priv;
  1582. struct iscsi_kwqe_conn_destroy *req =
  1583. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1584. u32 l5_cid = req->reserved0;
  1585. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1586. int ret = 0;
  1587. struct iscsi_kcqe kcqe;
  1588. struct kcqe *cqes[1];
  1589. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1590. goto skip_cfc_delete;
  1591. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1592. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1593. if (delta > (2 * HZ))
  1594. delta = 0;
  1595. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1596. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1597. goto destroy_reply;
  1598. }
  1599. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1600. skip_cfc_delete:
  1601. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1602. if (!ret) {
  1603. atomic_dec(&cp->iscsi_conn);
  1604. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1605. }
  1606. destroy_reply:
  1607. memset(&kcqe, 0, sizeof(kcqe));
  1608. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1609. kcqe.iscsi_conn_id = l5_cid;
  1610. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1611. kcqe.iscsi_conn_context_id = req->context_id;
  1612. cqes[0] = (struct kcqe *) &kcqe;
  1613. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1614. return ret;
  1615. }
  1616. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1617. struct l4_kwq_connect_req1 *kwqe1,
  1618. struct l4_kwq_connect_req3 *kwqe3,
  1619. struct l5cm_active_conn_buffer *conn_buf)
  1620. {
  1621. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1622. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1623. &conn_buf->xstorm_conn_buffer;
  1624. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1625. &conn_buf->tstorm_conn_buffer;
  1626. struct regpair context_addr;
  1627. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1628. struct in6_addr src_ip, dst_ip;
  1629. int i;
  1630. u32 *addrp;
  1631. addrp = (u32 *) &conn_addr->local_ip_addr;
  1632. for (i = 0; i < 4; i++, addrp++)
  1633. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1634. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1635. for (i = 0; i < 4; i++, addrp++)
  1636. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1637. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1638. xstorm_buf->context_addr.hi = context_addr.hi;
  1639. xstorm_buf->context_addr.lo = context_addr.lo;
  1640. xstorm_buf->mss = 0xffff;
  1641. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1642. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1643. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1644. xstorm_buf->pseudo_header_checksum =
  1645. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1646. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1647. tstorm_buf->params |=
  1648. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1649. if (kwqe3->ka_timeout) {
  1650. tstorm_buf->ka_enable = 1;
  1651. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1652. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1653. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1654. }
  1655. tstorm_buf->max_rt_time = 0xffffffff;
  1656. }
  1657. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1658. {
  1659. struct cnic_local *cp = dev->cnic_priv;
  1660. u32 pfid = cp->pfid;
  1661. u8 *mac = dev->mac_addr;
  1662. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1663. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1664. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1665. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1666. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1667. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1668. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1669. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1670. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1671. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1672. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1673. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1674. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1675. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1676. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1677. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1678. mac[4]);
  1679. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1680. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1681. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1682. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1683. mac[2]);
  1684. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1685. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1686. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1687. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1688. mac[0]);
  1689. }
  1690. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1691. {
  1692. struct cnic_local *cp = dev->cnic_priv;
  1693. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1694. u16 tstorm_flags = 0;
  1695. if (tcp_ts) {
  1696. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1697. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1698. }
  1699. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1700. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1701. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1702. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1703. }
  1704. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1705. u32 num, int *work)
  1706. {
  1707. struct cnic_local *cp = dev->cnic_priv;
  1708. struct l4_kwq_connect_req1 *kwqe1 =
  1709. (struct l4_kwq_connect_req1 *) wqes[0];
  1710. struct l4_kwq_connect_req3 *kwqe3;
  1711. struct l5cm_active_conn_buffer *conn_buf;
  1712. struct l5cm_conn_addr_params *conn_addr;
  1713. union l5cm_specific_data l5_data;
  1714. u32 l5_cid = kwqe1->pg_cid;
  1715. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1716. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1717. int ret;
  1718. if (num < 2) {
  1719. *work = num;
  1720. return -EINVAL;
  1721. }
  1722. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1723. *work = 3;
  1724. else
  1725. *work = 2;
  1726. if (num < *work) {
  1727. *work = num;
  1728. return -EINVAL;
  1729. }
  1730. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1731. netdev_err(dev->netdev, "conn_buf size too big\n");
  1732. return -ENOMEM;
  1733. }
  1734. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1735. if (!conn_buf)
  1736. return -ENOMEM;
  1737. memset(conn_buf, 0, sizeof(*conn_buf));
  1738. conn_addr = &conn_buf->conn_addr_buf;
  1739. conn_addr->remote_addr_0 = csk->ha[0];
  1740. conn_addr->remote_addr_1 = csk->ha[1];
  1741. conn_addr->remote_addr_2 = csk->ha[2];
  1742. conn_addr->remote_addr_3 = csk->ha[3];
  1743. conn_addr->remote_addr_4 = csk->ha[4];
  1744. conn_addr->remote_addr_5 = csk->ha[5];
  1745. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1746. struct l4_kwq_connect_req2 *kwqe2 =
  1747. (struct l4_kwq_connect_req2 *) wqes[1];
  1748. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1749. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1750. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1751. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1752. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1753. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1754. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1755. }
  1756. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1757. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1758. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1759. conn_addr->local_tcp_port = kwqe1->src_port;
  1760. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1761. conn_addr->pmtu = kwqe3->pmtu;
  1762. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1763. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1764. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1765. cnic_bnx2x_set_tcp_timestamp(dev,
  1766. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1767. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1768. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1769. if (!ret)
  1770. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1771. return ret;
  1772. }
  1773. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1774. {
  1775. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1776. union l5cm_specific_data l5_data;
  1777. int ret;
  1778. memset(&l5_data, 0, sizeof(l5_data));
  1779. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1780. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1781. return ret;
  1782. }
  1783. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1784. {
  1785. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1786. union l5cm_specific_data l5_data;
  1787. int ret;
  1788. memset(&l5_data, 0, sizeof(l5_data));
  1789. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1790. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1791. return ret;
  1792. }
  1793. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1794. {
  1795. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1796. struct l4_kcq kcqe;
  1797. struct kcqe *cqes[1];
  1798. memset(&kcqe, 0, sizeof(kcqe));
  1799. kcqe.pg_host_opaque = req->host_opaque;
  1800. kcqe.pg_cid = req->host_opaque;
  1801. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1802. cqes[0] = (struct kcqe *) &kcqe;
  1803. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1804. return 0;
  1805. }
  1806. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1807. {
  1808. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1809. struct l4_kcq kcqe;
  1810. struct kcqe *cqes[1];
  1811. memset(&kcqe, 0, sizeof(kcqe));
  1812. kcqe.pg_host_opaque = req->pg_host_opaque;
  1813. kcqe.pg_cid = req->pg_cid;
  1814. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1815. cqes[0] = (struct kcqe *) &kcqe;
  1816. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1817. return 0;
  1818. }
  1819. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1820. {
  1821. struct fcoe_kwqe_stat *req;
  1822. struct fcoe_stat_ramrod_params *fcoe_stat;
  1823. union l5cm_specific_data l5_data;
  1824. struct cnic_local *cp = dev->cnic_priv;
  1825. int ret;
  1826. u32 cid;
  1827. req = (struct fcoe_kwqe_stat *) kwqe;
  1828. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1829. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1830. if (!fcoe_stat)
  1831. return -ENOMEM;
  1832. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1833. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1834. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1835. FCOE_CONNECTION_TYPE, &l5_data);
  1836. return ret;
  1837. }
  1838. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1839. u32 num, int *work)
  1840. {
  1841. int ret;
  1842. struct cnic_local *cp = dev->cnic_priv;
  1843. u32 cid;
  1844. struct fcoe_init_ramrod_params *fcoe_init;
  1845. struct fcoe_kwqe_init1 *req1;
  1846. struct fcoe_kwqe_init2 *req2;
  1847. struct fcoe_kwqe_init3 *req3;
  1848. union l5cm_specific_data l5_data;
  1849. if (num < 3) {
  1850. *work = num;
  1851. return -EINVAL;
  1852. }
  1853. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1854. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1855. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1856. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1857. *work = 1;
  1858. return -EINVAL;
  1859. }
  1860. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1861. *work = 2;
  1862. return -EINVAL;
  1863. }
  1864. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1865. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1866. return -ENOMEM;
  1867. }
  1868. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1869. if (!fcoe_init)
  1870. return -ENOMEM;
  1871. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1872. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1873. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1874. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1875. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1876. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1877. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1878. fcoe_init->sb_num = cp->status_blk_num;
  1879. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1880. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1881. cp->kcq2.sw_prod_idx = 0;
  1882. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1883. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1884. FCOE_CONNECTION_TYPE, &l5_data);
  1885. *work = 3;
  1886. return ret;
  1887. }
  1888. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1889. u32 num, int *work)
  1890. {
  1891. int ret = 0;
  1892. u32 cid = -1, l5_cid;
  1893. struct cnic_local *cp = dev->cnic_priv;
  1894. struct fcoe_kwqe_conn_offload1 *req1;
  1895. struct fcoe_kwqe_conn_offload2 *req2;
  1896. struct fcoe_kwqe_conn_offload3 *req3;
  1897. struct fcoe_kwqe_conn_offload4 *req4;
  1898. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1899. struct cnic_context *ctx;
  1900. struct fcoe_context *fctx;
  1901. struct regpair ctx_addr;
  1902. union l5cm_specific_data l5_data;
  1903. struct fcoe_kcqe kcqe;
  1904. struct kcqe *cqes[1];
  1905. if (num < 4) {
  1906. *work = num;
  1907. return -EINVAL;
  1908. }
  1909. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1910. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1911. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1912. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1913. *work = 4;
  1914. l5_cid = req1->fcoe_conn_id;
  1915. if (l5_cid >= dev->max_fcoe_conn)
  1916. goto err_reply;
  1917. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1918. ctx = &cp->ctx_tbl[l5_cid];
  1919. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1920. goto err_reply;
  1921. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1922. if (ret) {
  1923. ret = 0;
  1924. goto err_reply;
  1925. }
  1926. cid = ctx->cid;
  1927. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1928. if (fctx) {
  1929. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1930. u32 val;
  1931. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1932. FCOE_CONNECTION_TYPE);
  1933. fctx->xstorm_ag_context.cdu_reserved = val;
  1934. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1935. FCOE_CONNECTION_TYPE);
  1936. fctx->ustorm_ag_context.cdu_usage = val;
  1937. }
  1938. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1939. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1940. goto err_reply;
  1941. }
  1942. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1943. if (!fcoe_offload)
  1944. goto err_reply;
  1945. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1946. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1947. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1948. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1949. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1950. cid = BNX2X_HW_CID(cp, cid);
  1951. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1952. FCOE_CONNECTION_TYPE, &l5_data);
  1953. if (!ret)
  1954. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1955. return ret;
  1956. err_reply:
  1957. if (cid != -1)
  1958. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1959. memset(&kcqe, 0, sizeof(kcqe));
  1960. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1961. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1962. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1963. cqes[0] = (struct kcqe *) &kcqe;
  1964. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1965. return ret;
  1966. }
  1967. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1968. {
  1969. struct fcoe_kwqe_conn_enable_disable *req;
  1970. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1971. union l5cm_specific_data l5_data;
  1972. int ret;
  1973. u32 cid, l5_cid;
  1974. struct cnic_local *cp = dev->cnic_priv;
  1975. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1976. cid = req->context_id;
  1977. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1978. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1979. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1980. return -ENOMEM;
  1981. }
  1982. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1983. if (!fcoe_enable)
  1984. return -ENOMEM;
  1985. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1986. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1987. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1988. FCOE_CONNECTION_TYPE, &l5_data);
  1989. return ret;
  1990. }
  1991. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1992. {
  1993. struct fcoe_kwqe_conn_enable_disable *req;
  1994. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1995. union l5cm_specific_data l5_data;
  1996. int ret;
  1997. u32 cid, l5_cid;
  1998. struct cnic_local *cp = dev->cnic_priv;
  1999. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2000. cid = req->context_id;
  2001. l5_cid = req->conn_id;
  2002. if (l5_cid >= dev->max_fcoe_conn)
  2003. return -EINVAL;
  2004. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2005. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2006. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2007. return -ENOMEM;
  2008. }
  2009. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2010. if (!fcoe_disable)
  2011. return -ENOMEM;
  2012. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2013. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2014. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2015. FCOE_CONNECTION_TYPE, &l5_data);
  2016. return ret;
  2017. }
  2018. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2019. {
  2020. struct fcoe_kwqe_conn_destroy *req;
  2021. union l5cm_specific_data l5_data;
  2022. int ret;
  2023. u32 cid, l5_cid;
  2024. struct cnic_local *cp = dev->cnic_priv;
  2025. struct cnic_context *ctx;
  2026. struct fcoe_kcqe kcqe;
  2027. struct kcqe *cqes[1];
  2028. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2029. cid = req->context_id;
  2030. l5_cid = req->conn_id;
  2031. if (l5_cid >= dev->max_fcoe_conn)
  2032. return -EINVAL;
  2033. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2034. ctx = &cp->ctx_tbl[l5_cid];
  2035. init_waitqueue_head(&ctx->waitq);
  2036. ctx->wait_cond = 0;
  2037. memset(&kcqe, 0, sizeof(kcqe));
  2038. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2039. memset(&l5_data, 0, sizeof(l5_data));
  2040. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2041. FCOE_CONNECTION_TYPE, &l5_data);
  2042. if (ret == 0) {
  2043. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2044. if (ctx->wait_cond)
  2045. kcqe.completion_status = 0;
  2046. }
  2047. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2048. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2049. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2050. kcqe.fcoe_conn_id = req->conn_id;
  2051. kcqe.fcoe_conn_context_id = cid;
  2052. cqes[0] = (struct kcqe *) &kcqe;
  2053. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2054. return ret;
  2055. }
  2056. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2057. {
  2058. struct cnic_local *cp = dev->cnic_priv;
  2059. u32 i;
  2060. for (i = start_cid; i < cp->max_cid_space; i++) {
  2061. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2062. int j;
  2063. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2064. msleep(10);
  2065. for (j = 0; j < 5; j++) {
  2066. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2067. break;
  2068. msleep(20);
  2069. }
  2070. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2071. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2072. ctx->cid);
  2073. }
  2074. }
  2075. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2076. {
  2077. struct fcoe_kwqe_destroy *req;
  2078. union l5cm_specific_data l5_data;
  2079. struct cnic_local *cp = dev->cnic_priv;
  2080. int ret;
  2081. u32 cid;
  2082. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2083. req = (struct fcoe_kwqe_destroy *) kwqe;
  2084. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2085. memset(&l5_data, 0, sizeof(l5_data));
  2086. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2087. FCOE_CONNECTION_TYPE, &l5_data);
  2088. return ret;
  2089. }
  2090. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2091. struct kwqe *wqes[], u32 num_wqes)
  2092. {
  2093. int i, work, ret;
  2094. u32 opcode;
  2095. struct kwqe *kwqe;
  2096. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2097. return -EAGAIN; /* bnx2 is down */
  2098. for (i = 0; i < num_wqes; ) {
  2099. kwqe = wqes[i];
  2100. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2101. work = 1;
  2102. switch (opcode) {
  2103. case ISCSI_KWQE_OPCODE_INIT1:
  2104. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2105. break;
  2106. case ISCSI_KWQE_OPCODE_INIT2:
  2107. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2108. break;
  2109. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2110. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2111. num_wqes - i, &work);
  2112. break;
  2113. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2114. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2115. break;
  2116. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2117. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2118. break;
  2119. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2120. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2121. &work);
  2122. break;
  2123. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2124. ret = cnic_bnx2x_close(dev, kwqe);
  2125. break;
  2126. case L4_KWQE_OPCODE_VALUE_RESET:
  2127. ret = cnic_bnx2x_reset(dev, kwqe);
  2128. break;
  2129. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2130. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2131. break;
  2132. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2133. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2134. break;
  2135. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2136. ret = 0;
  2137. break;
  2138. default:
  2139. ret = 0;
  2140. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2141. opcode);
  2142. break;
  2143. }
  2144. if (ret < 0)
  2145. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2146. opcode);
  2147. i += work;
  2148. }
  2149. return 0;
  2150. }
  2151. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2152. struct kwqe *wqes[], u32 num_wqes)
  2153. {
  2154. struct cnic_local *cp = dev->cnic_priv;
  2155. int i, work, ret;
  2156. u32 opcode;
  2157. struct kwqe *kwqe;
  2158. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2159. return -EAGAIN; /* bnx2 is down */
  2160. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2161. return -EINVAL;
  2162. for (i = 0; i < num_wqes; ) {
  2163. kwqe = wqes[i];
  2164. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2165. work = 1;
  2166. switch (opcode) {
  2167. case FCOE_KWQE_OPCODE_INIT1:
  2168. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2169. num_wqes - i, &work);
  2170. break;
  2171. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2172. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2173. num_wqes - i, &work);
  2174. break;
  2175. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2176. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2177. break;
  2178. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2179. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2180. break;
  2181. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2182. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2183. break;
  2184. case FCOE_KWQE_OPCODE_DESTROY:
  2185. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2186. break;
  2187. case FCOE_KWQE_OPCODE_STAT:
  2188. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2189. break;
  2190. default:
  2191. ret = 0;
  2192. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2193. opcode);
  2194. break;
  2195. }
  2196. if (ret < 0)
  2197. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2198. opcode);
  2199. i += work;
  2200. }
  2201. return 0;
  2202. }
  2203. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2204. u32 num_wqes)
  2205. {
  2206. int ret = -EINVAL;
  2207. u32 layer_code;
  2208. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2209. return -EAGAIN; /* bnx2x is down */
  2210. if (!num_wqes)
  2211. return 0;
  2212. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2213. switch (layer_code) {
  2214. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2215. case KWQE_FLAGS_LAYER_MASK_L4:
  2216. case KWQE_FLAGS_LAYER_MASK_L2:
  2217. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2218. break;
  2219. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2220. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2221. break;
  2222. }
  2223. return ret;
  2224. }
  2225. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2226. {
  2227. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2228. return KCQE_FLAGS_LAYER_MASK_L4;
  2229. return opflag & KCQE_FLAGS_LAYER_MASK;
  2230. }
  2231. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2232. {
  2233. struct cnic_local *cp = dev->cnic_priv;
  2234. int i, j, comp = 0;
  2235. i = 0;
  2236. j = 1;
  2237. while (num_cqes) {
  2238. struct cnic_ulp_ops *ulp_ops;
  2239. int ulp_type;
  2240. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2241. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2242. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2243. comp++;
  2244. while (j < num_cqes) {
  2245. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2246. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2247. break;
  2248. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2249. comp++;
  2250. j++;
  2251. }
  2252. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2253. ulp_type = CNIC_ULP_RDMA;
  2254. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2255. ulp_type = CNIC_ULP_ISCSI;
  2256. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2257. ulp_type = CNIC_ULP_FCOE;
  2258. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2259. ulp_type = CNIC_ULP_L4;
  2260. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2261. goto end;
  2262. else {
  2263. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2264. kcqe_op_flag);
  2265. goto end;
  2266. }
  2267. rcu_read_lock();
  2268. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2269. if (likely(ulp_ops)) {
  2270. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2271. cp->completed_kcq + i, j);
  2272. }
  2273. rcu_read_unlock();
  2274. end:
  2275. num_cqes -= j;
  2276. i += j;
  2277. j = 1;
  2278. }
  2279. if (unlikely(comp))
  2280. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2281. }
  2282. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2283. {
  2284. struct cnic_local *cp = dev->cnic_priv;
  2285. u16 i, ri, hw_prod, last;
  2286. struct kcqe *kcqe;
  2287. int kcqe_cnt = 0, last_cnt = 0;
  2288. i = ri = last = info->sw_prod_idx;
  2289. ri &= MAX_KCQ_IDX;
  2290. hw_prod = *info->hw_prod_idx_ptr;
  2291. hw_prod = info->hw_idx(hw_prod);
  2292. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2293. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2294. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2295. i = info->next_idx(i);
  2296. ri = i & MAX_KCQ_IDX;
  2297. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2298. last_cnt = kcqe_cnt;
  2299. last = i;
  2300. }
  2301. }
  2302. info->sw_prod_idx = last;
  2303. return last_cnt;
  2304. }
  2305. static int cnic_l2_completion(struct cnic_local *cp)
  2306. {
  2307. u16 hw_cons, sw_cons;
  2308. struct cnic_uio_dev *udev = cp->udev;
  2309. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2310. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2311. u32 cmd;
  2312. int comp = 0;
  2313. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2314. return 0;
  2315. hw_cons = *cp->rx_cons_ptr;
  2316. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2317. hw_cons++;
  2318. sw_cons = cp->rx_cons;
  2319. while (sw_cons != hw_cons) {
  2320. u8 cqe_fp_flags;
  2321. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2322. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2323. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2324. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2325. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2326. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2327. cmd == RAMROD_CMD_ID_ETH_HALT)
  2328. comp++;
  2329. }
  2330. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2331. }
  2332. return comp;
  2333. }
  2334. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2335. {
  2336. u16 rx_cons, tx_cons;
  2337. int comp = 0;
  2338. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2339. return;
  2340. rx_cons = *cp->rx_cons_ptr;
  2341. tx_cons = *cp->tx_cons_ptr;
  2342. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2343. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2344. comp = cnic_l2_completion(cp);
  2345. cp->tx_cons = tx_cons;
  2346. cp->rx_cons = rx_cons;
  2347. if (cp->udev)
  2348. uio_event_notify(&cp->udev->cnic_uinfo);
  2349. }
  2350. if (comp)
  2351. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2352. }
  2353. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2354. {
  2355. struct cnic_local *cp = dev->cnic_priv;
  2356. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2357. int kcqe_cnt;
  2358. /* status block index must be read before reading other fields */
  2359. rmb();
  2360. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2361. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2362. service_kcqes(dev, kcqe_cnt);
  2363. /* Tell compiler that status_blk fields can change. */
  2364. barrier();
  2365. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2366. /* status block index must be read first */
  2367. rmb();
  2368. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2369. }
  2370. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2371. cnic_chk_pkt_rings(cp);
  2372. return status_idx;
  2373. }
  2374. static int cnic_service_bnx2(void *data, void *status_blk)
  2375. {
  2376. struct cnic_dev *dev = data;
  2377. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2378. struct status_block *sblk = status_blk;
  2379. return sblk->status_idx;
  2380. }
  2381. return cnic_service_bnx2_queues(dev);
  2382. }
  2383. static void cnic_service_bnx2_msix(unsigned long data)
  2384. {
  2385. struct cnic_dev *dev = (struct cnic_dev *) data;
  2386. struct cnic_local *cp = dev->cnic_priv;
  2387. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2388. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2389. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2390. }
  2391. static void cnic_doirq(struct cnic_dev *dev)
  2392. {
  2393. struct cnic_local *cp = dev->cnic_priv;
  2394. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2395. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2396. prefetch(cp->status_blk.gen);
  2397. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2398. tasklet_schedule(&cp->cnic_irq_task);
  2399. }
  2400. }
  2401. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2402. {
  2403. struct cnic_dev *dev = dev_instance;
  2404. struct cnic_local *cp = dev->cnic_priv;
  2405. if (cp->ack_int)
  2406. cp->ack_int(dev);
  2407. cnic_doirq(dev);
  2408. return IRQ_HANDLED;
  2409. }
  2410. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2411. u16 index, u8 op, u8 update)
  2412. {
  2413. struct cnic_local *cp = dev->cnic_priv;
  2414. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2415. COMMAND_REG_INT_ACK);
  2416. struct igu_ack_register igu_ack;
  2417. igu_ack.status_block_index = index;
  2418. igu_ack.sb_id_and_flags =
  2419. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2420. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2421. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2422. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2423. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2424. }
  2425. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2426. u16 index, u8 op, u8 update)
  2427. {
  2428. struct igu_regular cmd_data;
  2429. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2430. cmd_data.sb_id_and_flags =
  2431. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2432. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2433. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2434. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2435. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2436. }
  2437. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2438. {
  2439. struct cnic_local *cp = dev->cnic_priv;
  2440. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2441. IGU_INT_DISABLE, 0);
  2442. }
  2443. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2444. {
  2445. struct cnic_local *cp = dev->cnic_priv;
  2446. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2447. IGU_INT_DISABLE, 0);
  2448. }
  2449. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2450. {
  2451. u32 last_status = *info->status_idx_ptr;
  2452. int kcqe_cnt;
  2453. /* status block index must be read before reading the KCQ */
  2454. rmb();
  2455. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2456. service_kcqes(dev, kcqe_cnt);
  2457. /* Tell compiler that sblk fields can change. */
  2458. barrier();
  2459. last_status = *info->status_idx_ptr;
  2460. /* status block index must be read before reading the KCQ */
  2461. rmb();
  2462. }
  2463. return last_status;
  2464. }
  2465. static void cnic_service_bnx2x_bh(unsigned long data)
  2466. {
  2467. struct cnic_dev *dev = (struct cnic_dev *) data;
  2468. struct cnic_local *cp = dev->cnic_priv;
  2469. u32 status_idx, new_status_idx;
  2470. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2471. return;
  2472. while (1) {
  2473. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2474. CNIC_WR16(dev, cp->kcq1.io_addr,
  2475. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2476. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2477. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2478. status_idx, IGU_INT_ENABLE, 1);
  2479. break;
  2480. }
  2481. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2482. if (new_status_idx != status_idx)
  2483. continue;
  2484. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2485. MAX_KCQ_IDX);
  2486. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2487. status_idx, IGU_INT_ENABLE, 1);
  2488. break;
  2489. }
  2490. }
  2491. static int cnic_service_bnx2x(void *data, void *status_blk)
  2492. {
  2493. struct cnic_dev *dev = data;
  2494. struct cnic_local *cp = dev->cnic_priv;
  2495. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2496. cnic_doirq(dev);
  2497. cnic_chk_pkt_rings(cp);
  2498. return 0;
  2499. }
  2500. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2501. {
  2502. struct cnic_ulp_ops *ulp_ops;
  2503. if (if_type == CNIC_ULP_ISCSI)
  2504. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2505. mutex_lock(&cnic_lock);
  2506. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2507. lockdep_is_held(&cnic_lock));
  2508. if (!ulp_ops) {
  2509. mutex_unlock(&cnic_lock);
  2510. return;
  2511. }
  2512. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2513. mutex_unlock(&cnic_lock);
  2514. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2515. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2516. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2517. }
  2518. static void cnic_ulp_stop(struct cnic_dev *dev)
  2519. {
  2520. struct cnic_local *cp = dev->cnic_priv;
  2521. int if_type;
  2522. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2523. cnic_ulp_stop_one(cp, if_type);
  2524. }
  2525. static void cnic_ulp_start(struct cnic_dev *dev)
  2526. {
  2527. struct cnic_local *cp = dev->cnic_priv;
  2528. int if_type;
  2529. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2530. struct cnic_ulp_ops *ulp_ops;
  2531. mutex_lock(&cnic_lock);
  2532. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2533. lockdep_is_held(&cnic_lock));
  2534. if (!ulp_ops || !ulp_ops->cnic_start) {
  2535. mutex_unlock(&cnic_lock);
  2536. continue;
  2537. }
  2538. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2539. mutex_unlock(&cnic_lock);
  2540. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2541. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2542. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2543. }
  2544. }
  2545. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2546. {
  2547. struct cnic_local *cp = dev->cnic_priv;
  2548. struct cnic_ulp_ops *ulp_ops;
  2549. int rc;
  2550. mutex_lock(&cnic_lock);
  2551. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2552. if (ulp_ops && ulp_ops->cnic_get_stats)
  2553. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2554. else
  2555. rc = -ENODEV;
  2556. mutex_unlock(&cnic_lock);
  2557. return rc;
  2558. }
  2559. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2560. {
  2561. struct cnic_dev *dev = data;
  2562. int ulp_type = CNIC_ULP_ISCSI;
  2563. switch (info->cmd) {
  2564. case CNIC_CTL_STOP_CMD:
  2565. cnic_hold(dev);
  2566. cnic_ulp_stop(dev);
  2567. cnic_stop_hw(dev);
  2568. cnic_put(dev);
  2569. break;
  2570. case CNIC_CTL_START_CMD:
  2571. cnic_hold(dev);
  2572. if (!cnic_start_hw(dev))
  2573. cnic_ulp_start(dev);
  2574. cnic_put(dev);
  2575. break;
  2576. case CNIC_CTL_STOP_ISCSI_CMD: {
  2577. struct cnic_local *cp = dev->cnic_priv;
  2578. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2579. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2580. break;
  2581. }
  2582. case CNIC_CTL_COMPLETION_CMD: {
  2583. struct cnic_ctl_completion *comp = &info->data.comp;
  2584. u32 cid = BNX2X_SW_CID(comp->cid);
  2585. u32 l5_cid;
  2586. struct cnic_local *cp = dev->cnic_priv;
  2587. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2588. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2589. if (unlikely(comp->error)) {
  2590. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2591. netdev_err(dev->netdev,
  2592. "CID %x CFC delete comp error %x\n",
  2593. cid, comp->error);
  2594. }
  2595. ctx->wait_cond = 1;
  2596. wake_up(&ctx->waitq);
  2597. }
  2598. break;
  2599. }
  2600. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2601. ulp_type = CNIC_ULP_FCOE;
  2602. /* fall through */
  2603. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2604. cnic_hold(dev);
  2605. cnic_copy_ulp_stats(dev, ulp_type);
  2606. cnic_put(dev);
  2607. break;
  2608. default:
  2609. return -EINVAL;
  2610. }
  2611. return 0;
  2612. }
  2613. static void cnic_ulp_init(struct cnic_dev *dev)
  2614. {
  2615. int i;
  2616. struct cnic_local *cp = dev->cnic_priv;
  2617. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2618. struct cnic_ulp_ops *ulp_ops;
  2619. mutex_lock(&cnic_lock);
  2620. ulp_ops = cnic_ulp_tbl_prot(i);
  2621. if (!ulp_ops || !ulp_ops->cnic_init) {
  2622. mutex_unlock(&cnic_lock);
  2623. continue;
  2624. }
  2625. ulp_get(ulp_ops);
  2626. mutex_unlock(&cnic_lock);
  2627. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2628. ulp_ops->cnic_init(dev);
  2629. ulp_put(ulp_ops);
  2630. }
  2631. }
  2632. static void cnic_ulp_exit(struct cnic_dev *dev)
  2633. {
  2634. int i;
  2635. struct cnic_local *cp = dev->cnic_priv;
  2636. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2637. struct cnic_ulp_ops *ulp_ops;
  2638. mutex_lock(&cnic_lock);
  2639. ulp_ops = cnic_ulp_tbl_prot(i);
  2640. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2641. mutex_unlock(&cnic_lock);
  2642. continue;
  2643. }
  2644. ulp_get(ulp_ops);
  2645. mutex_unlock(&cnic_lock);
  2646. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2647. ulp_ops->cnic_exit(dev);
  2648. ulp_put(ulp_ops);
  2649. }
  2650. }
  2651. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2652. {
  2653. struct cnic_dev *dev = csk->dev;
  2654. struct l4_kwq_offload_pg *l4kwqe;
  2655. struct kwqe *wqes[1];
  2656. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2657. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2658. wqes[0] = (struct kwqe *) l4kwqe;
  2659. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2660. l4kwqe->flags =
  2661. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2662. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2663. l4kwqe->da0 = csk->ha[0];
  2664. l4kwqe->da1 = csk->ha[1];
  2665. l4kwqe->da2 = csk->ha[2];
  2666. l4kwqe->da3 = csk->ha[3];
  2667. l4kwqe->da4 = csk->ha[4];
  2668. l4kwqe->da5 = csk->ha[5];
  2669. l4kwqe->sa0 = dev->mac_addr[0];
  2670. l4kwqe->sa1 = dev->mac_addr[1];
  2671. l4kwqe->sa2 = dev->mac_addr[2];
  2672. l4kwqe->sa3 = dev->mac_addr[3];
  2673. l4kwqe->sa4 = dev->mac_addr[4];
  2674. l4kwqe->sa5 = dev->mac_addr[5];
  2675. l4kwqe->etype = ETH_P_IP;
  2676. l4kwqe->ipid_start = DEF_IPID_START;
  2677. l4kwqe->host_opaque = csk->l5_cid;
  2678. if (csk->vlan_id) {
  2679. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2680. l4kwqe->vlan_tag = csk->vlan_id;
  2681. l4kwqe->l2hdr_nbytes += 4;
  2682. }
  2683. return dev->submit_kwqes(dev, wqes, 1);
  2684. }
  2685. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2686. {
  2687. struct cnic_dev *dev = csk->dev;
  2688. struct l4_kwq_update_pg *l4kwqe;
  2689. struct kwqe *wqes[1];
  2690. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2691. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2692. wqes[0] = (struct kwqe *) l4kwqe;
  2693. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2694. l4kwqe->flags =
  2695. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2696. l4kwqe->pg_cid = csk->pg_cid;
  2697. l4kwqe->da0 = csk->ha[0];
  2698. l4kwqe->da1 = csk->ha[1];
  2699. l4kwqe->da2 = csk->ha[2];
  2700. l4kwqe->da3 = csk->ha[3];
  2701. l4kwqe->da4 = csk->ha[4];
  2702. l4kwqe->da5 = csk->ha[5];
  2703. l4kwqe->pg_host_opaque = csk->l5_cid;
  2704. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2705. return dev->submit_kwqes(dev, wqes, 1);
  2706. }
  2707. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2708. {
  2709. struct cnic_dev *dev = csk->dev;
  2710. struct l4_kwq_upload *l4kwqe;
  2711. struct kwqe *wqes[1];
  2712. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2713. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2714. wqes[0] = (struct kwqe *) l4kwqe;
  2715. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2716. l4kwqe->flags =
  2717. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2718. l4kwqe->cid = csk->pg_cid;
  2719. return dev->submit_kwqes(dev, wqes, 1);
  2720. }
  2721. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2722. {
  2723. struct cnic_dev *dev = csk->dev;
  2724. struct l4_kwq_connect_req1 *l4kwqe1;
  2725. struct l4_kwq_connect_req2 *l4kwqe2;
  2726. struct l4_kwq_connect_req3 *l4kwqe3;
  2727. struct kwqe *wqes[3];
  2728. u8 tcp_flags = 0;
  2729. int num_wqes = 2;
  2730. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2731. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2732. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2733. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2734. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2735. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2736. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2737. l4kwqe3->flags =
  2738. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2739. l4kwqe3->ka_timeout = csk->ka_timeout;
  2740. l4kwqe3->ka_interval = csk->ka_interval;
  2741. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2742. l4kwqe3->tos = csk->tos;
  2743. l4kwqe3->ttl = csk->ttl;
  2744. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2745. l4kwqe3->pmtu = csk->mtu;
  2746. l4kwqe3->rcv_buf = csk->rcv_buf;
  2747. l4kwqe3->snd_buf = csk->snd_buf;
  2748. l4kwqe3->seed = csk->seed;
  2749. wqes[0] = (struct kwqe *) l4kwqe1;
  2750. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2751. wqes[1] = (struct kwqe *) l4kwqe2;
  2752. wqes[2] = (struct kwqe *) l4kwqe3;
  2753. num_wqes = 3;
  2754. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2755. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2756. l4kwqe2->flags =
  2757. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2758. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2759. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2760. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2761. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2762. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2763. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2764. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2765. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2766. sizeof(struct tcphdr);
  2767. } else {
  2768. wqes[1] = (struct kwqe *) l4kwqe3;
  2769. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2770. sizeof(struct tcphdr);
  2771. }
  2772. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2773. l4kwqe1->flags =
  2774. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2775. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2776. l4kwqe1->cid = csk->cid;
  2777. l4kwqe1->pg_cid = csk->pg_cid;
  2778. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2779. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2780. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2781. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2782. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2783. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2784. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2785. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2786. if (csk->tcp_flags & SK_TCP_NAGLE)
  2787. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2788. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2789. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2790. if (csk->tcp_flags & SK_TCP_SACK)
  2791. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2792. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2793. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2794. l4kwqe1->tcp_flags = tcp_flags;
  2795. return dev->submit_kwqes(dev, wqes, num_wqes);
  2796. }
  2797. static int cnic_cm_close_req(struct cnic_sock *csk)
  2798. {
  2799. struct cnic_dev *dev = csk->dev;
  2800. struct l4_kwq_close_req *l4kwqe;
  2801. struct kwqe *wqes[1];
  2802. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2803. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2804. wqes[0] = (struct kwqe *) l4kwqe;
  2805. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2806. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2807. l4kwqe->cid = csk->cid;
  2808. return dev->submit_kwqes(dev, wqes, 1);
  2809. }
  2810. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2811. {
  2812. struct cnic_dev *dev = csk->dev;
  2813. struct l4_kwq_reset_req *l4kwqe;
  2814. struct kwqe *wqes[1];
  2815. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2816. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2817. wqes[0] = (struct kwqe *) l4kwqe;
  2818. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2819. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2820. l4kwqe->cid = csk->cid;
  2821. return dev->submit_kwqes(dev, wqes, 1);
  2822. }
  2823. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2824. u32 l5_cid, struct cnic_sock **csk, void *context)
  2825. {
  2826. struct cnic_local *cp = dev->cnic_priv;
  2827. struct cnic_sock *csk1;
  2828. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2829. return -EINVAL;
  2830. if (cp->ctx_tbl) {
  2831. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2832. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2833. return -EAGAIN;
  2834. }
  2835. csk1 = &cp->csk_tbl[l5_cid];
  2836. if (atomic_read(&csk1->ref_count))
  2837. return -EAGAIN;
  2838. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2839. return -EBUSY;
  2840. csk1->dev = dev;
  2841. csk1->cid = cid;
  2842. csk1->l5_cid = l5_cid;
  2843. csk1->ulp_type = ulp_type;
  2844. csk1->context = context;
  2845. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2846. csk1->ka_interval = DEF_KA_INTERVAL;
  2847. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2848. csk1->tos = DEF_TOS;
  2849. csk1->ttl = DEF_TTL;
  2850. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2851. csk1->rcv_buf = DEF_RCV_BUF;
  2852. csk1->snd_buf = DEF_SND_BUF;
  2853. csk1->seed = DEF_SEED;
  2854. *csk = csk1;
  2855. return 0;
  2856. }
  2857. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2858. {
  2859. if (csk->src_port) {
  2860. struct cnic_dev *dev = csk->dev;
  2861. struct cnic_local *cp = dev->cnic_priv;
  2862. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2863. csk->src_port = 0;
  2864. }
  2865. }
  2866. static void cnic_close_conn(struct cnic_sock *csk)
  2867. {
  2868. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2869. cnic_cm_upload_pg(csk);
  2870. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2871. }
  2872. cnic_cm_cleanup(csk);
  2873. }
  2874. static int cnic_cm_destroy(struct cnic_sock *csk)
  2875. {
  2876. if (!cnic_in_use(csk))
  2877. return -EINVAL;
  2878. csk_hold(csk);
  2879. clear_bit(SK_F_INUSE, &csk->flags);
  2880. smp_mb__after_clear_bit();
  2881. while (atomic_read(&csk->ref_count) != 1)
  2882. msleep(1);
  2883. cnic_cm_cleanup(csk);
  2884. csk->flags = 0;
  2885. csk_put(csk);
  2886. return 0;
  2887. }
  2888. static inline u16 cnic_get_vlan(struct net_device *dev,
  2889. struct net_device **vlan_dev)
  2890. {
  2891. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2892. *vlan_dev = vlan_dev_real_dev(dev);
  2893. return vlan_dev_vlan_id(dev);
  2894. }
  2895. *vlan_dev = dev;
  2896. return 0;
  2897. }
  2898. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2899. struct dst_entry **dst)
  2900. {
  2901. #if defined(CONFIG_INET)
  2902. struct rtable *rt;
  2903. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2904. if (!IS_ERR(rt)) {
  2905. *dst = &rt->dst;
  2906. return 0;
  2907. }
  2908. return PTR_ERR(rt);
  2909. #else
  2910. return -ENETUNREACH;
  2911. #endif
  2912. }
  2913. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2914. struct dst_entry **dst)
  2915. {
  2916. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2917. struct flowi6 fl6;
  2918. memset(&fl6, 0, sizeof(fl6));
  2919. fl6.daddr = dst_addr->sin6_addr;
  2920. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2921. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2922. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2923. if (*dst)
  2924. return 0;
  2925. #endif
  2926. return -ENETUNREACH;
  2927. }
  2928. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2929. int ulp_type)
  2930. {
  2931. struct cnic_dev *dev = NULL;
  2932. struct dst_entry *dst;
  2933. struct net_device *netdev = NULL;
  2934. int err = -ENETUNREACH;
  2935. if (dst_addr->sin_family == AF_INET)
  2936. err = cnic_get_v4_route(dst_addr, &dst);
  2937. else if (dst_addr->sin_family == AF_INET6) {
  2938. struct sockaddr_in6 *dst_addr6 =
  2939. (struct sockaddr_in6 *) dst_addr;
  2940. err = cnic_get_v6_route(dst_addr6, &dst);
  2941. } else
  2942. return NULL;
  2943. if (err)
  2944. return NULL;
  2945. if (!dst->dev)
  2946. goto done;
  2947. cnic_get_vlan(dst->dev, &netdev);
  2948. dev = cnic_from_netdev(netdev);
  2949. done:
  2950. dst_release(dst);
  2951. if (dev)
  2952. cnic_put(dev);
  2953. return dev;
  2954. }
  2955. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2956. {
  2957. struct cnic_dev *dev = csk->dev;
  2958. struct cnic_local *cp = dev->cnic_priv;
  2959. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2960. }
  2961. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2962. {
  2963. struct cnic_dev *dev = csk->dev;
  2964. struct cnic_local *cp = dev->cnic_priv;
  2965. int is_v6, rc = 0;
  2966. struct dst_entry *dst = NULL;
  2967. struct net_device *realdev;
  2968. __be16 local_port;
  2969. u32 port_id;
  2970. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2971. saddr->remote.v6.sin6_family == AF_INET6)
  2972. is_v6 = 1;
  2973. else if (saddr->local.v4.sin_family == AF_INET &&
  2974. saddr->remote.v4.sin_family == AF_INET)
  2975. is_v6 = 0;
  2976. else
  2977. return -EINVAL;
  2978. clear_bit(SK_F_IPV6, &csk->flags);
  2979. if (is_v6) {
  2980. set_bit(SK_F_IPV6, &csk->flags);
  2981. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2982. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2983. sizeof(struct in6_addr));
  2984. csk->dst_port = saddr->remote.v6.sin6_port;
  2985. local_port = saddr->local.v6.sin6_port;
  2986. } else {
  2987. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2988. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2989. csk->dst_port = saddr->remote.v4.sin_port;
  2990. local_port = saddr->local.v4.sin_port;
  2991. }
  2992. csk->vlan_id = 0;
  2993. csk->mtu = dev->netdev->mtu;
  2994. if (dst && dst->dev) {
  2995. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2996. if (realdev == dev->netdev) {
  2997. csk->vlan_id = vlan;
  2998. csk->mtu = dst_mtu(dst);
  2999. }
  3000. }
  3001. port_id = be16_to_cpu(local_port);
  3002. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3003. port_id < CNIC_LOCAL_PORT_MAX) {
  3004. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3005. port_id = 0;
  3006. } else
  3007. port_id = 0;
  3008. if (!port_id) {
  3009. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3010. if (port_id == -1) {
  3011. rc = -ENOMEM;
  3012. goto err_out;
  3013. }
  3014. local_port = cpu_to_be16(port_id);
  3015. }
  3016. csk->src_port = local_port;
  3017. err_out:
  3018. dst_release(dst);
  3019. return rc;
  3020. }
  3021. static void cnic_init_csk_state(struct cnic_sock *csk)
  3022. {
  3023. csk->state = 0;
  3024. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3025. clear_bit(SK_F_CLOSING, &csk->flags);
  3026. }
  3027. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3028. {
  3029. struct cnic_local *cp = csk->dev->cnic_priv;
  3030. int err = 0;
  3031. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3032. return -EOPNOTSUPP;
  3033. if (!cnic_in_use(csk))
  3034. return -EINVAL;
  3035. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3036. return -EINVAL;
  3037. cnic_init_csk_state(csk);
  3038. err = cnic_get_route(csk, saddr);
  3039. if (err)
  3040. goto err_out;
  3041. err = cnic_resolve_addr(csk, saddr);
  3042. if (!err)
  3043. return 0;
  3044. err_out:
  3045. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3046. return err;
  3047. }
  3048. static int cnic_cm_abort(struct cnic_sock *csk)
  3049. {
  3050. struct cnic_local *cp = csk->dev->cnic_priv;
  3051. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3052. if (!cnic_in_use(csk))
  3053. return -EINVAL;
  3054. if (cnic_abort_prep(csk))
  3055. return cnic_cm_abort_req(csk);
  3056. /* Getting here means that we haven't started connect, or
  3057. * connect was not successful.
  3058. */
  3059. cp->close_conn(csk, opcode);
  3060. if (csk->state != opcode)
  3061. return -EALREADY;
  3062. return 0;
  3063. }
  3064. static int cnic_cm_close(struct cnic_sock *csk)
  3065. {
  3066. if (!cnic_in_use(csk))
  3067. return -EINVAL;
  3068. if (cnic_close_prep(csk)) {
  3069. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3070. return cnic_cm_close_req(csk);
  3071. } else {
  3072. return -EALREADY;
  3073. }
  3074. return 0;
  3075. }
  3076. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3077. u8 opcode)
  3078. {
  3079. struct cnic_ulp_ops *ulp_ops;
  3080. int ulp_type = csk->ulp_type;
  3081. rcu_read_lock();
  3082. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3083. if (ulp_ops) {
  3084. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3085. ulp_ops->cm_connect_complete(csk);
  3086. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3087. ulp_ops->cm_close_complete(csk);
  3088. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3089. ulp_ops->cm_remote_abort(csk);
  3090. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3091. ulp_ops->cm_abort_complete(csk);
  3092. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3093. ulp_ops->cm_remote_close(csk);
  3094. }
  3095. rcu_read_unlock();
  3096. }
  3097. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3098. {
  3099. if (cnic_offld_prep(csk)) {
  3100. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3101. cnic_cm_update_pg(csk);
  3102. else
  3103. cnic_cm_offload_pg(csk);
  3104. }
  3105. return 0;
  3106. }
  3107. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3108. {
  3109. struct cnic_local *cp = dev->cnic_priv;
  3110. u32 l5_cid = kcqe->pg_host_opaque;
  3111. u8 opcode = kcqe->op_code;
  3112. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3113. csk_hold(csk);
  3114. if (!cnic_in_use(csk))
  3115. goto done;
  3116. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3117. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3118. goto done;
  3119. }
  3120. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3121. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3122. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3123. cnic_cm_upcall(cp, csk,
  3124. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3125. goto done;
  3126. }
  3127. csk->pg_cid = kcqe->pg_cid;
  3128. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3129. cnic_cm_conn_req(csk);
  3130. done:
  3131. csk_put(csk);
  3132. }
  3133. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3134. {
  3135. struct cnic_local *cp = dev->cnic_priv;
  3136. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3137. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3138. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3139. ctx->timestamp = jiffies;
  3140. ctx->wait_cond = 1;
  3141. wake_up(&ctx->waitq);
  3142. }
  3143. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3144. {
  3145. struct cnic_local *cp = dev->cnic_priv;
  3146. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3147. u8 opcode = l4kcqe->op_code;
  3148. u32 l5_cid;
  3149. struct cnic_sock *csk;
  3150. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3151. cnic_process_fcoe_term_conn(dev, kcqe);
  3152. return;
  3153. }
  3154. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3155. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3156. cnic_cm_process_offld_pg(dev, l4kcqe);
  3157. return;
  3158. }
  3159. l5_cid = l4kcqe->conn_id;
  3160. if (opcode & 0x80)
  3161. l5_cid = l4kcqe->cid;
  3162. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3163. return;
  3164. csk = &cp->csk_tbl[l5_cid];
  3165. csk_hold(csk);
  3166. if (!cnic_in_use(csk)) {
  3167. csk_put(csk);
  3168. return;
  3169. }
  3170. switch (opcode) {
  3171. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3172. if (l4kcqe->status != 0) {
  3173. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3174. cnic_cm_upcall(cp, csk,
  3175. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3176. }
  3177. break;
  3178. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3179. if (l4kcqe->status == 0)
  3180. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3181. smp_mb__before_clear_bit();
  3182. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3183. cnic_cm_upcall(cp, csk, opcode);
  3184. break;
  3185. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3186. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3187. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3188. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3189. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3190. cp->close_conn(csk, opcode);
  3191. break;
  3192. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3193. /* after we already sent CLOSE_REQ */
  3194. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3195. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3196. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3197. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3198. else
  3199. cnic_cm_upcall(cp, csk, opcode);
  3200. break;
  3201. }
  3202. csk_put(csk);
  3203. }
  3204. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3205. {
  3206. struct cnic_dev *dev = data;
  3207. int i;
  3208. for (i = 0; i < num; i++)
  3209. cnic_cm_process_kcqe(dev, kcqe[i]);
  3210. }
  3211. static struct cnic_ulp_ops cm_ulp_ops = {
  3212. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3213. };
  3214. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3215. {
  3216. struct cnic_local *cp = dev->cnic_priv;
  3217. kfree(cp->csk_tbl);
  3218. cp->csk_tbl = NULL;
  3219. cnic_free_id_tbl(&cp->csk_port_tbl);
  3220. }
  3221. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3222. {
  3223. struct cnic_local *cp = dev->cnic_priv;
  3224. u32 port_id;
  3225. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3226. GFP_KERNEL);
  3227. if (!cp->csk_tbl)
  3228. return -ENOMEM;
  3229. port_id = random32();
  3230. port_id %= CNIC_LOCAL_PORT_RANGE;
  3231. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3232. CNIC_LOCAL_PORT_MIN, port_id)) {
  3233. cnic_cm_free_mem(dev);
  3234. return -ENOMEM;
  3235. }
  3236. return 0;
  3237. }
  3238. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3239. {
  3240. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3241. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3242. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3243. csk->state = opcode;
  3244. }
  3245. /* 1. If event opcode matches the expected event in csk->state
  3246. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3247. * event
  3248. * 3. If the expected event is 0, meaning the connection was never
  3249. * never established, we accept the opcode from cm_abort.
  3250. */
  3251. if (opcode == csk->state || csk->state == 0 ||
  3252. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3253. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3254. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3255. if (csk->state == 0)
  3256. csk->state = opcode;
  3257. return 1;
  3258. }
  3259. }
  3260. return 0;
  3261. }
  3262. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3263. {
  3264. struct cnic_dev *dev = csk->dev;
  3265. struct cnic_local *cp = dev->cnic_priv;
  3266. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3267. cnic_cm_upcall(cp, csk, opcode);
  3268. return;
  3269. }
  3270. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3271. cnic_close_conn(csk);
  3272. csk->state = opcode;
  3273. cnic_cm_upcall(cp, csk, opcode);
  3274. }
  3275. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3276. {
  3277. }
  3278. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3279. {
  3280. u32 seed;
  3281. seed = random32();
  3282. cnic_ctx_wr(dev, 45, 0, seed);
  3283. return 0;
  3284. }
  3285. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3286. {
  3287. struct cnic_dev *dev = csk->dev;
  3288. struct cnic_local *cp = dev->cnic_priv;
  3289. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3290. union l5cm_specific_data l5_data;
  3291. u32 cmd = 0;
  3292. int close_complete = 0;
  3293. switch (opcode) {
  3294. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3295. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3296. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3297. if (cnic_ready_to_close(csk, opcode)) {
  3298. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3299. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3300. else
  3301. close_complete = 1;
  3302. }
  3303. break;
  3304. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3305. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3306. break;
  3307. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3308. close_complete = 1;
  3309. break;
  3310. }
  3311. if (cmd) {
  3312. memset(&l5_data, 0, sizeof(l5_data));
  3313. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3314. &l5_data);
  3315. } else if (close_complete) {
  3316. ctx->timestamp = jiffies;
  3317. cnic_close_conn(csk);
  3318. cnic_cm_upcall(cp, csk, csk->state);
  3319. }
  3320. }
  3321. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3322. {
  3323. struct cnic_local *cp = dev->cnic_priv;
  3324. if (!cp->ctx_tbl)
  3325. return;
  3326. if (!netif_running(dev->netdev))
  3327. return;
  3328. cnic_bnx2x_delete_wait(dev, 0);
  3329. cancel_delayed_work(&cp->delete_task);
  3330. flush_workqueue(cnic_wq);
  3331. if (atomic_read(&cp->iscsi_conn) != 0)
  3332. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3333. atomic_read(&cp->iscsi_conn));
  3334. }
  3335. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3336. {
  3337. struct cnic_local *cp = dev->cnic_priv;
  3338. u32 pfid = cp->pfid;
  3339. u32 port = CNIC_PORT(cp);
  3340. cnic_init_bnx2x_mac(dev);
  3341. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3342. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3343. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3344. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3345. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3346. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3347. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3348. DEF_MAX_DA_COUNT);
  3349. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3350. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3351. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3352. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3353. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3354. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3355. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3356. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3357. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3358. DEF_MAX_CWND);
  3359. return 0;
  3360. }
  3361. static void cnic_delete_task(struct work_struct *work)
  3362. {
  3363. struct cnic_local *cp;
  3364. struct cnic_dev *dev;
  3365. u32 i;
  3366. int need_resched = 0;
  3367. cp = container_of(work, struct cnic_local, delete_task.work);
  3368. dev = cp->dev;
  3369. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3370. struct drv_ctl_info info;
  3371. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3372. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3373. cp->ethdev->drv_ctl(dev->netdev, &info);
  3374. }
  3375. for (i = 0; i < cp->max_cid_space; i++) {
  3376. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3377. int err;
  3378. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3379. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3380. continue;
  3381. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3382. need_resched = 1;
  3383. continue;
  3384. }
  3385. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3386. continue;
  3387. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3388. cnic_free_bnx2x_conn_resc(dev, i);
  3389. if (!err) {
  3390. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3391. atomic_dec(&cp->iscsi_conn);
  3392. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3393. }
  3394. }
  3395. if (need_resched)
  3396. queue_delayed_work(cnic_wq, &cp->delete_task,
  3397. msecs_to_jiffies(10));
  3398. }
  3399. static int cnic_cm_open(struct cnic_dev *dev)
  3400. {
  3401. struct cnic_local *cp = dev->cnic_priv;
  3402. int err;
  3403. err = cnic_cm_alloc_mem(dev);
  3404. if (err)
  3405. return err;
  3406. err = cp->start_cm(dev);
  3407. if (err)
  3408. goto err_out;
  3409. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3410. dev->cm_create = cnic_cm_create;
  3411. dev->cm_destroy = cnic_cm_destroy;
  3412. dev->cm_connect = cnic_cm_connect;
  3413. dev->cm_abort = cnic_cm_abort;
  3414. dev->cm_close = cnic_cm_close;
  3415. dev->cm_select_dev = cnic_cm_select_dev;
  3416. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3417. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3418. return 0;
  3419. err_out:
  3420. cnic_cm_free_mem(dev);
  3421. return err;
  3422. }
  3423. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3424. {
  3425. struct cnic_local *cp = dev->cnic_priv;
  3426. int i;
  3427. cp->stop_cm(dev);
  3428. if (!cp->csk_tbl)
  3429. return 0;
  3430. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3431. struct cnic_sock *csk = &cp->csk_tbl[i];
  3432. clear_bit(SK_F_INUSE, &csk->flags);
  3433. cnic_cm_cleanup(csk);
  3434. }
  3435. cnic_cm_free_mem(dev);
  3436. return 0;
  3437. }
  3438. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3439. {
  3440. u32 cid_addr;
  3441. int i;
  3442. cid_addr = GET_CID_ADDR(cid);
  3443. for (i = 0; i < CTX_SIZE; i += 4)
  3444. cnic_ctx_wr(dev, cid_addr, i, 0);
  3445. }
  3446. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3447. {
  3448. struct cnic_local *cp = dev->cnic_priv;
  3449. int ret = 0, i;
  3450. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3451. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3452. return 0;
  3453. for (i = 0; i < cp->ctx_blks; i++) {
  3454. int j;
  3455. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3456. u32 val;
  3457. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3458. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3459. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3460. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3461. (u64) cp->ctx_arr[i].mapping >> 32);
  3462. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3463. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3464. for (j = 0; j < 10; j++) {
  3465. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3466. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3467. break;
  3468. udelay(5);
  3469. }
  3470. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3471. ret = -EBUSY;
  3472. break;
  3473. }
  3474. }
  3475. return ret;
  3476. }
  3477. static void cnic_free_irq(struct cnic_dev *dev)
  3478. {
  3479. struct cnic_local *cp = dev->cnic_priv;
  3480. struct cnic_eth_dev *ethdev = cp->ethdev;
  3481. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3482. cp->disable_int_sync(dev);
  3483. tasklet_kill(&cp->cnic_irq_task);
  3484. free_irq(ethdev->irq_arr[0].vector, dev);
  3485. }
  3486. }
  3487. static int cnic_request_irq(struct cnic_dev *dev)
  3488. {
  3489. struct cnic_local *cp = dev->cnic_priv;
  3490. struct cnic_eth_dev *ethdev = cp->ethdev;
  3491. int err;
  3492. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3493. if (err)
  3494. tasklet_disable(&cp->cnic_irq_task);
  3495. return err;
  3496. }
  3497. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3498. {
  3499. struct cnic_local *cp = dev->cnic_priv;
  3500. struct cnic_eth_dev *ethdev = cp->ethdev;
  3501. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3502. int err, i = 0;
  3503. int sblk_num = cp->status_blk_num;
  3504. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3505. BNX2_HC_SB_CONFIG_1;
  3506. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3507. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3508. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3509. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3510. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3511. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3512. (unsigned long) dev);
  3513. err = cnic_request_irq(dev);
  3514. if (err)
  3515. return err;
  3516. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3517. i < 10) {
  3518. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3519. 1 << (11 + sblk_num));
  3520. udelay(10);
  3521. i++;
  3522. barrier();
  3523. }
  3524. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3525. cnic_free_irq(dev);
  3526. goto failed;
  3527. }
  3528. } else {
  3529. struct status_block *sblk = cp->status_blk.gen;
  3530. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3531. int i = 0;
  3532. while (sblk->status_completion_producer_index && i < 10) {
  3533. CNIC_WR(dev, BNX2_HC_COMMAND,
  3534. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3535. udelay(10);
  3536. i++;
  3537. barrier();
  3538. }
  3539. if (sblk->status_completion_producer_index)
  3540. goto failed;
  3541. }
  3542. return 0;
  3543. failed:
  3544. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3545. return -EBUSY;
  3546. }
  3547. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3548. {
  3549. struct cnic_local *cp = dev->cnic_priv;
  3550. struct cnic_eth_dev *ethdev = cp->ethdev;
  3551. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3552. return;
  3553. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3554. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3555. }
  3556. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3557. {
  3558. struct cnic_local *cp = dev->cnic_priv;
  3559. struct cnic_eth_dev *ethdev = cp->ethdev;
  3560. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3561. return;
  3562. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3563. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3564. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3565. synchronize_irq(ethdev->irq_arr[0].vector);
  3566. }
  3567. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3568. {
  3569. struct cnic_local *cp = dev->cnic_priv;
  3570. struct cnic_eth_dev *ethdev = cp->ethdev;
  3571. struct cnic_uio_dev *udev = cp->udev;
  3572. u32 cid_addr, tx_cid, sb_id;
  3573. u32 val, offset0, offset1, offset2, offset3;
  3574. int i;
  3575. struct tx_bd *txbd;
  3576. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3577. struct status_block *s_blk = cp->status_blk.gen;
  3578. sb_id = cp->status_blk_num;
  3579. tx_cid = 20;
  3580. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3581. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3582. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3583. tx_cid = TX_TSS_CID + sb_id - 1;
  3584. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3585. (TX_TSS_CID << 7));
  3586. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3587. }
  3588. cp->tx_cons = *cp->tx_cons_ptr;
  3589. cid_addr = GET_CID_ADDR(tx_cid);
  3590. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3591. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3592. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3593. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3594. offset0 = BNX2_L2CTX_TYPE_XI;
  3595. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3596. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3597. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3598. } else {
  3599. cnic_init_context(dev, tx_cid);
  3600. cnic_init_context(dev, tx_cid + 1);
  3601. offset0 = BNX2_L2CTX_TYPE;
  3602. offset1 = BNX2_L2CTX_CMD_TYPE;
  3603. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3604. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3605. }
  3606. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3607. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3608. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3609. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3610. txbd = udev->l2_ring;
  3611. buf_map = udev->l2_buf_map;
  3612. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3613. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3614. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3615. }
  3616. val = (u64) ring_map >> 32;
  3617. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3618. txbd->tx_bd_haddr_hi = val;
  3619. val = (u64) ring_map & 0xffffffff;
  3620. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3621. txbd->tx_bd_haddr_lo = val;
  3622. }
  3623. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3624. {
  3625. struct cnic_local *cp = dev->cnic_priv;
  3626. struct cnic_eth_dev *ethdev = cp->ethdev;
  3627. struct cnic_uio_dev *udev = cp->udev;
  3628. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3629. int i;
  3630. struct rx_bd *rxbd;
  3631. struct status_block *s_blk = cp->status_blk.gen;
  3632. dma_addr_t ring_map = udev->l2_ring_map;
  3633. sb_id = cp->status_blk_num;
  3634. cnic_init_context(dev, 2);
  3635. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3636. coal_reg = BNX2_HC_COMMAND;
  3637. coal_val = CNIC_RD(dev, coal_reg);
  3638. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3639. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3640. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3641. coal_reg = BNX2_HC_COALESCE_NOW;
  3642. coal_val = 1 << (11 + sb_id);
  3643. }
  3644. i = 0;
  3645. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3646. CNIC_WR(dev, coal_reg, coal_val);
  3647. udelay(10);
  3648. i++;
  3649. barrier();
  3650. }
  3651. cp->rx_cons = *cp->rx_cons_ptr;
  3652. cid_addr = GET_CID_ADDR(2);
  3653. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3654. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3655. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3656. if (sb_id == 0)
  3657. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3658. else
  3659. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3660. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3661. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3662. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3663. dma_addr_t buf_map;
  3664. int n = (i % cp->l2_rx_ring_size) + 1;
  3665. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3666. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3667. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3668. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3669. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3670. }
  3671. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3672. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3673. rxbd->rx_bd_haddr_hi = val;
  3674. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3675. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3676. rxbd->rx_bd_haddr_lo = val;
  3677. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3678. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3679. }
  3680. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3681. {
  3682. struct kwqe *wqes[1], l2kwqe;
  3683. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3684. wqes[0] = &l2kwqe;
  3685. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3686. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3687. KWQE_OPCODE_SHIFT) | 2;
  3688. dev->submit_kwqes(dev, wqes, 1);
  3689. }
  3690. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3691. {
  3692. struct cnic_local *cp = dev->cnic_priv;
  3693. u32 val;
  3694. val = cp->func << 2;
  3695. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3696. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3697. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3698. dev->mac_addr[0] = (u8) (val >> 8);
  3699. dev->mac_addr[1] = (u8) val;
  3700. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3701. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3702. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3703. dev->mac_addr[2] = (u8) (val >> 24);
  3704. dev->mac_addr[3] = (u8) (val >> 16);
  3705. dev->mac_addr[4] = (u8) (val >> 8);
  3706. dev->mac_addr[5] = (u8) val;
  3707. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3708. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3709. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3710. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3711. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3712. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3713. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3714. }
  3715. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3716. {
  3717. struct cnic_local *cp = dev->cnic_priv;
  3718. struct cnic_eth_dev *ethdev = cp->ethdev;
  3719. struct status_block *sblk = cp->status_blk.gen;
  3720. u32 val, kcq_cid_addr, kwq_cid_addr;
  3721. int err;
  3722. cnic_set_bnx2_mac(dev);
  3723. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3724. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3725. if (BCM_PAGE_BITS > 12)
  3726. val |= (12 - 8) << 4;
  3727. else
  3728. val |= (BCM_PAGE_BITS - 8) << 4;
  3729. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3730. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3731. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3732. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3733. err = cnic_setup_5709_context(dev, 1);
  3734. if (err)
  3735. return err;
  3736. cnic_init_context(dev, KWQ_CID);
  3737. cnic_init_context(dev, KCQ_CID);
  3738. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3739. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3740. cp->max_kwq_idx = MAX_KWQ_IDX;
  3741. cp->kwq_prod_idx = 0;
  3742. cp->kwq_con_idx = 0;
  3743. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3744. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3745. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3746. else
  3747. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3748. /* Initialize the kernel work queue context. */
  3749. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3750. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3751. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3752. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3753. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3754. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3755. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3756. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3757. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3758. val = (u32) cp->kwq_info.pgtbl_map;
  3759. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3760. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3761. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3762. cp->kcq1.sw_prod_idx = 0;
  3763. cp->kcq1.hw_prod_idx_ptr =
  3764. (u16 *) &sblk->status_completion_producer_index;
  3765. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3766. /* Initialize the kernel complete queue context. */
  3767. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3768. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3769. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3770. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3771. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3772. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3773. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3774. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3775. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3776. val = (u32) cp->kcq1.dma.pgtbl_map;
  3777. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3778. cp->int_num = 0;
  3779. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3780. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3781. u32 sb_id = cp->status_blk_num;
  3782. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3783. cp->kcq1.hw_prod_idx_ptr =
  3784. (u16 *) &msblk->status_completion_producer_index;
  3785. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3786. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3787. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3788. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3789. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3790. }
  3791. /* Enable Commnad Scheduler notification when we write to the
  3792. * host producer index of the kernel contexts. */
  3793. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3794. /* Enable Command Scheduler notification when we write to either
  3795. * the Send Queue or Receive Queue producer indexes of the kernel
  3796. * bypass contexts. */
  3797. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3798. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3799. /* Notify COM when the driver post an application buffer. */
  3800. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3801. /* Set the CP and COM doorbells. These two processors polls the
  3802. * doorbell for a non zero value before running. This must be done
  3803. * after setting up the kernel queue contexts. */
  3804. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3805. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3806. cnic_init_bnx2_tx_ring(dev);
  3807. cnic_init_bnx2_rx_ring(dev);
  3808. err = cnic_init_bnx2_irq(dev);
  3809. if (err) {
  3810. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3811. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3812. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3813. return err;
  3814. }
  3815. return 0;
  3816. }
  3817. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3818. {
  3819. struct cnic_local *cp = dev->cnic_priv;
  3820. struct cnic_eth_dev *ethdev = cp->ethdev;
  3821. u32 start_offset = ethdev->ctx_tbl_offset;
  3822. int i;
  3823. for (i = 0; i < cp->ctx_blks; i++) {
  3824. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3825. dma_addr_t map = ctx->mapping;
  3826. if (cp->ctx_align) {
  3827. unsigned long mask = cp->ctx_align - 1;
  3828. map = (map + mask) & ~mask;
  3829. }
  3830. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3831. }
  3832. }
  3833. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3834. {
  3835. struct cnic_local *cp = dev->cnic_priv;
  3836. struct cnic_eth_dev *ethdev = cp->ethdev;
  3837. int err = 0;
  3838. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3839. (unsigned long) dev);
  3840. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3841. err = cnic_request_irq(dev);
  3842. return err;
  3843. }
  3844. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3845. u16 sb_id, u8 sb_index,
  3846. u8 disable)
  3847. {
  3848. u32 addr = BAR_CSTRORM_INTMEM +
  3849. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3850. offsetof(struct hc_status_block_data_e1x, index_data) +
  3851. sizeof(struct hc_index_data)*sb_index +
  3852. offsetof(struct hc_index_data, flags);
  3853. u16 flags = CNIC_RD16(dev, addr);
  3854. /* clear and set */
  3855. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3856. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3857. HC_INDEX_DATA_HC_ENABLED);
  3858. CNIC_WR16(dev, addr, flags);
  3859. }
  3860. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3861. {
  3862. struct cnic_local *cp = dev->cnic_priv;
  3863. u8 sb_id = cp->status_blk_num;
  3864. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3865. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3866. offsetof(struct hc_status_block_data_e1x, index_data) +
  3867. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3868. offsetof(struct hc_index_data, timeout), 64 / 4);
  3869. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3870. }
  3871. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3872. {
  3873. }
  3874. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3875. struct client_init_ramrod_data *data)
  3876. {
  3877. struct cnic_local *cp = dev->cnic_priv;
  3878. struct cnic_uio_dev *udev = cp->udev;
  3879. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3880. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3881. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3882. int i;
  3883. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3884. u32 val;
  3885. memset(txbd, 0, BCM_PAGE_SIZE);
  3886. buf_map = udev->l2_buf_map;
  3887. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3888. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3889. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3890. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3891. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3892. reg_bd->addr_hi = start_bd->addr_hi;
  3893. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3894. start_bd->nbytes = cpu_to_le16(0x10);
  3895. start_bd->nbd = cpu_to_le16(3);
  3896. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3897. start_bd->general_data = (UNICAST_ADDRESS <<
  3898. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3899. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3900. }
  3901. val = (u64) ring_map >> 32;
  3902. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3903. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3904. val = (u64) ring_map & 0xffffffff;
  3905. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3906. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3907. /* Other ramrod params */
  3908. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3909. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3910. /* reset xstorm per client statistics */
  3911. if (cli < MAX_STAT_COUNTER_ID) {
  3912. data->general.statistics_zero_flg = 1;
  3913. data->general.statistics_en_flg = 1;
  3914. data->general.statistics_counter_id = cli;
  3915. }
  3916. cp->tx_cons_ptr =
  3917. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3918. }
  3919. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3920. struct client_init_ramrod_data *data)
  3921. {
  3922. struct cnic_local *cp = dev->cnic_priv;
  3923. struct cnic_uio_dev *udev = cp->udev;
  3924. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3925. BCM_PAGE_SIZE);
  3926. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3927. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3928. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3929. int i;
  3930. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3931. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3932. u32 val;
  3933. dma_addr_t ring_map = udev->l2_ring_map;
  3934. /* General data */
  3935. data->general.client_id = cli;
  3936. data->general.activate_flg = 1;
  3937. data->general.sp_client_id = cli;
  3938. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3939. data->general.func_id = cp->pfid;
  3940. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3941. dma_addr_t buf_map;
  3942. int n = (i % cp->l2_rx_ring_size) + 1;
  3943. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3944. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3945. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3946. }
  3947. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3948. rxbd->addr_hi = cpu_to_le32(val);
  3949. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3950. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3951. rxbd->addr_lo = cpu_to_le32(val);
  3952. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3953. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3954. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3955. rxcqe->addr_hi = cpu_to_le32(val);
  3956. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3957. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3958. rxcqe->addr_lo = cpu_to_le32(val);
  3959. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3960. /* Other ramrod params */
  3961. data->rx.client_qzone_id = cl_qzone_id;
  3962. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3963. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3964. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3965. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  3966. data->rx.outer_vlan_removal_enable_flg = 1;
  3967. data->rx.silent_vlan_removal_flg = 1;
  3968. data->rx.silent_vlan_value = 0;
  3969. data->rx.silent_vlan_mask = 0xffff;
  3970. cp->rx_cons_ptr =
  3971. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3972. cp->rx_cons = *cp->rx_cons_ptr;
  3973. }
  3974. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3975. {
  3976. struct cnic_local *cp = dev->cnic_priv;
  3977. u32 pfid = cp->pfid;
  3978. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3979. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3980. cp->kcq1.sw_prod_idx = 0;
  3981. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3982. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3983. cp->kcq1.hw_prod_idx_ptr =
  3984. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3985. cp->kcq1.status_idx_ptr =
  3986. &sb->sb.running_index[SM_RX_ID];
  3987. } else {
  3988. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3989. cp->kcq1.hw_prod_idx_ptr =
  3990. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3991. cp->kcq1.status_idx_ptr =
  3992. &sb->sb.running_index[SM_RX_ID];
  3993. }
  3994. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3995. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3996. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3997. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3998. cp->kcq2.sw_prod_idx = 0;
  3999. cp->kcq2.hw_prod_idx_ptr =
  4000. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4001. cp->kcq2.status_idx_ptr =
  4002. &sb->sb.running_index[SM_RX_ID];
  4003. }
  4004. }
  4005. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4006. {
  4007. struct cnic_local *cp = dev->cnic_priv;
  4008. struct cnic_eth_dev *ethdev = cp->ethdev;
  4009. int func = CNIC_FUNC(cp), ret;
  4010. u32 pfid;
  4011. cp->port_mode = CHIP_PORT_MODE_NONE;
  4012. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4013. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4014. if (!(val & 1))
  4015. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4016. else
  4017. val = (val >> 1) & 1;
  4018. if (val) {
  4019. cp->port_mode = CHIP_4_PORT_MODE;
  4020. cp->pfid = func >> 1;
  4021. } else {
  4022. cp->port_mode = CHIP_2_PORT_MODE;
  4023. cp->pfid = func & 0x6;
  4024. }
  4025. } else {
  4026. cp->pfid = func;
  4027. }
  4028. pfid = cp->pfid;
  4029. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4030. cp->iscsi_start_cid, 0);
  4031. if (ret)
  4032. return -ENOMEM;
  4033. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4034. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4035. cp->fcoe_start_cid, 0);
  4036. if (ret)
  4037. return -ENOMEM;
  4038. }
  4039. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4040. cnic_init_bnx2x_kcq(dev);
  4041. /* Only 1 EQ */
  4042. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4043. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4044. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4045. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4046. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4047. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4048. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4049. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4050. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4051. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4052. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4053. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4054. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4055. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4056. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4057. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4058. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4059. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4060. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4061. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4062. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4063. HC_INDEX_ISCSI_EQ_CONS);
  4064. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4065. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4066. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4067. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4068. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4069. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4070. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4071. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4072. cnic_setup_bnx2x_context(dev);
  4073. ret = cnic_init_bnx2x_irq(dev);
  4074. if (ret)
  4075. return ret;
  4076. return 0;
  4077. }
  4078. static void cnic_init_rings(struct cnic_dev *dev)
  4079. {
  4080. struct cnic_local *cp = dev->cnic_priv;
  4081. struct cnic_uio_dev *udev = cp->udev;
  4082. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4083. return;
  4084. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4085. cnic_init_bnx2_tx_ring(dev);
  4086. cnic_init_bnx2_rx_ring(dev);
  4087. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4088. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4089. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4090. u32 cid = cp->ethdev->iscsi_l2_cid;
  4091. u32 cl_qzone_id;
  4092. struct client_init_ramrod_data *data;
  4093. union l5cm_specific_data l5_data;
  4094. struct ustorm_eth_rx_producers rx_prods = {0};
  4095. u32 off, i, *cid_ptr;
  4096. rx_prods.bd_prod = 0;
  4097. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4098. barrier();
  4099. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4100. off = BAR_USTRORM_INTMEM +
  4101. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4102. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4103. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4104. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4105. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4106. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4107. data = udev->l2_buf;
  4108. cid_ptr = udev->l2_buf + 12;
  4109. memset(data, 0, sizeof(*data));
  4110. cnic_init_bnx2x_tx_ring(dev, data);
  4111. cnic_init_bnx2x_rx_ring(dev, data);
  4112. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4113. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4114. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4115. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4116. cid, ETH_CONNECTION_TYPE, &l5_data);
  4117. i = 0;
  4118. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4119. ++i < 10)
  4120. msleep(1);
  4121. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4122. netdev_err(dev->netdev,
  4123. "iSCSI CLIENT_SETUP did not complete\n");
  4124. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4125. cnic_ring_ctl(dev, cid, cli, 1);
  4126. *cid_ptr = cid;
  4127. }
  4128. }
  4129. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4130. {
  4131. struct cnic_local *cp = dev->cnic_priv;
  4132. struct cnic_uio_dev *udev = cp->udev;
  4133. void *rx_ring;
  4134. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4135. return;
  4136. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4137. cnic_shutdown_bnx2_rx_ring(dev);
  4138. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4139. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4140. u32 cid = cp->ethdev->iscsi_l2_cid;
  4141. union l5cm_specific_data l5_data;
  4142. int i;
  4143. cnic_ring_ctl(dev, cid, cli, 0);
  4144. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4145. l5_data.phy_address.lo = cli;
  4146. l5_data.phy_address.hi = 0;
  4147. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4148. cid, ETH_CONNECTION_TYPE, &l5_data);
  4149. i = 0;
  4150. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4151. ++i < 10)
  4152. msleep(1);
  4153. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4154. netdev_err(dev->netdev,
  4155. "iSCSI CLIENT_HALT did not complete\n");
  4156. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4157. memset(&l5_data, 0, sizeof(l5_data));
  4158. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4159. cid, NONE_CONNECTION_TYPE, &l5_data);
  4160. msleep(10);
  4161. }
  4162. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4163. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4164. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4165. }
  4166. static int cnic_register_netdev(struct cnic_dev *dev)
  4167. {
  4168. struct cnic_local *cp = dev->cnic_priv;
  4169. struct cnic_eth_dev *ethdev = cp->ethdev;
  4170. int err;
  4171. if (!ethdev)
  4172. return -ENODEV;
  4173. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4174. return 0;
  4175. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4176. if (err)
  4177. netdev_err(dev->netdev, "register_cnic failed\n");
  4178. return err;
  4179. }
  4180. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4181. {
  4182. struct cnic_local *cp = dev->cnic_priv;
  4183. struct cnic_eth_dev *ethdev = cp->ethdev;
  4184. if (!ethdev)
  4185. return;
  4186. ethdev->drv_unregister_cnic(dev->netdev);
  4187. }
  4188. static int cnic_start_hw(struct cnic_dev *dev)
  4189. {
  4190. struct cnic_local *cp = dev->cnic_priv;
  4191. struct cnic_eth_dev *ethdev = cp->ethdev;
  4192. int err;
  4193. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4194. return -EALREADY;
  4195. dev->regview = ethdev->io_base;
  4196. pci_dev_get(dev->pcidev);
  4197. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4198. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4199. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4200. err = cp->alloc_resc(dev);
  4201. if (err) {
  4202. netdev_err(dev->netdev, "allocate resource failure\n");
  4203. goto err1;
  4204. }
  4205. err = cp->start_hw(dev);
  4206. if (err)
  4207. goto err1;
  4208. err = cnic_cm_open(dev);
  4209. if (err)
  4210. goto err1;
  4211. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4212. cp->enable_int(dev);
  4213. return 0;
  4214. err1:
  4215. cp->free_resc(dev);
  4216. pci_dev_put(dev->pcidev);
  4217. return err;
  4218. }
  4219. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4220. {
  4221. cnic_disable_bnx2_int_sync(dev);
  4222. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4223. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4224. cnic_init_context(dev, KWQ_CID);
  4225. cnic_init_context(dev, KCQ_CID);
  4226. cnic_setup_5709_context(dev, 0);
  4227. cnic_free_irq(dev);
  4228. cnic_free_resc(dev);
  4229. }
  4230. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4231. {
  4232. struct cnic_local *cp = dev->cnic_priv;
  4233. cnic_free_irq(dev);
  4234. *cp->kcq1.hw_prod_idx_ptr = 0;
  4235. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4236. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4237. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4238. cnic_free_resc(dev);
  4239. }
  4240. static void cnic_stop_hw(struct cnic_dev *dev)
  4241. {
  4242. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4243. struct cnic_local *cp = dev->cnic_priv;
  4244. int i = 0;
  4245. /* Need to wait for the ring shutdown event to complete
  4246. * before clearing the CNIC_UP flag.
  4247. */
  4248. while (cp->udev->uio_dev != -1 && i < 15) {
  4249. msleep(100);
  4250. i++;
  4251. }
  4252. cnic_shutdown_rings(dev);
  4253. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4254. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4255. synchronize_rcu();
  4256. cnic_cm_shutdown(dev);
  4257. cp->stop_hw(dev);
  4258. pci_dev_put(dev->pcidev);
  4259. }
  4260. }
  4261. static void cnic_free_dev(struct cnic_dev *dev)
  4262. {
  4263. int i = 0;
  4264. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4265. msleep(100);
  4266. i++;
  4267. }
  4268. if (atomic_read(&dev->ref_count) != 0)
  4269. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4270. netdev_info(dev->netdev, "Removed CNIC device\n");
  4271. dev_put(dev->netdev);
  4272. kfree(dev);
  4273. }
  4274. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4275. struct pci_dev *pdev)
  4276. {
  4277. struct cnic_dev *cdev;
  4278. struct cnic_local *cp;
  4279. int alloc_size;
  4280. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4281. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4282. if (cdev == NULL) {
  4283. netdev_err(dev, "allocate dev struct failure\n");
  4284. return NULL;
  4285. }
  4286. cdev->netdev = dev;
  4287. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4288. cdev->register_device = cnic_register_device;
  4289. cdev->unregister_device = cnic_unregister_device;
  4290. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4291. cp = cdev->cnic_priv;
  4292. cp->dev = cdev;
  4293. cp->l2_single_buf_size = 0x400;
  4294. cp->l2_rx_ring_size = 3;
  4295. spin_lock_init(&cp->cnic_ulp_lock);
  4296. netdev_info(dev, "Added CNIC device\n");
  4297. return cdev;
  4298. }
  4299. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4300. {
  4301. struct pci_dev *pdev;
  4302. struct cnic_dev *cdev;
  4303. struct cnic_local *cp;
  4304. struct cnic_eth_dev *ethdev = NULL;
  4305. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4306. probe = symbol_get(bnx2_cnic_probe);
  4307. if (probe) {
  4308. ethdev = (*probe)(dev);
  4309. symbol_put(bnx2_cnic_probe);
  4310. }
  4311. if (!ethdev)
  4312. return NULL;
  4313. pdev = ethdev->pdev;
  4314. if (!pdev)
  4315. return NULL;
  4316. dev_hold(dev);
  4317. pci_dev_get(pdev);
  4318. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4319. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4320. (pdev->revision < 0x10)) {
  4321. pci_dev_put(pdev);
  4322. goto cnic_err;
  4323. }
  4324. pci_dev_put(pdev);
  4325. cdev = cnic_alloc_dev(dev, pdev);
  4326. if (cdev == NULL)
  4327. goto cnic_err;
  4328. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4329. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4330. cp = cdev->cnic_priv;
  4331. cp->ethdev = ethdev;
  4332. cdev->pcidev = pdev;
  4333. cp->chip_id = ethdev->chip_id;
  4334. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4335. cp->cnic_ops = &cnic_bnx2_ops;
  4336. cp->start_hw = cnic_start_bnx2_hw;
  4337. cp->stop_hw = cnic_stop_bnx2_hw;
  4338. cp->setup_pgtbl = cnic_setup_page_tbl;
  4339. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4340. cp->free_resc = cnic_free_resc;
  4341. cp->start_cm = cnic_cm_init_bnx2_hw;
  4342. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4343. cp->enable_int = cnic_enable_bnx2_int;
  4344. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4345. cp->close_conn = cnic_close_bnx2_conn;
  4346. return cdev;
  4347. cnic_err:
  4348. dev_put(dev);
  4349. return NULL;
  4350. }
  4351. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4352. {
  4353. struct pci_dev *pdev;
  4354. struct cnic_dev *cdev;
  4355. struct cnic_local *cp;
  4356. struct cnic_eth_dev *ethdev = NULL;
  4357. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4358. probe = symbol_get(bnx2x_cnic_probe);
  4359. if (probe) {
  4360. ethdev = (*probe)(dev);
  4361. symbol_put(bnx2x_cnic_probe);
  4362. }
  4363. if (!ethdev)
  4364. return NULL;
  4365. pdev = ethdev->pdev;
  4366. if (!pdev)
  4367. return NULL;
  4368. dev_hold(dev);
  4369. cdev = cnic_alloc_dev(dev, pdev);
  4370. if (cdev == NULL) {
  4371. dev_put(dev);
  4372. return NULL;
  4373. }
  4374. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4375. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4376. cp = cdev->cnic_priv;
  4377. cp->ethdev = ethdev;
  4378. cdev->pcidev = pdev;
  4379. cp->chip_id = ethdev->chip_id;
  4380. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4381. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4382. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4383. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4384. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4385. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4386. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4387. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4388. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4389. cp->cnic_ops = &cnic_bnx2x_ops;
  4390. cp->start_hw = cnic_start_bnx2x_hw;
  4391. cp->stop_hw = cnic_stop_bnx2x_hw;
  4392. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4393. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4394. cp->free_resc = cnic_free_resc;
  4395. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4396. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4397. cp->enable_int = cnic_enable_bnx2x_int;
  4398. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4399. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4400. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4401. else
  4402. cp->ack_int = cnic_ack_bnx2x_msix;
  4403. cp->close_conn = cnic_close_bnx2x_conn;
  4404. return cdev;
  4405. }
  4406. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4407. {
  4408. struct ethtool_drvinfo drvinfo;
  4409. struct cnic_dev *cdev = NULL;
  4410. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4411. memset(&drvinfo, 0, sizeof(drvinfo));
  4412. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4413. if (!strcmp(drvinfo.driver, "bnx2"))
  4414. cdev = init_bnx2_cnic(dev);
  4415. if (!strcmp(drvinfo.driver, "bnx2x"))
  4416. cdev = init_bnx2x_cnic(dev);
  4417. if (cdev) {
  4418. write_lock(&cnic_dev_lock);
  4419. list_add(&cdev->list, &cnic_dev_list);
  4420. write_unlock(&cnic_dev_lock);
  4421. }
  4422. }
  4423. return cdev;
  4424. }
  4425. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4426. u16 vlan_id)
  4427. {
  4428. int if_type;
  4429. rcu_read_lock();
  4430. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4431. struct cnic_ulp_ops *ulp_ops;
  4432. void *ctx;
  4433. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4434. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4435. continue;
  4436. ctx = cp->ulp_handle[if_type];
  4437. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4438. }
  4439. rcu_read_unlock();
  4440. }
  4441. /**
  4442. * netdev event handler
  4443. */
  4444. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4445. void *ptr)
  4446. {
  4447. struct net_device *netdev = ptr;
  4448. struct cnic_dev *dev;
  4449. int new_dev = 0;
  4450. dev = cnic_from_netdev(netdev);
  4451. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4452. /* Check for the hot-plug device */
  4453. dev = is_cnic_dev(netdev);
  4454. if (dev) {
  4455. new_dev = 1;
  4456. cnic_hold(dev);
  4457. }
  4458. }
  4459. if (dev) {
  4460. struct cnic_local *cp = dev->cnic_priv;
  4461. if (new_dev)
  4462. cnic_ulp_init(dev);
  4463. else if (event == NETDEV_UNREGISTER)
  4464. cnic_ulp_exit(dev);
  4465. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4466. if (cnic_register_netdev(dev) != 0) {
  4467. cnic_put(dev);
  4468. goto done;
  4469. }
  4470. if (!cnic_start_hw(dev))
  4471. cnic_ulp_start(dev);
  4472. }
  4473. cnic_rcv_netevent(cp, event, 0);
  4474. if (event == NETDEV_GOING_DOWN) {
  4475. cnic_ulp_stop(dev);
  4476. cnic_stop_hw(dev);
  4477. cnic_unregister_netdev(dev);
  4478. } else if (event == NETDEV_UNREGISTER) {
  4479. write_lock(&cnic_dev_lock);
  4480. list_del_init(&dev->list);
  4481. write_unlock(&cnic_dev_lock);
  4482. cnic_put(dev);
  4483. cnic_free_dev(dev);
  4484. goto done;
  4485. }
  4486. cnic_put(dev);
  4487. } else {
  4488. struct net_device *realdev;
  4489. u16 vid;
  4490. vid = cnic_get_vlan(netdev, &realdev);
  4491. if (realdev) {
  4492. dev = cnic_from_netdev(realdev);
  4493. if (dev) {
  4494. vid |= VLAN_TAG_PRESENT;
  4495. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4496. cnic_put(dev);
  4497. }
  4498. }
  4499. }
  4500. done:
  4501. return NOTIFY_DONE;
  4502. }
  4503. static struct notifier_block cnic_netdev_notifier = {
  4504. .notifier_call = cnic_netdev_event
  4505. };
  4506. static void cnic_release(void)
  4507. {
  4508. struct cnic_dev *dev;
  4509. struct cnic_uio_dev *udev;
  4510. while (!list_empty(&cnic_dev_list)) {
  4511. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4512. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4513. cnic_ulp_stop(dev);
  4514. cnic_stop_hw(dev);
  4515. }
  4516. cnic_ulp_exit(dev);
  4517. cnic_unregister_netdev(dev);
  4518. list_del_init(&dev->list);
  4519. cnic_free_dev(dev);
  4520. }
  4521. while (!list_empty(&cnic_udev_list)) {
  4522. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4523. list);
  4524. cnic_free_uio(udev);
  4525. }
  4526. }
  4527. static int __init cnic_init(void)
  4528. {
  4529. int rc = 0;
  4530. pr_info("%s", version);
  4531. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4532. if (rc) {
  4533. cnic_release();
  4534. return rc;
  4535. }
  4536. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4537. if (!cnic_wq) {
  4538. cnic_release();
  4539. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4540. return -ENOMEM;
  4541. }
  4542. return 0;
  4543. }
  4544. static void __exit cnic_exit(void)
  4545. {
  4546. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4547. cnic_release();
  4548. destroy_workqueue(cnic_wq);
  4549. }
  4550. module_init(cnic_init);
  4551. module_exit(cnic_exit);