mpc85xx_ds.c 7.3 KB

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  1. /*
  2. * MPC85xx DS Board Setup
  3. *
  4. * Author Xianghua Xiao (x.xiao@freescale.com)
  5. * Roy Zang <tie-fei.zang@freescale.com>
  6. * - Add PCI/PCI Exprees support
  7. * Copyright 2007 Freescale Semiconductor Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/stddef.h>
  15. #include <linux/kernel.h>
  16. #include <linux/pci.h>
  17. #include <linux/kdev_t.h>
  18. #include <linux/delay.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/memblock.h>
  23. #include <asm/system.h>
  24. #include <asm/time.h>
  25. #include <asm/machdep.h>
  26. #include <asm/pci-bridge.h>
  27. #include <mm/mmu_decl.h>
  28. #include <asm/prom.h>
  29. #include <asm/udbg.h>
  30. #include <asm/mpic.h>
  31. #include <asm/i8259.h>
  32. #include <asm/swiotlb.h>
  33. #include <sysdev/fsl_soc.h>
  34. #include <sysdev/fsl_pci.h>
  35. #undef DEBUG
  36. #ifdef DEBUG
  37. #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
  38. #else
  39. #define DBG(fmt, args...)
  40. #endif
  41. #ifdef CONFIG_PPC_I8259
  42. static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
  43. {
  44. struct irq_chip *chip = irq_desc_get_chip(desc);
  45. unsigned int cascade_irq = i8259_irq();
  46. if (cascade_irq != NO_IRQ) {
  47. generic_handle_irq(cascade_irq);
  48. }
  49. chip->irq_eoi(&desc->irq_data);
  50. }
  51. #endif /* CONFIG_PPC_I8259 */
  52. void __init mpc85xx_ds_pic_init(void)
  53. {
  54. struct mpic *mpic;
  55. struct resource r;
  56. struct device_node *np;
  57. #ifdef CONFIG_PPC_I8259
  58. struct device_node *cascade_node = NULL;
  59. int cascade_irq;
  60. #endif
  61. unsigned long root = of_get_flat_dt_root();
  62. np = of_find_node_by_type(NULL, "open-pic");
  63. if (np == NULL) {
  64. printk(KERN_ERR "Could not find open-pic node\n");
  65. return;
  66. }
  67. if (of_address_to_resource(np, 0, &r)) {
  68. printk(KERN_ERR "Failed to map mpic register space\n");
  69. of_node_put(np);
  70. return;
  71. }
  72. if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
  73. mpic = mpic_alloc(np, r.start,
  74. MPIC_PRIMARY |
  75. MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
  76. MPIC_SINGLE_DEST_CPU,
  77. 0, 256, " OpenPIC ");
  78. } else {
  79. mpic = mpic_alloc(np, r.start,
  80. MPIC_PRIMARY | MPIC_WANTS_RESET |
  81. MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
  82. MPIC_SINGLE_DEST_CPU,
  83. 0, 256, " OpenPIC ");
  84. }
  85. BUG_ON(mpic == NULL);
  86. of_node_put(np);
  87. mpic_init(mpic);
  88. #ifdef CONFIG_PPC_I8259
  89. /* Initialize the i8259 controller */
  90. for_each_node_by_type(np, "interrupt-controller")
  91. if (of_device_is_compatible(np, "chrp,iic")) {
  92. cascade_node = np;
  93. break;
  94. }
  95. if (cascade_node == NULL) {
  96. printk(KERN_DEBUG "Could not find i8259 PIC\n");
  97. return;
  98. }
  99. cascade_irq = irq_of_parse_and_map(cascade_node, 0);
  100. if (cascade_irq == NO_IRQ) {
  101. printk(KERN_ERR "Failed to map cascade interrupt\n");
  102. return;
  103. }
  104. DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);
  105. i8259_init(cascade_node, 0);
  106. of_node_put(cascade_node);
  107. irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
  108. #endif /* CONFIG_PPC_I8259 */
  109. }
  110. #ifdef CONFIG_PCI
  111. static int primary_phb_addr;
  112. extern int uli_exclude_device(struct pci_controller *hose,
  113. u_char bus, u_char devfn);
  114. static int mpc85xx_exclude_device(struct pci_controller *hose,
  115. u_char bus, u_char devfn)
  116. {
  117. struct device_node* node;
  118. struct resource rsrc;
  119. node = hose->dn;
  120. of_address_to_resource(node, 0, &rsrc);
  121. if ((rsrc.start & 0xfffff) == primary_phb_addr) {
  122. return uli_exclude_device(hose, bus, devfn);
  123. }
  124. return PCIBIOS_SUCCESSFUL;
  125. }
  126. #endif /* CONFIG_PCI */
  127. /*
  128. * Setup the architecture
  129. */
  130. #ifdef CONFIG_SMP
  131. extern void __init mpc85xx_smp_init(void);
  132. #endif
  133. static void __init mpc85xx_ds_setup_arch(void)
  134. {
  135. #ifdef CONFIG_PCI
  136. struct device_node *np;
  137. struct pci_controller *hose;
  138. #endif
  139. dma_addr_t max = 0xffffffff;
  140. if (ppc_md.progress)
  141. ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
  142. #ifdef CONFIG_PCI
  143. for_each_node_by_type(np, "pci") {
  144. if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
  145. of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
  146. of_device_is_compatible(np, "fsl,p2020-pcie")) {
  147. struct resource rsrc;
  148. of_address_to_resource(np, 0, &rsrc);
  149. if ((rsrc.start & 0xfffff) == primary_phb_addr)
  150. fsl_add_bridge(np, 1);
  151. else
  152. fsl_add_bridge(np, 0);
  153. hose = pci_find_hose_for_OF_device(np);
  154. max = min(max, hose->dma_window_base_cur +
  155. hose->dma_window_size);
  156. }
  157. }
  158. ppc_md.pci_exclude_device = mpc85xx_exclude_device;
  159. #endif
  160. #ifdef CONFIG_SMP
  161. mpc85xx_smp_init();
  162. #endif
  163. #ifdef CONFIG_SWIOTLB
  164. if (memblock_end_of_DRAM() > max) {
  165. ppc_swiotlb_enable = 1;
  166. set_pci_dma_ops(&swiotlb_dma_ops);
  167. ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
  168. }
  169. #endif
  170. printk("MPC85xx DS board from Freescale Semiconductor\n");
  171. }
  172. /*
  173. * Called very early, device-tree isn't unflattened
  174. */
  175. static int __init mpc8544_ds_probe(void)
  176. {
  177. unsigned long root = of_get_flat_dt_root();
  178. if (of_flat_dt_is_compatible(root, "MPC8544DS")) {
  179. #ifdef CONFIG_PCI
  180. primary_phb_addr = 0xb000;
  181. #endif
  182. return 1;
  183. }
  184. return 0;
  185. }
  186. static struct of_device_id __initdata mpc85xxds_ids[] = {
  187. { .type = "soc", },
  188. { .compatible = "soc", },
  189. { .compatible = "simple-bus", },
  190. { .compatible = "gianfar", },
  191. {},
  192. };
  193. static int __init mpc85xxds_publish_devices(void)
  194. {
  195. return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
  196. }
  197. machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
  198. machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
  199. machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
  200. machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
  201. machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
  202. machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier);
  203. /*
  204. * Called very early, device-tree isn't unflattened
  205. */
  206. static int __init mpc8572_ds_probe(void)
  207. {
  208. unsigned long root = of_get_flat_dt_root();
  209. if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) {
  210. #ifdef CONFIG_PCI
  211. primary_phb_addr = 0x8000;
  212. #endif
  213. return 1;
  214. }
  215. return 0;
  216. }
  217. /*
  218. * Called very early, device-tree isn't unflattened
  219. */
  220. static int __init p2020_ds_probe(void)
  221. {
  222. unsigned long root = of_get_flat_dt_root();
  223. if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
  224. #ifdef CONFIG_PCI
  225. primary_phb_addr = 0x9000;
  226. #endif
  227. return 1;
  228. }
  229. return 0;
  230. }
  231. define_machine(mpc8544_ds) {
  232. .name = "MPC8544 DS",
  233. .probe = mpc8544_ds_probe,
  234. .setup_arch = mpc85xx_ds_setup_arch,
  235. .init_IRQ = mpc85xx_ds_pic_init,
  236. #ifdef CONFIG_PCI
  237. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  238. #endif
  239. .get_irq = mpic_get_irq,
  240. .restart = fsl_rstcr_restart,
  241. .calibrate_decr = generic_calibrate_decr,
  242. .progress = udbg_progress,
  243. };
  244. define_machine(mpc8572_ds) {
  245. .name = "MPC8572 DS",
  246. .probe = mpc8572_ds_probe,
  247. .setup_arch = mpc85xx_ds_setup_arch,
  248. .init_IRQ = mpc85xx_ds_pic_init,
  249. #ifdef CONFIG_PCI
  250. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  251. #endif
  252. .get_irq = mpic_get_irq,
  253. .restart = fsl_rstcr_restart,
  254. .calibrate_decr = generic_calibrate_decr,
  255. .progress = udbg_progress,
  256. };
  257. define_machine(p2020_ds) {
  258. .name = "P2020 DS",
  259. .probe = p2020_ds_probe,
  260. .setup_arch = mpc85xx_ds_setup_arch,
  261. .init_IRQ = mpc85xx_ds_pic_init,
  262. #ifdef CONFIG_PCI
  263. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  264. #endif
  265. .get_irq = mpic_get_irq,
  266. .restart = fsl_rstcr_restart,
  267. .calibrate_decr = generic_calibrate_decr,
  268. .progress = udbg_progress,
  269. };