macints.c 10.0 KB

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  1. /*
  2. * Macintosh interrupts
  3. *
  4. * General design:
  5. * In contrary to the Amiga and Atari platforms, the Mac hardware seems to
  6. * exclusively use the autovector interrupts (the 'generic level0-level7'
  7. * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
  8. * are used:
  9. * 1 - VIA1
  10. * - slot 0: one second interrupt (CA2)
  11. * - slot 1: VBlank (CA1)
  12. * - slot 2: ADB data ready (SR full)
  13. * - slot 3: ADB data (CB2)
  14. * - slot 4: ADB clock (CB1)
  15. * - slot 5: timer 2
  16. * - slot 6: timer 1
  17. * - slot 7: status of IRQ; signals 'any enabled int.'
  18. *
  19. * 2 - VIA2 or RBV
  20. * - slot 0: SCSI DRQ (CA2)
  21. * - slot 1: NUBUS IRQ (CA1) need to read port A to find which
  22. * - slot 2: /EXP IRQ (only on IIci)
  23. * - slot 3: SCSI IRQ (CB2)
  24. * - slot 4: ASC IRQ (CB1)
  25. * - slot 5: timer 2 (not on IIci)
  26. * - slot 6: timer 1 (not on IIci)
  27. * - slot 7: status of IRQ; signals 'any enabled int.'
  28. *
  29. * 2 - OSS (IIfx only?)
  30. * - slot 0: SCSI interrupt
  31. * - slot 1: Sound interrupt
  32. *
  33. * Levels 3-6 vary by machine type. For VIA or RBV Macintoshes:
  34. *
  35. * 3 - unused (?)
  36. *
  37. * 4 - SCC
  38. *
  39. * 5 - unused (?)
  40. * [serial errors or special conditions seem to raise level 6
  41. * interrupts on some models (LC4xx?)]
  42. *
  43. * 6 - off switch (?)
  44. *
  45. * For OSS Macintoshes (IIfx only at this point):
  46. *
  47. * 3 - Nubus interrupt
  48. * - slot 0: Slot $9
  49. * - slot 1: Slot $A
  50. * - slot 2: Slot $B
  51. * - slot 3: Slot $C
  52. * - slot 4: Slot $D
  53. * - slot 5: Slot $E
  54. *
  55. * 4 - SCC IOP
  56. *
  57. * 5 - ISM IOP (ADB?)
  58. *
  59. * 6 - unused
  60. *
  61. * For PSC Macintoshes (660AV, 840AV):
  62. *
  63. * 3 - PSC level 3
  64. * - slot 0: MACE
  65. *
  66. * 4 - PSC level 4
  67. * - slot 1: SCC channel A interrupt
  68. * - slot 2: SCC channel B interrupt
  69. * - slot 3: MACE DMA
  70. *
  71. * 5 - PSC level 5
  72. *
  73. * 6 - PSC level 6
  74. *
  75. * Finally we have good 'ole level 7, the non-maskable interrupt:
  76. *
  77. * 7 - NMI (programmer's switch on the back of some Macs)
  78. * Also RAM parity error on models which support it (IIc, IIfx?)
  79. *
  80. * The current interrupt logic looks something like this:
  81. *
  82. * - We install dispatchers for the autovector interrupts (1-7). These
  83. * dispatchers are responsible for querying the hardware (the
  84. * VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
  85. * this information a machspec interrupt number is generated by placing the
  86. * index of the interrupt hardware into the low three bits and the original
  87. * autovector interrupt number in the upper 5 bits. The handlers for the
  88. * resulting machspec interrupt are then called.
  89. *
  90. * - Nubus is a special case because its interrupts are hidden behind two
  91. * layers of hardware. Nubus interrupts come in as index 1 on VIA #2,
  92. * which translates to IRQ number 17. In this spot we install _another_
  93. * dispatcher. This dispatcher finds the interrupting slot number (9-F) and
  94. * then forms a new machspec interrupt number as above with the slot number
  95. * minus 9 in the low three bits and the pseudo-level 7 in the upper five
  96. * bits. The handlers for this new machspec interrupt number are then
  97. * called. This puts Nubus interrupts into the range 56-62.
  98. *
  99. * - The Baboon interrupts (used on some PowerBooks) are an even more special
  100. * case. They're hidden behind the Nubus slot $C interrupt thus adding a
  101. * third layer of indirection. Why oh why did the Apple engineers do that?
  102. *
  103. * - We support "fast" and "slow" handlers, just like the Amiga port. The
  104. * fast handlers are called first and with all interrupts disabled. They
  105. * are expected to execute quickly (hence the name). The slow handlers are
  106. * called last with interrupts enabled and the interrupt level restored.
  107. * They must therefore be reentrant.
  108. *
  109. * TODO:
  110. *
  111. */
  112. #include <linux/module.h>
  113. #include <linux/types.h>
  114. #include <linux/kernel.h>
  115. #include <linux/sched.h>
  116. #include <linux/kernel_stat.h>
  117. #include <linux/interrupt.h> /* for intr_count */
  118. #include <linux/delay.h>
  119. #include <linux/seq_file.h>
  120. #include <asm/system.h>
  121. #include <asm/irq.h>
  122. #include <asm/traps.h>
  123. #include <asm/bootinfo.h>
  124. #include <asm/macintosh.h>
  125. #include <asm/mac_via.h>
  126. #include <asm/mac_psc.h>
  127. #include <asm/hwtest.h>
  128. #include <asm/errno.h>
  129. #include <asm/macints.h>
  130. #include <asm/irq_regs.h>
  131. #include <asm/mac_oss.h>
  132. #define SHUTUP_SONIC
  133. /*
  134. * VIA/RBV hooks
  135. */
  136. extern void via_register_interrupts(void);
  137. extern void via_irq_enable(int);
  138. extern void via_irq_disable(int);
  139. extern void via_irq_clear(int);
  140. extern int via_irq_pending(int);
  141. /*
  142. * OSS hooks
  143. */
  144. extern void oss_register_interrupts(void);
  145. extern void oss_irq_enable(int);
  146. extern void oss_irq_disable(int);
  147. extern void oss_irq_clear(int);
  148. extern int oss_irq_pending(int);
  149. /*
  150. * PSC hooks
  151. */
  152. extern void psc_register_interrupts(void);
  153. extern void psc_irq_enable(int);
  154. extern void psc_irq_disable(int);
  155. extern void psc_irq_clear(int);
  156. extern int psc_irq_pending(int);
  157. /*
  158. * IOP hooks
  159. */
  160. extern void iop_register_interrupts(void);
  161. /*
  162. * Baboon hooks
  163. */
  164. extern int baboon_present;
  165. extern void baboon_register_interrupts(void);
  166. extern void baboon_irq_enable(int);
  167. extern void baboon_irq_disable(int);
  168. extern void baboon_irq_clear(int);
  169. /*
  170. * console_loglevel determines NMI handler function
  171. */
  172. irqreturn_t mac_nmi_handler(int, void *);
  173. irqreturn_t mac_debug_handler(int, void *);
  174. /* #define DEBUG_MACINTS */
  175. static struct irq_chip mac_irq_chip = {
  176. .name = "mac",
  177. .irq_enable = mac_irq_enable,
  178. .irq_disable = mac_irq_disable,
  179. };
  180. void __init mac_init_IRQ(void)
  181. {
  182. #ifdef DEBUG_MACINTS
  183. printk("mac_init_IRQ(): Setting things up...\n");
  184. #endif
  185. m68k_setup_irq_controller(&mac_irq_chip, handle_simple_irq, IRQ_USER,
  186. NUM_MAC_SOURCES - IRQ_USER);
  187. /* Make sure the SONIC interrupt is cleared or things get ugly */
  188. #ifdef SHUTUP_SONIC
  189. printk("Killing onboard sonic... ");
  190. /* This address should hopefully be mapped already */
  191. if (hwreg_present((void*)(0x50f0a000))) {
  192. *(long *)(0x50f0a014) = 0x7fffL;
  193. *(long *)(0x50f0a010) = 0L;
  194. }
  195. printk("Done.\n");
  196. #endif /* SHUTUP_SONIC */
  197. /*
  198. * Now register the handlers for the master IRQ handlers
  199. * at levels 1-7. Most of the work is done elsewhere.
  200. */
  201. if (oss_present)
  202. oss_register_interrupts();
  203. else
  204. via_register_interrupts();
  205. if (psc_present)
  206. psc_register_interrupts();
  207. if (baboon_present)
  208. baboon_register_interrupts();
  209. iop_register_interrupts();
  210. if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI",
  211. mac_nmi_handler))
  212. pr_err("Couldn't register NMI\n");
  213. #ifdef DEBUG_MACINTS
  214. printk("mac_init_IRQ(): Done!\n");
  215. #endif
  216. }
  217. /*
  218. * mac_irq_enable - enable an interrupt source
  219. * mac_irq_disable - disable an interrupt source
  220. * mac_clear_irq - clears a pending interrupt
  221. * mac_irq_pending - returns the pending status of an IRQ (nonzero = pending)
  222. *
  223. * These routines are just dispatchers to the VIA/OSS/PSC routines.
  224. */
  225. void mac_irq_enable(struct irq_data *data)
  226. {
  227. int irq = data->irq;
  228. int irq_src = IRQ_SRC(irq);
  229. switch(irq_src) {
  230. case 1:
  231. via_irq_enable(irq);
  232. break;
  233. case 2:
  234. case 7:
  235. if (oss_present)
  236. oss_irq_enable(irq);
  237. else
  238. via_irq_enable(irq);
  239. break;
  240. case 3:
  241. case 5:
  242. case 6:
  243. if (psc_present)
  244. psc_irq_enable(irq);
  245. else if (oss_present)
  246. oss_irq_enable(irq);
  247. break;
  248. case 4:
  249. if (psc_present)
  250. psc_irq_enable(irq);
  251. break;
  252. case 8:
  253. if (baboon_present)
  254. baboon_irq_enable(irq);
  255. break;
  256. }
  257. }
  258. void mac_irq_disable(struct irq_data *data)
  259. {
  260. int irq = data->irq;
  261. int irq_src = IRQ_SRC(irq);
  262. switch(irq_src) {
  263. case 1:
  264. via_irq_disable(irq);
  265. break;
  266. case 2:
  267. case 7:
  268. if (oss_present)
  269. oss_irq_disable(irq);
  270. else
  271. via_irq_disable(irq);
  272. break;
  273. case 3:
  274. case 5:
  275. case 6:
  276. if (psc_present)
  277. psc_irq_disable(irq);
  278. else if (oss_present)
  279. oss_irq_disable(irq);
  280. break;
  281. case 4:
  282. if (psc_present)
  283. psc_irq_disable(irq);
  284. break;
  285. case 8:
  286. if (baboon_present)
  287. baboon_irq_disable(irq);
  288. break;
  289. }
  290. }
  291. void mac_clear_irq(unsigned int irq)
  292. {
  293. switch(IRQ_SRC(irq)) {
  294. case 1:
  295. via_irq_clear(irq);
  296. break;
  297. case 2:
  298. case 7:
  299. if (oss_present)
  300. oss_irq_clear(irq);
  301. else
  302. via_irq_clear(irq);
  303. break;
  304. case 3:
  305. case 5:
  306. case 6:
  307. if (psc_present)
  308. psc_irq_clear(irq);
  309. else if (oss_present)
  310. oss_irq_clear(irq);
  311. break;
  312. case 4:
  313. if (psc_present)
  314. psc_irq_clear(irq);
  315. break;
  316. case 8:
  317. if (baboon_present)
  318. baboon_irq_clear(irq);
  319. break;
  320. }
  321. }
  322. int mac_irq_pending(unsigned int irq)
  323. {
  324. switch(IRQ_SRC(irq)) {
  325. case 1:
  326. return via_irq_pending(irq);
  327. case 2:
  328. case 7:
  329. if (oss_present)
  330. return oss_irq_pending(irq);
  331. else
  332. return via_irq_pending(irq);
  333. case 3:
  334. case 5:
  335. case 6:
  336. if (psc_present)
  337. return psc_irq_pending(irq);
  338. else if (oss_present)
  339. return oss_irq_pending(irq);
  340. break;
  341. case 4:
  342. if (psc_present)
  343. return psc_irq_pending(irq);
  344. break;
  345. }
  346. return 0;
  347. }
  348. EXPORT_SYMBOL(mac_irq_pending);
  349. static int num_debug[8];
  350. irqreturn_t mac_debug_handler(int irq, void *dev_id)
  351. {
  352. if (num_debug[irq] < 10) {
  353. printk("DEBUG: Unexpected IRQ %d\n", irq);
  354. num_debug[irq]++;
  355. }
  356. return IRQ_HANDLED;
  357. }
  358. static int in_nmi;
  359. static volatile int nmi_hold;
  360. irqreturn_t mac_nmi_handler(int irq, void *dev_id)
  361. {
  362. int i;
  363. /*
  364. * generate debug output on NMI switch if 'debug' kernel option given
  365. * (only works with Penguin!)
  366. */
  367. in_nmi++;
  368. for (i=0; i<100; i++)
  369. udelay(1000);
  370. if (in_nmi == 1) {
  371. nmi_hold = 1;
  372. printk("... pausing, press NMI to resume ...");
  373. } else {
  374. printk(" ok!\n");
  375. nmi_hold = 0;
  376. }
  377. barrier();
  378. while (nmi_hold == 1)
  379. udelay(1000);
  380. if (console_loglevel >= 8) {
  381. #if 0
  382. struct pt_regs *fp = get_irq_regs();
  383. show_state();
  384. printk("PC: %08lx\nSR: %04x SP: %p\n", fp->pc, fp->sr, fp);
  385. printk("d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
  386. fp->d0, fp->d1, fp->d2, fp->d3);
  387. printk("d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
  388. fp->d4, fp->d5, fp->a0, fp->a1);
  389. if (STACK_MAGIC != *(unsigned long *)current->kernel_stack_page)
  390. printk("Corrupted stack page\n");
  391. printk("Process %s (pid: %d, stackpage=%08lx)\n",
  392. current->comm, current->pid, current->kernel_stack_page);
  393. if (intr_count == 1)
  394. dump_stack((struct frame *)fp);
  395. #else
  396. /* printk("NMI "); */
  397. #endif
  398. }
  399. in_nmi--;
  400. return IRQ_HANDLED;
  401. }