ezbrd.c 19 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/export.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mtd/mtd.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/mtd/physmap.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/spi/flash.h>
  16. #include <linux/i2c.h>
  17. #include <linux/irq.h>
  18. #include <linux/interrupt.h>
  19. #include <asm/dma.h>
  20. #include <asm/bfin5xx_spi.h>
  21. #include <asm/reboot.h>
  22. #include <asm/portmux.h>
  23. #include <asm/dpmc.h>
  24. #include <asm/bfin_sdh.h>
  25. #include <linux/spi/ad7877.h>
  26. #include <net/dsa.h>
  27. /*
  28. * Name the Board for the /proc/cpuinfo
  29. */
  30. const char bfin_board_name[] = "ADI BF518F-EZBRD";
  31. /*
  32. * Driver needs to know address, irq and flag pin.
  33. */
  34. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  35. static struct mtd_partition ezbrd_partitions[] = {
  36. {
  37. .name = "bootloader(nor)",
  38. .size = 0x40000,
  39. .offset = 0,
  40. }, {
  41. .name = "linux kernel(nor)",
  42. .size = 0x1C0000,
  43. .offset = MTDPART_OFS_APPEND,
  44. }, {
  45. .name = "file system(nor)",
  46. .size = MTDPART_SIZ_FULL,
  47. .offset = MTDPART_OFS_APPEND,
  48. }
  49. };
  50. static struct physmap_flash_data ezbrd_flash_data = {
  51. .width = 2,
  52. .parts = ezbrd_partitions,
  53. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  54. };
  55. static struct resource ezbrd_flash_resource = {
  56. .start = 0x20000000,
  57. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  58. .end = 0x202fffff,
  59. #else
  60. .end = 0x203fffff,
  61. #endif
  62. .flags = IORESOURCE_MEM,
  63. };
  64. static struct platform_device ezbrd_flash_device = {
  65. .name = "physmap-flash",
  66. .id = 0,
  67. .dev = {
  68. .platform_data = &ezbrd_flash_data,
  69. },
  70. .num_resources = 1,
  71. .resource = &ezbrd_flash_resource,
  72. };
  73. #endif
  74. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  75. static struct platform_device rtc_device = {
  76. .name = "rtc-bfin",
  77. .id = -1,
  78. };
  79. #endif
  80. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  81. #include <linux/bfin_mac.h>
  82. static const unsigned short bfin_mac_peripherals[] = {
  83. P_MII0_ETxD0,
  84. P_MII0_ETxD1,
  85. P_MII0_ETxEN,
  86. P_MII0_ERxD0,
  87. P_MII0_ERxD1,
  88. P_MII0_TxCLK,
  89. P_MII0_PHYINT,
  90. P_MII0_CRS,
  91. P_MII0_MDC,
  92. P_MII0_MDIO,
  93. 0
  94. };
  95. static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  96. {
  97. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  98. .addr = 3,
  99. #else
  100. .addr = 1,
  101. #endif
  102. .irq = IRQ_MAC_PHYINT,
  103. },
  104. };
  105. static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  106. .phydev_number = 1,
  107. .phydev_data = bfin_phydev_data,
  108. .phy_mode = PHY_INTERFACE_MODE_MII,
  109. .mac_peripherals = bfin_mac_peripherals,
  110. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  111. .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
  112. #endif
  113. };
  114. static struct platform_device bfin_mii_bus = {
  115. .name = "bfin_mii_bus",
  116. .dev = {
  117. .platform_data = &bfin_mii_bus_data,
  118. }
  119. };
  120. static struct platform_device bfin_mac_device = {
  121. .name = "bfin_mac",
  122. .dev = {
  123. .platform_data = &bfin_mii_bus,
  124. }
  125. };
  126. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  127. static struct dsa_chip_data ksz8893m_switch_chip_data = {
  128. .mii_bus = &bfin_mii_bus.dev,
  129. .port_names = {
  130. NULL,
  131. "eth%d",
  132. "eth%d",
  133. "cpu",
  134. },
  135. };
  136. static struct dsa_platform_data ksz8893m_switch_data = {
  137. .nr_chips = 1,
  138. .netdev = &bfin_mac_device.dev,
  139. .chip = &ksz8893m_switch_chip_data,
  140. };
  141. static struct platform_device ksz8893m_switch_device = {
  142. .name = "dsa",
  143. .id = 0,
  144. .num_resources = 0,
  145. .dev.platform_data = &ksz8893m_switch_data,
  146. };
  147. #endif
  148. #endif
  149. #if defined(CONFIG_MTD_M25P80) \
  150. || defined(CONFIG_MTD_M25P80_MODULE)
  151. static struct mtd_partition bfin_spi_flash_partitions[] = {
  152. {
  153. .name = "bootloader(spi)",
  154. .size = 0x00040000,
  155. .offset = 0,
  156. .mask_flags = MTD_CAP_ROM
  157. }, {
  158. .name = "linux kernel(spi)",
  159. .size = MTDPART_SIZ_FULL,
  160. .offset = MTDPART_OFS_APPEND,
  161. }
  162. };
  163. static struct flash_platform_data bfin_spi_flash_data = {
  164. .name = "m25p80",
  165. .parts = bfin_spi_flash_partitions,
  166. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  167. .type = "m25p16",
  168. };
  169. /* SPI flash chip (m25p64) */
  170. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  171. .enable_dma = 0, /* use dma transfer with this chip*/
  172. };
  173. #endif
  174. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  175. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  176. .enable_dma = 0,
  177. };
  178. #endif
  179. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  180. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  181. .model = 7877,
  182. .vref_delay_usecs = 50, /* internal, no capacitor */
  183. .x_plate_ohms = 419,
  184. .y_plate_ohms = 486,
  185. .pressure_max = 1000,
  186. .pressure_min = 0,
  187. .stopacq_polarity = 1,
  188. .first_conversion_delay = 3,
  189. .acquisition_time = 1,
  190. .averaging = 1,
  191. .pen_down_acc_interval = 1,
  192. };
  193. #endif
  194. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  195. #if defined(CONFIG_MTD_M25P80) \
  196. || defined(CONFIG_MTD_M25P80_MODULE)
  197. {
  198. /* the modalias must be the same as spi device driver name */
  199. .modalias = "m25p80", /* Name of spi_driver for this device */
  200. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  201. .bus_num = 0, /* Framework bus number */
  202. .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
  203. .platform_data = &bfin_spi_flash_data,
  204. .controller_data = &spi_flash_chip_info,
  205. .mode = SPI_MODE_3,
  206. },
  207. #endif
  208. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  209. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  210. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  211. {
  212. .modalias = "ksz8893m",
  213. .max_speed_hz = 5000000,
  214. .bus_num = 0,
  215. .chip_select = 1,
  216. .platform_data = NULL,
  217. .mode = SPI_MODE_3,
  218. },
  219. #endif
  220. #endif
  221. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  222. {
  223. .modalias = "mmc_spi",
  224. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  225. .bus_num = 0,
  226. .chip_select = 5,
  227. .controller_data = &mmc_spi_chip_info,
  228. .mode = SPI_MODE_3,
  229. },
  230. #endif
  231. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  232. {
  233. .modalias = "ad7877",
  234. .platform_data = &bfin_ad7877_ts_info,
  235. .irq = IRQ_PF8,
  236. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  237. .bus_num = 0,
  238. .chip_select = 2,
  239. },
  240. #endif
  241. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  242. && defined(CONFIG_SND_SOC_WM8731_SPI)
  243. {
  244. .modalias = "wm8731",
  245. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  246. .bus_num = 0,
  247. .chip_select = 5,
  248. .mode = SPI_MODE_0,
  249. },
  250. #endif
  251. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  252. {
  253. .modalias = "spidev",
  254. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  255. .bus_num = 0,
  256. .chip_select = 1,
  257. },
  258. #endif
  259. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  260. {
  261. .modalias = "bfin-lq035q1-spi",
  262. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  263. .bus_num = 0,
  264. .chip_select = 1,
  265. .mode = SPI_CPHA | SPI_CPOL,
  266. },
  267. #endif
  268. };
  269. /* SPI controller data */
  270. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  271. /* SPI (0) */
  272. static struct bfin5xx_spi_master bfin_spi0_info = {
  273. .num_chipselect = 6,
  274. .enable_dma = 1, /* master has the ability to do dma transfer */
  275. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  276. };
  277. static struct resource bfin_spi0_resource[] = {
  278. [0] = {
  279. .start = SPI0_REGBASE,
  280. .end = SPI0_REGBASE + 0xFF,
  281. .flags = IORESOURCE_MEM,
  282. },
  283. [1] = {
  284. .start = CH_SPI0,
  285. .end = CH_SPI0,
  286. .flags = IORESOURCE_DMA,
  287. },
  288. [2] = {
  289. .start = IRQ_SPI0,
  290. .end = IRQ_SPI0,
  291. .flags = IORESOURCE_IRQ,
  292. },
  293. };
  294. static struct platform_device bfin_spi0_device = {
  295. .name = "bfin-spi",
  296. .id = 0, /* Bus number */
  297. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  298. .resource = bfin_spi0_resource,
  299. .dev = {
  300. .platform_data = &bfin_spi0_info, /* Passed to driver */
  301. },
  302. };
  303. /* SPI (1) */
  304. static struct bfin5xx_spi_master bfin_spi1_info = {
  305. .num_chipselect = 6,
  306. .enable_dma = 1, /* master has the ability to do dma transfer */
  307. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  308. };
  309. static struct resource bfin_spi1_resource[] = {
  310. [0] = {
  311. .start = SPI1_REGBASE,
  312. .end = SPI1_REGBASE + 0xFF,
  313. .flags = IORESOURCE_MEM,
  314. },
  315. [1] = {
  316. .start = CH_SPI1,
  317. .end = CH_SPI1,
  318. .flags = IORESOURCE_DMA,
  319. },
  320. [2] = {
  321. .start = IRQ_SPI1,
  322. .end = IRQ_SPI1,
  323. .flags = IORESOURCE_IRQ,
  324. },
  325. };
  326. static struct platform_device bfin_spi1_device = {
  327. .name = "bfin-spi",
  328. .id = 1, /* Bus number */
  329. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  330. .resource = bfin_spi1_resource,
  331. .dev = {
  332. .platform_data = &bfin_spi1_info, /* Passed to driver */
  333. },
  334. };
  335. #endif /* spi master and devices */
  336. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  337. #ifdef CONFIG_SERIAL_BFIN_UART0
  338. static struct resource bfin_uart0_resources[] = {
  339. {
  340. .start = UART0_THR,
  341. .end = UART0_GCTL+2,
  342. .flags = IORESOURCE_MEM,
  343. },
  344. {
  345. .start = IRQ_UART0_TX,
  346. .end = IRQ_UART0_TX,
  347. .flags = IORESOURCE_IRQ,
  348. },
  349. {
  350. .start = IRQ_UART0_RX,
  351. .end = IRQ_UART0_RX,
  352. .flags = IORESOURCE_IRQ,
  353. },
  354. {
  355. .start = IRQ_UART0_ERROR,
  356. .end = IRQ_UART0_ERROR,
  357. .flags = IORESOURCE_IRQ,
  358. },
  359. {
  360. .start = CH_UART0_TX,
  361. .end = CH_UART0_TX,
  362. .flags = IORESOURCE_DMA,
  363. },
  364. {
  365. .start = CH_UART0_RX,
  366. .end = CH_UART0_RX,
  367. .flags = IORESOURCE_DMA,
  368. },
  369. };
  370. static unsigned short bfin_uart0_peripherals[] = {
  371. P_UART0_TX, P_UART0_RX, 0
  372. };
  373. static struct platform_device bfin_uart0_device = {
  374. .name = "bfin-uart",
  375. .id = 0,
  376. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  377. .resource = bfin_uart0_resources,
  378. .dev = {
  379. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  380. },
  381. };
  382. #endif
  383. #ifdef CONFIG_SERIAL_BFIN_UART1
  384. static struct resource bfin_uart1_resources[] = {
  385. {
  386. .start = UART1_THR,
  387. .end = UART1_GCTL+2,
  388. .flags = IORESOURCE_MEM,
  389. },
  390. {
  391. .start = IRQ_UART1_TX,
  392. .end = IRQ_UART1_TX,
  393. .flags = IORESOURCE_IRQ,
  394. },
  395. {
  396. .start = IRQ_UART1_RX,
  397. .end = IRQ_UART1_RX,
  398. .flags = IORESOURCE_IRQ,
  399. },
  400. {
  401. .start = IRQ_UART1_ERROR,
  402. .end = IRQ_UART1_ERROR,
  403. .flags = IORESOURCE_IRQ,
  404. },
  405. {
  406. .start = CH_UART1_TX,
  407. .end = CH_UART1_TX,
  408. .flags = IORESOURCE_DMA,
  409. },
  410. {
  411. .start = CH_UART1_RX,
  412. .end = CH_UART1_RX,
  413. .flags = IORESOURCE_DMA,
  414. },
  415. };
  416. static unsigned short bfin_uart1_peripherals[] = {
  417. P_UART1_TX, P_UART1_RX, 0
  418. };
  419. static struct platform_device bfin_uart1_device = {
  420. .name = "bfin-uart",
  421. .id = 1,
  422. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  423. .resource = bfin_uart1_resources,
  424. .dev = {
  425. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  426. },
  427. };
  428. #endif
  429. #endif
  430. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  431. #ifdef CONFIG_BFIN_SIR0
  432. static struct resource bfin_sir0_resources[] = {
  433. {
  434. .start = 0xFFC00400,
  435. .end = 0xFFC004FF,
  436. .flags = IORESOURCE_MEM,
  437. },
  438. {
  439. .start = IRQ_UART0_RX,
  440. .end = IRQ_UART0_RX+1,
  441. .flags = IORESOURCE_IRQ,
  442. },
  443. {
  444. .start = CH_UART0_RX,
  445. .end = CH_UART0_RX+1,
  446. .flags = IORESOURCE_DMA,
  447. },
  448. };
  449. static struct platform_device bfin_sir0_device = {
  450. .name = "bfin_sir",
  451. .id = 0,
  452. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  453. .resource = bfin_sir0_resources,
  454. };
  455. #endif
  456. #ifdef CONFIG_BFIN_SIR1
  457. static struct resource bfin_sir1_resources[] = {
  458. {
  459. .start = 0xFFC02000,
  460. .end = 0xFFC020FF,
  461. .flags = IORESOURCE_MEM,
  462. },
  463. {
  464. .start = IRQ_UART1_RX,
  465. .end = IRQ_UART1_RX+1,
  466. .flags = IORESOURCE_IRQ,
  467. },
  468. {
  469. .start = CH_UART1_RX,
  470. .end = CH_UART1_RX+1,
  471. .flags = IORESOURCE_DMA,
  472. },
  473. };
  474. static struct platform_device bfin_sir1_device = {
  475. .name = "bfin_sir",
  476. .id = 1,
  477. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  478. .resource = bfin_sir1_resources,
  479. };
  480. #endif
  481. #endif
  482. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  483. static struct platform_device bfin_i2s = {
  484. .name = "bfin-i2s",
  485. .id = CONFIG_SND_BF5XX_SPORT_NUM,
  486. /* TODO: add platform data here */
  487. };
  488. #endif
  489. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  490. static struct resource bfin_twi0_resource[] = {
  491. [0] = {
  492. .start = TWI0_REGBASE,
  493. .end = TWI0_REGBASE,
  494. .flags = IORESOURCE_MEM,
  495. },
  496. [1] = {
  497. .start = IRQ_TWI,
  498. .end = IRQ_TWI,
  499. .flags = IORESOURCE_IRQ,
  500. },
  501. };
  502. static struct platform_device i2c_bfin_twi_device = {
  503. .name = "i2c-bfin-twi",
  504. .id = 0,
  505. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  506. .resource = bfin_twi0_resource,
  507. };
  508. #endif
  509. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  510. #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
  511. {
  512. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  513. },
  514. #endif
  515. #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
  516. {
  517. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  518. .irq = IRQ_PF8,
  519. },
  520. #endif
  521. #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
  522. {
  523. I2C_BOARD_INFO("ssm2602", 0x1b),
  524. },
  525. #endif
  526. };
  527. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  528. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  529. static struct resource bfin_sport0_uart_resources[] = {
  530. {
  531. .start = SPORT0_TCR1,
  532. .end = SPORT0_MRCS3+4,
  533. .flags = IORESOURCE_MEM,
  534. },
  535. {
  536. .start = IRQ_SPORT0_RX,
  537. .end = IRQ_SPORT0_RX+1,
  538. .flags = IORESOURCE_IRQ,
  539. },
  540. {
  541. .start = IRQ_SPORT0_ERROR,
  542. .end = IRQ_SPORT0_ERROR,
  543. .flags = IORESOURCE_IRQ,
  544. },
  545. };
  546. static unsigned short bfin_sport0_peripherals[] = {
  547. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  548. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  549. };
  550. static struct platform_device bfin_sport0_uart_device = {
  551. .name = "bfin-sport-uart",
  552. .id = 0,
  553. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  554. .resource = bfin_sport0_uart_resources,
  555. .dev = {
  556. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  557. },
  558. };
  559. #endif
  560. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  561. static struct resource bfin_sport1_uart_resources[] = {
  562. {
  563. .start = SPORT1_TCR1,
  564. .end = SPORT1_MRCS3+4,
  565. .flags = IORESOURCE_MEM,
  566. },
  567. {
  568. .start = IRQ_SPORT1_RX,
  569. .end = IRQ_SPORT1_RX+1,
  570. .flags = IORESOURCE_IRQ,
  571. },
  572. {
  573. .start = IRQ_SPORT1_ERROR,
  574. .end = IRQ_SPORT1_ERROR,
  575. .flags = IORESOURCE_IRQ,
  576. },
  577. };
  578. static unsigned short bfin_sport1_peripherals[] = {
  579. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  580. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  581. };
  582. static struct platform_device bfin_sport1_uart_device = {
  583. .name = "bfin-sport-uart",
  584. .id = 1,
  585. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  586. .resource = bfin_sport1_uart_resources,
  587. .dev = {
  588. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  589. },
  590. };
  591. #endif
  592. #endif
  593. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  594. #include <linux/input.h>
  595. #include <linux/gpio_keys.h>
  596. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  597. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  598. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  599. };
  600. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  601. .buttons = bfin_gpio_keys_table,
  602. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  603. };
  604. static struct platform_device bfin_device_gpiokeys = {
  605. .name = "gpio-keys",
  606. .dev = {
  607. .platform_data = &bfin_gpio_keys_data,
  608. },
  609. };
  610. #endif
  611. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  612. static struct bfin_sd_host bfin_sdh_data = {
  613. .dma_chan = CH_RSI,
  614. .irq_int0 = IRQ_RSI_INT0,
  615. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  616. };
  617. static struct platform_device bf51x_sdh_device = {
  618. .name = "bfin-sdh",
  619. .id = 0,
  620. .dev = {
  621. .platform_data = &bfin_sdh_data,
  622. },
  623. };
  624. #endif
  625. static const unsigned int cclk_vlev_datasheet[] =
  626. {
  627. VRPAIR(VLEV_100, 400000000),
  628. VRPAIR(VLEV_105, 426000000),
  629. VRPAIR(VLEV_110, 500000000),
  630. VRPAIR(VLEV_115, 533000000),
  631. VRPAIR(VLEV_120, 600000000),
  632. };
  633. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  634. .tuple_tab = cclk_vlev_datasheet,
  635. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  636. .vr_settling_time = 25 /* us */,
  637. };
  638. static struct platform_device bfin_dpmc = {
  639. .name = "bfin dpmc",
  640. .dev = {
  641. .platform_data = &bfin_dmpc_vreg_data,
  642. },
  643. };
  644. static struct platform_device *stamp_devices[] __initdata = {
  645. &bfin_dpmc,
  646. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  647. &rtc_device,
  648. #endif
  649. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  650. &bfin_mii_bus,
  651. &bfin_mac_device,
  652. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  653. &ksz8893m_switch_device,
  654. #endif
  655. #endif
  656. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  657. &bfin_spi0_device,
  658. &bfin_spi1_device,
  659. #endif
  660. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  661. #ifdef CONFIG_SERIAL_BFIN_UART0
  662. &bfin_uart0_device,
  663. #endif
  664. #ifdef CONFIG_SERIAL_BFIN_UART1
  665. &bfin_uart1_device,
  666. #endif
  667. #endif
  668. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  669. #ifdef CONFIG_BFIN_SIR0
  670. &bfin_sir0_device,
  671. #endif
  672. #ifdef CONFIG_BFIN_SIR1
  673. &bfin_sir1_device,
  674. #endif
  675. #endif
  676. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  677. &i2c_bfin_twi_device,
  678. #endif
  679. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  680. &bfin_i2s,
  681. #endif
  682. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  683. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  684. &bfin_sport0_uart_device,
  685. #endif
  686. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  687. &bfin_sport1_uart_device,
  688. #endif
  689. #endif
  690. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  691. &bfin_device_gpiokeys,
  692. #endif
  693. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  694. &bf51x_sdh_device,
  695. #endif
  696. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  697. &ezbrd_flash_device,
  698. #endif
  699. };
  700. static int __init ezbrd_init(void)
  701. {
  702. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  703. i2c_register_board_info(0, bfin_i2c_board_info,
  704. ARRAY_SIZE(bfin_i2c_board_info));
  705. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  706. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  707. /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
  708. peripheral_request(P_AMS2, "ParaFlash");
  709. #if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
  710. peripheral_request(P_AMS3, "ParaFlash");
  711. #endif
  712. return 0;
  713. }
  714. arch_initcall(ezbrd_init);
  715. static struct platform_device *ezbrd_early_devices[] __initdata = {
  716. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  717. #ifdef CONFIG_SERIAL_BFIN_UART0
  718. &bfin_uart0_device,
  719. #endif
  720. #ifdef CONFIG_SERIAL_BFIN_UART1
  721. &bfin_uart1_device,
  722. #endif
  723. #endif
  724. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  725. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  726. &bfin_sport0_uart_device,
  727. #endif
  728. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  729. &bfin_sport1_uart_device,
  730. #endif
  731. #endif
  732. };
  733. void __init native_machine_early_platform_add_devices(void)
  734. {
  735. printk(KERN_INFO "register early platform devices\n");
  736. early_platform_add_devices(ezbrd_early_devices,
  737. ARRAY_SIZE(ezbrd_early_devices));
  738. }
  739. void native_machine_restart(char *cmd)
  740. {
  741. /* workaround reboot hang when booting from SPI */
  742. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  743. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  744. }
  745. void bfin_get_ether_addr(char *addr)
  746. {
  747. /* the MAC is stored in OTP memory page 0xDF */
  748. u32 ret;
  749. u64 otp_mac;
  750. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  751. ret = otp_read(0xDF, 0x00, &otp_mac);
  752. if (!(ret & 0x1)) {
  753. char *otp_mac_p = (char *)&otp_mac;
  754. for (ret = 0; ret < 6; ++ret)
  755. addr[ret] = otp_mac_p[5 - ret];
  756. }
  757. }
  758. EXPORT_SYMBOL(bfin_get_ether_addr);