io.h 2.7 KB

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  1. /*
  2. * arch/arm/mach-tegra/include/mach/io.h
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. *
  6. * Author:
  7. * Colin Cross <ccross@google.com>
  8. * Erik Gilling <konkers@google.com>
  9. *
  10. * This software is licensed under the terms of the GNU General Public
  11. * License version 2, as published by the Free Software Foundation, and
  12. * may be copied, distributed, and modified under those terms.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. */
  20. #ifndef __MACH_TEGRA_IO_H
  21. #define __MACH_TEGRA_IO_H
  22. #define IO_SPACE_LIMIT 0xffff
  23. /* On TEGRA, many peripherals are very closely packed in
  24. * two 256MB io windows (that actually only use about 64KB
  25. * at the start of each).
  26. *
  27. * We will just map the first 1MB of each window (to minimize
  28. * pt entries needed) and provide a macro to transform physical
  29. * io addresses to an appropriate void __iomem *.
  30. *
  31. */
  32. #ifdef __ASSEMBLY__
  33. #define IOMEM(x) (x)
  34. #else
  35. #define IOMEM(x) ((void __force __iomem *)(x))
  36. #endif
  37. #define IO_IRAM_PHYS 0x40000000
  38. #define IO_IRAM_VIRT IOMEM(0xFE400000)
  39. #define IO_IRAM_SIZE SZ_256K
  40. #define IO_CPU_PHYS 0x50040000
  41. #define IO_CPU_VIRT IOMEM(0xFE000000)
  42. #define IO_CPU_SIZE SZ_16K
  43. #define IO_PPSB_PHYS 0x60000000
  44. #define IO_PPSB_VIRT IOMEM(0xFE200000)
  45. #define IO_PPSB_SIZE SZ_1M
  46. #define IO_APB_PHYS 0x70000000
  47. #define IO_APB_VIRT IOMEM(0xFE300000)
  48. #define IO_APB_SIZE SZ_1M
  49. #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
  50. #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
  51. #define IO_TO_VIRT(n) ( \
  52. IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
  53. IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
  54. IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
  55. IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
  56. IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
  57. IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
  58. IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
  59. IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
  60. NULL)
  61. #ifndef __ASSEMBLER__
  62. #define __arch_ioremap tegra_ioremap
  63. #define __arch_iounmap tegra_iounmap
  64. void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
  65. void tegra_iounmap(volatile void __iomem *addr);
  66. #define IO_ADDRESS(n) (IO_TO_VIRT(n))
  67. #ifdef CONFIG_TEGRA_PCI
  68. extern void __iomem *tegra_pcie_io_base;
  69. static inline void __iomem *__io(unsigned long addr)
  70. {
  71. return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
  72. }
  73. #else
  74. static inline void __iomem *__io(unsigned long addr)
  75. {
  76. return (void __iomem *)addr;
  77. }
  78. #endif
  79. #define __io(a) __io(a)
  80. #define __mem_pci(a) (a)
  81. #endif
  82. #endif