clock.c 31 KB

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  1. /* linux/arch/arm/mach-s5pv210/clock.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * S5PV210 - Clock support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/list.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/sysdev.h>
  20. #include <linux/io.h>
  21. #include <mach/map.h>
  22. #include <plat/cpu-freq.h>
  23. #include <mach/regs-clock.h>
  24. #include <plat/clock.h>
  25. #include <plat/cpu.h>
  26. #include <plat/pll.h>
  27. #include <plat/s5p-clock.h>
  28. #include <plat/clock-clksrc.h>
  29. #include <plat/s5pv210.h>
  30. static unsigned long xtal;
  31. static struct clksrc_clk clk_mout_apll = {
  32. .clk = {
  33. .name = "mout_apll",
  34. },
  35. .sources = &clk_src_apll,
  36. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  37. };
  38. static struct clksrc_clk clk_mout_epll = {
  39. .clk = {
  40. .name = "mout_epll",
  41. },
  42. .sources = &clk_src_epll,
  43. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  44. };
  45. static struct clksrc_clk clk_mout_mpll = {
  46. .clk = {
  47. .name = "mout_mpll",
  48. },
  49. .sources = &clk_src_mpll,
  50. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  51. };
  52. static struct clk *clkset_armclk_list[] = {
  53. [0] = &clk_mout_apll.clk,
  54. [1] = &clk_mout_mpll.clk,
  55. };
  56. static struct clksrc_sources clkset_armclk = {
  57. .sources = clkset_armclk_list,
  58. .nr_sources = ARRAY_SIZE(clkset_armclk_list),
  59. };
  60. static struct clksrc_clk clk_armclk = {
  61. .clk = {
  62. .name = "armclk",
  63. },
  64. .sources = &clkset_armclk,
  65. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  66. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  67. };
  68. static struct clksrc_clk clk_hclk_msys = {
  69. .clk = {
  70. .name = "hclk_msys",
  71. .parent = &clk_armclk.clk,
  72. },
  73. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  74. };
  75. static struct clksrc_clk clk_pclk_msys = {
  76. .clk = {
  77. .name = "pclk_msys",
  78. .parent = &clk_hclk_msys.clk,
  79. },
  80. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  81. };
  82. static struct clksrc_clk clk_sclk_a2m = {
  83. .clk = {
  84. .name = "sclk_a2m",
  85. .parent = &clk_mout_apll.clk,
  86. },
  87. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
  88. };
  89. static struct clk *clkset_hclk_sys_list[] = {
  90. [0] = &clk_mout_mpll.clk,
  91. [1] = &clk_sclk_a2m.clk,
  92. };
  93. static struct clksrc_sources clkset_hclk_sys = {
  94. .sources = clkset_hclk_sys_list,
  95. .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
  96. };
  97. static struct clksrc_clk clk_hclk_dsys = {
  98. .clk = {
  99. .name = "hclk_dsys",
  100. },
  101. .sources = &clkset_hclk_sys,
  102. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
  103. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
  104. };
  105. static struct clksrc_clk clk_pclk_dsys = {
  106. .clk = {
  107. .name = "pclk_dsys",
  108. .parent = &clk_hclk_dsys.clk,
  109. },
  110. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
  111. };
  112. static struct clksrc_clk clk_hclk_psys = {
  113. .clk = {
  114. .name = "hclk_psys",
  115. },
  116. .sources = &clkset_hclk_sys,
  117. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
  118. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
  119. };
  120. static struct clksrc_clk clk_pclk_psys = {
  121. .clk = {
  122. .name = "pclk_psys",
  123. .parent = &clk_hclk_psys.clk,
  124. },
  125. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
  126. };
  127. static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
  128. {
  129. return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
  130. }
  131. static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
  132. {
  133. return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
  134. }
  135. static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
  136. {
  137. return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
  138. }
  139. static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
  140. {
  141. return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
  142. }
  143. static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
  144. {
  145. return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
  146. }
  147. static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
  148. {
  149. return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
  150. }
  151. static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
  152. {
  153. return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
  154. }
  155. static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
  156. {
  157. return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
  158. }
  159. static struct clk clk_sclk_hdmi27m = {
  160. .name = "sclk_hdmi27m",
  161. .rate = 27000000,
  162. };
  163. static struct clk clk_sclk_hdmiphy = {
  164. .name = "sclk_hdmiphy",
  165. };
  166. static struct clk clk_sclk_usbphy0 = {
  167. .name = "sclk_usbphy0",
  168. };
  169. static struct clk clk_sclk_usbphy1 = {
  170. .name = "sclk_usbphy1",
  171. };
  172. static struct clk clk_pcmcdclk0 = {
  173. .name = "pcmcdclk",
  174. };
  175. static struct clk clk_pcmcdclk1 = {
  176. .name = "pcmcdclk",
  177. };
  178. static struct clk clk_pcmcdclk2 = {
  179. .name = "pcmcdclk",
  180. };
  181. static struct clk dummy_apb_pclk = {
  182. .name = "apb_pclk",
  183. .id = -1,
  184. };
  185. static struct clk *clkset_vpllsrc_list[] = {
  186. [0] = &clk_fin_vpll,
  187. [1] = &clk_sclk_hdmi27m,
  188. };
  189. static struct clksrc_sources clkset_vpllsrc = {
  190. .sources = clkset_vpllsrc_list,
  191. .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
  192. };
  193. static struct clksrc_clk clk_vpllsrc = {
  194. .clk = {
  195. .name = "vpll_src",
  196. .enable = s5pv210_clk_mask0_ctrl,
  197. .ctrlbit = (1 << 7),
  198. },
  199. .sources = &clkset_vpllsrc,
  200. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
  201. };
  202. static struct clk *clkset_sclk_vpll_list[] = {
  203. [0] = &clk_vpllsrc.clk,
  204. [1] = &clk_fout_vpll,
  205. };
  206. static struct clksrc_sources clkset_sclk_vpll = {
  207. .sources = clkset_sclk_vpll_list,
  208. .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
  209. };
  210. static struct clksrc_clk clk_sclk_vpll = {
  211. .clk = {
  212. .name = "sclk_vpll",
  213. },
  214. .sources = &clkset_sclk_vpll,
  215. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
  216. };
  217. static struct clk *clkset_moutdmc0src_list[] = {
  218. [0] = &clk_sclk_a2m.clk,
  219. [1] = &clk_mout_mpll.clk,
  220. [2] = NULL,
  221. [3] = NULL,
  222. };
  223. static struct clksrc_sources clkset_moutdmc0src = {
  224. .sources = clkset_moutdmc0src_list,
  225. .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
  226. };
  227. static struct clksrc_clk clk_mout_dmc0 = {
  228. .clk = {
  229. .name = "mout_dmc0",
  230. },
  231. .sources = &clkset_moutdmc0src,
  232. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
  233. };
  234. static struct clksrc_clk clk_sclk_dmc0 = {
  235. .clk = {
  236. .name = "sclk_dmc0",
  237. .parent = &clk_mout_dmc0.clk,
  238. },
  239. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
  240. };
  241. static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
  242. {
  243. return clk_get_rate(clk->parent) / 2;
  244. }
  245. static struct clk_ops clk_hclk_imem_ops = {
  246. .get_rate = s5pv210_clk_imem_get_rate,
  247. };
  248. static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
  249. {
  250. return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
  251. }
  252. static struct clk_ops clk_fout_apll_ops = {
  253. .get_rate = s5pv210_clk_fout_apll_get_rate,
  254. };
  255. static struct clk init_clocks_off[] = {
  256. {
  257. .name = "dma",
  258. .devname = "dma-pl330.0",
  259. .parent = &clk_hclk_psys.clk,
  260. .enable = s5pv210_clk_ip0_ctrl,
  261. .ctrlbit = (1 << 3),
  262. }, {
  263. .name = "dma",
  264. .devname = "dma-pl330.1",
  265. .parent = &clk_hclk_psys.clk,
  266. .enable = s5pv210_clk_ip0_ctrl,
  267. .ctrlbit = (1 << 4),
  268. }, {
  269. .name = "rot",
  270. .parent = &clk_hclk_dsys.clk,
  271. .enable = s5pv210_clk_ip0_ctrl,
  272. .ctrlbit = (1<<29),
  273. }, {
  274. .name = "fimc",
  275. .devname = "s5pv210-fimc.0",
  276. .parent = &clk_hclk_dsys.clk,
  277. .enable = s5pv210_clk_ip0_ctrl,
  278. .ctrlbit = (1 << 24),
  279. }, {
  280. .name = "fimc",
  281. .devname = "s5pv210-fimc.1",
  282. .parent = &clk_hclk_dsys.clk,
  283. .enable = s5pv210_clk_ip0_ctrl,
  284. .ctrlbit = (1 << 25),
  285. }, {
  286. .name = "fimc",
  287. .devname = "s5pv210-fimc.2",
  288. .parent = &clk_hclk_dsys.clk,
  289. .enable = s5pv210_clk_ip0_ctrl,
  290. .ctrlbit = (1 << 26),
  291. }, {
  292. .name = "mfc",
  293. .devname = "s5p-mfc",
  294. .parent = &clk_pclk_psys.clk,
  295. .enable = s5pv210_clk_ip0_ctrl,
  296. .ctrlbit = (1 << 16),
  297. }, {
  298. .name = "dac",
  299. .devname = "s5p-sdo",
  300. .parent = &clk_hclk_dsys.clk,
  301. .enable = s5pv210_clk_ip1_ctrl,
  302. .ctrlbit = (1 << 10),
  303. }, {
  304. .name = "mixer",
  305. .devname = "s5p-mixer",
  306. .parent = &clk_hclk_dsys.clk,
  307. .enable = s5pv210_clk_ip1_ctrl,
  308. .ctrlbit = (1 << 9),
  309. }, {
  310. .name = "vp",
  311. .devname = "s5p-mixer",
  312. .parent = &clk_hclk_dsys.clk,
  313. .enable = s5pv210_clk_ip1_ctrl,
  314. .ctrlbit = (1 << 8),
  315. }, {
  316. .name = "hdmi",
  317. .devname = "s5pv210-hdmi",
  318. .parent = &clk_hclk_dsys.clk,
  319. .enable = s5pv210_clk_ip1_ctrl,
  320. .ctrlbit = (1 << 11),
  321. }, {
  322. .name = "hdmiphy",
  323. .devname = "s5pv210-hdmi",
  324. .enable = exynos4_clk_hdmiphy_ctrl,
  325. .ctrlbit = (1 << 0),
  326. }, {
  327. .name = "dacphy",
  328. .devname = "s5p-sdo",
  329. .enable = exynos4_clk_dac_ctrl,
  330. .ctrlbit = (1 << 0),
  331. }, {
  332. .name = "otg",
  333. .parent = &clk_hclk_psys.clk,
  334. .enable = s5pv210_clk_ip1_ctrl,
  335. .ctrlbit = (1<<16),
  336. }, {
  337. .name = "usb-host",
  338. .parent = &clk_hclk_psys.clk,
  339. .enable = s5pv210_clk_ip1_ctrl,
  340. .ctrlbit = (1<<17),
  341. }, {
  342. .name = "lcd",
  343. .parent = &clk_hclk_dsys.clk,
  344. .enable = s5pv210_clk_ip1_ctrl,
  345. .ctrlbit = (1<<0),
  346. }, {
  347. .name = "cfcon",
  348. .parent = &clk_hclk_psys.clk,
  349. .enable = s5pv210_clk_ip1_ctrl,
  350. .ctrlbit = (1<<25),
  351. }, {
  352. .name = "hsmmc",
  353. .devname = "s3c-sdhci.0",
  354. .parent = &clk_hclk_psys.clk,
  355. .enable = s5pv210_clk_ip2_ctrl,
  356. .ctrlbit = (1<<16),
  357. }, {
  358. .name = "hsmmc",
  359. .devname = "s3c-sdhci.1",
  360. .parent = &clk_hclk_psys.clk,
  361. .enable = s5pv210_clk_ip2_ctrl,
  362. .ctrlbit = (1<<17),
  363. }, {
  364. .name = "hsmmc",
  365. .devname = "s3c-sdhci.2",
  366. .parent = &clk_hclk_psys.clk,
  367. .enable = s5pv210_clk_ip2_ctrl,
  368. .ctrlbit = (1<<18),
  369. }, {
  370. .name = "hsmmc",
  371. .devname = "s3c-sdhci.3",
  372. .parent = &clk_hclk_psys.clk,
  373. .enable = s5pv210_clk_ip2_ctrl,
  374. .ctrlbit = (1<<19),
  375. }, {
  376. .name = "systimer",
  377. .parent = &clk_pclk_psys.clk,
  378. .enable = s5pv210_clk_ip3_ctrl,
  379. .ctrlbit = (1<<16),
  380. }, {
  381. .name = "watchdog",
  382. .parent = &clk_pclk_psys.clk,
  383. .enable = s5pv210_clk_ip3_ctrl,
  384. .ctrlbit = (1<<22),
  385. }, {
  386. .name = "rtc",
  387. .parent = &clk_pclk_psys.clk,
  388. .enable = s5pv210_clk_ip3_ctrl,
  389. .ctrlbit = (1<<15),
  390. }, {
  391. .name = "i2c",
  392. .devname = "s3c2440-i2c.0",
  393. .parent = &clk_pclk_psys.clk,
  394. .enable = s5pv210_clk_ip3_ctrl,
  395. .ctrlbit = (1<<7),
  396. }, {
  397. .name = "i2c",
  398. .devname = "s3c2440-i2c.1",
  399. .parent = &clk_pclk_psys.clk,
  400. .enable = s5pv210_clk_ip3_ctrl,
  401. .ctrlbit = (1 << 10),
  402. }, {
  403. .name = "i2c",
  404. .devname = "s3c2440-i2c.2",
  405. .parent = &clk_pclk_psys.clk,
  406. .enable = s5pv210_clk_ip3_ctrl,
  407. .ctrlbit = (1<<9),
  408. }, {
  409. .name = "i2c",
  410. .devname = "s3c2440-hdmiphy-i2c",
  411. .parent = &clk_pclk_psys.clk,
  412. .enable = s5pv210_clk_ip3_ctrl,
  413. .ctrlbit = (1 << 11),
  414. }, {
  415. .name = "spi",
  416. .devname = "s3c64xx-spi.0",
  417. .parent = &clk_pclk_psys.clk,
  418. .enable = s5pv210_clk_ip3_ctrl,
  419. .ctrlbit = (1<<12),
  420. }, {
  421. .name = "spi",
  422. .devname = "s3c64xx-spi.1",
  423. .parent = &clk_pclk_psys.clk,
  424. .enable = s5pv210_clk_ip3_ctrl,
  425. .ctrlbit = (1<<13),
  426. }, {
  427. .name = "spi",
  428. .devname = "s3c64xx-spi.2",
  429. .parent = &clk_pclk_psys.clk,
  430. .enable = s5pv210_clk_ip3_ctrl,
  431. .ctrlbit = (1<<14),
  432. }, {
  433. .name = "timers",
  434. .parent = &clk_pclk_psys.clk,
  435. .enable = s5pv210_clk_ip3_ctrl,
  436. .ctrlbit = (1<<23),
  437. }, {
  438. .name = "adc",
  439. .parent = &clk_pclk_psys.clk,
  440. .enable = s5pv210_clk_ip3_ctrl,
  441. .ctrlbit = (1<<24),
  442. }, {
  443. .name = "keypad",
  444. .parent = &clk_pclk_psys.clk,
  445. .enable = s5pv210_clk_ip3_ctrl,
  446. .ctrlbit = (1<<21),
  447. }, {
  448. .name = "iis",
  449. .devname = "samsung-i2s.0",
  450. .parent = &clk_p,
  451. .enable = s5pv210_clk_ip3_ctrl,
  452. .ctrlbit = (1<<4),
  453. }, {
  454. .name = "iis",
  455. .devname = "samsung-i2s.1",
  456. .parent = &clk_p,
  457. .enable = s5pv210_clk_ip3_ctrl,
  458. .ctrlbit = (1 << 5),
  459. }, {
  460. .name = "iis",
  461. .devname = "samsung-i2s.2",
  462. .parent = &clk_p,
  463. .enable = s5pv210_clk_ip3_ctrl,
  464. .ctrlbit = (1 << 6),
  465. }, {
  466. .name = "spdif",
  467. .parent = &clk_p,
  468. .enable = s5pv210_clk_ip3_ctrl,
  469. .ctrlbit = (1 << 0),
  470. },
  471. };
  472. static struct clk init_clocks[] = {
  473. {
  474. .name = "hclk_imem",
  475. .parent = &clk_hclk_msys.clk,
  476. .ctrlbit = (1 << 5),
  477. .enable = s5pv210_clk_ip0_ctrl,
  478. .ops = &clk_hclk_imem_ops,
  479. }, {
  480. .name = "uart",
  481. .devname = "s5pv210-uart.0",
  482. .parent = &clk_pclk_psys.clk,
  483. .enable = s5pv210_clk_ip3_ctrl,
  484. .ctrlbit = (1 << 17),
  485. }, {
  486. .name = "uart",
  487. .devname = "s5pv210-uart.1",
  488. .parent = &clk_pclk_psys.clk,
  489. .enable = s5pv210_clk_ip3_ctrl,
  490. .ctrlbit = (1 << 18),
  491. }, {
  492. .name = "uart",
  493. .devname = "s5pv210-uart.2",
  494. .parent = &clk_pclk_psys.clk,
  495. .enable = s5pv210_clk_ip3_ctrl,
  496. .ctrlbit = (1 << 19),
  497. }, {
  498. .name = "uart",
  499. .devname = "s5pv210-uart.3",
  500. .parent = &clk_pclk_psys.clk,
  501. .enable = s5pv210_clk_ip3_ctrl,
  502. .ctrlbit = (1 << 20),
  503. }, {
  504. .name = "sromc",
  505. .parent = &clk_hclk_psys.clk,
  506. .enable = s5pv210_clk_ip1_ctrl,
  507. .ctrlbit = (1 << 26),
  508. },
  509. };
  510. static struct clk *clkset_uart_list[] = {
  511. [6] = &clk_mout_mpll.clk,
  512. [7] = &clk_mout_epll.clk,
  513. };
  514. static struct clksrc_sources clkset_uart = {
  515. .sources = clkset_uart_list,
  516. .nr_sources = ARRAY_SIZE(clkset_uart_list),
  517. };
  518. static struct clk *clkset_group1_list[] = {
  519. [0] = &clk_sclk_a2m.clk,
  520. [1] = &clk_mout_mpll.clk,
  521. [2] = &clk_mout_epll.clk,
  522. [3] = &clk_sclk_vpll.clk,
  523. };
  524. static struct clksrc_sources clkset_group1 = {
  525. .sources = clkset_group1_list,
  526. .nr_sources = ARRAY_SIZE(clkset_group1_list),
  527. };
  528. static struct clk *clkset_sclk_onenand_list[] = {
  529. [0] = &clk_hclk_psys.clk,
  530. [1] = &clk_hclk_dsys.clk,
  531. };
  532. static struct clksrc_sources clkset_sclk_onenand = {
  533. .sources = clkset_sclk_onenand_list,
  534. .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
  535. };
  536. static struct clk *clkset_sclk_dac_list[] = {
  537. [0] = &clk_sclk_vpll.clk,
  538. [1] = &clk_sclk_hdmiphy,
  539. };
  540. static struct clksrc_sources clkset_sclk_dac = {
  541. .sources = clkset_sclk_dac_list,
  542. .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
  543. };
  544. static struct clksrc_clk clk_sclk_dac = {
  545. .clk = {
  546. .name = "sclk_dac",
  547. .enable = s5pv210_clk_mask0_ctrl,
  548. .ctrlbit = (1 << 2),
  549. },
  550. .sources = &clkset_sclk_dac,
  551. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
  552. };
  553. static struct clksrc_clk clk_sclk_pixel = {
  554. .clk = {
  555. .name = "sclk_pixel",
  556. .parent = &clk_sclk_vpll.clk,
  557. },
  558. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
  559. };
  560. static struct clk *clkset_sclk_hdmi_list[] = {
  561. [0] = &clk_sclk_pixel.clk,
  562. [1] = &clk_sclk_hdmiphy,
  563. };
  564. static struct clksrc_sources clkset_sclk_hdmi = {
  565. .sources = clkset_sclk_hdmi_list,
  566. .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
  567. };
  568. static struct clksrc_clk clk_sclk_hdmi = {
  569. .clk = {
  570. .name = "sclk_hdmi",
  571. .enable = s5pv210_clk_mask0_ctrl,
  572. .ctrlbit = (1 << 0),
  573. },
  574. .sources = &clkset_sclk_hdmi,
  575. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
  576. };
  577. static struct clk *clkset_sclk_mixer_list[] = {
  578. [0] = &clk_sclk_dac.clk,
  579. [1] = &clk_sclk_hdmi.clk,
  580. };
  581. static struct clksrc_sources clkset_sclk_mixer = {
  582. .sources = clkset_sclk_mixer_list,
  583. .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
  584. };
  585. static struct clksrc_clk clk_sclk_mixer = {
  586. .clk = {
  587. .name = "sclk_mixer",
  588. .enable = s5pv210_clk_mask0_ctrl,
  589. .ctrlbit = (1 << 1),
  590. },
  591. .sources = &clkset_sclk_mixer,
  592. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
  593. };
  594. static struct clksrc_clk *sclk_tv[] = {
  595. &clk_sclk_dac,
  596. &clk_sclk_pixel,
  597. &clk_sclk_hdmi,
  598. &clk_sclk_mixer,
  599. };
  600. static struct clk *clkset_sclk_audio0_list[] = {
  601. [0] = &clk_ext_xtal_mux,
  602. [1] = &clk_pcmcdclk0,
  603. [2] = &clk_sclk_hdmi27m,
  604. [3] = &clk_sclk_usbphy0,
  605. [4] = &clk_sclk_usbphy1,
  606. [5] = &clk_sclk_hdmiphy,
  607. [6] = &clk_mout_mpll.clk,
  608. [7] = &clk_mout_epll.clk,
  609. [8] = &clk_sclk_vpll.clk,
  610. };
  611. static struct clksrc_sources clkset_sclk_audio0 = {
  612. .sources = clkset_sclk_audio0_list,
  613. .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
  614. };
  615. static struct clksrc_clk clk_sclk_audio0 = {
  616. .clk = {
  617. .name = "sclk_audio",
  618. .devname = "soc-audio.0",
  619. .enable = s5pv210_clk_mask0_ctrl,
  620. .ctrlbit = (1 << 24),
  621. },
  622. .sources = &clkset_sclk_audio0,
  623. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
  624. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
  625. };
  626. static struct clk *clkset_sclk_audio1_list[] = {
  627. [0] = &clk_ext_xtal_mux,
  628. [1] = &clk_pcmcdclk1,
  629. [2] = &clk_sclk_hdmi27m,
  630. [3] = &clk_sclk_usbphy0,
  631. [4] = &clk_sclk_usbphy1,
  632. [5] = &clk_sclk_hdmiphy,
  633. [6] = &clk_mout_mpll.clk,
  634. [7] = &clk_mout_epll.clk,
  635. [8] = &clk_sclk_vpll.clk,
  636. };
  637. static struct clksrc_sources clkset_sclk_audio1 = {
  638. .sources = clkset_sclk_audio1_list,
  639. .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
  640. };
  641. static struct clksrc_clk clk_sclk_audio1 = {
  642. .clk = {
  643. .name = "sclk_audio",
  644. .devname = "soc-audio.1",
  645. .enable = s5pv210_clk_mask0_ctrl,
  646. .ctrlbit = (1 << 25),
  647. },
  648. .sources = &clkset_sclk_audio1,
  649. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
  650. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
  651. };
  652. static struct clk *clkset_sclk_audio2_list[] = {
  653. [0] = &clk_ext_xtal_mux,
  654. [1] = &clk_pcmcdclk0,
  655. [2] = &clk_sclk_hdmi27m,
  656. [3] = &clk_sclk_usbphy0,
  657. [4] = &clk_sclk_usbphy1,
  658. [5] = &clk_sclk_hdmiphy,
  659. [6] = &clk_mout_mpll.clk,
  660. [7] = &clk_mout_epll.clk,
  661. [8] = &clk_sclk_vpll.clk,
  662. };
  663. static struct clksrc_sources clkset_sclk_audio2 = {
  664. .sources = clkset_sclk_audio2_list,
  665. .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
  666. };
  667. static struct clksrc_clk clk_sclk_audio2 = {
  668. .clk = {
  669. .name = "sclk_audio",
  670. .devname = "soc-audio.2",
  671. .enable = s5pv210_clk_mask0_ctrl,
  672. .ctrlbit = (1 << 26),
  673. },
  674. .sources = &clkset_sclk_audio2,
  675. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
  676. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
  677. };
  678. static struct clk *clkset_sclk_spdif_list[] = {
  679. [0] = &clk_sclk_audio0.clk,
  680. [1] = &clk_sclk_audio1.clk,
  681. [2] = &clk_sclk_audio2.clk,
  682. };
  683. static struct clksrc_sources clkset_sclk_spdif = {
  684. .sources = clkset_sclk_spdif_list,
  685. .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
  686. };
  687. static struct clksrc_clk clk_sclk_spdif = {
  688. .clk = {
  689. .name = "sclk_spdif",
  690. .enable = s5pv210_clk_mask0_ctrl,
  691. .ctrlbit = (1 << 27),
  692. .ops = &s5p_sclk_spdif_ops,
  693. },
  694. .sources = &clkset_sclk_spdif,
  695. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
  696. };
  697. static struct clk *clkset_group2_list[] = {
  698. [0] = &clk_ext_xtal_mux,
  699. [1] = &clk_xusbxti,
  700. [2] = &clk_sclk_hdmi27m,
  701. [3] = &clk_sclk_usbphy0,
  702. [4] = &clk_sclk_usbphy1,
  703. [5] = &clk_sclk_hdmiphy,
  704. [6] = &clk_mout_mpll.clk,
  705. [7] = &clk_mout_epll.clk,
  706. [8] = &clk_sclk_vpll.clk,
  707. };
  708. static struct clksrc_sources clkset_group2 = {
  709. .sources = clkset_group2_list,
  710. .nr_sources = ARRAY_SIZE(clkset_group2_list),
  711. };
  712. static struct clksrc_clk clksrcs[] = {
  713. {
  714. .clk = {
  715. .name = "sclk_dmc",
  716. },
  717. .sources = &clkset_group1,
  718. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
  719. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
  720. }, {
  721. .clk = {
  722. .name = "sclk_onenand",
  723. },
  724. .sources = &clkset_sclk_onenand,
  725. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
  726. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
  727. }, {
  728. .clk = {
  729. .name = "uclk1",
  730. .devname = "s5pv210-uart.0",
  731. .enable = s5pv210_clk_mask0_ctrl,
  732. .ctrlbit = (1 << 12),
  733. },
  734. .sources = &clkset_uart,
  735. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
  736. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
  737. }, {
  738. .clk = {
  739. .name = "uclk1",
  740. .devname = "s5pv210-uart.1",
  741. .enable = s5pv210_clk_mask0_ctrl,
  742. .ctrlbit = (1 << 13),
  743. },
  744. .sources = &clkset_uart,
  745. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
  746. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
  747. }, {
  748. .clk = {
  749. .name = "uclk1",
  750. .devname = "s5pv210-uart.2",
  751. .enable = s5pv210_clk_mask0_ctrl,
  752. .ctrlbit = (1 << 14),
  753. },
  754. .sources = &clkset_uart,
  755. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
  756. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
  757. }, {
  758. .clk = {
  759. .name = "uclk1",
  760. .devname = "s5pv210-uart.3",
  761. .enable = s5pv210_clk_mask0_ctrl,
  762. .ctrlbit = (1 << 15),
  763. },
  764. .sources = &clkset_uart,
  765. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
  766. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
  767. }, {
  768. .clk = {
  769. .name = "sclk_fimc",
  770. .devname = "s5pv210-fimc.0",
  771. .enable = s5pv210_clk_mask1_ctrl,
  772. .ctrlbit = (1 << 2),
  773. },
  774. .sources = &clkset_group2,
  775. .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
  776. .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
  777. }, {
  778. .clk = {
  779. .name = "sclk_fimc",
  780. .devname = "s5pv210-fimc.1",
  781. .enable = s5pv210_clk_mask1_ctrl,
  782. .ctrlbit = (1 << 3),
  783. },
  784. .sources = &clkset_group2,
  785. .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
  786. .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
  787. }, {
  788. .clk = {
  789. .name = "sclk_fimc",
  790. .devname = "s5pv210-fimc.2",
  791. .enable = s5pv210_clk_mask1_ctrl,
  792. .ctrlbit = (1 << 4),
  793. },
  794. .sources = &clkset_group2,
  795. .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
  796. .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
  797. }, {
  798. .clk = {
  799. .name = "sclk_cam0",
  800. .enable = s5pv210_clk_mask0_ctrl,
  801. .ctrlbit = (1 << 3),
  802. },
  803. .sources = &clkset_group2,
  804. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
  805. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
  806. }, {
  807. .clk = {
  808. .name = "sclk_cam1",
  809. .enable = s5pv210_clk_mask0_ctrl,
  810. .ctrlbit = (1 << 4),
  811. },
  812. .sources = &clkset_group2,
  813. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
  814. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
  815. }, {
  816. .clk = {
  817. .name = "sclk_fimd",
  818. .enable = s5pv210_clk_mask0_ctrl,
  819. .ctrlbit = (1 << 5),
  820. },
  821. .sources = &clkset_group2,
  822. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
  823. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
  824. }, {
  825. .clk = {
  826. .name = "sclk_mmc",
  827. .devname = "s3c-sdhci.0",
  828. .enable = s5pv210_clk_mask0_ctrl,
  829. .ctrlbit = (1 << 8),
  830. },
  831. .sources = &clkset_group2,
  832. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
  833. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
  834. }, {
  835. .clk = {
  836. .name = "sclk_mmc",
  837. .devname = "s3c-sdhci.1",
  838. .enable = s5pv210_clk_mask0_ctrl,
  839. .ctrlbit = (1 << 9),
  840. },
  841. .sources = &clkset_group2,
  842. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
  843. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
  844. }, {
  845. .clk = {
  846. .name = "sclk_mmc",
  847. .devname = "s3c-sdhci.2",
  848. .enable = s5pv210_clk_mask0_ctrl,
  849. .ctrlbit = (1 << 10),
  850. },
  851. .sources = &clkset_group2,
  852. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
  853. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
  854. }, {
  855. .clk = {
  856. .name = "sclk_mmc",
  857. .devname = "s3c-sdhci.3",
  858. .enable = s5pv210_clk_mask0_ctrl,
  859. .ctrlbit = (1 << 11),
  860. },
  861. .sources = &clkset_group2,
  862. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
  863. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
  864. }, {
  865. .clk = {
  866. .name = "sclk_mfc",
  867. .devname = "s5p-mfc",
  868. .enable = s5pv210_clk_ip0_ctrl,
  869. .ctrlbit = (1 << 16),
  870. },
  871. .sources = &clkset_group1,
  872. .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
  873. .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
  874. }, {
  875. .clk = {
  876. .name = "sclk_g2d",
  877. .enable = s5pv210_clk_ip0_ctrl,
  878. .ctrlbit = (1 << 12),
  879. },
  880. .sources = &clkset_group1,
  881. .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
  882. .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
  883. }, {
  884. .clk = {
  885. .name = "sclk_g3d",
  886. .enable = s5pv210_clk_ip0_ctrl,
  887. .ctrlbit = (1 << 8),
  888. },
  889. .sources = &clkset_group1,
  890. .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
  891. .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
  892. }, {
  893. .clk = {
  894. .name = "sclk_csis",
  895. .enable = s5pv210_clk_mask0_ctrl,
  896. .ctrlbit = (1 << 6),
  897. },
  898. .sources = &clkset_group2,
  899. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
  900. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
  901. }, {
  902. .clk = {
  903. .name = "sclk_spi",
  904. .devname = "s3c64xx-spi.0",
  905. .enable = s5pv210_clk_mask0_ctrl,
  906. .ctrlbit = (1 << 16),
  907. },
  908. .sources = &clkset_group2,
  909. .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
  910. .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
  911. }, {
  912. .clk = {
  913. .name = "sclk_spi",
  914. .devname = "s3c64xx-spi.1",
  915. .enable = s5pv210_clk_mask0_ctrl,
  916. .ctrlbit = (1 << 17),
  917. },
  918. .sources = &clkset_group2,
  919. .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
  920. .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
  921. }, {
  922. .clk = {
  923. .name = "sclk_pwi",
  924. .enable = s5pv210_clk_mask0_ctrl,
  925. .ctrlbit = (1 << 29),
  926. },
  927. .sources = &clkset_group2,
  928. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
  929. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
  930. }, {
  931. .clk = {
  932. .name = "sclk_pwm",
  933. .enable = s5pv210_clk_mask0_ctrl,
  934. .ctrlbit = (1 << 19),
  935. },
  936. .sources = &clkset_group2,
  937. .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
  938. .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
  939. },
  940. };
  941. /* Clock initialisation code */
  942. static struct clksrc_clk *sysclks[] = {
  943. &clk_mout_apll,
  944. &clk_mout_epll,
  945. &clk_mout_mpll,
  946. &clk_armclk,
  947. &clk_hclk_msys,
  948. &clk_sclk_a2m,
  949. &clk_hclk_dsys,
  950. &clk_hclk_psys,
  951. &clk_pclk_msys,
  952. &clk_pclk_dsys,
  953. &clk_pclk_psys,
  954. &clk_vpllsrc,
  955. &clk_sclk_vpll,
  956. &clk_mout_dmc0,
  957. &clk_sclk_dmc0,
  958. &clk_sclk_audio0,
  959. &clk_sclk_audio1,
  960. &clk_sclk_audio2,
  961. &clk_sclk_spdif,
  962. };
  963. static u32 epll_div[][6] = {
  964. { 48000000, 0, 48, 3, 3, 0 },
  965. { 96000000, 0, 48, 3, 2, 0 },
  966. { 144000000, 1, 72, 3, 2, 0 },
  967. { 192000000, 0, 48, 3, 1, 0 },
  968. { 288000000, 1, 72, 3, 1, 0 },
  969. { 32750000, 1, 65, 3, 4, 35127 },
  970. { 32768000, 1, 65, 3, 4, 35127 },
  971. { 45158400, 0, 45, 3, 3, 10355 },
  972. { 45000000, 0, 45, 3, 3, 10355 },
  973. { 45158000, 0, 45, 3, 3, 10355 },
  974. { 49125000, 0, 49, 3, 3, 9961 },
  975. { 49152000, 0, 49, 3, 3, 9961 },
  976. { 67737600, 1, 67, 3, 3, 48366 },
  977. { 67738000, 1, 67, 3, 3, 48366 },
  978. { 73800000, 1, 73, 3, 3, 47710 },
  979. { 73728000, 1, 73, 3, 3, 47710 },
  980. { 36000000, 1, 32, 3, 4, 0 },
  981. { 60000000, 1, 60, 3, 3, 0 },
  982. { 72000000, 1, 72, 3, 3, 0 },
  983. { 80000000, 1, 80, 3, 3, 0 },
  984. { 84000000, 0, 42, 3, 2, 0 },
  985. { 50000000, 0, 50, 3, 3, 0 },
  986. };
  987. static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
  988. {
  989. unsigned int epll_con, epll_con_k;
  990. unsigned int i;
  991. /* Return if nothing changed */
  992. if (clk->rate == rate)
  993. return 0;
  994. epll_con = __raw_readl(S5P_EPLL_CON);
  995. epll_con_k = __raw_readl(S5P_EPLL_CON1);
  996. epll_con_k &= ~PLL46XX_KDIV_MASK;
  997. epll_con &= ~(1 << 27 |
  998. PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
  999. PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
  1000. PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
  1001. for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  1002. if (epll_div[i][0] == rate) {
  1003. epll_con_k |= epll_div[i][5] << 0;
  1004. epll_con |= (epll_div[i][1] << 27 |
  1005. epll_div[i][2] << PLL46XX_MDIV_SHIFT |
  1006. epll_div[i][3] << PLL46XX_PDIV_SHIFT |
  1007. epll_div[i][4] << PLL46XX_SDIV_SHIFT);
  1008. break;
  1009. }
  1010. }
  1011. if (i == ARRAY_SIZE(epll_div)) {
  1012. printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
  1013. __func__);
  1014. return -EINVAL;
  1015. }
  1016. __raw_writel(epll_con, S5P_EPLL_CON);
  1017. __raw_writel(epll_con_k, S5P_EPLL_CON1);
  1018. printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
  1019. clk->rate, rate);
  1020. clk->rate = rate;
  1021. return 0;
  1022. }
  1023. static struct clk_ops s5pv210_epll_ops = {
  1024. .set_rate = s5pv210_epll_set_rate,
  1025. .get_rate = s5p_epll_get_rate,
  1026. };
  1027. static u32 vpll_div[][5] = {
  1028. { 54000000, 3, 53, 3, 0 },
  1029. { 108000000, 3, 53, 2, 0 },
  1030. };
  1031. static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
  1032. {
  1033. return clk->rate;
  1034. }
  1035. static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
  1036. {
  1037. unsigned int vpll_con;
  1038. unsigned int i;
  1039. /* Return if nothing changed */
  1040. if (clk->rate == rate)
  1041. return 0;
  1042. vpll_con = __raw_readl(S5P_VPLL_CON);
  1043. vpll_con &= ~(0x1 << 27 | \
  1044. PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
  1045. PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
  1046. PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
  1047. for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
  1048. if (vpll_div[i][0] == rate) {
  1049. vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
  1050. vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
  1051. vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
  1052. vpll_con |= vpll_div[i][4] << 27;
  1053. break;
  1054. }
  1055. }
  1056. if (i == ARRAY_SIZE(vpll_div)) {
  1057. printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
  1058. __func__);
  1059. return -EINVAL;
  1060. }
  1061. __raw_writel(vpll_con, S5P_VPLL_CON);
  1062. /* Wait for VPLL lock */
  1063. while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
  1064. continue;
  1065. clk->rate = rate;
  1066. return 0;
  1067. }
  1068. static struct clk_ops s5pv210_vpll_ops = {
  1069. .get_rate = s5pv210_vpll_get_rate,
  1070. .set_rate = s5pv210_vpll_set_rate,
  1071. };
  1072. void __init_or_cpufreq s5pv210_setup_clocks(void)
  1073. {
  1074. struct clk *xtal_clk;
  1075. unsigned long vpllsrc;
  1076. unsigned long armclk;
  1077. unsigned long hclk_msys;
  1078. unsigned long hclk_dsys;
  1079. unsigned long hclk_psys;
  1080. unsigned long pclk_msys;
  1081. unsigned long pclk_dsys;
  1082. unsigned long pclk_psys;
  1083. unsigned long apll;
  1084. unsigned long mpll;
  1085. unsigned long epll;
  1086. unsigned long vpll;
  1087. unsigned int ptr;
  1088. u32 clkdiv0, clkdiv1;
  1089. /* Set functions for clk_fout_epll */
  1090. clk_fout_epll.enable = s5p_epll_enable;
  1091. clk_fout_epll.ops = &s5pv210_epll_ops;
  1092. printk(KERN_DEBUG "%s: registering clocks\n", __func__);
  1093. clkdiv0 = __raw_readl(S5P_CLK_DIV0);
  1094. clkdiv1 = __raw_readl(S5P_CLK_DIV1);
  1095. printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
  1096. __func__, clkdiv0, clkdiv1);
  1097. xtal_clk = clk_get(NULL, "xtal");
  1098. BUG_ON(IS_ERR(xtal_clk));
  1099. xtal = clk_get_rate(xtal_clk);
  1100. clk_put(xtal_clk);
  1101. printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
  1102. apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
  1103. mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
  1104. epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
  1105. __raw_readl(S5P_EPLL_CON1), pll_4600);
  1106. vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
  1107. vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
  1108. clk_fout_apll.ops = &clk_fout_apll_ops;
  1109. clk_fout_mpll.rate = mpll;
  1110. clk_fout_epll.rate = epll;
  1111. clk_fout_vpll.ops = &s5pv210_vpll_ops;
  1112. clk_fout_vpll.rate = vpll;
  1113. printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
  1114. apll, mpll, epll, vpll);
  1115. armclk = clk_get_rate(&clk_armclk.clk);
  1116. hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
  1117. hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
  1118. hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
  1119. pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
  1120. pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
  1121. pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
  1122. printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
  1123. "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
  1124. armclk, hclk_msys, hclk_dsys, hclk_psys,
  1125. pclk_msys, pclk_dsys, pclk_psys);
  1126. clk_f.rate = armclk;
  1127. clk_h.rate = hclk_psys;
  1128. clk_p.rate = pclk_psys;
  1129. for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
  1130. s3c_set_clksrc(&clksrcs[ptr], true);
  1131. }
  1132. static struct clk *clks[] __initdata = {
  1133. &clk_sclk_hdmi27m,
  1134. &clk_sclk_hdmiphy,
  1135. &clk_sclk_usbphy0,
  1136. &clk_sclk_usbphy1,
  1137. &clk_pcmcdclk0,
  1138. &clk_pcmcdclk1,
  1139. &clk_pcmcdclk2,
  1140. };
  1141. void __init s5pv210_register_clocks(void)
  1142. {
  1143. int ptr;
  1144. s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
  1145. for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
  1146. s3c_register_clksrc(sysclks[ptr], 1);
  1147. for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
  1148. s3c_register_clksrc(sclk_tv[ptr], 1);
  1149. s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
  1150. s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
  1151. s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
  1152. s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
  1153. s3c24xx_register_clock(&dummy_apb_pclk);
  1154. s3c_pwmclk_init();
  1155. }