mach-origen.c 17 KB

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  1. /* linux/arch/arm/mach-exynos4/mach-origen.c
  2. *
  3. * Copyright (c) 2011 Insignal Co., Ltd.
  4. * http://www.insignal.co.kr/
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/serial_core.h>
  11. #include <linux/gpio.h>
  12. #include <linux/mmc/host.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/io.h>
  15. #include <linux/input.h>
  16. #include <linux/pwm_backlight.h>
  17. #include <linux/gpio_keys.h>
  18. #include <linux/i2c.h>
  19. #include <linux/regulator/machine.h>
  20. #include <linux/mfd/max8997.h>
  21. #include <linux/lcd.h>
  22. #include <asm/mach/arch.h>
  23. #include <asm/mach-types.h>
  24. #include <video/platform_lcd.h>
  25. #include <plat/regs-serial.h>
  26. #include <plat/regs-fb-v4.h>
  27. #include <plat/exynos4.h>
  28. #include <plat/cpu.h>
  29. #include <plat/devs.h>
  30. #include <plat/sdhci.h>
  31. #include <plat/iic.h>
  32. #include <plat/ehci.h>
  33. #include <plat/clock.h>
  34. #include <plat/gpio-cfg.h>
  35. #include <plat/backlight.h>
  36. #include <plat/pd.h>
  37. #include <plat/fb.h>
  38. #include <plat/mfc.h>
  39. #include <mach/map.h>
  40. /* Following are default values for UCON, ULCON and UFCON UART registers */
  41. #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
  42. S3C2410_UCON_RXILEVEL | \
  43. S3C2410_UCON_TXIRQMODE | \
  44. S3C2410_UCON_RXIRQMODE | \
  45. S3C2410_UCON_RXFIFO_TOI | \
  46. S3C2443_UCON_RXERR_IRQEN)
  47. #define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8
  48. #define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
  49. S5PV210_UFCON_TXTRIG4 | \
  50. S5PV210_UFCON_RXTRIG4)
  51. static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
  52. [0] = {
  53. .hwport = 0,
  54. .flags = 0,
  55. .ucon = ORIGEN_UCON_DEFAULT,
  56. .ulcon = ORIGEN_ULCON_DEFAULT,
  57. .ufcon = ORIGEN_UFCON_DEFAULT,
  58. },
  59. [1] = {
  60. .hwport = 1,
  61. .flags = 0,
  62. .ucon = ORIGEN_UCON_DEFAULT,
  63. .ulcon = ORIGEN_ULCON_DEFAULT,
  64. .ufcon = ORIGEN_UFCON_DEFAULT,
  65. },
  66. [2] = {
  67. .hwport = 2,
  68. .flags = 0,
  69. .ucon = ORIGEN_UCON_DEFAULT,
  70. .ulcon = ORIGEN_ULCON_DEFAULT,
  71. .ufcon = ORIGEN_UFCON_DEFAULT,
  72. },
  73. [3] = {
  74. .hwport = 3,
  75. .flags = 0,
  76. .ucon = ORIGEN_UCON_DEFAULT,
  77. .ulcon = ORIGEN_ULCON_DEFAULT,
  78. .ufcon = ORIGEN_UFCON_DEFAULT,
  79. },
  80. };
  81. static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
  82. REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
  83. REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
  84. REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
  85. };
  86. static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
  87. REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
  88. };
  89. static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
  90. REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
  91. };
  92. static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
  93. REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
  94. REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
  95. };
  96. static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
  97. REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
  98. };
  99. static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
  100. REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
  101. };
  102. static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
  103. REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
  104. };
  105. static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
  106. REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
  107. };
  108. static struct regulator_consumer_supply __initdata buck1_consumer[] = {
  109. REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
  110. };
  111. static struct regulator_consumer_supply __initdata buck2_consumer[] = {
  112. REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
  113. };
  114. static struct regulator_consumer_supply __initdata buck3_consumer[] = {
  115. REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
  116. };
  117. static struct regulator_consumer_supply __initdata buck7_consumer[] = {
  118. REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
  119. };
  120. static struct regulator_init_data __initdata max8997_ldo1_data = {
  121. .constraints = {
  122. .name = "VDD_ABB_3.3V",
  123. .min_uV = 3300000,
  124. .max_uV = 3300000,
  125. .apply_uV = 1,
  126. .state_mem = {
  127. .disabled = 1,
  128. },
  129. },
  130. };
  131. static struct regulator_init_data __initdata max8997_ldo2_data = {
  132. .constraints = {
  133. .name = "VDD_ALIVE_1.1V",
  134. .min_uV = 1100000,
  135. .max_uV = 1100000,
  136. .apply_uV = 1,
  137. .always_on = 1,
  138. .state_mem = {
  139. .enabled = 1,
  140. },
  141. },
  142. };
  143. static struct regulator_init_data __initdata max8997_ldo3_data = {
  144. .constraints = {
  145. .name = "VMIPI_1.1V",
  146. .min_uV = 1100000,
  147. .max_uV = 1100000,
  148. .apply_uV = 1,
  149. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  150. .state_mem = {
  151. .disabled = 1,
  152. },
  153. },
  154. .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer),
  155. .consumer_supplies = ldo3_consumer,
  156. };
  157. static struct regulator_init_data __initdata max8997_ldo4_data = {
  158. .constraints = {
  159. .name = "VDD_RTC_1.8V",
  160. .min_uV = 1800000,
  161. .max_uV = 1800000,
  162. .apply_uV = 1,
  163. .always_on = 1,
  164. .state_mem = {
  165. .disabled = 1,
  166. },
  167. },
  168. };
  169. static struct regulator_init_data __initdata max8997_ldo6_data = {
  170. .constraints = {
  171. .name = "VMIPI_1.8V",
  172. .min_uV = 1800000,
  173. .max_uV = 1800000,
  174. .apply_uV = 1,
  175. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  176. .state_mem = {
  177. .disabled = 1,
  178. },
  179. },
  180. .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer),
  181. .consumer_supplies = ldo6_consumer,
  182. };
  183. static struct regulator_init_data __initdata max8997_ldo7_data = {
  184. .constraints = {
  185. .name = "VDD_AUD_1.8V",
  186. .min_uV = 1800000,
  187. .max_uV = 1800000,
  188. .apply_uV = 1,
  189. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  190. .state_mem = {
  191. .disabled = 1,
  192. },
  193. },
  194. .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer),
  195. .consumer_supplies = ldo7_consumer,
  196. };
  197. static struct regulator_init_data __initdata max8997_ldo8_data = {
  198. .constraints = {
  199. .name = "VADC_3.3V",
  200. .min_uV = 3300000,
  201. .max_uV = 3300000,
  202. .apply_uV = 1,
  203. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  204. .state_mem = {
  205. .disabled = 1,
  206. },
  207. },
  208. .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer),
  209. .consumer_supplies = ldo8_consumer,
  210. };
  211. static struct regulator_init_data __initdata max8997_ldo9_data = {
  212. .constraints = {
  213. .name = "DVDD_SWB_2.8V",
  214. .min_uV = 2800000,
  215. .max_uV = 2800000,
  216. .apply_uV = 1,
  217. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  218. .state_mem = {
  219. .disabled = 1,
  220. },
  221. },
  222. .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer),
  223. .consumer_supplies = ldo9_consumer,
  224. };
  225. static struct regulator_init_data __initdata max8997_ldo10_data = {
  226. .constraints = {
  227. .name = "VDD_PLL_1.1V",
  228. .min_uV = 1100000,
  229. .max_uV = 1100000,
  230. .apply_uV = 1,
  231. .always_on = 1,
  232. .state_mem = {
  233. .disabled = 1,
  234. },
  235. },
  236. };
  237. static struct regulator_init_data __initdata max8997_ldo11_data = {
  238. .constraints = {
  239. .name = "VDD_AUD_3V",
  240. .min_uV = 3000000,
  241. .max_uV = 3000000,
  242. .apply_uV = 1,
  243. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  244. .state_mem = {
  245. .disabled = 1,
  246. },
  247. },
  248. .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer),
  249. .consumer_supplies = ldo11_consumer,
  250. };
  251. static struct regulator_init_data __initdata max8997_ldo14_data = {
  252. .constraints = {
  253. .name = "AVDD18_SWB_1.8V",
  254. .min_uV = 1800000,
  255. .max_uV = 1800000,
  256. .apply_uV = 1,
  257. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  258. .state_mem = {
  259. .disabled = 1,
  260. },
  261. },
  262. .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer),
  263. .consumer_supplies = ldo14_consumer,
  264. };
  265. static struct regulator_init_data __initdata max8997_ldo17_data = {
  266. .constraints = {
  267. .name = "VDD_SWB_3.3V",
  268. .min_uV = 3300000,
  269. .max_uV = 3300000,
  270. .apply_uV = 1,
  271. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  272. .state_mem = {
  273. .disabled = 1,
  274. },
  275. },
  276. .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer),
  277. .consumer_supplies = ldo17_consumer,
  278. };
  279. static struct regulator_init_data __initdata max8997_ldo21_data = {
  280. .constraints = {
  281. .name = "VDD_MIF_1.2V",
  282. .min_uV = 1200000,
  283. .max_uV = 1200000,
  284. .apply_uV = 1,
  285. .always_on = 1,
  286. .state_mem = {
  287. .disabled = 1,
  288. },
  289. },
  290. };
  291. static struct regulator_init_data __initdata max8997_buck1_data = {
  292. .constraints = {
  293. .name = "VDD_ARM_1.2V",
  294. .min_uV = 950000,
  295. .max_uV = 1350000,
  296. .always_on = 1,
  297. .boot_on = 1,
  298. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  299. .state_mem = {
  300. .disabled = 1,
  301. },
  302. },
  303. .num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
  304. .consumer_supplies = buck1_consumer,
  305. };
  306. static struct regulator_init_data __initdata max8997_buck2_data = {
  307. .constraints = {
  308. .name = "VDD_INT_1.1V",
  309. .min_uV = 900000,
  310. .max_uV = 1100000,
  311. .always_on = 1,
  312. .boot_on = 1,
  313. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  314. .state_mem = {
  315. .disabled = 1,
  316. },
  317. },
  318. .num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
  319. .consumer_supplies = buck2_consumer,
  320. };
  321. static struct regulator_init_data __initdata max8997_buck3_data = {
  322. .constraints = {
  323. .name = "VDD_G3D_1.1V",
  324. .min_uV = 900000,
  325. .max_uV = 1100000,
  326. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
  327. REGULATOR_CHANGE_STATUS,
  328. .state_mem = {
  329. .disabled = 1,
  330. },
  331. },
  332. .num_consumer_supplies = ARRAY_SIZE(buck3_consumer),
  333. .consumer_supplies = buck3_consumer,
  334. };
  335. static struct regulator_init_data __initdata max8997_buck5_data = {
  336. .constraints = {
  337. .name = "VDDQ_M1M2_1.2V",
  338. .min_uV = 1200000,
  339. .max_uV = 1200000,
  340. .apply_uV = 1,
  341. .always_on = 1,
  342. .state_mem = {
  343. .disabled = 1,
  344. },
  345. },
  346. };
  347. static struct regulator_init_data __initdata max8997_buck7_data = {
  348. .constraints = {
  349. .name = "VDD_LCD_3.3V",
  350. .min_uV = 3300000,
  351. .max_uV = 3300000,
  352. .boot_on = 1,
  353. .apply_uV = 1,
  354. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  355. .state_mem = {
  356. .disabled = 1
  357. },
  358. },
  359. .num_consumer_supplies = ARRAY_SIZE(buck7_consumer),
  360. .consumer_supplies = buck7_consumer,
  361. };
  362. static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
  363. { MAX8997_LDO1, &max8997_ldo1_data },
  364. { MAX8997_LDO2, &max8997_ldo2_data },
  365. { MAX8997_LDO3, &max8997_ldo3_data },
  366. { MAX8997_LDO4, &max8997_ldo4_data },
  367. { MAX8997_LDO6, &max8997_ldo6_data },
  368. { MAX8997_LDO7, &max8997_ldo7_data },
  369. { MAX8997_LDO8, &max8997_ldo8_data },
  370. { MAX8997_LDO9, &max8997_ldo9_data },
  371. { MAX8997_LDO10, &max8997_ldo10_data },
  372. { MAX8997_LDO11, &max8997_ldo11_data },
  373. { MAX8997_LDO14, &max8997_ldo14_data },
  374. { MAX8997_LDO17, &max8997_ldo17_data },
  375. { MAX8997_LDO21, &max8997_ldo21_data },
  376. { MAX8997_BUCK1, &max8997_buck1_data },
  377. { MAX8997_BUCK2, &max8997_buck2_data },
  378. { MAX8997_BUCK3, &max8997_buck3_data },
  379. { MAX8997_BUCK5, &max8997_buck5_data },
  380. { MAX8997_BUCK7, &max8997_buck7_data },
  381. };
  382. struct max8997_platform_data __initdata origen_max8997_pdata = {
  383. .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
  384. .regulators = origen_max8997_regulators,
  385. .wakeup = true,
  386. .buck1_gpiodvs = false,
  387. .buck2_gpiodvs = false,
  388. .buck5_gpiodvs = false,
  389. .irq_base = IRQ_GPIO_END + 1,
  390. .ignore_gpiodvs_side_effect = true,
  391. .buck125_default_idx = 0x0,
  392. .buck125_gpios[0] = EXYNOS4_GPX0(0),
  393. .buck125_gpios[1] = EXYNOS4_GPX0(1),
  394. .buck125_gpios[2] = EXYNOS4_GPX0(2),
  395. .buck1_voltage[0] = 1350000,
  396. .buck1_voltage[1] = 1300000,
  397. .buck1_voltage[2] = 1250000,
  398. .buck1_voltage[3] = 1200000,
  399. .buck1_voltage[4] = 1150000,
  400. .buck1_voltage[5] = 1100000,
  401. .buck1_voltage[6] = 1000000,
  402. .buck1_voltage[7] = 950000,
  403. .buck2_voltage[0] = 1100000,
  404. .buck2_voltage[1] = 1100000,
  405. .buck2_voltage[2] = 1100000,
  406. .buck2_voltage[3] = 1100000,
  407. .buck2_voltage[4] = 1000000,
  408. .buck2_voltage[5] = 1000000,
  409. .buck2_voltage[6] = 1000000,
  410. .buck2_voltage[7] = 1000000,
  411. .buck5_voltage[0] = 1200000,
  412. .buck5_voltage[1] = 1200000,
  413. .buck5_voltage[2] = 1200000,
  414. .buck5_voltage[3] = 1200000,
  415. .buck5_voltage[4] = 1200000,
  416. .buck5_voltage[5] = 1200000,
  417. .buck5_voltage[6] = 1200000,
  418. .buck5_voltage[7] = 1200000,
  419. };
  420. /* I2C0 */
  421. static struct i2c_board_info i2c0_devs[] __initdata = {
  422. {
  423. I2C_BOARD_INFO("max8997", (0xCC >> 1)),
  424. .platform_data = &origen_max8997_pdata,
  425. .irq = IRQ_EINT(4),
  426. },
  427. };
  428. static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
  429. .cd_type = S3C_SDHCI_CD_INTERNAL,
  430. .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
  431. };
  432. static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
  433. .cd_type = S3C_SDHCI_CD_INTERNAL,
  434. .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
  435. };
  436. /* USB EHCI */
  437. static struct s5p_ehci_platdata origen_ehci_pdata;
  438. static void __init origen_ehci_init(void)
  439. {
  440. struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
  441. s5p_ehci_set_platdata(pdata);
  442. }
  443. static struct gpio_keys_button origen_gpio_keys_table[] = {
  444. {
  445. .code = KEY_MENU,
  446. .gpio = EXYNOS4_GPX1(5),
  447. .desc = "gpio-keys: KEY_MENU",
  448. .type = EV_KEY,
  449. .active_low = 1,
  450. .wakeup = 1,
  451. .debounce_interval = 1,
  452. }, {
  453. .code = KEY_HOME,
  454. .gpio = EXYNOS4_GPX1(6),
  455. .desc = "gpio-keys: KEY_HOME",
  456. .type = EV_KEY,
  457. .active_low = 1,
  458. .wakeup = 1,
  459. .debounce_interval = 1,
  460. }, {
  461. .code = KEY_BACK,
  462. .gpio = EXYNOS4_GPX1(7),
  463. .desc = "gpio-keys: KEY_BACK",
  464. .type = EV_KEY,
  465. .active_low = 1,
  466. .wakeup = 1,
  467. .debounce_interval = 1,
  468. }, {
  469. .code = KEY_UP,
  470. .gpio = EXYNOS4_GPX2(0),
  471. .desc = "gpio-keys: KEY_UP",
  472. .type = EV_KEY,
  473. .active_low = 1,
  474. .wakeup = 1,
  475. .debounce_interval = 1,
  476. }, {
  477. .code = KEY_DOWN,
  478. .gpio = EXYNOS4_GPX2(1),
  479. .desc = "gpio-keys: KEY_DOWN",
  480. .type = EV_KEY,
  481. .active_low = 1,
  482. .wakeup = 1,
  483. .debounce_interval = 1,
  484. },
  485. };
  486. static struct gpio_keys_platform_data origen_gpio_keys_data = {
  487. .buttons = origen_gpio_keys_table,
  488. .nbuttons = ARRAY_SIZE(origen_gpio_keys_table),
  489. };
  490. static struct platform_device origen_device_gpiokeys = {
  491. .name = "gpio-keys",
  492. .dev = {
  493. .platform_data = &origen_gpio_keys_data,
  494. },
  495. };
  496. static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
  497. {
  498. int ret;
  499. if (power)
  500. ret = gpio_request_one(EXYNOS4_GPE3(4),
  501. GPIOF_OUT_INIT_HIGH, "GPE3_4");
  502. else
  503. ret = gpio_request_one(EXYNOS4_GPE3(4),
  504. GPIOF_OUT_INIT_LOW, "GPE3_4");
  505. gpio_free(EXYNOS4_GPE3(4));
  506. if (ret)
  507. pr_err("failed to request gpio for LCD power: %d\n", ret);
  508. }
  509. static struct plat_lcd_data origen_lcd_hv070wsa_data = {
  510. .set_power = lcd_hv070wsa_set_power,
  511. };
  512. static struct platform_device origen_lcd_hv070wsa = {
  513. .name = "platform-lcd",
  514. .dev.parent = &s5p_device_fimd0.dev,
  515. .dev.platform_data = &origen_lcd_hv070wsa_data,
  516. };
  517. static struct s3c_fb_pd_win origen_fb_win0 = {
  518. .win_mode = {
  519. .left_margin = 64,
  520. .right_margin = 16,
  521. .upper_margin = 64,
  522. .lower_margin = 16,
  523. .hsync_len = 48,
  524. .vsync_len = 3,
  525. .xres = 1024,
  526. .yres = 600,
  527. },
  528. .max_bpp = 32,
  529. .default_bpp = 24,
  530. };
  531. static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
  532. .win[0] = &origen_fb_win0,
  533. .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
  534. .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
  535. .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
  536. };
  537. static struct platform_device *origen_devices[] __initdata = {
  538. &s3c_device_hsmmc2,
  539. &s3c_device_hsmmc0,
  540. &s3c_device_i2c0,
  541. &s3c_device_rtc,
  542. &s3c_device_wdt,
  543. &s5p_device_ehci,
  544. &s5p_device_fimc0,
  545. &s5p_device_fimc1,
  546. &s5p_device_fimc2,
  547. &s5p_device_fimc3,
  548. &s5p_device_fimd0,
  549. &s5p_device_hdmi,
  550. &s5p_device_i2c_hdmiphy,
  551. &s5p_device_mfc,
  552. &s5p_device_mfc_l,
  553. &s5p_device_mfc_r,
  554. &s5p_device_mixer,
  555. &exynos4_device_pd[PD_LCD0],
  556. &exynos4_device_pd[PD_TV],
  557. &exynos4_device_pd[PD_G3D],
  558. &exynos4_device_pd[PD_LCD1],
  559. &exynos4_device_pd[PD_CAM],
  560. &exynos4_device_pd[PD_GPS],
  561. &exynos4_device_pd[PD_MFC],
  562. &origen_device_gpiokeys,
  563. &origen_lcd_hv070wsa,
  564. };
  565. /* LCD Backlight data */
  566. static struct samsung_bl_gpio_info origen_bl_gpio_info = {
  567. .no = EXYNOS4_GPD0(0),
  568. .func = S3C_GPIO_SFN(2),
  569. };
  570. static struct platform_pwm_backlight_data origen_bl_data = {
  571. .pwm_id = 0,
  572. .pwm_period_ns = 1000,
  573. };
  574. static void s5p_tv_setup(void)
  575. {
  576. /* Direct HPD to HDMI chip */
  577. gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
  578. s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
  579. s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
  580. }
  581. static void __init origen_map_io(void)
  582. {
  583. s5p_init_io(NULL, 0, S5P_VA_CHIPID);
  584. s3c24xx_init_clocks(24000000);
  585. s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
  586. }
  587. static void __init origen_power_init(void)
  588. {
  589. gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
  590. s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
  591. s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
  592. }
  593. static void __init origen_reserve(void)
  594. {
  595. s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
  596. }
  597. static void __init origen_machine_init(void)
  598. {
  599. origen_power_init();
  600. s3c_i2c0_set_platdata(NULL);
  601. i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
  602. /*
  603. * Since sdhci instance 2 can contain a bootable media,
  604. * sdhci instance 0 is registered after instance 2.
  605. */
  606. s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
  607. s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
  608. origen_ehci_init();
  609. clk_xusbxti.rate = 24000000;
  610. s5p_tv_setup();
  611. s5p_i2c_hdmiphy_set_platdata(NULL);
  612. s5p_fimd0_set_platdata(&origen_lcd_pdata);
  613. platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
  614. s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
  615. s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
  616. s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
  617. s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
  618. samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
  619. }
  620. MACHINE_START(ORIGEN, "ORIGEN")
  621. /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
  622. .atag_offset = 0x100,
  623. .init_irq = exynos4_init_irq,
  624. .map_io = origen_map_io,
  625. .init_machine = origen_machine_init,
  626. .timer = &exynos4_timer,
  627. .reserve = &origen_reserve,
  628. MACHINE_END