twl4030.c 73 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x00, /* REG_CODEC_MODE (0x1) */
  43. 0x00, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x00, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0f, /* REG_ATXL1PGA (0xA) */
  52. 0x0f, /* REG_ATXR1PGA (0xB) */
  53. 0x0f, /* REG_AVTXL2PGA (0xC) */
  54. 0x0f, /* REG_AVTXR2PGA (0xD) */
  55. 0x00, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x3f, /* REG_ARXR1PGA (0x10) */
  58. 0x3f, /* REG_ARXL1PGA (0x11) */
  59. 0x3f, /* REG_ARXR2PGA (0x12) */
  60. 0x3f, /* REG_ARXL2PGA (0x13) */
  61. 0x25, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x00, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x55, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x00, /* REG_HS_SEL (0x22) */
  76. 0x00, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x05, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x13, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x79, /* REG_DTMF_TONOFF (0x35) */
  95. 0x11, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x06, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x32, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. struct snd_soc_codec codec;
  120. unsigned int codec_powered;
  121. /* reference counts of AIF/APLL users */
  122. unsigned int apll_enabled;
  123. struct snd_pcm_substream *master_substream;
  124. struct snd_pcm_substream *slave_substream;
  125. unsigned int configured;
  126. unsigned int rate;
  127. unsigned int sample_bits;
  128. unsigned int channels;
  129. unsigned int sysclk;
  130. /* Output (with associated amp) states */
  131. u8 hsl_enabled, hsr_enabled;
  132. u8 earpiece_enabled;
  133. u8 predrivel_enabled, predriver_enabled;
  134. u8 carkitl_enabled, carkitr_enabled;
  135. };
  136. /*
  137. * read twl4030 register cache
  138. */
  139. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  140. unsigned int reg)
  141. {
  142. u8 *cache = codec->reg_cache;
  143. if (reg >= TWL4030_CACHEREGNUM)
  144. return -EIO;
  145. return cache[reg];
  146. }
  147. /*
  148. * write twl4030 register cache
  149. */
  150. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  151. u8 reg, u8 value)
  152. {
  153. u8 *cache = codec->reg_cache;
  154. if (reg >= TWL4030_CACHEREGNUM)
  155. return;
  156. cache[reg] = value;
  157. }
  158. /*
  159. * write to the twl4030 register space
  160. */
  161. static int twl4030_write(struct snd_soc_codec *codec,
  162. unsigned int reg, unsigned int value)
  163. {
  164. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  165. int write_to_reg = 0;
  166. twl4030_write_reg_cache(codec, reg, value);
  167. if (likely(reg < TWL4030_REG_SW_SHADOW)) {
  168. /* Decide if the given register can be written */
  169. switch (reg) {
  170. case TWL4030_REG_EAR_CTL:
  171. if (twl4030->earpiece_enabled)
  172. write_to_reg = 1;
  173. break;
  174. case TWL4030_REG_PREDL_CTL:
  175. if (twl4030->predrivel_enabled)
  176. write_to_reg = 1;
  177. break;
  178. case TWL4030_REG_PREDR_CTL:
  179. if (twl4030->predriver_enabled)
  180. write_to_reg = 1;
  181. break;
  182. case TWL4030_REG_PRECKL_CTL:
  183. if (twl4030->carkitl_enabled)
  184. write_to_reg = 1;
  185. break;
  186. case TWL4030_REG_PRECKR_CTL:
  187. if (twl4030->carkitr_enabled)
  188. write_to_reg = 1;
  189. break;
  190. case TWL4030_REG_HS_GAIN_SET:
  191. if (twl4030->hsl_enabled || twl4030->hsr_enabled)
  192. write_to_reg = 1;
  193. break;
  194. default:
  195. /* All other register can be written */
  196. write_to_reg = 1;
  197. break;
  198. }
  199. if (write_to_reg)
  200. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  201. value, reg);
  202. }
  203. return 0;
  204. }
  205. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  206. {
  207. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  208. int mode;
  209. if (enable == twl4030->codec_powered)
  210. return;
  211. if (enable)
  212. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  213. else
  214. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  215. if (mode >= 0) {
  216. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  217. twl4030->codec_powered = enable;
  218. }
  219. /* REVISIT: this delay is present in TI sample drivers */
  220. /* but there seems to be no TRM requirement for it */
  221. udelay(10);
  222. }
  223. static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
  224. {
  225. int i, difference = 0;
  226. u8 val;
  227. dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
  228. for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
  229. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
  230. if (val != twl4030_reg[i]) {
  231. difference++;
  232. dev_dbg(codec->dev,
  233. "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
  234. i, val, twl4030_reg[i]);
  235. }
  236. }
  237. dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
  238. difference, difference ? "Not OK" : "OK");
  239. }
  240. static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
  241. {
  242. int i;
  243. /* set all audio section registers to reasonable defaults */
  244. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  245. if (i != TWL4030_REG_APLL_CTL)
  246. twl4030_write(codec, i, twl4030_reg[i]);
  247. }
  248. static void twl4030_init_chip(struct platform_device *pdev)
  249. {
  250. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  251. struct twl4030_setup_data *setup = socdev->codec_data;
  252. struct snd_soc_codec *codec = socdev->card->codec;
  253. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  254. u8 reg, byte;
  255. int i = 0;
  256. /* Check defaults, if instructed before anything else */
  257. if (setup && setup->check_defaults)
  258. twl4030_check_defaults(codec);
  259. /* Reset registers, if no setup data or if instructed to do so */
  260. if (!setup || (setup && setup->reset_registers))
  261. twl4030_reset_registers(codec);
  262. /* Refresh APLL_CTL register from HW */
  263. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  264. TWL4030_REG_APLL_CTL);
  265. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
  266. /* anti-pop when changing analog gain */
  267. reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  268. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  269. reg | TWL4030_SMOOTH_ANAVOL_EN);
  270. twl4030_write(codec, TWL4030_REG_OPTION,
  271. TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
  272. TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
  273. /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
  274. twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
  275. /* Machine dependent setup */
  276. if (!setup)
  277. return;
  278. /* Configuration for headset ramp delay from setup data */
  279. if (setup->sysclk != twl4030->sysclk)
  280. dev_warn(codec->dev,
  281. "Mismatch in APLL mclk: %u (configured: %u)\n",
  282. setup->sysclk, twl4030->sysclk);
  283. reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  284. reg &= ~TWL4030_RAMP_DELAY;
  285. reg |= (setup->ramp_delay_value << 2);
  286. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
  287. /* initiate offset cancellation */
  288. twl4030_codec_enable(codec, 1);
  289. reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  290. reg &= ~TWL4030_OFFSET_CNCL_SEL;
  291. reg |= setup->offset_cncl_path;
  292. twl4030_write(codec, TWL4030_REG_ANAMICL,
  293. reg | TWL4030_CNCL_OFFSET_START);
  294. /* wait for offset cancellation to complete */
  295. do {
  296. /* this takes a little while, so don't slam i2c */
  297. udelay(2000);
  298. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  299. TWL4030_REG_ANAMICL);
  300. } while ((i++ < 100) &&
  301. ((byte & TWL4030_CNCL_OFFSET_START) ==
  302. TWL4030_CNCL_OFFSET_START));
  303. /* Make sure that the reg_cache has the same value as the HW */
  304. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  305. twl4030_codec_enable(codec, 0);
  306. }
  307. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  308. {
  309. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  310. int status = -1;
  311. if (enable) {
  312. twl4030->apll_enabled++;
  313. if (twl4030->apll_enabled == 1)
  314. status = twl4030_codec_enable_resource(
  315. TWL4030_CODEC_RES_APLL);
  316. } else {
  317. twl4030->apll_enabled--;
  318. if (!twl4030->apll_enabled)
  319. status = twl4030_codec_disable_resource(
  320. TWL4030_CODEC_RES_APLL);
  321. }
  322. if (status >= 0)
  323. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  324. }
  325. /* Earpiece */
  326. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  327. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  328. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  329. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  330. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  331. };
  332. /* PreDrive Left */
  333. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  334. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  335. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  336. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  337. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  338. };
  339. /* PreDrive Right */
  340. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  341. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  342. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  343. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  344. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  345. };
  346. /* Headset Left */
  347. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  348. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  349. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  350. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  351. };
  352. /* Headset Right */
  353. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  354. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  355. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  356. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  357. };
  358. /* Carkit Left */
  359. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  360. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  361. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  362. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  363. };
  364. /* Carkit Right */
  365. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  366. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  367. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  368. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  369. };
  370. /* Handsfree Left */
  371. static const char *twl4030_handsfreel_texts[] =
  372. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  373. static const struct soc_enum twl4030_handsfreel_enum =
  374. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  375. ARRAY_SIZE(twl4030_handsfreel_texts),
  376. twl4030_handsfreel_texts);
  377. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  378. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  379. /* Handsfree Left virtual mute */
  380. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  381. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  382. /* Handsfree Right */
  383. static const char *twl4030_handsfreer_texts[] =
  384. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  385. static const struct soc_enum twl4030_handsfreer_enum =
  386. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  387. ARRAY_SIZE(twl4030_handsfreer_texts),
  388. twl4030_handsfreer_texts);
  389. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  390. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  391. /* Handsfree Right virtual mute */
  392. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  393. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  394. /* Vibra */
  395. /* Vibra audio path selection */
  396. static const char *twl4030_vibra_texts[] =
  397. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  398. static const struct soc_enum twl4030_vibra_enum =
  399. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  400. ARRAY_SIZE(twl4030_vibra_texts),
  401. twl4030_vibra_texts);
  402. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  403. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  404. /* Vibra path selection: local vibrator (PWM) or audio driven */
  405. static const char *twl4030_vibrapath_texts[] =
  406. {"Local vibrator", "Audio"};
  407. static const struct soc_enum twl4030_vibrapath_enum =
  408. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  409. ARRAY_SIZE(twl4030_vibrapath_texts),
  410. twl4030_vibrapath_texts);
  411. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  412. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  413. /* Left analog microphone selection */
  414. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  415. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  416. TWL4030_REG_ANAMICL, 0, 1, 0),
  417. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  418. TWL4030_REG_ANAMICL, 1, 1, 0),
  419. SOC_DAPM_SINGLE("AUXL Capture Switch",
  420. TWL4030_REG_ANAMICL, 2, 1, 0),
  421. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  422. TWL4030_REG_ANAMICL, 3, 1, 0),
  423. };
  424. /* Right analog microphone selection */
  425. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  426. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  427. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  428. };
  429. /* TX1 L/R Analog/Digital microphone selection */
  430. static const char *twl4030_micpathtx1_texts[] =
  431. {"Analog", "Digimic0"};
  432. static const struct soc_enum twl4030_micpathtx1_enum =
  433. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  434. ARRAY_SIZE(twl4030_micpathtx1_texts),
  435. twl4030_micpathtx1_texts);
  436. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  437. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  438. /* TX2 L/R Analog/Digital microphone selection */
  439. static const char *twl4030_micpathtx2_texts[] =
  440. {"Analog", "Digimic1"};
  441. static const struct soc_enum twl4030_micpathtx2_enum =
  442. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  443. ARRAY_SIZE(twl4030_micpathtx2_texts),
  444. twl4030_micpathtx2_texts);
  445. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  446. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  447. /* Analog bypass for AudioR1 */
  448. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  449. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  450. /* Analog bypass for AudioL1 */
  451. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  452. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  453. /* Analog bypass for AudioR2 */
  454. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  455. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  456. /* Analog bypass for AudioL2 */
  457. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  458. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  459. /* Analog bypass for Voice */
  460. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  461. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  462. /* Digital bypass gain, 0 mutes the bypass */
  463. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  464. TLV_DB_RANGE_HEAD(2),
  465. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  466. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  467. };
  468. /* Digital bypass left (TX1L -> RX2L) */
  469. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  470. SOC_DAPM_SINGLE_TLV("Volume",
  471. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  472. twl4030_dapm_dbypass_tlv);
  473. /* Digital bypass right (TX1R -> RX2R) */
  474. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  475. SOC_DAPM_SINGLE_TLV("Volume",
  476. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  477. twl4030_dapm_dbypass_tlv);
  478. /*
  479. * Voice Sidetone GAIN volume control:
  480. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  481. */
  482. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  483. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  484. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  485. SOC_DAPM_SINGLE_TLV("Volume",
  486. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  487. twl4030_dapm_dbypassv_tlv);
  488. static int micpath_event(struct snd_soc_dapm_widget *w,
  489. struct snd_kcontrol *kcontrol, int event)
  490. {
  491. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  492. unsigned char adcmicsel, micbias_ctl;
  493. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  494. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  495. /* Prepare the bits for the given TX path:
  496. * shift_l == 0: TX1 microphone path
  497. * shift_l == 2: TX2 microphone path */
  498. if (e->shift_l) {
  499. /* TX2 microphone path */
  500. if (adcmicsel & TWL4030_TX2IN_SEL)
  501. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  502. else
  503. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  504. } else {
  505. /* TX1 microphone path */
  506. if (adcmicsel & TWL4030_TX1IN_SEL)
  507. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  508. else
  509. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  510. }
  511. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  512. return 0;
  513. }
  514. /*
  515. * Output PGA builder:
  516. * Handle the muting and unmuting of the given output (turning off the
  517. * amplifier associated with the output pin)
  518. * On mute bypass the reg_cache and write 0 to the register
  519. * On unmute: restore the register content from the reg_cache
  520. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  521. */
  522. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  523. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  524. struct snd_kcontrol *kcontrol, int event) \
  525. { \
  526. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
  527. \
  528. switch (event) { \
  529. case SND_SOC_DAPM_POST_PMU: \
  530. twl4030->pin_name##_enabled = 1; \
  531. twl4030_write(w->codec, reg, \
  532. twl4030_read_reg_cache(w->codec, reg)); \
  533. break; \
  534. case SND_SOC_DAPM_POST_PMD: \
  535. twl4030->pin_name##_enabled = 0; \
  536. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  537. 0, reg); \
  538. break; \
  539. } \
  540. return 0; \
  541. }
  542. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  543. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  544. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  545. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  546. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  547. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  548. {
  549. unsigned char hs_ctl;
  550. hs_ctl = twl4030_read_reg_cache(codec, reg);
  551. if (ramp) {
  552. /* HF ramp-up */
  553. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  554. twl4030_write(codec, reg, hs_ctl);
  555. udelay(10);
  556. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  557. twl4030_write(codec, reg, hs_ctl);
  558. udelay(40);
  559. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  560. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  561. twl4030_write(codec, reg, hs_ctl);
  562. } else {
  563. /* HF ramp-down */
  564. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  565. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  566. twl4030_write(codec, reg, hs_ctl);
  567. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  568. twl4030_write(codec, reg, hs_ctl);
  569. udelay(40);
  570. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  571. twl4030_write(codec, reg, hs_ctl);
  572. }
  573. }
  574. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  575. struct snd_kcontrol *kcontrol, int event)
  576. {
  577. switch (event) {
  578. case SND_SOC_DAPM_POST_PMU:
  579. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  580. break;
  581. case SND_SOC_DAPM_POST_PMD:
  582. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  583. break;
  584. }
  585. return 0;
  586. }
  587. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  588. struct snd_kcontrol *kcontrol, int event)
  589. {
  590. switch (event) {
  591. case SND_SOC_DAPM_POST_PMU:
  592. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  593. break;
  594. case SND_SOC_DAPM_POST_PMD:
  595. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  596. break;
  597. }
  598. return 0;
  599. }
  600. static int vibramux_event(struct snd_soc_dapm_widget *w,
  601. struct snd_kcontrol *kcontrol, int event)
  602. {
  603. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  604. return 0;
  605. }
  606. static int apll_event(struct snd_soc_dapm_widget *w,
  607. struct snd_kcontrol *kcontrol, int event)
  608. {
  609. switch (event) {
  610. case SND_SOC_DAPM_PRE_PMU:
  611. twl4030_apll_enable(w->codec, 1);
  612. break;
  613. case SND_SOC_DAPM_POST_PMD:
  614. twl4030_apll_enable(w->codec, 0);
  615. break;
  616. }
  617. return 0;
  618. }
  619. static int aif_event(struct snd_soc_dapm_widget *w,
  620. struct snd_kcontrol *kcontrol, int event)
  621. {
  622. u8 audio_if;
  623. audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
  624. switch (event) {
  625. case SND_SOC_DAPM_PRE_PMU:
  626. /* Enable AIF */
  627. /* enable the PLL before we use it to clock the DAI */
  628. twl4030_apll_enable(w->codec, 1);
  629. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  630. audio_if | TWL4030_AIF_EN);
  631. break;
  632. case SND_SOC_DAPM_POST_PMD:
  633. /* disable the DAI before we stop it's source PLL */
  634. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  635. audio_if & ~TWL4030_AIF_EN);
  636. twl4030_apll_enable(w->codec, 0);
  637. break;
  638. }
  639. return 0;
  640. }
  641. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  642. {
  643. struct snd_soc_device *socdev = codec->socdev;
  644. struct twl4030_setup_data *setup = socdev->codec_data;
  645. unsigned char hs_gain, hs_pop;
  646. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  647. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  648. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  649. 8388608, 16777216, 33554432, 67108864};
  650. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  651. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  652. /* Enable external mute control, this dramatically reduces
  653. * the pop-noise */
  654. if (setup && setup->hs_extmute) {
  655. if (setup->set_hs_extmute) {
  656. setup->set_hs_extmute(1);
  657. } else {
  658. hs_pop |= TWL4030_EXTMUTE;
  659. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  660. }
  661. }
  662. if (ramp) {
  663. /* Headset ramp-up according to the TRM */
  664. hs_pop |= TWL4030_VMID_EN;
  665. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  666. /* Actually write to the register */
  667. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  668. hs_gain,
  669. TWL4030_REG_HS_GAIN_SET);
  670. hs_pop |= TWL4030_RAMP_EN;
  671. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  672. /* Wait ramp delay time + 1, so the VMID can settle */
  673. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  674. twl4030->sysclk) + 1);
  675. } else {
  676. /* Headset ramp-down _not_ according to
  677. * the TRM, but in a way that it is working */
  678. hs_pop &= ~TWL4030_RAMP_EN;
  679. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  680. /* Wait ramp delay time + 1, so the VMID can settle */
  681. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  682. twl4030->sysclk) + 1);
  683. /* Bypass the reg_cache to mute the headset */
  684. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  685. hs_gain & (~0x0f),
  686. TWL4030_REG_HS_GAIN_SET);
  687. hs_pop &= ~TWL4030_VMID_EN;
  688. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  689. }
  690. /* Disable external mute */
  691. if (setup && setup->hs_extmute) {
  692. if (setup->set_hs_extmute) {
  693. setup->set_hs_extmute(0);
  694. } else {
  695. hs_pop &= ~TWL4030_EXTMUTE;
  696. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  697. }
  698. }
  699. }
  700. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  701. struct snd_kcontrol *kcontrol, int event)
  702. {
  703. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  704. switch (event) {
  705. case SND_SOC_DAPM_POST_PMU:
  706. /* Do the ramp-up only once */
  707. if (!twl4030->hsr_enabled)
  708. headset_ramp(w->codec, 1);
  709. twl4030->hsl_enabled = 1;
  710. break;
  711. case SND_SOC_DAPM_POST_PMD:
  712. /* Do the ramp-down only if both headsetL/R is disabled */
  713. if (!twl4030->hsr_enabled)
  714. headset_ramp(w->codec, 0);
  715. twl4030->hsl_enabled = 0;
  716. break;
  717. }
  718. return 0;
  719. }
  720. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  721. struct snd_kcontrol *kcontrol, int event)
  722. {
  723. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  724. switch (event) {
  725. case SND_SOC_DAPM_POST_PMU:
  726. /* Do the ramp-up only once */
  727. if (!twl4030->hsl_enabled)
  728. headset_ramp(w->codec, 1);
  729. twl4030->hsr_enabled = 1;
  730. break;
  731. case SND_SOC_DAPM_POST_PMD:
  732. /* Do the ramp-down only if both headsetL/R is disabled */
  733. if (!twl4030->hsl_enabled)
  734. headset_ramp(w->codec, 0);
  735. twl4030->hsr_enabled = 0;
  736. break;
  737. }
  738. return 0;
  739. }
  740. /*
  741. * Some of the gain controls in TWL (mostly those which are associated with
  742. * the outputs) are implemented in an interesting way:
  743. * 0x0 : Power down (mute)
  744. * 0x1 : 6dB
  745. * 0x2 : 0 dB
  746. * 0x3 : -6 dB
  747. * Inverting not going to help with these.
  748. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  749. */
  750. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  751. xinvert, tlv_array) \
  752. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  753. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  754. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  755. .tlv.p = (tlv_array), \
  756. .info = snd_soc_info_volsw, \
  757. .get = snd_soc_get_volsw_twl4030, \
  758. .put = snd_soc_put_volsw_twl4030, \
  759. .private_value = (unsigned long)&(struct soc_mixer_control) \
  760. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  761. .max = xmax, .invert = xinvert} }
  762. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  763. xinvert, tlv_array) \
  764. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  765. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  766. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  767. .tlv.p = (tlv_array), \
  768. .info = snd_soc_info_volsw_2r, \
  769. .get = snd_soc_get_volsw_r2_twl4030,\
  770. .put = snd_soc_put_volsw_r2_twl4030, \
  771. .private_value = (unsigned long)&(struct soc_mixer_control) \
  772. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  773. .rshift = xshift, .max = xmax, .invert = xinvert} }
  774. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  775. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  776. xinvert, tlv_array)
  777. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  778. struct snd_ctl_elem_value *ucontrol)
  779. {
  780. struct soc_mixer_control *mc =
  781. (struct soc_mixer_control *)kcontrol->private_value;
  782. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  783. unsigned int reg = mc->reg;
  784. unsigned int shift = mc->shift;
  785. unsigned int rshift = mc->rshift;
  786. int max = mc->max;
  787. int mask = (1 << fls(max)) - 1;
  788. ucontrol->value.integer.value[0] =
  789. (snd_soc_read(codec, reg) >> shift) & mask;
  790. if (ucontrol->value.integer.value[0])
  791. ucontrol->value.integer.value[0] =
  792. max + 1 - ucontrol->value.integer.value[0];
  793. if (shift != rshift) {
  794. ucontrol->value.integer.value[1] =
  795. (snd_soc_read(codec, reg) >> rshift) & mask;
  796. if (ucontrol->value.integer.value[1])
  797. ucontrol->value.integer.value[1] =
  798. max + 1 - ucontrol->value.integer.value[1];
  799. }
  800. return 0;
  801. }
  802. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  803. struct snd_ctl_elem_value *ucontrol)
  804. {
  805. struct soc_mixer_control *mc =
  806. (struct soc_mixer_control *)kcontrol->private_value;
  807. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  808. unsigned int reg = mc->reg;
  809. unsigned int shift = mc->shift;
  810. unsigned int rshift = mc->rshift;
  811. int max = mc->max;
  812. int mask = (1 << fls(max)) - 1;
  813. unsigned short val, val2, val_mask;
  814. val = (ucontrol->value.integer.value[0] & mask);
  815. val_mask = mask << shift;
  816. if (val)
  817. val = max + 1 - val;
  818. val = val << shift;
  819. if (shift != rshift) {
  820. val2 = (ucontrol->value.integer.value[1] & mask);
  821. val_mask |= mask << rshift;
  822. if (val2)
  823. val2 = max + 1 - val2;
  824. val |= val2 << rshift;
  825. }
  826. return snd_soc_update_bits(codec, reg, val_mask, val);
  827. }
  828. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. struct soc_mixer_control *mc =
  832. (struct soc_mixer_control *)kcontrol->private_value;
  833. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  834. unsigned int reg = mc->reg;
  835. unsigned int reg2 = mc->rreg;
  836. unsigned int shift = mc->shift;
  837. int max = mc->max;
  838. int mask = (1<<fls(max))-1;
  839. ucontrol->value.integer.value[0] =
  840. (snd_soc_read(codec, reg) >> shift) & mask;
  841. ucontrol->value.integer.value[1] =
  842. (snd_soc_read(codec, reg2) >> shift) & mask;
  843. if (ucontrol->value.integer.value[0])
  844. ucontrol->value.integer.value[0] =
  845. max + 1 - ucontrol->value.integer.value[0];
  846. if (ucontrol->value.integer.value[1])
  847. ucontrol->value.integer.value[1] =
  848. max + 1 - ucontrol->value.integer.value[1];
  849. return 0;
  850. }
  851. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  852. struct snd_ctl_elem_value *ucontrol)
  853. {
  854. struct soc_mixer_control *mc =
  855. (struct soc_mixer_control *)kcontrol->private_value;
  856. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  857. unsigned int reg = mc->reg;
  858. unsigned int reg2 = mc->rreg;
  859. unsigned int shift = mc->shift;
  860. int max = mc->max;
  861. int mask = (1 << fls(max)) - 1;
  862. int err;
  863. unsigned short val, val2, val_mask;
  864. val_mask = mask << shift;
  865. val = (ucontrol->value.integer.value[0] & mask);
  866. val2 = (ucontrol->value.integer.value[1] & mask);
  867. if (val)
  868. val = max + 1 - val;
  869. if (val2)
  870. val2 = max + 1 - val2;
  871. val = val << shift;
  872. val2 = val2 << shift;
  873. err = snd_soc_update_bits(codec, reg, val_mask, val);
  874. if (err < 0)
  875. return err;
  876. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  877. return err;
  878. }
  879. /* Codec operation modes */
  880. static const char *twl4030_op_modes_texts[] = {
  881. "Option 2 (voice/audio)", "Option 1 (audio)"
  882. };
  883. static const struct soc_enum twl4030_op_modes_enum =
  884. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  885. ARRAY_SIZE(twl4030_op_modes_texts),
  886. twl4030_op_modes_texts);
  887. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  888. struct snd_ctl_elem_value *ucontrol)
  889. {
  890. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  891. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  892. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  893. unsigned short val;
  894. unsigned short mask, bitmask;
  895. if (twl4030->configured) {
  896. printk(KERN_ERR "twl4030 operation mode cannot be "
  897. "changed on-the-fly\n");
  898. return -EBUSY;
  899. }
  900. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  901. ;
  902. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  903. return -EINVAL;
  904. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  905. mask = (bitmask - 1) << e->shift_l;
  906. if (e->shift_l != e->shift_r) {
  907. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  908. return -EINVAL;
  909. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  910. mask |= (bitmask - 1) << e->shift_r;
  911. }
  912. return snd_soc_update_bits(codec, e->reg, mask, val);
  913. }
  914. /*
  915. * FGAIN volume control:
  916. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  917. */
  918. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  919. /*
  920. * CGAIN volume control:
  921. * 0 dB to 12 dB in 6 dB steps
  922. * value 2 and 3 means 12 dB
  923. */
  924. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  925. /*
  926. * Voice Downlink GAIN volume control:
  927. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  928. */
  929. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  930. /*
  931. * Analog playback gain
  932. * -24 dB to 12 dB in 2 dB steps
  933. */
  934. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  935. /*
  936. * Gain controls tied to outputs
  937. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  938. */
  939. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  940. /*
  941. * Gain control for earpiece amplifier
  942. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  943. */
  944. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  945. /*
  946. * Capture gain after the ADCs
  947. * from 0 dB to 31 dB in 1 dB steps
  948. */
  949. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  950. /*
  951. * Gain control for input amplifiers
  952. * 0 dB to 30 dB in 6 dB steps
  953. */
  954. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  955. /* AVADC clock priority */
  956. static const char *twl4030_avadc_clk_priority_texts[] = {
  957. "Voice high priority", "HiFi high priority"
  958. };
  959. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  960. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  961. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  962. twl4030_avadc_clk_priority_texts);
  963. static const char *twl4030_rampdelay_texts[] = {
  964. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  965. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  966. "3495/2581/1748 ms"
  967. };
  968. static const struct soc_enum twl4030_rampdelay_enum =
  969. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  970. ARRAY_SIZE(twl4030_rampdelay_texts),
  971. twl4030_rampdelay_texts);
  972. /* Vibra H-bridge direction mode */
  973. static const char *twl4030_vibradirmode_texts[] = {
  974. "Vibra H-bridge direction", "Audio data MSB",
  975. };
  976. static const struct soc_enum twl4030_vibradirmode_enum =
  977. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  978. ARRAY_SIZE(twl4030_vibradirmode_texts),
  979. twl4030_vibradirmode_texts);
  980. /* Vibra H-bridge direction */
  981. static const char *twl4030_vibradir_texts[] = {
  982. "Positive polarity", "Negative polarity",
  983. };
  984. static const struct soc_enum twl4030_vibradir_enum =
  985. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  986. ARRAY_SIZE(twl4030_vibradir_texts),
  987. twl4030_vibradir_texts);
  988. /* Digimic Left and right swapping */
  989. static const char *twl4030_digimicswap_texts[] = {
  990. "Not swapped", "Swapped",
  991. };
  992. static const struct soc_enum twl4030_digimicswap_enum =
  993. SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
  994. ARRAY_SIZE(twl4030_digimicswap_texts),
  995. twl4030_digimicswap_texts);
  996. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  997. /* Codec operation mode control */
  998. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  999. snd_soc_get_enum_double,
  1000. snd_soc_put_twl4030_opmode_enum_double),
  1001. /* Common playback gain controls */
  1002. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  1003. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1004. 0, 0x3f, 0, digital_fine_tlv),
  1005. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  1006. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1007. 0, 0x3f, 0, digital_fine_tlv),
  1008. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  1009. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1010. 6, 0x2, 0, digital_coarse_tlv),
  1011. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  1012. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1013. 6, 0x2, 0, digital_coarse_tlv),
  1014. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  1015. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1016. 3, 0x12, 1, analog_tlv),
  1017. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  1018. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1019. 3, 0x12, 1, analog_tlv),
  1020. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  1021. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1022. 1, 1, 0),
  1023. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  1024. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1025. 1, 1, 0),
  1026. /* Common voice downlink gain controls */
  1027. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  1028. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  1029. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  1030. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  1031. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  1032. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  1033. /* Separate output gain controls */
  1034. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  1035. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  1036. 4, 3, 0, output_tvl),
  1037. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  1038. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  1039. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  1040. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  1041. 4, 3, 0, output_tvl),
  1042. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  1043. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  1044. /* Common capture gain controls */
  1045. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  1046. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  1047. 0, 0x1f, 0, digital_capture_tlv),
  1048. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  1049. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  1050. 0, 0x1f, 0, digital_capture_tlv),
  1051. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  1052. 0, 3, 5, 0, input_gain_tlv),
  1053. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  1054. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  1055. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  1056. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  1057. SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
  1058. };
  1059. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  1060. /* Left channel inputs */
  1061. SND_SOC_DAPM_INPUT("MAINMIC"),
  1062. SND_SOC_DAPM_INPUT("HSMIC"),
  1063. SND_SOC_DAPM_INPUT("AUXL"),
  1064. SND_SOC_DAPM_INPUT("CARKITMIC"),
  1065. /* Right channel inputs */
  1066. SND_SOC_DAPM_INPUT("SUBMIC"),
  1067. SND_SOC_DAPM_INPUT("AUXR"),
  1068. /* Digital microphones (Stereo) */
  1069. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1070. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1071. /* Outputs */
  1072. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1073. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1074. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1075. SND_SOC_DAPM_OUTPUT("HSOL"),
  1076. SND_SOC_DAPM_OUTPUT("HSOR"),
  1077. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1078. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1079. SND_SOC_DAPM_OUTPUT("HFL"),
  1080. SND_SOC_DAPM_OUTPUT("HFR"),
  1081. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1082. /* AIF and APLL clocks for running DAIs (including loopback) */
  1083. SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
  1084. SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
  1085. SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
  1086. /* DACs */
  1087. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1088. SND_SOC_NOPM, 0, 0),
  1089. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1090. SND_SOC_NOPM, 0, 0),
  1091. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1092. SND_SOC_NOPM, 0, 0),
  1093. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1094. SND_SOC_NOPM, 0, 0),
  1095. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1096. SND_SOC_NOPM, 0, 0),
  1097. /* Analog bypasses */
  1098. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1099. &twl4030_dapm_abypassr1_control),
  1100. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1101. &twl4030_dapm_abypassl1_control),
  1102. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1103. &twl4030_dapm_abypassr2_control),
  1104. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1105. &twl4030_dapm_abypassl2_control),
  1106. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1107. &twl4030_dapm_abypassv_control),
  1108. /* Master analog loopback switch */
  1109. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1110. NULL, 0),
  1111. /* Digital bypasses */
  1112. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1113. &twl4030_dapm_dbypassl_control),
  1114. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1115. &twl4030_dapm_dbypassr_control),
  1116. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1117. &twl4030_dapm_dbypassv_control),
  1118. /* Digital mixers, power control for the physical DACs */
  1119. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1120. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1121. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1122. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1123. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1124. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1125. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1126. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1127. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1128. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1129. /* Analog mixers, power control for the physical PGAs */
  1130. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1131. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1132. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1133. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1134. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1135. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1136. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1137. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1138. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1139. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1140. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1141. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1142. SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
  1143. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1144. /* Output MIXER controls */
  1145. /* Earpiece */
  1146. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1147. &twl4030_dapm_earpiece_controls[0],
  1148. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1149. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1150. 0, 0, NULL, 0, earpiecepga_event,
  1151. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1152. /* PreDrivL/R */
  1153. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1154. &twl4030_dapm_predrivel_controls[0],
  1155. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1156. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1157. 0, 0, NULL, 0, predrivelpga_event,
  1158. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1159. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1160. &twl4030_dapm_predriver_controls[0],
  1161. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1162. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1163. 0, 0, NULL, 0, predriverpga_event,
  1164. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1165. /* HeadsetL/R */
  1166. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1167. &twl4030_dapm_hsol_controls[0],
  1168. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1169. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1170. 0, 0, NULL, 0, headsetlpga_event,
  1171. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1172. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1173. &twl4030_dapm_hsor_controls[0],
  1174. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1175. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1176. 0, 0, NULL, 0, headsetrpga_event,
  1177. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1178. /* CarkitL/R */
  1179. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1180. &twl4030_dapm_carkitl_controls[0],
  1181. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1182. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1183. 0, 0, NULL, 0, carkitlpga_event,
  1184. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1185. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1186. &twl4030_dapm_carkitr_controls[0],
  1187. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1188. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1189. 0, 0, NULL, 0, carkitrpga_event,
  1190. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1191. /* Output MUX controls */
  1192. /* HandsfreeL/R */
  1193. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1194. &twl4030_dapm_handsfreel_control),
  1195. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1196. &twl4030_dapm_handsfreelmute_control),
  1197. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1198. 0, 0, NULL, 0, handsfreelpga_event,
  1199. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1200. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1201. &twl4030_dapm_handsfreer_control),
  1202. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1203. &twl4030_dapm_handsfreermute_control),
  1204. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1205. 0, 0, NULL, 0, handsfreerpga_event,
  1206. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1207. /* Vibra */
  1208. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1209. &twl4030_dapm_vibra_control, vibramux_event,
  1210. SND_SOC_DAPM_PRE_PMU),
  1211. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1212. &twl4030_dapm_vibrapath_control),
  1213. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1214. capture */
  1215. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1216. SND_SOC_NOPM, 0, 0),
  1217. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1218. SND_SOC_NOPM, 0, 0),
  1219. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1220. SND_SOC_NOPM, 0, 0),
  1221. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1222. SND_SOC_NOPM, 0, 0),
  1223. /* Analog/Digital mic path selection.
  1224. TX1 Left/Right: either analog Left/Right or Digimic0
  1225. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1226. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1227. &twl4030_dapm_micpathtx1_control, micpath_event,
  1228. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1229. SND_SOC_DAPM_POST_REG),
  1230. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1231. &twl4030_dapm_micpathtx2_control, micpath_event,
  1232. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1233. SND_SOC_DAPM_POST_REG),
  1234. /* Analog input mixers for the capture amplifiers */
  1235. SND_SOC_DAPM_MIXER("Analog Left",
  1236. TWL4030_REG_ANAMICL, 4, 0,
  1237. &twl4030_dapm_analoglmic_controls[0],
  1238. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1239. SND_SOC_DAPM_MIXER("Analog Right",
  1240. TWL4030_REG_ANAMICR, 4, 0,
  1241. &twl4030_dapm_analogrmic_controls[0],
  1242. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1243. SND_SOC_DAPM_PGA("ADC Physical Left",
  1244. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1245. SND_SOC_DAPM_PGA("ADC Physical Right",
  1246. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1247. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1248. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1249. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1250. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1251. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1252. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1253. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1254. };
  1255. static const struct snd_soc_dapm_route intercon[] = {
  1256. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1257. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1258. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1259. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1260. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1261. /* Supply for the digital part (APLL) */
  1262. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1263. {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
  1264. {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
  1265. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1266. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1267. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1268. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1269. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1270. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1271. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1272. /* Internal playback routings */
  1273. /* Earpiece */
  1274. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1275. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1276. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1277. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1278. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1279. /* PreDrivL */
  1280. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1281. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1282. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1283. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1284. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1285. /* PreDrivR */
  1286. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1287. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1288. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1289. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1290. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1291. /* HeadsetL */
  1292. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1293. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1294. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1295. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1296. /* HeadsetR */
  1297. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1298. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1299. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1300. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1301. /* CarkitL */
  1302. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1303. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1304. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1305. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1306. /* CarkitR */
  1307. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1308. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1309. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1310. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1311. /* HandsfreeL */
  1312. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1313. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1314. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1315. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1316. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1317. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1318. /* HandsfreeR */
  1319. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1320. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1321. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1322. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1323. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1324. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1325. /* Vibra */
  1326. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1327. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1328. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1329. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1330. /* outputs */
  1331. /* Must be always connected (for AIF and APLL) */
  1332. {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
  1333. {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
  1334. {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
  1335. {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
  1336. /* Must be always connected (for APLL) */
  1337. {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
  1338. /* Physical outputs */
  1339. {"EARPIECE", NULL, "Earpiece PGA"},
  1340. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1341. {"PREDRIVER", NULL, "PredriveR PGA"},
  1342. {"HSOL", NULL, "HeadsetL PGA"},
  1343. {"HSOR", NULL, "HeadsetR PGA"},
  1344. {"CARKITL", NULL, "CarkitL PGA"},
  1345. {"CARKITR", NULL, "CarkitR PGA"},
  1346. {"HFL", NULL, "HandsfreeL PGA"},
  1347. {"HFR", NULL, "HandsfreeR PGA"},
  1348. {"Vibra Route", "Audio", "Vibra Mux"},
  1349. {"VIBRA", NULL, "Vibra Route"},
  1350. /* Capture path */
  1351. /* Must be always connected (for AIF and APLL) */
  1352. {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
  1353. {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
  1354. {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
  1355. {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
  1356. /* Physical inputs */
  1357. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1358. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1359. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1360. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1361. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1362. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1363. {"ADC Physical Left", NULL, "Analog Left"},
  1364. {"ADC Physical Right", NULL, "Analog Right"},
  1365. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1366. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1367. /* TX1 Left capture path */
  1368. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1369. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1370. /* TX1 Right capture path */
  1371. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1372. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1373. /* TX2 Left capture path */
  1374. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1375. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1376. /* TX2 Right capture path */
  1377. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1378. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1379. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1380. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1381. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1382. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1383. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1384. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1385. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1386. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1387. /* Analog bypass routes */
  1388. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1389. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1390. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1391. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1392. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1393. /* Supply for the Analog loopbacks */
  1394. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1395. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1396. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1397. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1398. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1399. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1400. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1401. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1402. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1403. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1404. /* Digital bypass routes */
  1405. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1406. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1407. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1408. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1409. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1410. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1411. };
  1412. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1413. {
  1414. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1415. ARRAY_SIZE(twl4030_dapm_widgets));
  1416. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1417. return 0;
  1418. }
  1419. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1420. enum snd_soc_bias_level level)
  1421. {
  1422. switch (level) {
  1423. case SND_SOC_BIAS_ON:
  1424. break;
  1425. case SND_SOC_BIAS_PREPARE:
  1426. break;
  1427. case SND_SOC_BIAS_STANDBY:
  1428. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1429. twl4030_codec_enable(codec, 1);
  1430. break;
  1431. case SND_SOC_BIAS_OFF:
  1432. twl4030_codec_enable(codec, 0);
  1433. break;
  1434. }
  1435. codec->bias_level = level;
  1436. return 0;
  1437. }
  1438. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1439. struct snd_pcm_substream *mst_substream)
  1440. {
  1441. struct snd_pcm_substream *slv_substream;
  1442. /* Pick the stream, which need to be constrained */
  1443. if (mst_substream == twl4030->master_substream)
  1444. slv_substream = twl4030->slave_substream;
  1445. else if (mst_substream == twl4030->slave_substream)
  1446. slv_substream = twl4030->master_substream;
  1447. else /* This should not happen.. */
  1448. return;
  1449. /* Set the constraints according to the already configured stream */
  1450. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1451. SNDRV_PCM_HW_PARAM_RATE,
  1452. twl4030->rate,
  1453. twl4030->rate);
  1454. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1455. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1456. twl4030->sample_bits,
  1457. twl4030->sample_bits);
  1458. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1459. SNDRV_PCM_HW_PARAM_CHANNELS,
  1460. twl4030->channels,
  1461. twl4030->channels);
  1462. }
  1463. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1464. * capture has to be enabled/disabled. */
  1465. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1466. int enable)
  1467. {
  1468. u8 reg, mask;
  1469. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1470. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1471. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1472. else
  1473. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1474. if (enable)
  1475. reg |= mask;
  1476. else
  1477. reg &= ~mask;
  1478. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1479. }
  1480. static int twl4030_startup(struct snd_pcm_substream *substream,
  1481. struct snd_soc_dai *dai)
  1482. {
  1483. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1484. struct snd_soc_device *socdev = rtd->socdev;
  1485. struct snd_soc_codec *codec = socdev->card->codec;
  1486. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1487. if (twl4030->master_substream) {
  1488. twl4030->slave_substream = substream;
  1489. /* The DAI has one configuration for playback and capture, so
  1490. * if the DAI has been already configured then constrain this
  1491. * substream to match it. */
  1492. if (twl4030->configured)
  1493. twl4030_constraints(twl4030, twl4030->master_substream);
  1494. } else {
  1495. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1496. TWL4030_OPTION_1)) {
  1497. /* In option2 4 channel is not supported, set the
  1498. * constraint for the first stream for channels, the
  1499. * second stream will 'inherit' this cosntraint */
  1500. snd_pcm_hw_constraint_minmax(substream->runtime,
  1501. SNDRV_PCM_HW_PARAM_CHANNELS,
  1502. 2, 2);
  1503. }
  1504. twl4030->master_substream = substream;
  1505. }
  1506. return 0;
  1507. }
  1508. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1509. struct snd_soc_dai *dai)
  1510. {
  1511. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1512. struct snd_soc_device *socdev = rtd->socdev;
  1513. struct snd_soc_codec *codec = socdev->card->codec;
  1514. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1515. if (twl4030->master_substream == substream)
  1516. twl4030->master_substream = twl4030->slave_substream;
  1517. twl4030->slave_substream = NULL;
  1518. /* If all streams are closed, or the remaining stream has not yet
  1519. * been configured than set the DAI as not configured. */
  1520. if (!twl4030->master_substream)
  1521. twl4030->configured = 0;
  1522. else if (!twl4030->master_substream->runtime->channels)
  1523. twl4030->configured = 0;
  1524. /* If the closing substream had 4 channel, do the necessary cleanup */
  1525. if (substream->runtime->channels == 4)
  1526. twl4030_tdm_enable(codec, substream->stream, 0);
  1527. }
  1528. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1529. struct snd_pcm_hw_params *params,
  1530. struct snd_soc_dai *dai)
  1531. {
  1532. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1533. struct snd_soc_device *socdev = rtd->socdev;
  1534. struct snd_soc_codec *codec = socdev->card->codec;
  1535. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1536. u8 mode, old_mode, format, old_format;
  1537. /* If the substream has 4 channel, do the necessary setup */
  1538. if (params_channels(params) == 4) {
  1539. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1540. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1541. /* Safety check: are we in the correct operating mode and
  1542. * the interface is in TDM mode? */
  1543. if ((mode & TWL4030_OPTION_1) &&
  1544. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1545. twl4030_tdm_enable(codec, substream->stream, 1);
  1546. else
  1547. return -EINVAL;
  1548. }
  1549. if (twl4030->configured)
  1550. /* Ignoring hw_params for already configured DAI */
  1551. return 0;
  1552. /* bit rate */
  1553. old_mode = twl4030_read_reg_cache(codec,
  1554. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1555. mode = old_mode & ~TWL4030_APLL_RATE;
  1556. switch (params_rate(params)) {
  1557. case 8000:
  1558. mode |= TWL4030_APLL_RATE_8000;
  1559. break;
  1560. case 11025:
  1561. mode |= TWL4030_APLL_RATE_11025;
  1562. break;
  1563. case 12000:
  1564. mode |= TWL4030_APLL_RATE_12000;
  1565. break;
  1566. case 16000:
  1567. mode |= TWL4030_APLL_RATE_16000;
  1568. break;
  1569. case 22050:
  1570. mode |= TWL4030_APLL_RATE_22050;
  1571. break;
  1572. case 24000:
  1573. mode |= TWL4030_APLL_RATE_24000;
  1574. break;
  1575. case 32000:
  1576. mode |= TWL4030_APLL_RATE_32000;
  1577. break;
  1578. case 44100:
  1579. mode |= TWL4030_APLL_RATE_44100;
  1580. break;
  1581. case 48000:
  1582. mode |= TWL4030_APLL_RATE_48000;
  1583. break;
  1584. case 96000:
  1585. mode |= TWL4030_APLL_RATE_96000;
  1586. break;
  1587. default:
  1588. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1589. params_rate(params));
  1590. return -EINVAL;
  1591. }
  1592. /* sample size */
  1593. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1594. format = old_format;
  1595. format &= ~TWL4030_DATA_WIDTH;
  1596. switch (params_format(params)) {
  1597. case SNDRV_PCM_FORMAT_S16_LE:
  1598. format |= TWL4030_DATA_WIDTH_16S_16W;
  1599. break;
  1600. case SNDRV_PCM_FORMAT_S24_LE:
  1601. format |= TWL4030_DATA_WIDTH_32S_24W;
  1602. break;
  1603. default:
  1604. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1605. params_format(params));
  1606. return -EINVAL;
  1607. }
  1608. if (format != old_format || mode != old_mode) {
  1609. if (twl4030->codec_powered) {
  1610. /*
  1611. * If the codec is powered, than we need to toggle the
  1612. * codec power.
  1613. */
  1614. twl4030_codec_enable(codec, 0);
  1615. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1616. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1617. twl4030_codec_enable(codec, 1);
  1618. } else {
  1619. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1620. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1621. }
  1622. }
  1623. /* Store the important parameters for the DAI configuration and set
  1624. * the DAI as configured */
  1625. twl4030->configured = 1;
  1626. twl4030->rate = params_rate(params);
  1627. twl4030->sample_bits = hw_param_interval(params,
  1628. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1629. twl4030->channels = params_channels(params);
  1630. /* If both playback and capture streams are open, and one of them
  1631. * is setting the hw parameters right now (since we are here), set
  1632. * constraints to the other stream to match the current one. */
  1633. if (twl4030->slave_substream)
  1634. twl4030_constraints(twl4030, substream);
  1635. return 0;
  1636. }
  1637. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1638. int clk_id, unsigned int freq, int dir)
  1639. {
  1640. struct snd_soc_codec *codec = codec_dai->codec;
  1641. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1642. switch (freq) {
  1643. case 19200000:
  1644. case 26000000:
  1645. case 38400000:
  1646. break;
  1647. default:
  1648. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1649. return -EINVAL;
  1650. }
  1651. if ((freq / 1000) != twl4030->sysclk) {
  1652. dev_err(codec->dev,
  1653. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1654. freq, twl4030->sysclk * 1000);
  1655. return -EINVAL;
  1656. }
  1657. return 0;
  1658. }
  1659. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1660. unsigned int fmt)
  1661. {
  1662. struct snd_soc_codec *codec = codec_dai->codec;
  1663. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1664. u8 old_format, format;
  1665. /* get format */
  1666. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1667. format = old_format;
  1668. /* set master/slave audio interface */
  1669. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1670. case SND_SOC_DAIFMT_CBM_CFM:
  1671. format &= ~(TWL4030_AIF_SLAVE_EN);
  1672. format &= ~(TWL4030_CLK256FS_EN);
  1673. break;
  1674. case SND_SOC_DAIFMT_CBS_CFS:
  1675. format |= TWL4030_AIF_SLAVE_EN;
  1676. format |= TWL4030_CLK256FS_EN;
  1677. break;
  1678. default:
  1679. return -EINVAL;
  1680. }
  1681. /* interface format */
  1682. format &= ~TWL4030_AIF_FORMAT;
  1683. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1684. case SND_SOC_DAIFMT_I2S:
  1685. format |= TWL4030_AIF_FORMAT_CODEC;
  1686. break;
  1687. case SND_SOC_DAIFMT_DSP_A:
  1688. format |= TWL4030_AIF_FORMAT_TDM;
  1689. break;
  1690. default:
  1691. return -EINVAL;
  1692. }
  1693. if (format != old_format) {
  1694. if (twl4030->codec_powered) {
  1695. /*
  1696. * If the codec is powered, than we need to toggle the
  1697. * codec power.
  1698. */
  1699. twl4030_codec_enable(codec, 0);
  1700. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1701. twl4030_codec_enable(codec, 1);
  1702. } else {
  1703. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1704. }
  1705. }
  1706. return 0;
  1707. }
  1708. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1709. {
  1710. struct snd_soc_codec *codec = dai->codec;
  1711. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1712. if (tristate)
  1713. reg |= TWL4030_AIF_TRI_EN;
  1714. else
  1715. reg &= ~TWL4030_AIF_TRI_EN;
  1716. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1717. }
  1718. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1719. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1720. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1721. int enable)
  1722. {
  1723. u8 reg, mask;
  1724. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1725. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1726. mask = TWL4030_ARXL1_VRX_EN;
  1727. else
  1728. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1729. if (enable)
  1730. reg |= mask;
  1731. else
  1732. reg &= ~mask;
  1733. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1734. }
  1735. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1736. struct snd_soc_dai *dai)
  1737. {
  1738. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1739. struct snd_soc_device *socdev = rtd->socdev;
  1740. struct snd_soc_codec *codec = socdev->card->codec;
  1741. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1742. u8 mode;
  1743. /* If the system master clock is not 26MHz, the voice PCM interface is
  1744. * not avilable.
  1745. */
  1746. if (twl4030->sysclk != 26000) {
  1747. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1748. "the Voice interface needs 26MHz APLL mclk\n",
  1749. twl4030->sysclk * 1000);
  1750. return -EINVAL;
  1751. }
  1752. /* If the codec mode is not option2, the voice PCM interface is not
  1753. * avilable.
  1754. */
  1755. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1756. & TWL4030_OPT_MODE;
  1757. if (mode != TWL4030_OPTION_2) {
  1758. printk(KERN_ERR "TWL4030 voice startup: "
  1759. "the codec mode is not option2\n");
  1760. return -EINVAL;
  1761. }
  1762. return 0;
  1763. }
  1764. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1765. struct snd_soc_dai *dai)
  1766. {
  1767. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1768. struct snd_soc_device *socdev = rtd->socdev;
  1769. struct snd_soc_codec *codec = socdev->card->codec;
  1770. /* Enable voice digital filters */
  1771. twl4030_voice_enable(codec, substream->stream, 0);
  1772. }
  1773. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1774. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1775. {
  1776. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1777. struct snd_soc_device *socdev = rtd->socdev;
  1778. struct snd_soc_codec *codec = socdev->card->codec;
  1779. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1780. u8 old_mode, mode;
  1781. /* Enable voice digital filters */
  1782. twl4030_voice_enable(codec, substream->stream, 1);
  1783. /* bit rate */
  1784. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1785. & ~(TWL4030_CODECPDZ);
  1786. mode = old_mode;
  1787. switch (params_rate(params)) {
  1788. case 8000:
  1789. mode &= ~(TWL4030_SEL_16K);
  1790. break;
  1791. case 16000:
  1792. mode |= TWL4030_SEL_16K;
  1793. break;
  1794. default:
  1795. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1796. params_rate(params));
  1797. return -EINVAL;
  1798. }
  1799. if (mode != old_mode) {
  1800. if (twl4030->codec_powered) {
  1801. /*
  1802. * If the codec is powered, than we need to toggle the
  1803. * codec power.
  1804. */
  1805. twl4030_codec_enable(codec, 0);
  1806. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1807. twl4030_codec_enable(codec, 1);
  1808. } else {
  1809. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1810. }
  1811. }
  1812. return 0;
  1813. }
  1814. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1815. int clk_id, unsigned int freq, int dir)
  1816. {
  1817. struct snd_soc_codec *codec = codec_dai->codec;
  1818. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1819. if (freq != 26000000) {
  1820. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1821. "interface needs 26MHz APLL mclk\n", freq);
  1822. return -EINVAL;
  1823. }
  1824. if ((freq / 1000) != twl4030->sysclk) {
  1825. dev_err(codec->dev,
  1826. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1827. freq, twl4030->sysclk * 1000);
  1828. return -EINVAL;
  1829. }
  1830. return 0;
  1831. }
  1832. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1833. unsigned int fmt)
  1834. {
  1835. struct snd_soc_codec *codec = codec_dai->codec;
  1836. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1837. u8 old_format, format;
  1838. /* get format */
  1839. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1840. format = old_format;
  1841. /* set master/slave audio interface */
  1842. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1843. case SND_SOC_DAIFMT_CBM_CFM:
  1844. format &= ~(TWL4030_VIF_SLAVE_EN);
  1845. break;
  1846. case SND_SOC_DAIFMT_CBS_CFS:
  1847. format |= TWL4030_VIF_SLAVE_EN;
  1848. break;
  1849. default:
  1850. return -EINVAL;
  1851. }
  1852. /* clock inversion */
  1853. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1854. case SND_SOC_DAIFMT_IB_NF:
  1855. format &= ~(TWL4030_VIF_FORMAT);
  1856. break;
  1857. case SND_SOC_DAIFMT_NB_IF:
  1858. format |= TWL4030_VIF_FORMAT;
  1859. break;
  1860. default:
  1861. return -EINVAL;
  1862. }
  1863. if (format != old_format) {
  1864. if (twl4030->codec_powered) {
  1865. /*
  1866. * If the codec is powered, than we need to toggle the
  1867. * codec power.
  1868. */
  1869. twl4030_codec_enable(codec, 0);
  1870. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1871. twl4030_codec_enable(codec, 1);
  1872. } else {
  1873. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1874. }
  1875. }
  1876. return 0;
  1877. }
  1878. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1879. {
  1880. struct snd_soc_codec *codec = dai->codec;
  1881. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1882. if (tristate)
  1883. reg |= TWL4030_VIF_TRI_EN;
  1884. else
  1885. reg &= ~TWL4030_VIF_TRI_EN;
  1886. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1887. }
  1888. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1889. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1890. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1891. .startup = twl4030_startup,
  1892. .shutdown = twl4030_shutdown,
  1893. .hw_params = twl4030_hw_params,
  1894. .set_sysclk = twl4030_set_dai_sysclk,
  1895. .set_fmt = twl4030_set_dai_fmt,
  1896. .set_tristate = twl4030_set_tristate,
  1897. };
  1898. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1899. .startup = twl4030_voice_startup,
  1900. .shutdown = twl4030_voice_shutdown,
  1901. .hw_params = twl4030_voice_hw_params,
  1902. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1903. .set_fmt = twl4030_voice_set_dai_fmt,
  1904. .set_tristate = twl4030_voice_set_tristate,
  1905. };
  1906. struct snd_soc_dai twl4030_dai[] = {
  1907. {
  1908. .name = "twl4030",
  1909. .playback = {
  1910. .stream_name = "HiFi Playback",
  1911. .channels_min = 2,
  1912. .channels_max = 4,
  1913. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1914. .formats = TWL4030_FORMATS,},
  1915. .capture = {
  1916. .stream_name = "Capture",
  1917. .channels_min = 2,
  1918. .channels_max = 4,
  1919. .rates = TWL4030_RATES,
  1920. .formats = TWL4030_FORMATS,},
  1921. .ops = &twl4030_dai_ops,
  1922. },
  1923. {
  1924. .name = "twl4030 Voice",
  1925. .playback = {
  1926. .stream_name = "Voice Playback",
  1927. .channels_min = 1,
  1928. .channels_max = 1,
  1929. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1930. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1931. .capture = {
  1932. .stream_name = "Capture",
  1933. .channels_min = 1,
  1934. .channels_max = 2,
  1935. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1936. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1937. .ops = &twl4030_dai_voice_ops,
  1938. },
  1939. };
  1940. EXPORT_SYMBOL_GPL(twl4030_dai);
  1941. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1942. {
  1943. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1944. struct snd_soc_codec *codec = socdev->card->codec;
  1945. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1946. return 0;
  1947. }
  1948. static int twl4030_soc_resume(struct platform_device *pdev)
  1949. {
  1950. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1951. struct snd_soc_codec *codec = socdev->card->codec;
  1952. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1953. return 0;
  1954. }
  1955. static struct snd_soc_codec *twl4030_codec;
  1956. static int twl4030_soc_probe(struct platform_device *pdev)
  1957. {
  1958. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1959. struct snd_soc_codec *codec;
  1960. int ret;
  1961. BUG_ON(!twl4030_codec);
  1962. codec = twl4030_codec;
  1963. socdev->card->codec = codec;
  1964. twl4030_init_chip(pdev);
  1965. /* register pcms */
  1966. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1967. if (ret < 0) {
  1968. dev_err(&pdev->dev, "failed to create pcms\n");
  1969. return ret;
  1970. }
  1971. snd_soc_add_controls(codec, twl4030_snd_controls,
  1972. ARRAY_SIZE(twl4030_snd_controls));
  1973. twl4030_add_widgets(codec);
  1974. return 0;
  1975. }
  1976. static int twl4030_soc_remove(struct platform_device *pdev)
  1977. {
  1978. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1979. struct snd_soc_codec *codec = socdev->card->codec;
  1980. /* Reset registers to their chip default before leaving */
  1981. twl4030_reset_registers(codec);
  1982. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1983. snd_soc_free_pcms(socdev);
  1984. snd_soc_dapm_free(socdev);
  1985. return 0;
  1986. }
  1987. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1988. {
  1989. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1990. struct snd_soc_codec *codec;
  1991. struct twl4030_priv *twl4030;
  1992. int ret;
  1993. if (!pdata) {
  1994. dev_err(&pdev->dev, "platform_data is missing\n");
  1995. return -EINVAL;
  1996. }
  1997. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1998. if (twl4030 == NULL) {
  1999. dev_err(&pdev->dev, "Can not allocate memroy\n");
  2000. return -ENOMEM;
  2001. }
  2002. codec = &twl4030->codec;
  2003. snd_soc_codec_set_drvdata(codec, twl4030);
  2004. codec->dev = &pdev->dev;
  2005. twl4030_dai[0].dev = &pdev->dev;
  2006. twl4030_dai[1].dev = &pdev->dev;
  2007. mutex_init(&codec->mutex);
  2008. INIT_LIST_HEAD(&codec->dapm_widgets);
  2009. INIT_LIST_HEAD(&codec->dapm_paths);
  2010. codec->name = "twl4030";
  2011. codec->owner = THIS_MODULE;
  2012. codec->read = twl4030_read_reg_cache;
  2013. codec->write = twl4030_write;
  2014. codec->set_bias_level = twl4030_set_bias_level;
  2015. codec->idle_bias_off = 1;
  2016. codec->dai = twl4030_dai;
  2017. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  2018. codec->reg_cache_size = sizeof(twl4030_reg);
  2019. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  2020. GFP_KERNEL);
  2021. if (codec->reg_cache == NULL) {
  2022. ret = -ENOMEM;
  2023. goto error_cache;
  2024. }
  2025. platform_set_drvdata(pdev, twl4030);
  2026. twl4030_codec = codec;
  2027. /* Set the defaults, and power up the codec */
  2028. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  2029. codec->bias_level = SND_SOC_BIAS_OFF;
  2030. ret = snd_soc_register_codec(codec);
  2031. if (ret != 0) {
  2032. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  2033. goto error_codec;
  2034. }
  2035. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2036. if (ret != 0) {
  2037. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  2038. snd_soc_unregister_codec(codec);
  2039. goto error_codec;
  2040. }
  2041. return 0;
  2042. error_codec:
  2043. twl4030_codec_enable(codec, 0);
  2044. kfree(codec->reg_cache);
  2045. error_cache:
  2046. kfree(twl4030);
  2047. return ret;
  2048. }
  2049. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  2050. {
  2051. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  2052. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2053. snd_soc_unregister_codec(&twl4030->codec);
  2054. kfree(twl4030->codec.reg_cache);
  2055. kfree(twl4030);
  2056. twl4030_codec = NULL;
  2057. return 0;
  2058. }
  2059. MODULE_ALIAS("platform:twl4030_codec_audio");
  2060. static struct platform_driver twl4030_codec_driver = {
  2061. .probe = twl4030_codec_probe,
  2062. .remove = __devexit_p(twl4030_codec_remove),
  2063. .driver = {
  2064. .name = "twl4030_codec_audio",
  2065. .owner = THIS_MODULE,
  2066. },
  2067. };
  2068. static int __init twl4030_modinit(void)
  2069. {
  2070. return platform_driver_register(&twl4030_codec_driver);
  2071. }
  2072. module_init(twl4030_modinit);
  2073. static void __exit twl4030_exit(void)
  2074. {
  2075. platform_driver_unregister(&twl4030_codec_driver);
  2076. }
  2077. module_exit(twl4030_exit);
  2078. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  2079. .probe = twl4030_soc_probe,
  2080. .remove = twl4030_soc_remove,
  2081. .suspend = twl4030_soc_suspend,
  2082. .resume = twl4030_soc_resume,
  2083. };
  2084. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  2085. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2086. MODULE_AUTHOR("Steve Sakoman");
  2087. MODULE_LICENSE("GPL");