iwl3945-base.c 233 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-3945-core.h"
  47. #include "iwl-commands.h"
  48. #include "iwl-3945.h"
  49. #include "iwl-3945-fh.h"
  50. #include "iwl-helpers.h"
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. */
  68. #define DRV_DESCRIPTION \
  69. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  70. #ifdef CONFIG_IWL3945_DEBUG
  71. #define VD "d"
  72. #else
  73. #define VD
  74. #endif
  75. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  76. #define VS "s"
  77. #else
  78. #define VS
  79. #endif
  80. #define IWLWIFI_VERSION "1.2.26k" VD VS
  81. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  82. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  83. #define DRV_VERSION IWLWIFI_VERSION
  84. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85. MODULE_VERSION(DRV_VERSION);
  86. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87. MODULE_LICENSE("GPL");
  88. static const struct ieee80211_supported_band *iwl3945_get_band(
  89. struct iwl3945_priv *priv, enum ieee80211_band band)
  90. {
  91. return priv->hw->wiphy->bands[band];
  92. }
  93. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  94. * DMA services
  95. *
  96. * Theory of operation
  97. *
  98. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  99. * of buffer descriptors, each of which points to one or more data buffers for
  100. * the device to read from or fill. Driver and device exchange status of each
  101. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  102. * entries in each circular buffer, to protect against confusing empty and full
  103. * queue states.
  104. *
  105. * The device reads or writes the data in the queues via the device's several
  106. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  107. *
  108. * For Tx queue, there are low mark and high mark limits. If, after queuing
  109. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  110. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  111. * Tx queue resumed.
  112. *
  113. * The 3945 operates with six queues: One receive queue, one transmit queue
  114. * (#4) for sending commands to the device firmware, and four transmit queues
  115. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  116. ***************************************************/
  117. int iwl3945_queue_space(const struct iwl3945_queue *q)
  118. {
  119. int s = q->read_ptr - q->write_ptr;
  120. if (q->read_ptr > q->write_ptr)
  121. s -= q->n_bd;
  122. if (s <= 0)
  123. s += q->n_window;
  124. /* keep some reserve to not confuse empty and full situations */
  125. s -= 2;
  126. if (s < 0)
  127. s = 0;
  128. return s;
  129. }
  130. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  131. {
  132. return q->write_ptr > q->read_ptr ?
  133. (i >= q->read_ptr && i < q->write_ptr) :
  134. !(i < q->read_ptr && i >= q->write_ptr);
  135. }
  136. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  137. {
  138. /* This is for scan command, the big buffer at end of command array */
  139. if (is_huge)
  140. return q->n_window; /* must be power of 2 */
  141. /* Otherwise, use normal size buffers */
  142. return index & (q->n_window - 1);
  143. }
  144. /**
  145. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  146. */
  147. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  148. int count, int slots_num, u32 id)
  149. {
  150. q->n_bd = count;
  151. q->n_window = slots_num;
  152. q->id = id;
  153. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  154. * and iwl_queue_dec_wrap are broken. */
  155. BUG_ON(!is_power_of_2(count));
  156. /* slots_num must be power-of-two size, otherwise
  157. * get_cmd_index is broken. */
  158. BUG_ON(!is_power_of_2(slots_num));
  159. q->low_mark = q->n_window / 4;
  160. if (q->low_mark < 4)
  161. q->low_mark = 4;
  162. q->high_mark = q->n_window / 8;
  163. if (q->high_mark < 2)
  164. q->high_mark = 2;
  165. q->write_ptr = q->read_ptr = 0;
  166. return 0;
  167. }
  168. /**
  169. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  170. */
  171. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  172. struct iwl3945_tx_queue *txq, u32 id)
  173. {
  174. struct pci_dev *dev = priv->pci_dev;
  175. /* Driver private data, only for Tx (not command) queues,
  176. * not shared with device. */
  177. if (id != IWL_CMD_QUEUE_NUM) {
  178. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  179. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  180. if (!txq->txb) {
  181. IWL_ERROR("kmalloc for auxiliary BD "
  182. "structures failed\n");
  183. goto error;
  184. }
  185. } else
  186. txq->txb = NULL;
  187. /* Circular buffer of transmit frame descriptors (TFDs),
  188. * shared with device */
  189. txq->bd = pci_alloc_consistent(dev,
  190. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  191. &txq->q.dma_addr);
  192. if (!txq->bd) {
  193. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  194. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  195. goto error;
  196. }
  197. txq->q.id = id;
  198. return 0;
  199. error:
  200. kfree(txq->txb);
  201. txq->txb = NULL;
  202. return -ENOMEM;
  203. }
  204. /**
  205. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  206. */
  207. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  208. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  209. {
  210. struct pci_dev *dev = priv->pci_dev;
  211. int len;
  212. int rc = 0;
  213. /*
  214. * Alloc buffer array for commands (Tx or other types of commands).
  215. * For the command queue (#4), allocate command space + one big
  216. * command for scan, since scan command is very huge; the system will
  217. * not have two scans at the same time, so only one is needed.
  218. * For data Tx queues (all other queues), no super-size command
  219. * space is needed.
  220. */
  221. len = sizeof(struct iwl3945_cmd) * slots_num;
  222. if (txq_id == IWL_CMD_QUEUE_NUM)
  223. len += IWL_MAX_SCAN_SIZE;
  224. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  225. if (!txq->cmd)
  226. return -ENOMEM;
  227. /* Alloc driver data array and TFD circular buffer */
  228. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  229. if (rc) {
  230. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  231. return -ENOMEM;
  232. }
  233. txq->need_update = 0;
  234. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  235. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  236. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  237. /* Initialize queue high/low-water, head/tail indexes */
  238. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  239. /* Tell device where to find queue, enable DMA channel. */
  240. iwl3945_hw_tx_queue_init(priv, txq);
  241. return 0;
  242. }
  243. /**
  244. * iwl3945_tx_queue_free - Deallocate DMA queue.
  245. * @txq: Transmit queue to deallocate.
  246. *
  247. * Empty queue by removing and destroying all BD's.
  248. * Free all buffers.
  249. * 0-fill, but do not free "txq" descriptor structure.
  250. */
  251. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  252. {
  253. struct iwl3945_queue *q = &txq->q;
  254. struct pci_dev *dev = priv->pci_dev;
  255. int len;
  256. if (q->n_bd == 0)
  257. return;
  258. /* first, empty all BD's */
  259. for (; q->write_ptr != q->read_ptr;
  260. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  261. iwl3945_hw_txq_free_tfd(priv, txq);
  262. len = sizeof(struct iwl3945_cmd) * q->n_window;
  263. if (q->id == IWL_CMD_QUEUE_NUM)
  264. len += IWL_MAX_SCAN_SIZE;
  265. /* De-alloc array of command/tx buffers */
  266. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  267. /* De-alloc circular buffer of TFDs */
  268. if (txq->q.n_bd)
  269. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  270. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  271. /* De-alloc array of per-TFD driver data */
  272. kfree(txq->txb);
  273. txq->txb = NULL;
  274. /* 0-fill queue descriptor structure */
  275. memset(txq, 0, sizeof(*txq));
  276. }
  277. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  278. /*************** STATION TABLE MANAGEMENT ****
  279. * mac80211 should be examined to determine if sta_info is duplicating
  280. * the functionality provided here
  281. */
  282. /**************************************************************/
  283. #if 0 /* temporary disable till we add real remove station */
  284. /**
  285. * iwl3945_remove_station - Remove driver's knowledge of station.
  286. *
  287. * NOTE: This does not remove station from device's station table.
  288. */
  289. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  290. {
  291. int index = IWL_INVALID_STATION;
  292. int i;
  293. unsigned long flags;
  294. spin_lock_irqsave(&priv->sta_lock, flags);
  295. if (is_ap)
  296. index = IWL_AP_ID;
  297. else if (is_broadcast_ether_addr(addr))
  298. index = priv->hw_setting.bcast_sta_id;
  299. else
  300. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  301. if (priv->stations[i].used &&
  302. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  303. addr)) {
  304. index = i;
  305. break;
  306. }
  307. if (unlikely(index == IWL_INVALID_STATION))
  308. goto out;
  309. if (priv->stations[index].used) {
  310. priv->stations[index].used = 0;
  311. priv->num_stations--;
  312. }
  313. BUG_ON(priv->num_stations < 0);
  314. out:
  315. spin_unlock_irqrestore(&priv->sta_lock, flags);
  316. return 0;
  317. }
  318. #endif
  319. /**
  320. * iwl3945_clear_stations_table - Clear the driver's station table
  321. *
  322. * NOTE: This does not clear or otherwise alter the device's station table.
  323. */
  324. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  325. {
  326. unsigned long flags;
  327. spin_lock_irqsave(&priv->sta_lock, flags);
  328. priv->num_stations = 0;
  329. memset(priv->stations, 0, sizeof(priv->stations));
  330. spin_unlock_irqrestore(&priv->sta_lock, flags);
  331. }
  332. /**
  333. * iwl3945_add_station - Add station to station tables in driver and device
  334. */
  335. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  336. {
  337. int i;
  338. int index = IWL_INVALID_STATION;
  339. struct iwl3945_station_entry *station;
  340. unsigned long flags_spin;
  341. u8 rate;
  342. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  343. if (is_ap)
  344. index = IWL_AP_ID;
  345. else if (is_broadcast_ether_addr(addr))
  346. index = priv->hw_setting.bcast_sta_id;
  347. else
  348. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  349. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  350. addr)) {
  351. index = i;
  352. break;
  353. }
  354. if (!priv->stations[i].used &&
  355. index == IWL_INVALID_STATION)
  356. index = i;
  357. }
  358. /* These two conditions has the same outcome but keep them separate
  359. since they have different meaning */
  360. if (unlikely(index == IWL_INVALID_STATION)) {
  361. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  362. return index;
  363. }
  364. if (priv->stations[index].used &&
  365. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  366. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  367. return index;
  368. }
  369. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  370. station = &priv->stations[index];
  371. station->used = 1;
  372. priv->num_stations++;
  373. /* Set up the REPLY_ADD_STA command to send to device */
  374. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  375. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  376. station->sta.mode = 0;
  377. station->sta.sta.sta_id = index;
  378. station->sta.station_flags = 0;
  379. if (priv->band == IEEE80211_BAND_5GHZ)
  380. rate = IWL_RATE_6M_PLCP;
  381. else
  382. rate = IWL_RATE_1M_PLCP;
  383. /* Turn on both antennas for the station... */
  384. station->sta.rate_n_flags =
  385. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  386. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  387. /* Add station to device's station table */
  388. iwl3945_send_add_station(priv, &station->sta, flags);
  389. return index;
  390. }
  391. /*************** DRIVER STATUS FUNCTIONS *****/
  392. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  393. {
  394. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  395. * set but EXIT_PENDING is not */
  396. return test_bit(STATUS_READY, &priv->status) &&
  397. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  398. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  399. }
  400. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  401. {
  402. return test_bit(STATUS_ALIVE, &priv->status);
  403. }
  404. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  405. {
  406. return test_bit(STATUS_INIT, &priv->status);
  407. }
  408. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  409. {
  410. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  411. }
  412. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  413. {
  414. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  415. }
  416. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  417. {
  418. return iwl3945_is_rfkill_hw(priv) ||
  419. iwl3945_is_rfkill_sw(priv);
  420. }
  421. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  422. {
  423. if (iwl3945_is_rfkill(priv))
  424. return 0;
  425. return iwl3945_is_ready(priv);
  426. }
  427. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  428. #define IWL_CMD(x) case x: return #x
  429. static const char *get_cmd_string(u8 cmd)
  430. {
  431. switch (cmd) {
  432. IWL_CMD(REPLY_ALIVE);
  433. IWL_CMD(REPLY_ERROR);
  434. IWL_CMD(REPLY_RXON);
  435. IWL_CMD(REPLY_RXON_ASSOC);
  436. IWL_CMD(REPLY_QOS_PARAM);
  437. IWL_CMD(REPLY_RXON_TIMING);
  438. IWL_CMD(REPLY_ADD_STA);
  439. IWL_CMD(REPLY_REMOVE_STA);
  440. IWL_CMD(REPLY_REMOVE_ALL_STA);
  441. IWL_CMD(REPLY_3945_RX);
  442. IWL_CMD(REPLY_TX);
  443. IWL_CMD(REPLY_RATE_SCALE);
  444. IWL_CMD(REPLY_LEDS_CMD);
  445. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  446. IWL_CMD(RADAR_NOTIFICATION);
  447. IWL_CMD(REPLY_QUIET_CMD);
  448. IWL_CMD(REPLY_CHANNEL_SWITCH);
  449. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  450. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  451. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  452. IWL_CMD(POWER_TABLE_CMD);
  453. IWL_CMD(PM_SLEEP_NOTIFICATION);
  454. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  455. IWL_CMD(REPLY_SCAN_CMD);
  456. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  457. IWL_CMD(SCAN_START_NOTIFICATION);
  458. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  459. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  460. IWL_CMD(BEACON_NOTIFICATION);
  461. IWL_CMD(REPLY_TX_BEACON);
  462. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  463. IWL_CMD(QUIET_NOTIFICATION);
  464. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  465. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  466. IWL_CMD(REPLY_BT_CONFIG);
  467. IWL_CMD(REPLY_STATISTICS_CMD);
  468. IWL_CMD(STATISTICS_NOTIFICATION);
  469. IWL_CMD(REPLY_CARD_STATE_CMD);
  470. IWL_CMD(CARD_STATE_NOTIFICATION);
  471. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  472. default:
  473. return "UNKNOWN";
  474. }
  475. }
  476. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  477. /**
  478. * iwl3945_enqueue_hcmd - enqueue a uCode command
  479. * @priv: device private data point
  480. * @cmd: a point to the ucode command structure
  481. *
  482. * The function returns < 0 values to indicate the operation is
  483. * failed. On success, it turns the index (> 0) of command in the
  484. * command queue.
  485. */
  486. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  487. {
  488. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  489. struct iwl3945_queue *q = &txq->q;
  490. struct iwl3945_tfd_frame *tfd;
  491. u32 *control_flags;
  492. struct iwl3945_cmd *out_cmd;
  493. u32 idx;
  494. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  495. dma_addr_t phys_addr;
  496. int pad;
  497. u16 count;
  498. int ret;
  499. unsigned long flags;
  500. /* If any of the command structures end up being larger than
  501. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  502. * we will need to increase the size of the TFD entries */
  503. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  504. !(cmd->meta.flags & CMD_SIZE_HUGE));
  505. if (iwl3945_is_rfkill(priv)) {
  506. IWL_DEBUG_INFO("Not sending command - RF KILL");
  507. return -EIO;
  508. }
  509. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  510. IWL_ERROR("No space for Tx\n");
  511. return -ENOSPC;
  512. }
  513. spin_lock_irqsave(&priv->hcmd_lock, flags);
  514. tfd = &txq->bd[q->write_ptr];
  515. memset(tfd, 0, sizeof(*tfd));
  516. control_flags = (u32 *) tfd;
  517. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  518. out_cmd = &txq->cmd[idx];
  519. out_cmd->hdr.cmd = cmd->id;
  520. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  521. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  522. /* At this point, the out_cmd now has all of the incoming cmd
  523. * information */
  524. out_cmd->hdr.flags = 0;
  525. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  526. INDEX_TO_SEQ(q->write_ptr));
  527. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  528. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  529. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  530. offsetof(struct iwl3945_cmd, hdr);
  531. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  532. pad = U32_PAD(cmd->len);
  533. count = TFD_CTL_COUNT_GET(*control_flags);
  534. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  535. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  536. "%d bytes at %d[%d]:%d\n",
  537. get_cmd_string(out_cmd->hdr.cmd),
  538. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  539. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  540. txq->need_update = 1;
  541. /* Increment and update queue's write index */
  542. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  543. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  544. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  545. return ret ? ret : idx;
  546. }
  547. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  548. {
  549. int ret;
  550. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  551. /* An asynchronous command can not expect an SKB to be set. */
  552. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  553. /* An asynchronous command MUST have a callback. */
  554. BUG_ON(!cmd->meta.u.callback);
  555. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  556. return -EBUSY;
  557. ret = iwl3945_enqueue_hcmd(priv, cmd);
  558. if (ret < 0) {
  559. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  560. get_cmd_string(cmd->id), ret);
  561. return ret;
  562. }
  563. return 0;
  564. }
  565. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  566. {
  567. int cmd_idx;
  568. int ret;
  569. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  570. /* A synchronous command can not have a callback set. */
  571. BUG_ON(cmd->meta.u.callback != NULL);
  572. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  573. IWL_ERROR("Error sending %s: Already sending a host command\n",
  574. get_cmd_string(cmd->id));
  575. ret = -EBUSY;
  576. goto out;
  577. }
  578. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  579. if (cmd->meta.flags & CMD_WANT_SKB)
  580. cmd->meta.source = &cmd->meta;
  581. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  582. if (cmd_idx < 0) {
  583. ret = cmd_idx;
  584. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  585. get_cmd_string(cmd->id), ret);
  586. goto out;
  587. }
  588. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  589. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  590. HOST_COMPLETE_TIMEOUT);
  591. if (!ret) {
  592. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  593. IWL_ERROR("Error sending %s: time out after %dms.\n",
  594. get_cmd_string(cmd->id),
  595. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  596. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  597. ret = -ETIMEDOUT;
  598. goto cancel;
  599. }
  600. }
  601. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  602. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  603. get_cmd_string(cmd->id));
  604. ret = -ECANCELED;
  605. goto fail;
  606. }
  607. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  608. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  609. get_cmd_string(cmd->id));
  610. ret = -EIO;
  611. goto fail;
  612. }
  613. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  614. IWL_ERROR("Error: Response NULL in '%s'\n",
  615. get_cmd_string(cmd->id));
  616. ret = -EIO;
  617. goto cancel;
  618. }
  619. ret = 0;
  620. goto out;
  621. cancel:
  622. if (cmd->meta.flags & CMD_WANT_SKB) {
  623. struct iwl3945_cmd *qcmd;
  624. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  625. * TX cmd queue. Otherwise in case the cmd comes
  626. * in later, it will possibly set an invalid
  627. * address (cmd->meta.source). */
  628. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  629. qcmd->meta.flags &= ~CMD_WANT_SKB;
  630. }
  631. fail:
  632. if (cmd->meta.u.skb) {
  633. dev_kfree_skb_any(cmd->meta.u.skb);
  634. cmd->meta.u.skb = NULL;
  635. }
  636. out:
  637. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  638. return ret;
  639. }
  640. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  641. {
  642. if (cmd->meta.flags & CMD_ASYNC)
  643. return iwl3945_send_cmd_async(priv, cmd);
  644. return iwl3945_send_cmd_sync(priv, cmd);
  645. }
  646. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  647. {
  648. struct iwl3945_host_cmd cmd = {
  649. .id = id,
  650. .len = len,
  651. .data = data,
  652. };
  653. return iwl3945_send_cmd_sync(priv, &cmd);
  654. }
  655. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  656. {
  657. struct iwl3945_host_cmd cmd = {
  658. .id = id,
  659. .len = sizeof(val),
  660. .data = &val,
  661. };
  662. return iwl3945_send_cmd_sync(priv, &cmd);
  663. }
  664. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  665. {
  666. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  667. }
  668. /**
  669. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  670. * @band: 2.4 or 5 GHz band
  671. * @channel: Any channel valid for the requested band
  672. * In addition to setting the staging RXON, priv->band is also set.
  673. *
  674. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  675. * in the staging RXON flag structure based on the band
  676. */
  677. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  678. enum ieee80211_band band,
  679. u16 channel)
  680. {
  681. if (!iwl3945_get_channel_info(priv, band, channel)) {
  682. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  683. channel, band);
  684. return -EINVAL;
  685. }
  686. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  687. (priv->band == band))
  688. return 0;
  689. priv->staging_rxon.channel = cpu_to_le16(channel);
  690. if (band == IEEE80211_BAND_5GHZ)
  691. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  692. else
  693. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  694. priv->band = band;
  695. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  696. return 0;
  697. }
  698. /**
  699. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  700. *
  701. * NOTE: This is really only useful during development and can eventually
  702. * be #ifdef'd out once the driver is stable and folks aren't actively
  703. * making changes
  704. */
  705. static int iwl3945_check_rxon_cmd(struct iwl3945_priv *priv)
  706. {
  707. int error = 0;
  708. int counter = 1;
  709. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  710. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  711. error |= le32_to_cpu(rxon->flags &
  712. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  713. RXON_FLG_RADAR_DETECT_MSK));
  714. if (error)
  715. IWL_WARNING("check 24G fields %d | %d\n",
  716. counter++, error);
  717. } else {
  718. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  719. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  720. if (error)
  721. IWL_WARNING("check 52 fields %d | %d\n",
  722. counter++, error);
  723. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  724. if (error)
  725. IWL_WARNING("check 52 CCK %d | %d\n",
  726. counter++, error);
  727. }
  728. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  729. if (error)
  730. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  731. /* make sure basic rates 6Mbps and 1Mbps are supported */
  732. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  733. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  734. if (error)
  735. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  736. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  737. if (error)
  738. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  739. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  740. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  741. if (error)
  742. IWL_WARNING("check CCK and short slot %d | %d\n",
  743. counter++, error);
  744. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  745. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  746. if (error)
  747. IWL_WARNING("check CCK & auto detect %d | %d\n",
  748. counter++, error);
  749. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  750. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  751. if (error)
  752. IWL_WARNING("check TGG and auto detect %d | %d\n",
  753. counter++, error);
  754. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  755. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  756. RXON_FLG_ANT_A_MSK)) == 0);
  757. if (error)
  758. IWL_WARNING("check antenna %d %d\n", counter++, error);
  759. if (error)
  760. IWL_WARNING("Tuning to channel %d\n",
  761. le16_to_cpu(rxon->channel));
  762. if (error) {
  763. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  764. return -1;
  765. }
  766. return 0;
  767. }
  768. /**
  769. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  770. * @priv: staging_rxon is compared to active_rxon
  771. *
  772. * If the RXON structure is changing enough to require a new tune,
  773. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  774. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  775. */
  776. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  777. {
  778. /* These items are only settable from the full RXON command */
  779. if (!(iwl3945_is_associated(priv)) ||
  780. compare_ether_addr(priv->staging_rxon.bssid_addr,
  781. priv->active_rxon.bssid_addr) ||
  782. compare_ether_addr(priv->staging_rxon.node_addr,
  783. priv->active_rxon.node_addr) ||
  784. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  785. priv->active_rxon.wlap_bssid_addr) ||
  786. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  787. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  788. (priv->staging_rxon.air_propagation !=
  789. priv->active_rxon.air_propagation) ||
  790. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  791. return 1;
  792. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  793. * be updated with the RXON_ASSOC command -- however only some
  794. * flag transitions are allowed using RXON_ASSOC */
  795. /* Check if we are not switching bands */
  796. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  797. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  798. return 1;
  799. /* Check if we are switching association toggle */
  800. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  801. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  802. return 1;
  803. return 0;
  804. }
  805. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  806. {
  807. int rc = 0;
  808. struct iwl_rx_packet *res = NULL;
  809. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  810. struct iwl3945_host_cmd cmd = {
  811. .id = REPLY_RXON_ASSOC,
  812. .len = sizeof(rxon_assoc),
  813. .meta.flags = CMD_WANT_SKB,
  814. .data = &rxon_assoc,
  815. };
  816. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  817. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  818. if ((rxon1->flags == rxon2->flags) &&
  819. (rxon1->filter_flags == rxon2->filter_flags) &&
  820. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  821. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  822. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  823. return 0;
  824. }
  825. rxon_assoc.flags = priv->staging_rxon.flags;
  826. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  827. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  828. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  829. rxon_assoc.reserved = 0;
  830. rc = iwl3945_send_cmd_sync(priv, &cmd);
  831. if (rc)
  832. return rc;
  833. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  834. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  835. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  836. rc = -EIO;
  837. }
  838. priv->alloc_rxb_skb--;
  839. dev_kfree_skb_any(cmd.meta.u.skb);
  840. return rc;
  841. }
  842. /**
  843. * iwl3945_commit_rxon - commit staging_rxon to hardware
  844. *
  845. * The RXON command in staging_rxon is committed to the hardware and
  846. * the active_rxon structure is updated with the new data. This
  847. * function correctly transitions out of the RXON_ASSOC_MSK state if
  848. * a HW tune is required based on the RXON structure changes.
  849. */
  850. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  851. {
  852. /* cast away the const for active_rxon in this function */
  853. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  854. int rc = 0;
  855. if (!iwl3945_is_alive(priv))
  856. return -1;
  857. /* always get timestamp with Rx frame */
  858. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  859. /* select antenna */
  860. priv->staging_rxon.flags &=
  861. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  862. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  863. rc = iwl3945_check_rxon_cmd(priv);
  864. if (rc) {
  865. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  866. return -EINVAL;
  867. }
  868. /* If we don't need to send a full RXON, we can use
  869. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  870. * and other flags for the current radio configuration. */
  871. if (!iwl3945_full_rxon_required(priv)) {
  872. rc = iwl3945_send_rxon_assoc(priv);
  873. if (rc) {
  874. IWL_ERROR("Error setting RXON_ASSOC "
  875. "configuration (%d).\n", rc);
  876. return rc;
  877. }
  878. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  879. return 0;
  880. }
  881. /* If we are currently associated and the new config requires
  882. * an RXON_ASSOC and the new config wants the associated mask enabled,
  883. * we must clear the associated from the active configuration
  884. * before we apply the new config */
  885. if (iwl3945_is_associated(priv) &&
  886. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  887. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  888. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  889. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  890. sizeof(struct iwl3945_rxon_cmd),
  891. &priv->active_rxon);
  892. /* If the mask clearing failed then we set
  893. * active_rxon back to what it was previously */
  894. if (rc) {
  895. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  896. IWL_ERROR("Error clearing ASSOC_MSK on current "
  897. "configuration (%d).\n", rc);
  898. return rc;
  899. }
  900. }
  901. IWL_DEBUG_INFO("Sending RXON\n"
  902. "* with%s RXON_FILTER_ASSOC_MSK\n"
  903. "* channel = %d\n"
  904. "* bssid = %pM\n",
  905. ((priv->staging_rxon.filter_flags &
  906. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  907. le16_to_cpu(priv->staging_rxon.channel),
  908. priv->staging_rxon.bssid_addr);
  909. /* Apply the new configuration */
  910. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  911. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  912. if (rc) {
  913. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  914. return rc;
  915. }
  916. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  917. iwl3945_clear_stations_table(priv);
  918. /* If we issue a new RXON command which required a tune then we must
  919. * send a new TXPOWER command or we won't be able to Tx any frames */
  920. rc = iwl3945_hw_reg_send_txpower(priv);
  921. if (rc) {
  922. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  923. return rc;
  924. }
  925. /* Add the broadcast address so we can send broadcast frames */
  926. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  927. IWL_INVALID_STATION) {
  928. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  929. return -EIO;
  930. }
  931. /* If we have set the ASSOC_MSK and we are in BSS mode then
  932. * add the IWL_AP_ID to the station rate table */
  933. if (iwl3945_is_associated(priv) &&
  934. (priv->iw_mode == NL80211_IFTYPE_STATION))
  935. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  936. == IWL_INVALID_STATION) {
  937. IWL_ERROR("Error adding AP address for transmit.\n");
  938. return -EIO;
  939. }
  940. /* Init the hardware's rate fallback order based on the band */
  941. rc = iwl3945_init_hw_rate_table(priv);
  942. if (rc) {
  943. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  944. return -EIO;
  945. }
  946. return 0;
  947. }
  948. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  949. {
  950. struct iwl_bt_cmd bt_cmd = {
  951. .flags = 3,
  952. .lead_time = 0xAA,
  953. .max_kill = 1,
  954. .kill_ack_mask = 0,
  955. .kill_cts_mask = 0,
  956. };
  957. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  958. sizeof(bt_cmd), &bt_cmd);
  959. }
  960. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  961. {
  962. int rc = 0;
  963. struct iwl_rx_packet *res;
  964. struct iwl3945_host_cmd cmd = {
  965. .id = REPLY_SCAN_ABORT_CMD,
  966. .meta.flags = CMD_WANT_SKB,
  967. };
  968. /* If there isn't a scan actively going on in the hardware
  969. * then we are in between scan bands and not actually
  970. * actively scanning, so don't send the abort command */
  971. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  972. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  973. return 0;
  974. }
  975. rc = iwl3945_send_cmd_sync(priv, &cmd);
  976. if (rc) {
  977. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  978. return rc;
  979. }
  980. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  981. if (res->u.status != CAN_ABORT_STATUS) {
  982. /* The scan abort will return 1 for success or
  983. * 2 for "failure". A failure condition can be
  984. * due to simply not being in an active scan which
  985. * can occur if we send the scan abort before we
  986. * the microcode has notified us that a scan is
  987. * completed. */
  988. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  989. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  990. clear_bit(STATUS_SCAN_HW, &priv->status);
  991. }
  992. dev_kfree_skb_any(cmd.meta.u.skb);
  993. return rc;
  994. }
  995. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  996. struct iwl3945_cmd *cmd,
  997. struct sk_buff *skb)
  998. {
  999. return 1;
  1000. }
  1001. /*
  1002. * CARD_STATE_CMD
  1003. *
  1004. * Use: Sets the device's internal card state to enable, disable, or halt
  1005. *
  1006. * When in the 'enable' state the card operates as normal.
  1007. * When in the 'disable' state, the card enters into a low power mode.
  1008. * When in the 'halt' state, the card is shut down and must be fully
  1009. * restarted to come back on.
  1010. */
  1011. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1012. {
  1013. struct iwl3945_host_cmd cmd = {
  1014. .id = REPLY_CARD_STATE_CMD,
  1015. .len = sizeof(u32),
  1016. .data = &flags,
  1017. .meta.flags = meta_flag,
  1018. };
  1019. if (meta_flag & CMD_ASYNC)
  1020. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1021. return iwl3945_send_cmd(priv, &cmd);
  1022. }
  1023. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1024. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1025. {
  1026. struct iwl_rx_packet *res = NULL;
  1027. if (!skb) {
  1028. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1029. return 1;
  1030. }
  1031. res = (struct iwl_rx_packet *)skb->data;
  1032. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1033. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1034. res->hdr.flags);
  1035. return 1;
  1036. }
  1037. switch (res->u.add_sta.status) {
  1038. case ADD_STA_SUCCESS_MSK:
  1039. break;
  1040. default:
  1041. break;
  1042. }
  1043. /* We didn't cache the SKB; let the caller free it */
  1044. return 1;
  1045. }
  1046. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1047. struct iwl3945_addsta_cmd *sta, u8 flags)
  1048. {
  1049. struct iwl_rx_packet *res = NULL;
  1050. int rc = 0;
  1051. struct iwl3945_host_cmd cmd = {
  1052. .id = REPLY_ADD_STA,
  1053. .len = sizeof(struct iwl3945_addsta_cmd),
  1054. .meta.flags = flags,
  1055. .data = sta,
  1056. };
  1057. if (flags & CMD_ASYNC)
  1058. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1059. else
  1060. cmd.meta.flags |= CMD_WANT_SKB;
  1061. rc = iwl3945_send_cmd(priv, &cmd);
  1062. if (rc || (flags & CMD_ASYNC))
  1063. return rc;
  1064. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  1065. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1066. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1067. res->hdr.flags);
  1068. rc = -EIO;
  1069. }
  1070. if (rc == 0) {
  1071. switch (res->u.add_sta.status) {
  1072. case ADD_STA_SUCCESS_MSK:
  1073. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1074. break;
  1075. default:
  1076. rc = -EIO;
  1077. IWL_WARNING("REPLY_ADD_STA failed\n");
  1078. break;
  1079. }
  1080. }
  1081. priv->alloc_rxb_skb--;
  1082. dev_kfree_skb_any(cmd.meta.u.skb);
  1083. return rc;
  1084. }
  1085. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1086. struct ieee80211_key_conf *keyconf,
  1087. u8 sta_id)
  1088. {
  1089. unsigned long flags;
  1090. __le16 key_flags = 0;
  1091. switch (keyconf->alg) {
  1092. case ALG_CCMP:
  1093. key_flags |= STA_KEY_FLG_CCMP;
  1094. key_flags |= cpu_to_le16(
  1095. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1096. key_flags &= ~STA_KEY_FLG_INVALID;
  1097. break;
  1098. case ALG_TKIP:
  1099. case ALG_WEP:
  1100. default:
  1101. return -EINVAL;
  1102. }
  1103. spin_lock_irqsave(&priv->sta_lock, flags);
  1104. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1105. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1106. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1107. keyconf->keylen);
  1108. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1109. keyconf->keylen);
  1110. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1111. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1112. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1113. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1114. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1115. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1116. return 0;
  1117. }
  1118. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1119. {
  1120. unsigned long flags;
  1121. spin_lock_irqsave(&priv->sta_lock, flags);
  1122. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1123. memset(&priv->stations[sta_id].sta.key, 0,
  1124. sizeof(struct iwl4965_keyinfo));
  1125. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1126. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1127. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1128. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1129. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1130. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1131. return 0;
  1132. }
  1133. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1134. {
  1135. struct list_head *element;
  1136. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1137. priv->frames_count);
  1138. while (!list_empty(&priv->free_frames)) {
  1139. element = priv->free_frames.next;
  1140. list_del(element);
  1141. kfree(list_entry(element, struct iwl3945_frame, list));
  1142. priv->frames_count--;
  1143. }
  1144. if (priv->frames_count) {
  1145. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1146. priv->frames_count);
  1147. priv->frames_count = 0;
  1148. }
  1149. }
  1150. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1151. {
  1152. struct iwl3945_frame *frame;
  1153. struct list_head *element;
  1154. if (list_empty(&priv->free_frames)) {
  1155. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1156. if (!frame) {
  1157. IWL_ERROR("Could not allocate frame!\n");
  1158. return NULL;
  1159. }
  1160. priv->frames_count++;
  1161. return frame;
  1162. }
  1163. element = priv->free_frames.next;
  1164. list_del(element);
  1165. return list_entry(element, struct iwl3945_frame, list);
  1166. }
  1167. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1168. {
  1169. memset(frame, 0, sizeof(*frame));
  1170. list_add(&frame->list, &priv->free_frames);
  1171. }
  1172. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1173. struct ieee80211_hdr *hdr,
  1174. int left)
  1175. {
  1176. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1177. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1178. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1179. return 0;
  1180. if (priv->ibss_beacon->len > left)
  1181. return 0;
  1182. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1183. return priv->ibss_beacon->len;
  1184. }
  1185. static u8 iwl3945_rate_get_lowest_plcp(struct iwl3945_priv *priv)
  1186. {
  1187. u8 i;
  1188. int rate_mask;
  1189. /* Set rate mask*/
  1190. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1191. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1192. else
  1193. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1194. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1195. i = iwl3945_rates[i].next_ieee) {
  1196. if (rate_mask & (1 << i))
  1197. return iwl3945_rates[i].plcp;
  1198. }
  1199. /* No valid rate was found. Assign the lowest one */
  1200. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1201. return IWL_RATE_1M_PLCP;
  1202. else
  1203. return IWL_RATE_6M_PLCP;
  1204. }
  1205. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1206. {
  1207. struct iwl3945_frame *frame;
  1208. unsigned int frame_size;
  1209. int rc;
  1210. u8 rate;
  1211. frame = iwl3945_get_free_frame(priv);
  1212. if (!frame) {
  1213. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1214. "command.\n");
  1215. return -ENOMEM;
  1216. }
  1217. rate = iwl3945_rate_get_lowest_plcp(priv);
  1218. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1219. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1220. &frame->u.cmd[0]);
  1221. iwl3945_free_frame(priv, frame);
  1222. return rc;
  1223. }
  1224. /******************************************************************************
  1225. *
  1226. * EEPROM related functions
  1227. *
  1228. ******************************************************************************/
  1229. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1230. {
  1231. memcpy(mac, priv->eeprom.mac_address, 6);
  1232. }
  1233. /*
  1234. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1235. * embedded controller) as EEPROM reader; each read is a series of pulses
  1236. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1237. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1238. * simply claims ownership, which should be safe when this function is called
  1239. * (i.e. before loading uCode!).
  1240. */
  1241. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1242. {
  1243. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1244. return 0;
  1245. }
  1246. /**
  1247. * iwl3945_eeprom_init - read EEPROM contents
  1248. *
  1249. * Load the EEPROM contents from adapter into priv->eeprom
  1250. *
  1251. * NOTE: This routine uses the non-debug IO access functions.
  1252. */
  1253. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1254. {
  1255. u16 *e = (u16 *)&priv->eeprom;
  1256. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1257. int sz = sizeof(priv->eeprom);
  1258. int ret;
  1259. u16 addr;
  1260. /* The EEPROM structure has several padding buffers within it
  1261. * and when adding new EEPROM maps is subject to programmer errors
  1262. * which may be very difficult to identify without explicitly
  1263. * checking the resulting size of the eeprom map. */
  1264. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1265. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1266. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1267. return -ENOENT;
  1268. }
  1269. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1270. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1271. if (ret < 0) {
  1272. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1273. return -ENOENT;
  1274. }
  1275. /* eeprom is an array of 16bit values */
  1276. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1277. u32 r;
  1278. _iwl3945_write32(priv, CSR_EEPROM_REG,
  1279. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1280. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1281. ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG,
  1282. CSR_EEPROM_REG_READ_VALID_MSK,
  1283. IWL_EEPROM_ACCESS_TIMEOUT);
  1284. if (ret < 0) {
  1285. IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
  1286. return ret;
  1287. }
  1288. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1289. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1290. }
  1291. return 0;
  1292. }
  1293. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1294. {
  1295. if (priv->hw_setting.shared_virt)
  1296. pci_free_consistent(priv->pci_dev,
  1297. sizeof(struct iwl3945_shared),
  1298. priv->hw_setting.shared_virt,
  1299. priv->hw_setting.shared_phys);
  1300. }
  1301. /**
  1302. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1303. *
  1304. * return : set the bit for each supported rate insert in ie
  1305. */
  1306. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1307. u16 basic_rate, int *left)
  1308. {
  1309. u16 ret_rates = 0, bit;
  1310. int i;
  1311. u8 *cnt = ie;
  1312. u8 *rates = ie + 1;
  1313. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1314. if (bit & supported_rate) {
  1315. ret_rates |= bit;
  1316. rates[*cnt] = iwl3945_rates[i].ieee |
  1317. ((bit & basic_rate) ? 0x80 : 0x00);
  1318. (*cnt)++;
  1319. (*left)--;
  1320. if ((*left <= 0) ||
  1321. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1322. break;
  1323. }
  1324. }
  1325. return ret_rates;
  1326. }
  1327. /**
  1328. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1329. */
  1330. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1331. struct ieee80211_mgmt *frame,
  1332. int left)
  1333. {
  1334. int len = 0;
  1335. u8 *pos = NULL;
  1336. u16 active_rates, ret_rates, cck_rates;
  1337. /* Make sure there is enough space for the probe request,
  1338. * two mandatory IEs and the data */
  1339. left -= 24;
  1340. if (left < 0)
  1341. return 0;
  1342. len += 24;
  1343. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1344. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1345. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1346. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1347. frame->seq_ctrl = 0;
  1348. /* fill in our indirect SSID IE */
  1349. /* ...next IE... */
  1350. left -= 2;
  1351. if (left < 0)
  1352. return 0;
  1353. len += 2;
  1354. pos = &(frame->u.probe_req.variable[0]);
  1355. *pos++ = WLAN_EID_SSID;
  1356. *pos++ = 0;
  1357. /* fill in supported rate */
  1358. /* ...next IE... */
  1359. left -= 2;
  1360. if (left < 0)
  1361. return 0;
  1362. /* ... fill it in... */
  1363. *pos++ = WLAN_EID_SUPP_RATES;
  1364. *pos = 0;
  1365. priv->active_rate = priv->rates_mask;
  1366. active_rates = priv->active_rate;
  1367. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1368. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1369. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1370. priv->active_rate_basic, &left);
  1371. active_rates &= ~ret_rates;
  1372. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1373. priv->active_rate_basic, &left);
  1374. active_rates &= ~ret_rates;
  1375. len += 2 + *pos;
  1376. pos += (*pos) + 1;
  1377. if (active_rates == 0)
  1378. goto fill_end;
  1379. /* fill in supported extended rate */
  1380. /* ...next IE... */
  1381. left -= 2;
  1382. if (left < 0)
  1383. return 0;
  1384. /* ... fill it in... */
  1385. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1386. *pos = 0;
  1387. iwl3945_supported_rate_to_ie(pos, active_rates,
  1388. priv->active_rate_basic, &left);
  1389. if (*pos > 0)
  1390. len += 2 + *pos;
  1391. fill_end:
  1392. return (u16)len;
  1393. }
  1394. /*
  1395. * QoS support
  1396. */
  1397. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1398. struct iwl_qosparam_cmd *qos)
  1399. {
  1400. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1401. sizeof(struct iwl_qosparam_cmd), qos);
  1402. }
  1403. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1404. {
  1405. u16 cw_min = 15;
  1406. u16 cw_max = 1023;
  1407. u8 aifs = 2;
  1408. u8 is_legacy = 0;
  1409. unsigned long flags;
  1410. int i;
  1411. spin_lock_irqsave(&priv->lock, flags);
  1412. priv->qos_data.qos_active = 0;
  1413. /* QoS always active in AP and ADHOC mode
  1414. * In STA mode wait for association
  1415. */
  1416. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  1417. priv->iw_mode == NL80211_IFTYPE_AP)
  1418. priv->qos_data.qos_active = 1;
  1419. else
  1420. priv->qos_data.qos_active = 0;
  1421. /* check for legacy mode */
  1422. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  1423. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  1424. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  1425. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  1426. cw_min = 31;
  1427. is_legacy = 1;
  1428. }
  1429. if (priv->qos_data.qos_active)
  1430. aifs = 3;
  1431. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1432. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1433. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1434. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1435. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1436. if (priv->qos_data.qos_active) {
  1437. i = 1;
  1438. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1439. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1440. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1441. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1442. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1443. i = 2;
  1444. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1445. cpu_to_le16((cw_min + 1) / 2 - 1);
  1446. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1447. cpu_to_le16(cw_max);
  1448. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1449. if (is_legacy)
  1450. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1451. cpu_to_le16(6016);
  1452. else
  1453. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1454. cpu_to_le16(3008);
  1455. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1456. i = 3;
  1457. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1458. cpu_to_le16((cw_min + 1) / 4 - 1);
  1459. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1460. cpu_to_le16((cw_max + 1) / 2 - 1);
  1461. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1462. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1463. if (is_legacy)
  1464. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1465. cpu_to_le16(3264);
  1466. else
  1467. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1468. cpu_to_le16(1504);
  1469. } else {
  1470. for (i = 1; i < 4; i++) {
  1471. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1472. cpu_to_le16(cw_min);
  1473. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1474. cpu_to_le16(cw_max);
  1475. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1476. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1477. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1478. }
  1479. }
  1480. IWL_DEBUG_QOS("set QoS to default \n");
  1481. spin_unlock_irqrestore(&priv->lock, flags);
  1482. }
  1483. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1484. {
  1485. unsigned long flags;
  1486. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1487. return;
  1488. spin_lock_irqsave(&priv->lock, flags);
  1489. priv->qos_data.def_qos_parm.qos_flags = 0;
  1490. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1491. !priv->qos_data.qos_cap.q_AP.txop_request)
  1492. priv->qos_data.def_qos_parm.qos_flags |=
  1493. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1494. if (priv->qos_data.qos_active)
  1495. priv->qos_data.def_qos_parm.qos_flags |=
  1496. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1497. spin_unlock_irqrestore(&priv->lock, flags);
  1498. if (force || iwl3945_is_associated(priv)) {
  1499. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1500. priv->qos_data.qos_active);
  1501. iwl3945_send_qos_params_command(priv,
  1502. &(priv->qos_data.def_qos_parm));
  1503. }
  1504. }
  1505. /*
  1506. * Power management (not Tx power!) functions
  1507. */
  1508. #define MSEC_TO_USEC 1024
  1509. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1510. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1511. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1512. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1513. __constant_cpu_to_le32(X1), \
  1514. __constant_cpu_to_le32(X2), \
  1515. __constant_cpu_to_le32(X3), \
  1516. __constant_cpu_to_le32(X4)}
  1517. /* default power management (not Tx power) table values */
  1518. /* for TIM 0-10 */
  1519. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1520. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1521. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1522. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1523. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1524. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1525. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1526. };
  1527. /* for TIM > 10 */
  1528. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1529. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1530. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1531. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1532. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1533. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1534. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1535. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1536. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1537. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1538. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1539. };
  1540. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1541. {
  1542. int rc = 0, i;
  1543. struct iwl3945_power_mgr *pow_data;
  1544. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1545. u16 pci_pm;
  1546. IWL_DEBUG_POWER("Initialize power \n");
  1547. pow_data = &(priv->power_data);
  1548. memset(pow_data, 0, sizeof(*pow_data));
  1549. pow_data->active_index = IWL_POWER_RANGE_0;
  1550. pow_data->dtim_val = 0xffff;
  1551. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1552. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1553. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1554. if (rc != 0)
  1555. return 0;
  1556. else {
  1557. struct iwl_powertable_cmd *cmd;
  1558. IWL_DEBUG_POWER("adjust power command flags\n");
  1559. for (i = 0; i < IWL_POWER_AC; i++) {
  1560. cmd = &pow_data->pwr_range_0[i].cmd;
  1561. if (pci_pm & 0x1)
  1562. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1563. else
  1564. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1565. }
  1566. }
  1567. return rc;
  1568. }
  1569. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1570. struct iwl_powertable_cmd *cmd, u32 mode)
  1571. {
  1572. int rc = 0, i;
  1573. u8 skip;
  1574. u32 max_sleep = 0;
  1575. struct iwl3945_power_vec_entry *range;
  1576. u8 period = 0;
  1577. struct iwl3945_power_mgr *pow_data;
  1578. if (mode > IWL_POWER_INDEX_5) {
  1579. IWL_DEBUG_POWER("Error invalid power mode \n");
  1580. return -1;
  1581. }
  1582. pow_data = &(priv->power_data);
  1583. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1584. range = &pow_data->pwr_range_0[0];
  1585. else
  1586. range = &pow_data->pwr_range_1[1];
  1587. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1588. #ifdef IWL_MAC80211_DISABLE
  1589. if (priv->assoc_network != NULL) {
  1590. unsigned long flags;
  1591. period = priv->assoc_network->tim.tim_period;
  1592. }
  1593. #endif /*IWL_MAC80211_DISABLE */
  1594. skip = range[mode].no_dtim;
  1595. if (period == 0) {
  1596. period = 1;
  1597. skip = 0;
  1598. }
  1599. if (skip == 0) {
  1600. max_sleep = period;
  1601. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1602. } else {
  1603. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1604. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1605. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1606. }
  1607. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1608. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1609. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1610. }
  1611. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1612. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1613. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1614. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1615. le32_to_cpu(cmd->sleep_interval[0]),
  1616. le32_to_cpu(cmd->sleep_interval[1]),
  1617. le32_to_cpu(cmd->sleep_interval[2]),
  1618. le32_to_cpu(cmd->sleep_interval[3]),
  1619. le32_to_cpu(cmd->sleep_interval[4]));
  1620. return rc;
  1621. }
  1622. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1623. {
  1624. u32 uninitialized_var(final_mode);
  1625. int rc;
  1626. struct iwl_powertable_cmd cmd;
  1627. /* If on battery, set to 3,
  1628. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1629. * else user level */
  1630. switch (mode) {
  1631. case IWL_POWER_BATTERY:
  1632. final_mode = IWL_POWER_INDEX_3;
  1633. break;
  1634. case IWL_POWER_AC:
  1635. final_mode = IWL_POWER_MODE_CAM;
  1636. break;
  1637. default:
  1638. final_mode = mode;
  1639. break;
  1640. }
  1641. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1642. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1643. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1644. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1645. if (final_mode == IWL_POWER_MODE_CAM)
  1646. clear_bit(STATUS_POWER_PMI, &priv->status);
  1647. else
  1648. set_bit(STATUS_POWER_PMI, &priv->status);
  1649. return rc;
  1650. }
  1651. /**
  1652. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1653. *
  1654. * NOTE: priv->mutex is not required before calling this function
  1655. */
  1656. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1657. {
  1658. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1659. clear_bit(STATUS_SCANNING, &priv->status);
  1660. return 0;
  1661. }
  1662. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1663. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1664. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1665. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1666. queue_work(priv->workqueue, &priv->abort_scan);
  1667. } else
  1668. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1669. return test_bit(STATUS_SCANNING, &priv->status);
  1670. }
  1671. return 0;
  1672. }
  1673. /**
  1674. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1675. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1676. *
  1677. * NOTE: priv->mutex must be held before calling this function
  1678. */
  1679. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1680. {
  1681. unsigned long now = jiffies;
  1682. int ret;
  1683. ret = iwl3945_scan_cancel(priv);
  1684. if (ret && ms) {
  1685. mutex_unlock(&priv->mutex);
  1686. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1687. test_bit(STATUS_SCANNING, &priv->status))
  1688. msleep(1);
  1689. mutex_lock(&priv->mutex);
  1690. return test_bit(STATUS_SCANNING, &priv->status);
  1691. }
  1692. return ret;
  1693. }
  1694. #define MAX_UCODE_BEACON_INTERVAL 1024
  1695. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1696. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1697. {
  1698. u16 new_val = 0;
  1699. u16 beacon_factor = 0;
  1700. beacon_factor =
  1701. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1702. / MAX_UCODE_BEACON_INTERVAL;
  1703. new_val = beacon_val / beacon_factor;
  1704. return cpu_to_le16(new_val);
  1705. }
  1706. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1707. {
  1708. u64 interval_tm_unit;
  1709. u64 tsf, result;
  1710. unsigned long flags;
  1711. struct ieee80211_conf *conf = NULL;
  1712. u16 beacon_int = 0;
  1713. conf = ieee80211_get_hw_conf(priv->hw);
  1714. spin_lock_irqsave(&priv->lock, flags);
  1715. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1716. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1717. tsf = priv->timestamp;
  1718. beacon_int = priv->beacon_int;
  1719. spin_unlock_irqrestore(&priv->lock, flags);
  1720. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1721. if (beacon_int == 0) {
  1722. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1723. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1724. } else {
  1725. priv->rxon_timing.beacon_interval =
  1726. cpu_to_le16(beacon_int);
  1727. priv->rxon_timing.beacon_interval =
  1728. iwl3945_adjust_beacon_interval(
  1729. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1730. }
  1731. priv->rxon_timing.atim_window = 0;
  1732. } else {
  1733. priv->rxon_timing.beacon_interval =
  1734. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1735. /* TODO: we need to get atim_window from upper stack
  1736. * for now we set to 0 */
  1737. priv->rxon_timing.atim_window = 0;
  1738. }
  1739. interval_tm_unit =
  1740. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1741. result = do_div(tsf, interval_tm_unit);
  1742. priv->rxon_timing.beacon_init_val =
  1743. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1744. IWL_DEBUG_ASSOC
  1745. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1746. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1747. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1748. le16_to_cpu(priv->rxon_timing.atim_window));
  1749. }
  1750. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1751. {
  1752. if (!iwl3945_is_ready_rf(priv)) {
  1753. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1754. return -EIO;
  1755. }
  1756. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1757. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1758. return -EAGAIN;
  1759. }
  1760. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1761. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1762. "Queuing.\n");
  1763. return -EAGAIN;
  1764. }
  1765. IWL_DEBUG_INFO("Starting scan...\n");
  1766. if (priv->cfg->sku & IWL_SKU_G)
  1767. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1768. if (priv->cfg->sku & IWL_SKU_A)
  1769. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1770. set_bit(STATUS_SCANNING, &priv->status);
  1771. priv->scan_start = jiffies;
  1772. priv->scan_pass_start = priv->scan_start;
  1773. queue_work(priv->workqueue, &priv->request_scan);
  1774. return 0;
  1775. }
  1776. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1777. {
  1778. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1779. if (hw_decrypt)
  1780. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1781. else
  1782. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1783. return 0;
  1784. }
  1785. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1786. enum ieee80211_band band)
  1787. {
  1788. if (band == IEEE80211_BAND_5GHZ) {
  1789. priv->staging_rxon.flags &=
  1790. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1791. | RXON_FLG_CCK_MSK);
  1792. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1793. } else {
  1794. /* Copied from iwl3945_bg_post_associate() */
  1795. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1796. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1797. else
  1798. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1799. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1800. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1801. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1802. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1803. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1804. }
  1805. }
  1806. /*
  1807. * initialize rxon structure with default values from eeprom
  1808. */
  1809. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
  1810. int mode)
  1811. {
  1812. const struct iwl3945_channel_info *ch_info;
  1813. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1814. switch (mode) {
  1815. case NL80211_IFTYPE_AP:
  1816. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1817. break;
  1818. case NL80211_IFTYPE_STATION:
  1819. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1820. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1821. break;
  1822. case NL80211_IFTYPE_ADHOC:
  1823. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1824. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1825. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1826. RXON_FILTER_ACCEPT_GRP_MSK;
  1827. break;
  1828. case NL80211_IFTYPE_MONITOR:
  1829. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1830. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1831. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1832. break;
  1833. default:
  1834. IWL_ERROR("Unsupported interface type %d\n", mode);
  1835. break;
  1836. }
  1837. #if 0
  1838. /* TODO: Figure out when short_preamble would be set and cache from
  1839. * that */
  1840. if (!hw_to_local(priv->hw)->short_preamble)
  1841. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1842. else
  1843. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1844. #endif
  1845. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1846. le16_to_cpu(priv->active_rxon.channel));
  1847. if (!ch_info)
  1848. ch_info = &priv->channel_info[0];
  1849. /*
  1850. * in some case A channels are all non IBSS
  1851. * in this case force B/G channel
  1852. */
  1853. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1854. ch_info = &priv->channel_info[0];
  1855. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1856. if (is_channel_a_band(ch_info))
  1857. priv->band = IEEE80211_BAND_5GHZ;
  1858. else
  1859. priv->band = IEEE80211_BAND_2GHZ;
  1860. iwl3945_set_flags_for_phymode(priv, priv->band);
  1861. priv->staging_rxon.ofdm_basic_rates =
  1862. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1863. priv->staging_rxon.cck_basic_rates =
  1864. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1865. }
  1866. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1867. {
  1868. if (mode == NL80211_IFTYPE_ADHOC) {
  1869. const struct iwl3945_channel_info *ch_info;
  1870. ch_info = iwl3945_get_channel_info(priv,
  1871. priv->band,
  1872. le16_to_cpu(priv->staging_rxon.channel));
  1873. if (!ch_info || !is_channel_ibss(ch_info)) {
  1874. IWL_ERROR("channel %d not IBSS channel\n",
  1875. le16_to_cpu(priv->staging_rxon.channel));
  1876. return -EINVAL;
  1877. }
  1878. }
  1879. iwl3945_connection_init_rx_config(priv, mode);
  1880. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1881. iwl3945_clear_stations_table(priv);
  1882. /* don't commit rxon if rf-kill is on*/
  1883. if (!iwl3945_is_ready_rf(priv))
  1884. return -EAGAIN;
  1885. cancel_delayed_work(&priv->scan_check);
  1886. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1887. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1888. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1889. return -EAGAIN;
  1890. }
  1891. iwl3945_commit_rxon(priv);
  1892. return 0;
  1893. }
  1894. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1895. struct ieee80211_tx_info *info,
  1896. struct iwl3945_cmd *cmd,
  1897. struct sk_buff *skb_frag,
  1898. int last_frag)
  1899. {
  1900. struct iwl3945_hw_key *keyinfo =
  1901. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1902. switch (keyinfo->alg) {
  1903. case ALG_CCMP:
  1904. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1905. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1906. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1907. break;
  1908. case ALG_TKIP:
  1909. #if 0
  1910. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1911. if (last_frag)
  1912. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1913. 8);
  1914. else
  1915. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1916. #endif
  1917. break;
  1918. case ALG_WEP:
  1919. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1920. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1921. if (keyinfo->keylen == 13)
  1922. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1923. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1924. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1925. "with key %d\n", info->control.hw_key->hw_key_idx);
  1926. break;
  1927. default:
  1928. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  1929. break;
  1930. }
  1931. }
  1932. /*
  1933. * handle build REPLY_TX command notification.
  1934. */
  1935. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  1936. struct iwl3945_cmd *cmd,
  1937. struct ieee80211_tx_info *info,
  1938. struct ieee80211_hdr *hdr,
  1939. int is_unicast, u8 std_id)
  1940. {
  1941. __le16 fc = hdr->frame_control;
  1942. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1943. u8 rc_flags = info->control.rates[0].flags;
  1944. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1945. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1946. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1947. if (ieee80211_is_mgmt(fc))
  1948. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1949. if (ieee80211_is_probe_resp(fc) &&
  1950. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1951. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1952. } else {
  1953. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1954. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1955. }
  1956. cmd->cmd.tx.sta_id = std_id;
  1957. if (ieee80211_has_morefrags(fc))
  1958. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1959. if (ieee80211_is_data_qos(fc)) {
  1960. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1961. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1962. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1963. } else {
  1964. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1965. }
  1966. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1967. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1968. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1969. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1970. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1971. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1972. }
  1973. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1974. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1975. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1976. if (ieee80211_is_mgmt(fc)) {
  1977. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1978. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1979. else
  1980. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1981. } else {
  1982. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1983. #ifdef CONFIG_IWL3945_LEDS
  1984. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1985. #endif
  1986. }
  1987. cmd->cmd.tx.driver_txop = 0;
  1988. cmd->cmd.tx.tx_flags = tx_flags;
  1989. cmd->cmd.tx.next_frame_len = 0;
  1990. }
  1991. /**
  1992. * iwl3945_get_sta_id - Find station's index within station table
  1993. */
  1994. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  1995. {
  1996. int sta_id;
  1997. u16 fc = le16_to_cpu(hdr->frame_control);
  1998. /* If this frame is broadcast or management, use broadcast station id */
  1999. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2000. is_multicast_ether_addr(hdr->addr1))
  2001. return priv->hw_setting.bcast_sta_id;
  2002. switch (priv->iw_mode) {
  2003. /* If we are a client station in a BSS network, use the special
  2004. * AP station entry (that's the only station we communicate with) */
  2005. case NL80211_IFTYPE_STATION:
  2006. return IWL_AP_ID;
  2007. /* If we are an AP, then find the station, or use BCAST */
  2008. case NL80211_IFTYPE_AP:
  2009. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2010. if (sta_id != IWL_INVALID_STATION)
  2011. return sta_id;
  2012. return priv->hw_setting.bcast_sta_id;
  2013. /* If this frame is going out to an IBSS network, find the station,
  2014. * or create a new station table entry */
  2015. case NL80211_IFTYPE_ADHOC: {
  2016. /* Create new station table entry */
  2017. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2018. if (sta_id != IWL_INVALID_STATION)
  2019. return sta_id;
  2020. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2021. if (sta_id != IWL_INVALID_STATION)
  2022. return sta_id;
  2023. IWL_DEBUG_DROP("Station %pM not in station map. "
  2024. "Defaulting to broadcast...\n",
  2025. hdr->addr1);
  2026. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2027. return priv->hw_setting.bcast_sta_id;
  2028. }
  2029. /* If we are in monitor mode, use BCAST. This is required for
  2030. * packet injection. */
  2031. case NL80211_IFTYPE_MONITOR:
  2032. return priv->hw_setting.bcast_sta_id;
  2033. default:
  2034. IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
  2035. return priv->hw_setting.bcast_sta_id;
  2036. }
  2037. }
  2038. /*
  2039. * start REPLY_TX command process
  2040. */
  2041. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2042. {
  2043. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2044. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2045. struct iwl3945_tfd_frame *tfd;
  2046. u32 *control_flags;
  2047. int txq_id = skb_get_queue_mapping(skb);
  2048. struct iwl3945_tx_queue *txq = NULL;
  2049. struct iwl3945_queue *q = NULL;
  2050. dma_addr_t phys_addr;
  2051. dma_addr_t txcmd_phys;
  2052. struct iwl3945_cmd *out_cmd = NULL;
  2053. u16 len, idx, len_org, hdr_len;
  2054. u8 id;
  2055. u8 unicast;
  2056. u8 sta_id;
  2057. u8 tid = 0;
  2058. u16 seq_number = 0;
  2059. __le16 fc;
  2060. u8 wait_write_ptr = 0;
  2061. u8 *qc = NULL;
  2062. unsigned long flags;
  2063. int rc;
  2064. spin_lock_irqsave(&priv->lock, flags);
  2065. if (iwl3945_is_rfkill(priv)) {
  2066. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2067. goto drop_unlock;
  2068. }
  2069. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2070. IWL_ERROR("ERROR: No TX rate available.\n");
  2071. goto drop_unlock;
  2072. }
  2073. unicast = !is_multicast_ether_addr(hdr->addr1);
  2074. id = 0;
  2075. fc = hdr->frame_control;
  2076. #ifdef CONFIG_IWL3945_DEBUG
  2077. if (ieee80211_is_auth(fc))
  2078. IWL_DEBUG_TX("Sending AUTH frame\n");
  2079. else if (ieee80211_is_assoc_req(fc))
  2080. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2081. else if (ieee80211_is_reassoc_req(fc))
  2082. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2083. #endif
  2084. /* drop all data frame if we are not associated */
  2085. if (ieee80211_is_data(fc) &&
  2086. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  2087. (!iwl3945_is_associated(priv) ||
  2088. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  2089. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2090. goto drop_unlock;
  2091. }
  2092. spin_unlock_irqrestore(&priv->lock, flags);
  2093. hdr_len = ieee80211_hdrlen(fc);
  2094. /* Find (or create) index into station table for destination station */
  2095. sta_id = iwl3945_get_sta_id(priv, hdr);
  2096. if (sta_id == IWL_INVALID_STATION) {
  2097. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  2098. hdr->addr1);
  2099. goto drop;
  2100. }
  2101. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2102. if (ieee80211_is_data_qos(fc)) {
  2103. qc = ieee80211_get_qos_ctl(hdr);
  2104. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  2105. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2106. IEEE80211_SCTL_SEQ;
  2107. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2108. (hdr->seq_ctrl &
  2109. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2110. seq_number += 0x10;
  2111. }
  2112. /* Descriptor for chosen Tx queue */
  2113. txq = &priv->txq[txq_id];
  2114. q = &txq->q;
  2115. spin_lock_irqsave(&priv->lock, flags);
  2116. /* Set up first empty TFD within this queue's circular TFD buffer */
  2117. tfd = &txq->bd[q->write_ptr];
  2118. memset(tfd, 0, sizeof(*tfd));
  2119. control_flags = (u32 *) tfd;
  2120. idx = get_cmd_index(q, q->write_ptr, 0);
  2121. /* Set up driver data for this TFD */
  2122. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2123. txq->txb[q->write_ptr].skb[0] = skb;
  2124. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2125. out_cmd = &txq->cmd[idx];
  2126. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2127. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2128. /*
  2129. * Set up the Tx-command (not MAC!) header.
  2130. * Store the chosen Tx queue and TFD index within the sequence field;
  2131. * after Tx, uCode's Tx response will return this value so driver can
  2132. * locate the frame within the tx queue and do post-tx processing.
  2133. */
  2134. out_cmd->hdr.cmd = REPLY_TX;
  2135. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2136. INDEX_TO_SEQ(q->write_ptr)));
  2137. /* Copy MAC header from skb into command buffer */
  2138. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2139. /*
  2140. * Use the first empty entry in this queue's command buffer array
  2141. * to contain the Tx command and MAC header concatenated together
  2142. * (payload data will be in another buffer).
  2143. * Size of this varies, due to varying MAC header length.
  2144. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2145. * of the MAC header (device reads on dword boundaries).
  2146. * We'll tell device about this padding later.
  2147. */
  2148. len = priv->hw_setting.tx_cmd_len +
  2149. sizeof(struct iwl_cmd_header) + hdr_len;
  2150. len_org = len;
  2151. len = (len + 3) & ~3;
  2152. if (len_org != len)
  2153. len_org = 1;
  2154. else
  2155. len_org = 0;
  2156. /* Physical address of this Tx command's header (not MAC header!),
  2157. * within command buffer array. */
  2158. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2159. offsetof(struct iwl3945_cmd, hdr);
  2160. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2161. * first entry */
  2162. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2163. if (info->control.hw_key)
  2164. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2165. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2166. * if any (802.11 null frames have no payload). */
  2167. len = skb->len - hdr_len;
  2168. if (len) {
  2169. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2170. len, PCI_DMA_TODEVICE);
  2171. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2172. }
  2173. if (!len)
  2174. /* If there is no payload, then we use only one Tx buffer */
  2175. *control_flags = TFD_CTL_COUNT_SET(1);
  2176. else
  2177. /* Else use 2 buffers.
  2178. * Tell 3945 about any padding after MAC header */
  2179. *control_flags = TFD_CTL_COUNT_SET(2) |
  2180. TFD_CTL_PAD_SET(U32_PAD(len));
  2181. /* Total # bytes to be transmitted */
  2182. len = (u16)skb->len;
  2183. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2184. /* TODO need this for burst mode later on */
  2185. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2186. /* set is_hcca to 0; it probably will never be implemented */
  2187. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2188. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2189. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2190. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2191. txq->need_update = 1;
  2192. if (qc)
  2193. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2194. } else {
  2195. wait_write_ptr = 1;
  2196. txq->need_update = 0;
  2197. }
  2198. iwl_print_hex_dump(priv, IWL_DL_TX, out_cmd->cmd.payload,
  2199. sizeof(out_cmd->cmd.tx));
  2200. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2201. ieee80211_hdrlen(fc));
  2202. /* Tell device the write index *just past* this latest filled TFD */
  2203. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2204. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2205. spin_unlock_irqrestore(&priv->lock, flags);
  2206. if (rc)
  2207. return rc;
  2208. if ((iwl3945_queue_space(q) < q->high_mark)
  2209. && priv->mac80211_registered) {
  2210. if (wait_write_ptr) {
  2211. spin_lock_irqsave(&priv->lock, flags);
  2212. txq->need_update = 1;
  2213. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2214. spin_unlock_irqrestore(&priv->lock, flags);
  2215. }
  2216. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2217. }
  2218. return 0;
  2219. drop_unlock:
  2220. spin_unlock_irqrestore(&priv->lock, flags);
  2221. drop:
  2222. return -1;
  2223. }
  2224. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2225. {
  2226. const struct ieee80211_supported_band *sband = NULL;
  2227. struct ieee80211_rate *rate;
  2228. int i;
  2229. sband = iwl3945_get_band(priv, priv->band);
  2230. if (!sband) {
  2231. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2232. return;
  2233. }
  2234. priv->active_rate = 0;
  2235. priv->active_rate_basic = 0;
  2236. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2237. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2238. for (i = 0; i < sband->n_bitrates; i++) {
  2239. rate = &sband->bitrates[i];
  2240. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2241. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2242. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2243. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2244. priv->active_rate |= (1 << rate->hw_value);
  2245. }
  2246. }
  2247. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2248. priv->active_rate, priv->active_rate_basic);
  2249. /*
  2250. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2251. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2252. * OFDM
  2253. */
  2254. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2255. priv->staging_rxon.cck_basic_rates =
  2256. ((priv->active_rate_basic &
  2257. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2258. else
  2259. priv->staging_rxon.cck_basic_rates =
  2260. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2261. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2262. priv->staging_rxon.ofdm_basic_rates =
  2263. ((priv->active_rate_basic &
  2264. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2265. IWL_FIRST_OFDM_RATE) & 0xFF;
  2266. else
  2267. priv->staging_rxon.ofdm_basic_rates =
  2268. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2269. }
  2270. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2271. {
  2272. unsigned long flags;
  2273. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2274. return;
  2275. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2276. disable_radio ? "OFF" : "ON");
  2277. if (disable_radio) {
  2278. iwl3945_scan_cancel(priv);
  2279. /* FIXME: This is a workaround for AP */
  2280. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2281. spin_lock_irqsave(&priv->lock, flags);
  2282. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2283. CSR_UCODE_SW_BIT_RFKILL);
  2284. spin_unlock_irqrestore(&priv->lock, flags);
  2285. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2286. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2287. }
  2288. return;
  2289. }
  2290. spin_lock_irqsave(&priv->lock, flags);
  2291. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2292. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2293. spin_unlock_irqrestore(&priv->lock, flags);
  2294. /* wake up ucode */
  2295. msleep(10);
  2296. spin_lock_irqsave(&priv->lock, flags);
  2297. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2298. if (!iwl3945_grab_nic_access(priv))
  2299. iwl3945_release_nic_access(priv);
  2300. spin_unlock_irqrestore(&priv->lock, flags);
  2301. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2302. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2303. "disabled by HW switch\n");
  2304. return;
  2305. }
  2306. if (priv->is_open)
  2307. queue_work(priv->workqueue, &priv->restart);
  2308. return;
  2309. }
  2310. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2311. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2312. {
  2313. u16 fc =
  2314. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2315. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2316. return;
  2317. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2318. return;
  2319. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2320. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2321. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2322. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2323. RX_RES_STATUS_BAD_ICV_MIC)
  2324. stats->flag |= RX_FLAG_MMIC_ERROR;
  2325. case RX_RES_STATUS_SEC_TYPE_WEP:
  2326. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2327. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2328. RX_RES_STATUS_DECRYPT_OK) {
  2329. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2330. stats->flag |= RX_FLAG_DECRYPTED;
  2331. }
  2332. break;
  2333. default:
  2334. break;
  2335. }
  2336. }
  2337. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2338. #include "iwl-spectrum.h"
  2339. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2340. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2341. #define TIME_UNIT 1024
  2342. /*
  2343. * extended beacon time format
  2344. * time in usec will be changed into a 32-bit value in 8:24 format
  2345. * the high 1 byte is the beacon counts
  2346. * the lower 3 bytes is the time in usec within one beacon interval
  2347. */
  2348. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2349. {
  2350. u32 quot;
  2351. u32 rem;
  2352. u32 interval = beacon_interval * 1024;
  2353. if (!interval || !usec)
  2354. return 0;
  2355. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2356. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2357. return (quot << 24) + rem;
  2358. }
  2359. /* base is usually what we get from ucode with each received frame,
  2360. * the same as HW timer counter counting down
  2361. */
  2362. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2363. {
  2364. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2365. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2366. u32 interval = beacon_interval * TIME_UNIT;
  2367. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2368. (addon & BEACON_TIME_MASK_HIGH);
  2369. if (base_low > addon_low)
  2370. res += base_low - addon_low;
  2371. else if (base_low < addon_low) {
  2372. res += interval + base_low - addon_low;
  2373. res += (1 << 24);
  2374. } else
  2375. res += (1 << 24);
  2376. return cpu_to_le32(res);
  2377. }
  2378. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2379. struct ieee80211_measurement_params *params,
  2380. u8 type)
  2381. {
  2382. struct iwl_spectrum_cmd spectrum;
  2383. struct iwl_rx_packet *res;
  2384. struct iwl3945_host_cmd cmd = {
  2385. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2386. .data = (void *)&spectrum,
  2387. .meta.flags = CMD_WANT_SKB,
  2388. };
  2389. u32 add_time = le64_to_cpu(params->start_time);
  2390. int rc;
  2391. int spectrum_resp_status;
  2392. int duration = le16_to_cpu(params->duration);
  2393. if (iwl3945_is_associated(priv))
  2394. add_time =
  2395. iwl3945_usecs_to_beacons(
  2396. le64_to_cpu(params->start_time) - priv->last_tsf,
  2397. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2398. memset(&spectrum, 0, sizeof(spectrum));
  2399. spectrum.channel_count = cpu_to_le16(1);
  2400. spectrum.flags =
  2401. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2402. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2403. cmd.len = sizeof(spectrum);
  2404. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2405. if (iwl3945_is_associated(priv))
  2406. spectrum.start_time =
  2407. iwl3945_add_beacon_time(priv->last_beacon_time,
  2408. add_time,
  2409. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2410. else
  2411. spectrum.start_time = 0;
  2412. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2413. spectrum.channels[0].channel = params->channel;
  2414. spectrum.channels[0].type = type;
  2415. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2416. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2417. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2418. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2419. if (rc)
  2420. return rc;
  2421. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2422. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2423. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2424. rc = -EIO;
  2425. }
  2426. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2427. switch (spectrum_resp_status) {
  2428. case 0: /* Command will be handled */
  2429. if (res->u.spectrum.id != 0xff) {
  2430. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2431. res->u.spectrum.id);
  2432. priv->measurement_status &= ~MEASUREMENT_READY;
  2433. }
  2434. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2435. rc = 0;
  2436. break;
  2437. case 1: /* Command will not be handled */
  2438. rc = -EAGAIN;
  2439. break;
  2440. }
  2441. dev_kfree_skb_any(cmd.meta.u.skb);
  2442. return rc;
  2443. }
  2444. #endif
  2445. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2446. struct iwl3945_rx_mem_buffer *rxb)
  2447. {
  2448. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2449. struct iwl_alive_resp *palive;
  2450. struct delayed_work *pwork;
  2451. palive = &pkt->u.alive_frame;
  2452. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2453. "0x%01X 0x%01X\n",
  2454. palive->is_valid, palive->ver_type,
  2455. palive->ver_subtype);
  2456. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2457. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2458. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2459. sizeof(struct iwl_alive_resp));
  2460. pwork = &priv->init_alive_start;
  2461. } else {
  2462. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2463. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2464. sizeof(struct iwl_alive_resp));
  2465. pwork = &priv->alive_start;
  2466. iwl3945_disable_events(priv);
  2467. }
  2468. /* We delay the ALIVE response by 5ms to
  2469. * give the HW RF Kill time to activate... */
  2470. if (palive->is_valid == UCODE_VALID_OK)
  2471. queue_delayed_work(priv->workqueue, pwork,
  2472. msecs_to_jiffies(5));
  2473. else
  2474. IWL_WARNING("uCode did not respond OK.\n");
  2475. }
  2476. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2477. struct iwl3945_rx_mem_buffer *rxb)
  2478. {
  2479. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2480. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2481. return;
  2482. }
  2483. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2484. struct iwl3945_rx_mem_buffer *rxb)
  2485. {
  2486. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2487. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2488. "seq 0x%04X ser 0x%08X\n",
  2489. le32_to_cpu(pkt->u.err_resp.error_type),
  2490. get_cmd_string(pkt->u.err_resp.cmd_id),
  2491. pkt->u.err_resp.cmd_id,
  2492. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2493. le32_to_cpu(pkt->u.err_resp.error_info));
  2494. }
  2495. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2496. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2497. {
  2498. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2499. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2500. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2501. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2502. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2503. rxon->channel = csa->channel;
  2504. priv->staging_rxon.channel = csa->channel;
  2505. }
  2506. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2507. struct iwl3945_rx_mem_buffer *rxb)
  2508. {
  2509. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2510. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2511. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2512. if (!report->state) {
  2513. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2514. "Spectrum Measure Notification: Start\n");
  2515. return;
  2516. }
  2517. memcpy(&priv->measure_report, report, sizeof(*report));
  2518. priv->measurement_status |= MEASUREMENT_READY;
  2519. #endif
  2520. }
  2521. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2522. struct iwl3945_rx_mem_buffer *rxb)
  2523. {
  2524. #ifdef CONFIG_IWL3945_DEBUG
  2525. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2526. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2527. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2528. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2529. #endif
  2530. }
  2531. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2532. struct iwl3945_rx_mem_buffer *rxb)
  2533. {
  2534. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2535. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2536. "notification for %s:\n",
  2537. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2538. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2539. le32_to_cpu(pkt->len));
  2540. }
  2541. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2542. {
  2543. struct iwl3945_priv *priv =
  2544. container_of(work, struct iwl3945_priv, beacon_update);
  2545. struct sk_buff *beacon;
  2546. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2547. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2548. if (!beacon) {
  2549. IWL_ERROR("update beacon failed\n");
  2550. return;
  2551. }
  2552. mutex_lock(&priv->mutex);
  2553. /* new beacon skb is allocated every time; dispose previous.*/
  2554. if (priv->ibss_beacon)
  2555. dev_kfree_skb(priv->ibss_beacon);
  2556. priv->ibss_beacon = beacon;
  2557. mutex_unlock(&priv->mutex);
  2558. iwl3945_send_beacon_cmd(priv);
  2559. }
  2560. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2561. struct iwl3945_rx_mem_buffer *rxb)
  2562. {
  2563. #ifdef CONFIG_IWL3945_DEBUG
  2564. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2565. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2566. u8 rate = beacon->beacon_notify_hdr.rate;
  2567. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2568. "tsf %d %d rate %d\n",
  2569. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2570. beacon->beacon_notify_hdr.failure_frame,
  2571. le32_to_cpu(beacon->ibss_mgr_status),
  2572. le32_to_cpu(beacon->high_tsf),
  2573. le32_to_cpu(beacon->low_tsf), rate);
  2574. #endif
  2575. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2576. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2577. queue_work(priv->workqueue, &priv->beacon_update);
  2578. }
  2579. /* Service response to REPLY_SCAN_CMD (0x80) */
  2580. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2581. struct iwl3945_rx_mem_buffer *rxb)
  2582. {
  2583. #ifdef CONFIG_IWL3945_DEBUG
  2584. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2585. struct iwl_scanreq_notification *notif =
  2586. (struct iwl_scanreq_notification *)pkt->u.raw;
  2587. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2588. #endif
  2589. }
  2590. /* Service SCAN_START_NOTIFICATION (0x82) */
  2591. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2592. struct iwl3945_rx_mem_buffer *rxb)
  2593. {
  2594. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2595. struct iwl_scanstart_notification *notif =
  2596. (struct iwl_scanstart_notification *)pkt->u.raw;
  2597. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2598. IWL_DEBUG_SCAN("Scan start: "
  2599. "%d [802.11%s] "
  2600. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2601. notif->channel,
  2602. notif->band ? "bg" : "a",
  2603. notif->tsf_high,
  2604. notif->tsf_low, notif->status, notif->beacon_timer);
  2605. }
  2606. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2607. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2608. struct iwl3945_rx_mem_buffer *rxb)
  2609. {
  2610. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2611. struct iwl_scanresults_notification *notif =
  2612. (struct iwl_scanresults_notification *)pkt->u.raw;
  2613. IWL_DEBUG_SCAN("Scan ch.res: "
  2614. "%d [802.11%s] "
  2615. "(TSF: 0x%08X:%08X) - %d "
  2616. "elapsed=%lu usec (%dms since last)\n",
  2617. notif->channel,
  2618. notif->band ? "bg" : "a",
  2619. le32_to_cpu(notif->tsf_high),
  2620. le32_to_cpu(notif->tsf_low),
  2621. le32_to_cpu(notif->statistics[0]),
  2622. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2623. jiffies_to_msecs(elapsed_jiffies
  2624. (priv->last_scan_jiffies, jiffies)));
  2625. priv->last_scan_jiffies = jiffies;
  2626. priv->next_scan_jiffies = 0;
  2627. }
  2628. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2629. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2630. struct iwl3945_rx_mem_buffer *rxb)
  2631. {
  2632. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2633. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2634. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2635. scan_notif->scanned_channels,
  2636. scan_notif->tsf_low,
  2637. scan_notif->tsf_high, scan_notif->status);
  2638. /* The HW is no longer scanning */
  2639. clear_bit(STATUS_SCAN_HW, &priv->status);
  2640. /* The scan completion notification came in, so kill that timer... */
  2641. cancel_delayed_work(&priv->scan_check);
  2642. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2643. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2644. "2.4" : "5.2",
  2645. jiffies_to_msecs(elapsed_jiffies
  2646. (priv->scan_pass_start, jiffies)));
  2647. /* Remove this scanned band from the list of pending
  2648. * bands to scan, band G precedes A in order of scanning
  2649. * as seen in iwl3945_bg_request_scan */
  2650. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2651. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2652. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2653. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2654. /* If a request to abort was given, or the scan did not succeed
  2655. * then we reset the scan state machine and terminate,
  2656. * re-queuing another scan if one has been requested */
  2657. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2658. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2659. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2660. } else {
  2661. /* If there are more bands on this scan pass reschedule */
  2662. if (priv->scan_bands > 0)
  2663. goto reschedule;
  2664. }
  2665. priv->last_scan_jiffies = jiffies;
  2666. priv->next_scan_jiffies = 0;
  2667. IWL_DEBUG_INFO("Setting scan to off\n");
  2668. clear_bit(STATUS_SCANNING, &priv->status);
  2669. IWL_DEBUG_INFO("Scan took %dms\n",
  2670. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2671. queue_work(priv->workqueue, &priv->scan_completed);
  2672. return;
  2673. reschedule:
  2674. priv->scan_pass_start = jiffies;
  2675. queue_work(priv->workqueue, &priv->request_scan);
  2676. }
  2677. /* Handle notification from uCode that card's power state is changing
  2678. * due to software, hardware, or critical temperature RFKILL */
  2679. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2680. struct iwl3945_rx_mem_buffer *rxb)
  2681. {
  2682. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2683. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2684. unsigned long status = priv->status;
  2685. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2686. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2687. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2688. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2689. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2690. if (flags & HW_CARD_DISABLED)
  2691. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2692. else
  2693. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2694. if (flags & SW_CARD_DISABLED)
  2695. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2696. else
  2697. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2698. iwl3945_scan_cancel(priv);
  2699. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2700. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2701. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2702. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2703. queue_work(priv->workqueue, &priv->rf_kill);
  2704. else
  2705. wake_up_interruptible(&priv->wait_command_queue);
  2706. }
  2707. /**
  2708. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2709. *
  2710. * Setup the RX handlers for each of the reply types sent from the uCode
  2711. * to the host.
  2712. *
  2713. * This function chains into the hardware specific files for them to setup
  2714. * any hardware specific handlers as well.
  2715. */
  2716. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2717. {
  2718. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2719. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2720. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2721. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2722. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2723. iwl3945_rx_spectrum_measure_notif;
  2724. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2725. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2726. iwl3945_rx_pm_debug_statistics_notif;
  2727. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2728. /*
  2729. * The same handler is used for both the REPLY to a discrete
  2730. * statistics request from the host as well as for the periodic
  2731. * statistics notifications (after received beacons) from the uCode.
  2732. */
  2733. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2734. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2735. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2736. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2737. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2738. iwl3945_rx_scan_results_notif;
  2739. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2740. iwl3945_rx_scan_complete_notif;
  2741. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2742. /* Set up hardware specific Rx handlers */
  2743. iwl3945_hw_rx_handler_setup(priv);
  2744. }
  2745. /**
  2746. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2747. * When FW advances 'R' index, all entries between old and new 'R' index
  2748. * need to be reclaimed.
  2749. */
  2750. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2751. int txq_id, int index)
  2752. {
  2753. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2754. struct iwl3945_queue *q = &txq->q;
  2755. int nfreed = 0;
  2756. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2757. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2758. "is out of range [0-%d] %d %d.\n", txq_id,
  2759. index, q->n_bd, q->write_ptr, q->read_ptr);
  2760. return;
  2761. }
  2762. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2763. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2764. if (nfreed > 1) {
  2765. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2766. q->write_ptr, q->read_ptr);
  2767. queue_work(priv->workqueue, &priv->restart);
  2768. break;
  2769. }
  2770. nfreed++;
  2771. }
  2772. }
  2773. /**
  2774. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2775. * @rxb: Rx buffer to reclaim
  2776. *
  2777. * If an Rx buffer has an async callback associated with it the callback
  2778. * will be executed. The attached skb (if present) will only be freed
  2779. * if the callback returns 1
  2780. */
  2781. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2782. struct iwl3945_rx_mem_buffer *rxb)
  2783. {
  2784. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2785. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2786. int txq_id = SEQ_TO_QUEUE(sequence);
  2787. int index = SEQ_TO_INDEX(sequence);
  2788. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2789. int cmd_index;
  2790. struct iwl3945_cmd *cmd;
  2791. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2792. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2793. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2794. /* Input error checking is done when commands are added to queue. */
  2795. if (cmd->meta.flags & CMD_WANT_SKB) {
  2796. cmd->meta.source->u.skb = rxb->skb;
  2797. rxb->skb = NULL;
  2798. } else if (cmd->meta.u.callback &&
  2799. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2800. rxb->skb = NULL;
  2801. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2802. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2803. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2804. wake_up_interruptible(&priv->wait_command_queue);
  2805. }
  2806. }
  2807. /************************** RX-FUNCTIONS ****************************/
  2808. /*
  2809. * Rx theory of operation
  2810. *
  2811. * The host allocates 32 DMA target addresses and passes the host address
  2812. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2813. * 0 to 31
  2814. *
  2815. * Rx Queue Indexes
  2816. * The host/firmware share two index registers for managing the Rx buffers.
  2817. *
  2818. * The READ index maps to the first position that the firmware may be writing
  2819. * to -- the driver can read up to (but not including) this position and get
  2820. * good data.
  2821. * The READ index is managed by the firmware once the card is enabled.
  2822. *
  2823. * The WRITE index maps to the last position the driver has read from -- the
  2824. * position preceding WRITE is the last slot the firmware can place a packet.
  2825. *
  2826. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2827. * WRITE = READ.
  2828. *
  2829. * During initialization, the host sets up the READ queue position to the first
  2830. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2831. *
  2832. * When the firmware places a packet in a buffer, it will advance the READ index
  2833. * and fire the RX interrupt. The driver can then query the READ index and
  2834. * process as many packets as possible, moving the WRITE index forward as it
  2835. * resets the Rx queue buffers with new memory.
  2836. *
  2837. * The management in the driver is as follows:
  2838. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2839. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2840. * to replenish the iwl->rxq->rx_free.
  2841. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2842. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2843. * 'processed' and 'read' driver indexes as well)
  2844. * + A received packet is processed and handed to the kernel network stack,
  2845. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2846. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2847. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2848. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2849. * were enough free buffers and RX_STALLED is set it is cleared.
  2850. *
  2851. *
  2852. * Driver sequence:
  2853. *
  2854. * iwl3945_rx_queue_alloc() Allocates rx_free
  2855. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2856. * iwl3945_rx_queue_restock
  2857. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2858. * queue, updates firmware pointers, and updates
  2859. * the WRITE index. If insufficient rx_free buffers
  2860. * are available, schedules iwl3945_rx_replenish
  2861. *
  2862. * -- enable interrupts --
  2863. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  2864. * READ INDEX, detaching the SKB from the pool.
  2865. * Moves the packet buffer from queue to rx_used.
  2866. * Calls iwl3945_rx_queue_restock to refill any empty
  2867. * slots.
  2868. * ...
  2869. *
  2870. */
  2871. /**
  2872. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2873. */
  2874. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  2875. {
  2876. int s = q->read - q->write;
  2877. if (s <= 0)
  2878. s += RX_QUEUE_SIZE;
  2879. /* keep some buffer to not confuse full and empty queue */
  2880. s -= 2;
  2881. if (s < 0)
  2882. s = 0;
  2883. return s;
  2884. }
  2885. /**
  2886. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2887. */
  2888. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  2889. {
  2890. u32 reg = 0;
  2891. int rc = 0;
  2892. unsigned long flags;
  2893. spin_lock_irqsave(&q->lock, flags);
  2894. if (q->need_update == 0)
  2895. goto exit_unlock;
  2896. /* If power-saving is in use, make sure device is awake */
  2897. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2898. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2899. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2900. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  2901. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2902. goto exit_unlock;
  2903. }
  2904. rc = iwl3945_grab_nic_access(priv);
  2905. if (rc)
  2906. goto exit_unlock;
  2907. /* Device expects a multiple of 8 */
  2908. iwl3945_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2909. q->write & ~0x7);
  2910. iwl3945_release_nic_access(priv);
  2911. /* Else device is assumed to be awake */
  2912. } else
  2913. /* Device expects a multiple of 8 */
  2914. iwl3945_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2915. q->need_update = 0;
  2916. exit_unlock:
  2917. spin_unlock_irqrestore(&q->lock, flags);
  2918. return rc;
  2919. }
  2920. /**
  2921. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2922. */
  2923. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  2924. dma_addr_t dma_addr)
  2925. {
  2926. return cpu_to_le32((u32)dma_addr);
  2927. }
  2928. /**
  2929. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2930. *
  2931. * If there are slots in the RX queue that need to be restocked,
  2932. * and we have free pre-allocated buffers, fill the ranks as much
  2933. * as we can, pulling from rx_free.
  2934. *
  2935. * This moves the 'write' index forward to catch up with 'processed', and
  2936. * also updates the memory address in the firmware to reference the new
  2937. * target buffer.
  2938. */
  2939. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  2940. {
  2941. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2942. struct list_head *element;
  2943. struct iwl3945_rx_mem_buffer *rxb;
  2944. unsigned long flags;
  2945. int write, rc;
  2946. spin_lock_irqsave(&rxq->lock, flags);
  2947. write = rxq->write & ~0x7;
  2948. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2949. /* Get next free Rx buffer, remove from free list */
  2950. element = rxq->rx_free.next;
  2951. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2952. list_del(element);
  2953. /* Point to Rx buffer via next RBD in circular buffer */
  2954. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  2955. rxq->queue[rxq->write] = rxb;
  2956. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2957. rxq->free_count--;
  2958. }
  2959. spin_unlock_irqrestore(&rxq->lock, flags);
  2960. /* If the pre-allocated buffer pool is dropping low, schedule to
  2961. * refill it */
  2962. if (rxq->free_count <= RX_LOW_WATERMARK)
  2963. queue_work(priv->workqueue, &priv->rx_replenish);
  2964. /* If we've added more space for the firmware to place data, tell it.
  2965. * Increment device's write pointer in multiples of 8. */
  2966. if ((write != (rxq->write & ~0x7))
  2967. || (abs(rxq->write - rxq->read) > 7)) {
  2968. spin_lock_irqsave(&rxq->lock, flags);
  2969. rxq->need_update = 1;
  2970. spin_unlock_irqrestore(&rxq->lock, flags);
  2971. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2972. if (rc)
  2973. return rc;
  2974. }
  2975. return 0;
  2976. }
  2977. /**
  2978. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2979. *
  2980. * When moving to rx_free an SKB is allocated for the slot.
  2981. *
  2982. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2983. * This is called as a scheduled work item (except for during initialization)
  2984. */
  2985. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  2986. {
  2987. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2988. struct list_head *element;
  2989. struct iwl3945_rx_mem_buffer *rxb;
  2990. unsigned long flags;
  2991. spin_lock_irqsave(&rxq->lock, flags);
  2992. while (!list_empty(&rxq->rx_used)) {
  2993. element = rxq->rx_used.next;
  2994. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2995. /* Alloc a new receive buffer */
  2996. rxb->skb =
  2997. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2998. if (!rxb->skb) {
  2999. if (net_ratelimit())
  3000. printk(KERN_CRIT DRV_NAME
  3001. ": Can not allocate SKB buffers\n");
  3002. /* We don't reschedule replenish work here -- we will
  3003. * call the restock method and if it still needs
  3004. * more buffers it will schedule replenish */
  3005. break;
  3006. }
  3007. /* If radiotap head is required, reserve some headroom here.
  3008. * The physical head count is a variable rx_stats->phy_count.
  3009. * We reserve 4 bytes here. Plus these extra bytes, the
  3010. * headroom of the physical head should be enough for the
  3011. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3012. */
  3013. skb_reserve(rxb->skb, 4);
  3014. priv->alloc_rxb_skb++;
  3015. list_del(element);
  3016. /* Get physical address of RB/SKB */
  3017. rxb->dma_addr =
  3018. pci_map_single(priv->pci_dev, rxb->skb->data,
  3019. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3020. list_add_tail(&rxb->list, &rxq->rx_free);
  3021. rxq->free_count++;
  3022. }
  3023. spin_unlock_irqrestore(&rxq->lock, flags);
  3024. }
  3025. /*
  3026. * this should be called while priv->lock is locked
  3027. */
  3028. static void __iwl3945_rx_replenish(void *data)
  3029. {
  3030. struct iwl3945_priv *priv = data;
  3031. iwl3945_rx_allocate(priv);
  3032. iwl3945_rx_queue_restock(priv);
  3033. }
  3034. void iwl3945_rx_replenish(void *data)
  3035. {
  3036. struct iwl3945_priv *priv = data;
  3037. unsigned long flags;
  3038. iwl3945_rx_allocate(priv);
  3039. spin_lock_irqsave(&priv->lock, flags);
  3040. iwl3945_rx_queue_restock(priv);
  3041. spin_unlock_irqrestore(&priv->lock, flags);
  3042. }
  3043. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3044. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3045. * This free routine walks the list of POOL entries and if SKB is set to
  3046. * non NULL it is unmapped and freed
  3047. */
  3048. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3049. {
  3050. int i;
  3051. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3052. if (rxq->pool[i].skb != NULL) {
  3053. pci_unmap_single(priv->pci_dev,
  3054. rxq->pool[i].dma_addr,
  3055. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3056. dev_kfree_skb(rxq->pool[i].skb);
  3057. }
  3058. }
  3059. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3060. rxq->dma_addr);
  3061. rxq->bd = NULL;
  3062. }
  3063. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3064. {
  3065. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3066. struct pci_dev *dev = priv->pci_dev;
  3067. int i;
  3068. spin_lock_init(&rxq->lock);
  3069. INIT_LIST_HEAD(&rxq->rx_free);
  3070. INIT_LIST_HEAD(&rxq->rx_used);
  3071. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3072. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3073. if (!rxq->bd)
  3074. return -ENOMEM;
  3075. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3076. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3077. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3078. /* Set us so that we have processed and used all buffers, but have
  3079. * not restocked the Rx queue with fresh buffers */
  3080. rxq->read = rxq->write = 0;
  3081. rxq->free_count = 0;
  3082. rxq->need_update = 0;
  3083. return 0;
  3084. }
  3085. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3086. {
  3087. unsigned long flags;
  3088. int i;
  3089. spin_lock_irqsave(&rxq->lock, flags);
  3090. INIT_LIST_HEAD(&rxq->rx_free);
  3091. INIT_LIST_HEAD(&rxq->rx_used);
  3092. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3093. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3094. /* In the reset function, these buffers may have been allocated
  3095. * to an SKB, so we need to unmap and free potential storage */
  3096. if (rxq->pool[i].skb != NULL) {
  3097. pci_unmap_single(priv->pci_dev,
  3098. rxq->pool[i].dma_addr,
  3099. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3100. priv->alloc_rxb_skb--;
  3101. dev_kfree_skb(rxq->pool[i].skb);
  3102. rxq->pool[i].skb = NULL;
  3103. }
  3104. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3105. }
  3106. /* Set us so that we have processed and used all buffers, but have
  3107. * not restocked the Rx queue with fresh buffers */
  3108. rxq->read = rxq->write = 0;
  3109. rxq->free_count = 0;
  3110. spin_unlock_irqrestore(&rxq->lock, flags);
  3111. }
  3112. /* Convert linear signal-to-noise ratio into dB */
  3113. static u8 ratio2dB[100] = {
  3114. /* 0 1 2 3 4 5 6 7 8 9 */
  3115. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3116. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3117. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3118. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3119. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3120. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3121. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3122. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3123. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3124. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3125. };
  3126. /* Calculates a relative dB value from a ratio of linear
  3127. * (i.e. not dB) signal levels.
  3128. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3129. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3130. {
  3131. /* 1000:1 or higher just report as 60 dB */
  3132. if (sig_ratio >= 1000)
  3133. return 60;
  3134. /* 100:1 or higher, divide by 10 and use table,
  3135. * add 20 dB to make up for divide by 10 */
  3136. if (sig_ratio >= 100)
  3137. return 20 + (int)ratio2dB[sig_ratio/10];
  3138. /* We shouldn't see this */
  3139. if (sig_ratio < 1)
  3140. return 0;
  3141. /* Use table for ratios 1:1 - 99:1 */
  3142. return (int)ratio2dB[sig_ratio];
  3143. }
  3144. #define PERFECT_RSSI (-20) /* dBm */
  3145. #define WORST_RSSI (-95) /* dBm */
  3146. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3147. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3148. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3149. * about formulas used below. */
  3150. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3151. {
  3152. int sig_qual;
  3153. int degradation = PERFECT_RSSI - rssi_dbm;
  3154. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3155. * as indicator; formula is (signal dbm - noise dbm).
  3156. * SNR at or above 40 is a great signal (100%).
  3157. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3158. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3159. if (noise_dbm) {
  3160. if (rssi_dbm - noise_dbm >= 40)
  3161. return 100;
  3162. else if (rssi_dbm < noise_dbm)
  3163. return 0;
  3164. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3165. /* Else use just the signal level.
  3166. * This formula is a least squares fit of data points collected and
  3167. * compared with a reference system that had a percentage (%) display
  3168. * for signal quality. */
  3169. } else
  3170. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3171. (15 * RSSI_RANGE + 62 * degradation)) /
  3172. (RSSI_RANGE * RSSI_RANGE);
  3173. if (sig_qual > 100)
  3174. sig_qual = 100;
  3175. else if (sig_qual < 1)
  3176. sig_qual = 0;
  3177. return sig_qual;
  3178. }
  3179. /**
  3180. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3181. *
  3182. * Uses the priv->rx_handlers callback function array to invoke
  3183. * the appropriate handlers, including command responses,
  3184. * frame-received notifications, and other notifications.
  3185. */
  3186. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3187. {
  3188. struct iwl3945_rx_mem_buffer *rxb;
  3189. struct iwl_rx_packet *pkt;
  3190. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3191. u32 r, i;
  3192. int reclaim;
  3193. unsigned long flags;
  3194. u8 fill_rx = 0;
  3195. u32 count = 8;
  3196. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3197. * buffer that the driver may process (last buffer filled by ucode). */
  3198. r = iwl3945_hw_get_rx_read(priv);
  3199. i = rxq->read;
  3200. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3201. fill_rx = 1;
  3202. /* Rx interrupt, but nothing sent from uCode */
  3203. if (i == r)
  3204. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3205. while (i != r) {
  3206. rxb = rxq->queue[i];
  3207. /* If an RXB doesn't have a Rx queue slot associated with it,
  3208. * then a bug has been introduced in the queue refilling
  3209. * routines -- catch it here */
  3210. BUG_ON(rxb == NULL);
  3211. rxq->queue[i] = NULL;
  3212. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3213. IWL_RX_BUF_SIZE,
  3214. PCI_DMA_FROMDEVICE);
  3215. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  3216. /* Reclaim a command buffer only if this packet is a response
  3217. * to a (driver-originated) command.
  3218. * If the packet (e.g. Rx frame) originated from uCode,
  3219. * there is no command buffer to reclaim.
  3220. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3221. * but apparently a few don't get set; catch them here. */
  3222. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3223. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3224. (pkt->hdr.cmd != REPLY_TX);
  3225. /* Based on type of command response or notification,
  3226. * handle those that need handling via function in
  3227. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3228. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3229. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3230. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3231. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3232. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3233. } else {
  3234. /* No handling needed */
  3235. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3236. "r %d i %d No handler needed for %s, 0x%02x\n",
  3237. r, i, get_cmd_string(pkt->hdr.cmd),
  3238. pkt->hdr.cmd);
  3239. }
  3240. if (reclaim) {
  3241. /* Invoke any callbacks, transfer the skb to caller, and
  3242. * fire off the (possibly) blocking iwl3945_send_cmd()
  3243. * as we reclaim the driver command queue */
  3244. if (rxb && rxb->skb)
  3245. iwl3945_tx_cmd_complete(priv, rxb);
  3246. else
  3247. IWL_WARNING("Claim null rxb?\n");
  3248. }
  3249. /* For now we just don't re-use anything. We can tweak this
  3250. * later to try and re-use notification packets and SKBs that
  3251. * fail to Rx correctly */
  3252. if (rxb->skb != NULL) {
  3253. priv->alloc_rxb_skb--;
  3254. dev_kfree_skb_any(rxb->skb);
  3255. rxb->skb = NULL;
  3256. }
  3257. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3258. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3259. spin_lock_irqsave(&rxq->lock, flags);
  3260. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3261. spin_unlock_irqrestore(&rxq->lock, flags);
  3262. i = (i + 1) & RX_QUEUE_MASK;
  3263. /* If there are a lot of unused frames,
  3264. * restock the Rx queue so ucode won't assert. */
  3265. if (fill_rx) {
  3266. count++;
  3267. if (count >= 8) {
  3268. priv->rxq.read = i;
  3269. __iwl3945_rx_replenish(priv);
  3270. count = 0;
  3271. }
  3272. }
  3273. }
  3274. /* Backtrack one entry */
  3275. priv->rxq.read = i;
  3276. iwl3945_rx_queue_restock(priv);
  3277. }
  3278. /**
  3279. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3280. */
  3281. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3282. struct iwl3945_tx_queue *txq)
  3283. {
  3284. u32 reg = 0;
  3285. int rc = 0;
  3286. int txq_id = txq->q.id;
  3287. if (txq->need_update == 0)
  3288. return rc;
  3289. /* if we're trying to save power */
  3290. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3291. /* wake up nic if it's powered down ...
  3292. * uCode will wake up, and interrupt us again, so next
  3293. * time we'll skip this part. */
  3294. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3295. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3296. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3297. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3298. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3299. return rc;
  3300. }
  3301. /* restore this queue's parameters in nic hardware. */
  3302. rc = iwl3945_grab_nic_access(priv);
  3303. if (rc)
  3304. return rc;
  3305. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3306. txq->q.write_ptr | (txq_id << 8));
  3307. iwl3945_release_nic_access(priv);
  3308. /* else not in power-save mode, uCode will never sleep when we're
  3309. * trying to tx (during RFKILL, we're not trying to tx). */
  3310. } else
  3311. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3312. txq->q.write_ptr | (txq_id << 8));
  3313. txq->need_update = 0;
  3314. return rc;
  3315. }
  3316. #ifdef CONFIG_IWL3945_DEBUG
  3317. static void iwl3945_print_rx_config_cmd(struct iwl3945_priv *priv,
  3318. struct iwl3945_rxon_cmd *rxon)
  3319. {
  3320. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3321. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3322. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3323. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3324. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3325. le32_to_cpu(rxon->filter_flags));
  3326. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3327. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3328. rxon->ofdm_basic_rates);
  3329. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3330. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3331. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3332. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3333. }
  3334. #endif
  3335. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3336. {
  3337. IWL_DEBUG_ISR("Enabling interrupts\n");
  3338. set_bit(STATUS_INT_ENABLED, &priv->status);
  3339. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3340. }
  3341. /* call this function to flush any scheduled tasklet */
  3342. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3343. {
  3344. /* wait to make sure we flush pending tasklet*/
  3345. synchronize_irq(priv->pci_dev->irq);
  3346. tasklet_kill(&priv->irq_tasklet);
  3347. }
  3348. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3349. {
  3350. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3351. /* disable interrupts from uCode/NIC to host */
  3352. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3353. /* acknowledge/clear/reset any interrupts still pending
  3354. * from uCode or flow handler (Rx/Tx DMA) */
  3355. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3356. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3357. IWL_DEBUG_ISR("Disabled interrupts\n");
  3358. }
  3359. static const char *desc_lookup(int i)
  3360. {
  3361. switch (i) {
  3362. case 1:
  3363. return "FAIL";
  3364. case 2:
  3365. return "BAD_PARAM";
  3366. case 3:
  3367. return "BAD_CHECKSUM";
  3368. case 4:
  3369. return "NMI_INTERRUPT";
  3370. case 5:
  3371. return "SYSASSERT";
  3372. case 6:
  3373. return "FATAL_ERROR";
  3374. }
  3375. return "UNKNOWN";
  3376. }
  3377. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3378. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3379. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3380. {
  3381. u32 i;
  3382. u32 desc, time, count, base, data1;
  3383. u32 blink1, blink2, ilink1, ilink2;
  3384. int rc;
  3385. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3386. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3387. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3388. return;
  3389. }
  3390. rc = iwl3945_grab_nic_access(priv);
  3391. if (rc) {
  3392. IWL_WARNING("Can not read from adapter at this time.\n");
  3393. return;
  3394. }
  3395. count = iwl3945_read_targ_mem(priv, base);
  3396. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3397. IWL_ERROR("Start IWL Error Log Dump:\n");
  3398. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3399. }
  3400. IWL_ERROR("Desc Time asrtPC blink2 "
  3401. "ilink1 nmiPC Line\n");
  3402. for (i = ERROR_START_OFFSET;
  3403. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3404. i += ERROR_ELEM_SIZE) {
  3405. desc = iwl3945_read_targ_mem(priv, base + i);
  3406. time =
  3407. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3408. blink1 =
  3409. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3410. blink2 =
  3411. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3412. ilink1 =
  3413. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3414. ilink2 =
  3415. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3416. data1 =
  3417. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3418. IWL_ERROR
  3419. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3420. desc_lookup(desc), desc, time, blink1, blink2,
  3421. ilink1, ilink2, data1);
  3422. }
  3423. iwl3945_release_nic_access(priv);
  3424. }
  3425. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3426. /**
  3427. * iwl3945_print_event_log - Dump error event log to syslog
  3428. *
  3429. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3430. */
  3431. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3432. u32 num_events, u32 mode)
  3433. {
  3434. u32 i;
  3435. u32 base; /* SRAM byte address of event log header */
  3436. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3437. u32 ptr; /* SRAM byte address of log data */
  3438. u32 ev, time, data; /* event log data */
  3439. if (num_events == 0)
  3440. return;
  3441. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3442. if (mode == 0)
  3443. event_size = 2 * sizeof(u32);
  3444. else
  3445. event_size = 3 * sizeof(u32);
  3446. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3447. /* "time" is actually "data" for mode 0 (no timestamp).
  3448. * place event id # at far right for easier visual parsing. */
  3449. for (i = 0; i < num_events; i++) {
  3450. ev = iwl3945_read_targ_mem(priv, ptr);
  3451. ptr += sizeof(u32);
  3452. time = iwl3945_read_targ_mem(priv, ptr);
  3453. ptr += sizeof(u32);
  3454. if (mode == 0)
  3455. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3456. else {
  3457. data = iwl3945_read_targ_mem(priv, ptr);
  3458. ptr += sizeof(u32);
  3459. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3460. }
  3461. }
  3462. }
  3463. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3464. {
  3465. int rc;
  3466. u32 base; /* SRAM byte address of event log header */
  3467. u32 capacity; /* event log capacity in # entries */
  3468. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3469. u32 num_wraps; /* # times uCode wrapped to top of log */
  3470. u32 next_entry; /* index of next entry to be written by uCode */
  3471. u32 size; /* # entries that we'll print */
  3472. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3473. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3474. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3475. return;
  3476. }
  3477. rc = iwl3945_grab_nic_access(priv);
  3478. if (rc) {
  3479. IWL_WARNING("Can not read from adapter at this time.\n");
  3480. return;
  3481. }
  3482. /* event log header */
  3483. capacity = iwl3945_read_targ_mem(priv, base);
  3484. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3485. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3486. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3487. size = num_wraps ? capacity : next_entry;
  3488. /* bail out if nothing in log */
  3489. if (size == 0) {
  3490. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3491. iwl3945_release_nic_access(priv);
  3492. return;
  3493. }
  3494. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3495. size, num_wraps);
  3496. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3497. * i.e the next one that uCode would fill. */
  3498. if (num_wraps)
  3499. iwl3945_print_event_log(priv, next_entry,
  3500. capacity - next_entry, mode);
  3501. /* (then/else) start at top of log */
  3502. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3503. iwl3945_release_nic_access(priv);
  3504. }
  3505. /**
  3506. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3507. */
  3508. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3509. {
  3510. /* Set the FW error flag -- cleared on iwl3945_down */
  3511. set_bit(STATUS_FW_ERROR, &priv->status);
  3512. /* Cancel currently queued command. */
  3513. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3514. #ifdef CONFIG_IWL3945_DEBUG
  3515. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3516. iwl3945_dump_nic_error_log(priv);
  3517. iwl3945_dump_nic_event_log(priv);
  3518. iwl3945_print_rx_config_cmd(priv, &priv->staging_rxon);
  3519. }
  3520. #endif
  3521. wake_up_interruptible(&priv->wait_command_queue);
  3522. /* Keep the restart process from trying to send host
  3523. * commands by clearing the INIT status bit */
  3524. clear_bit(STATUS_READY, &priv->status);
  3525. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3526. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3527. "Restarting adapter due to uCode error.\n");
  3528. if (iwl3945_is_associated(priv)) {
  3529. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3530. sizeof(priv->recovery_rxon));
  3531. priv->error_recovering = 1;
  3532. }
  3533. queue_work(priv->workqueue, &priv->restart);
  3534. }
  3535. }
  3536. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3537. {
  3538. unsigned long flags;
  3539. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3540. sizeof(priv->staging_rxon));
  3541. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3542. iwl3945_commit_rxon(priv);
  3543. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3544. spin_lock_irqsave(&priv->lock, flags);
  3545. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3546. priv->error_recovering = 0;
  3547. spin_unlock_irqrestore(&priv->lock, flags);
  3548. }
  3549. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3550. {
  3551. u32 inta, handled = 0;
  3552. u32 inta_fh;
  3553. unsigned long flags;
  3554. #ifdef CONFIG_IWL3945_DEBUG
  3555. u32 inta_mask;
  3556. #endif
  3557. spin_lock_irqsave(&priv->lock, flags);
  3558. /* Ack/clear/reset pending uCode interrupts.
  3559. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3560. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3561. inta = iwl3945_read32(priv, CSR_INT);
  3562. iwl3945_write32(priv, CSR_INT, inta);
  3563. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3564. * Any new interrupts that happen after this, either while we're
  3565. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3566. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3567. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3568. #ifdef CONFIG_IWL3945_DEBUG
  3569. if (priv->debug_level & IWL_DL_ISR) {
  3570. /* just for debug */
  3571. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3572. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3573. inta, inta_mask, inta_fh);
  3574. }
  3575. #endif
  3576. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3577. * atomic, make sure that inta covers all the interrupts that
  3578. * we've discovered, even if FH interrupt came in just after
  3579. * reading CSR_INT. */
  3580. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3581. inta |= CSR_INT_BIT_FH_RX;
  3582. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3583. inta |= CSR_INT_BIT_FH_TX;
  3584. /* Now service all interrupt bits discovered above. */
  3585. if (inta & CSR_INT_BIT_HW_ERR) {
  3586. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3587. /* Tell the device to stop sending interrupts */
  3588. iwl3945_disable_interrupts(priv);
  3589. iwl3945_irq_handle_error(priv);
  3590. handled |= CSR_INT_BIT_HW_ERR;
  3591. spin_unlock_irqrestore(&priv->lock, flags);
  3592. return;
  3593. }
  3594. #ifdef CONFIG_IWL3945_DEBUG
  3595. if (priv->debug_level & (IWL_DL_ISR)) {
  3596. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3597. if (inta & CSR_INT_BIT_SCD)
  3598. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3599. "the frame/frames.\n");
  3600. /* Alive notification via Rx interrupt will do the real work */
  3601. if (inta & CSR_INT_BIT_ALIVE)
  3602. IWL_DEBUG_ISR("Alive interrupt\n");
  3603. }
  3604. #endif
  3605. /* Safely ignore these bits for debug checks below */
  3606. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3607. /* Error detected by uCode */
  3608. if (inta & CSR_INT_BIT_SW_ERR) {
  3609. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3610. inta);
  3611. iwl3945_irq_handle_error(priv);
  3612. handled |= CSR_INT_BIT_SW_ERR;
  3613. }
  3614. /* uCode wakes up after power-down sleep */
  3615. if (inta & CSR_INT_BIT_WAKEUP) {
  3616. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3617. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3618. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3619. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3620. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3621. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3622. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3623. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3624. handled |= CSR_INT_BIT_WAKEUP;
  3625. }
  3626. /* All uCode command responses, including Tx command responses,
  3627. * Rx "responses" (frame-received notification), and other
  3628. * notifications from uCode come through here*/
  3629. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3630. iwl3945_rx_handle(priv);
  3631. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3632. }
  3633. if (inta & CSR_INT_BIT_FH_TX) {
  3634. IWL_DEBUG_ISR("Tx interrupt\n");
  3635. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3636. if (!iwl3945_grab_nic_access(priv)) {
  3637. iwl3945_write_direct32(priv, FH39_TCSR_CREDIT
  3638. (FH39_SRVC_CHNL), 0x0);
  3639. iwl3945_release_nic_access(priv);
  3640. }
  3641. handled |= CSR_INT_BIT_FH_TX;
  3642. }
  3643. if (inta & ~handled)
  3644. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3645. if (inta & ~CSR_INI_SET_MASK) {
  3646. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3647. inta & ~CSR_INI_SET_MASK);
  3648. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3649. }
  3650. /* Re-enable all interrupts */
  3651. /* only Re-enable if disabled by irq */
  3652. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3653. iwl3945_enable_interrupts(priv);
  3654. #ifdef CONFIG_IWL3945_DEBUG
  3655. if (priv->debug_level & (IWL_DL_ISR)) {
  3656. inta = iwl3945_read32(priv, CSR_INT);
  3657. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3658. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3659. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3660. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3661. }
  3662. #endif
  3663. spin_unlock_irqrestore(&priv->lock, flags);
  3664. }
  3665. static irqreturn_t iwl3945_isr(int irq, void *data)
  3666. {
  3667. struct iwl3945_priv *priv = data;
  3668. u32 inta, inta_mask;
  3669. u32 inta_fh;
  3670. if (!priv)
  3671. return IRQ_NONE;
  3672. spin_lock(&priv->lock);
  3673. /* Disable (but don't clear!) interrupts here to avoid
  3674. * back-to-back ISRs and sporadic interrupts from our NIC.
  3675. * If we have something to service, the tasklet will re-enable ints.
  3676. * If we *don't* have something, we'll re-enable before leaving here. */
  3677. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3678. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3679. /* Discover which interrupts are active/pending */
  3680. inta = iwl3945_read32(priv, CSR_INT);
  3681. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3682. /* Ignore interrupt if there's nothing in NIC to service.
  3683. * This may be due to IRQ shared with another device,
  3684. * or due to sporadic interrupts thrown from our NIC. */
  3685. if (!inta && !inta_fh) {
  3686. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3687. goto none;
  3688. }
  3689. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3690. /* Hardware disappeared */
  3691. IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3692. goto unplugged;
  3693. }
  3694. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3695. inta, inta_mask, inta_fh);
  3696. inta &= ~CSR_INT_BIT_SCD;
  3697. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3698. if (likely(inta || inta_fh))
  3699. tasklet_schedule(&priv->irq_tasklet);
  3700. unplugged:
  3701. spin_unlock(&priv->lock);
  3702. return IRQ_HANDLED;
  3703. none:
  3704. /* re-enable interrupts here since we don't have anything to service. */
  3705. /* only Re-enable if disabled by irq */
  3706. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3707. iwl3945_enable_interrupts(priv);
  3708. spin_unlock(&priv->lock);
  3709. return IRQ_NONE;
  3710. }
  3711. /************************** EEPROM BANDS ****************************
  3712. *
  3713. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3714. * EEPROM contents to the specific channel number supported for each
  3715. * band.
  3716. *
  3717. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3718. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3719. * The specific geography and calibration information for that channel
  3720. * is contained in the eeprom map itself.
  3721. *
  3722. * During init, we copy the eeprom information and channel map
  3723. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3724. *
  3725. * channel_map_24/52 provides the index in the channel_info array for a
  3726. * given channel. We have to have two separate maps as there is channel
  3727. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3728. * band_2
  3729. *
  3730. * A value of 0xff stored in the channel_map indicates that the channel
  3731. * is not supported by the hardware at all.
  3732. *
  3733. * A value of 0xfe in the channel_map indicates that the channel is not
  3734. * valid for Tx with the current hardware. This means that
  3735. * while the system can tune and receive on a given channel, it may not
  3736. * be able to associate or transmit any frames on that
  3737. * channel. There is no corresponding channel information for that
  3738. * entry.
  3739. *
  3740. *********************************************************************/
  3741. /* 2.4 GHz */
  3742. static const u8 iwl3945_eeprom_band_1[14] = {
  3743. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3744. };
  3745. /* 5.2 GHz bands */
  3746. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3747. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3748. };
  3749. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3750. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3751. };
  3752. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3753. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3754. };
  3755. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3756. 145, 149, 153, 157, 161, 165
  3757. };
  3758. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3759. int *eeprom_ch_count,
  3760. const struct iwl3945_eeprom_channel
  3761. **eeprom_ch_info,
  3762. const u8 **eeprom_ch_index)
  3763. {
  3764. switch (band) {
  3765. case 1: /* 2.4GHz band */
  3766. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3767. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3768. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3769. break;
  3770. case 2: /* 4.9GHz band */
  3771. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3772. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3773. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3774. break;
  3775. case 3: /* 5.2GHz band */
  3776. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3777. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3778. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3779. break;
  3780. case 4: /* 5.5GHz band */
  3781. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3782. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3783. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3784. break;
  3785. case 5: /* 5.7GHz band */
  3786. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3787. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3788. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3789. break;
  3790. default:
  3791. BUG();
  3792. return;
  3793. }
  3794. }
  3795. /**
  3796. * iwl3945_get_channel_info - Find driver's private channel info
  3797. *
  3798. * Based on band and channel number.
  3799. */
  3800. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3801. enum ieee80211_band band, u16 channel)
  3802. {
  3803. int i;
  3804. switch (band) {
  3805. case IEEE80211_BAND_5GHZ:
  3806. for (i = 14; i < priv->channel_count; i++) {
  3807. if (priv->channel_info[i].channel == channel)
  3808. return &priv->channel_info[i];
  3809. }
  3810. break;
  3811. case IEEE80211_BAND_2GHZ:
  3812. if (channel >= 1 && channel <= 14)
  3813. return &priv->channel_info[channel - 1];
  3814. break;
  3815. case IEEE80211_NUM_BANDS:
  3816. WARN_ON(1);
  3817. }
  3818. return NULL;
  3819. }
  3820. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3821. ? # x " " : "")
  3822. /**
  3823. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3824. */
  3825. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3826. {
  3827. int eeprom_ch_count = 0;
  3828. const u8 *eeprom_ch_index = NULL;
  3829. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  3830. int band, ch;
  3831. struct iwl3945_channel_info *ch_info;
  3832. if (priv->channel_count) {
  3833. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3834. return 0;
  3835. }
  3836. if (priv->eeprom.version < 0x2f) {
  3837. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3838. priv->eeprom.version);
  3839. return -EINVAL;
  3840. }
  3841. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3842. priv->channel_count =
  3843. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3844. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3845. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3846. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3847. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3848. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3849. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  3850. priv->channel_count, GFP_KERNEL);
  3851. if (!priv->channel_info) {
  3852. IWL_ERROR("Could not allocate channel_info\n");
  3853. priv->channel_count = 0;
  3854. return -ENOMEM;
  3855. }
  3856. ch_info = priv->channel_info;
  3857. /* Loop through the 5 EEPROM bands adding them in order to the
  3858. * channel map we maintain (that contains additional information than
  3859. * what just in the EEPROM) */
  3860. for (band = 1; band <= 5; band++) {
  3861. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3862. &eeprom_ch_info, &eeprom_ch_index);
  3863. /* Loop through each band adding each of the channels */
  3864. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3865. ch_info->channel = eeprom_ch_index[ch];
  3866. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3867. IEEE80211_BAND_5GHZ;
  3868. /* permanently store EEPROM's channel regulatory flags
  3869. * and max power in channel info database. */
  3870. ch_info->eeprom = eeprom_ch_info[ch];
  3871. /* Copy the run-time flags so they are there even on
  3872. * invalid channels */
  3873. ch_info->flags = eeprom_ch_info[ch].flags;
  3874. if (!(is_channel_valid(ch_info))) {
  3875. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3876. "No traffic\n",
  3877. ch_info->channel,
  3878. ch_info->flags,
  3879. is_channel_a_band(ch_info) ?
  3880. "5.2" : "2.4");
  3881. ch_info++;
  3882. continue;
  3883. }
  3884. /* Initialize regulatory-based run-time data */
  3885. ch_info->max_power_avg = ch_info->curr_txpow =
  3886. eeprom_ch_info[ch].max_power_avg;
  3887. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3888. ch_info->min_power = 0;
  3889. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3890. " %ddBm): Ad-Hoc %ssupported\n",
  3891. ch_info->channel,
  3892. is_channel_a_band(ch_info) ?
  3893. "5.2" : "2.4",
  3894. CHECK_AND_PRINT(VALID),
  3895. CHECK_AND_PRINT(IBSS),
  3896. CHECK_AND_PRINT(ACTIVE),
  3897. CHECK_AND_PRINT(RADAR),
  3898. CHECK_AND_PRINT(WIDE),
  3899. CHECK_AND_PRINT(DFS),
  3900. eeprom_ch_info[ch].flags,
  3901. eeprom_ch_info[ch].max_power_avg,
  3902. ((eeprom_ch_info[ch].
  3903. flags & EEPROM_CHANNEL_IBSS)
  3904. && !(eeprom_ch_info[ch].
  3905. flags & EEPROM_CHANNEL_RADAR))
  3906. ? "" : "not ");
  3907. /* Set the user_txpower_limit to the highest power
  3908. * supported by any channel */
  3909. if (eeprom_ch_info[ch].max_power_avg >
  3910. priv->user_txpower_limit)
  3911. priv->user_txpower_limit =
  3912. eeprom_ch_info[ch].max_power_avg;
  3913. ch_info++;
  3914. }
  3915. }
  3916. /* Set up txpower settings in driver for all channels */
  3917. if (iwl3945_txpower_set_from_eeprom(priv))
  3918. return -EIO;
  3919. return 0;
  3920. }
  3921. /*
  3922. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3923. */
  3924. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  3925. {
  3926. kfree(priv->channel_info);
  3927. priv->channel_count = 0;
  3928. }
  3929. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3930. * sending probe req. This should be set long enough to hear probe responses
  3931. * from more than one AP. */
  3932. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3933. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3934. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3935. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3936. /* For faster active scanning, scan will move to the next channel if fewer than
  3937. * PLCP_QUIET_THRESH packets are heard on this channel within
  3938. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3939. * time if it's a quiet channel (nothing responded to our probe, and there's
  3940. * no other traffic).
  3941. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3942. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3943. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3944. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3945. * Must be set longer than active dwell time.
  3946. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3947. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3948. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3949. #define IWL_PASSIVE_DWELL_BASE (100)
  3950. #define IWL_CHANNEL_TUNE_TIME 5
  3951. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3952. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  3953. enum ieee80211_band band,
  3954. u8 n_probes)
  3955. {
  3956. if (band == IEEE80211_BAND_5GHZ)
  3957. return IWL_ACTIVE_DWELL_TIME_52 +
  3958. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3959. else
  3960. return IWL_ACTIVE_DWELL_TIME_24 +
  3961. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3962. }
  3963. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  3964. enum ieee80211_band band)
  3965. {
  3966. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3967. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3968. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3969. if (iwl3945_is_associated(priv)) {
  3970. /* If we're associated, we clamp the maximum passive
  3971. * dwell time to be 98% of the beacon interval (minus
  3972. * 2 * channel tune time) */
  3973. passive = priv->beacon_int;
  3974. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3975. passive = IWL_PASSIVE_DWELL_BASE;
  3976. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3977. }
  3978. return passive;
  3979. }
  3980. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  3981. enum ieee80211_band band,
  3982. u8 is_active, u8 n_probes,
  3983. struct iwl3945_scan_channel *scan_ch)
  3984. {
  3985. const struct ieee80211_channel *channels = NULL;
  3986. const struct ieee80211_supported_band *sband;
  3987. const struct iwl3945_channel_info *ch_info;
  3988. u16 passive_dwell = 0;
  3989. u16 active_dwell = 0;
  3990. int added, i;
  3991. sband = iwl3945_get_band(priv, band);
  3992. if (!sband)
  3993. return 0;
  3994. channels = sband->channels;
  3995. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3996. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3997. if (passive_dwell <= active_dwell)
  3998. passive_dwell = active_dwell + 1;
  3999. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4000. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4001. continue;
  4002. scan_ch->channel = channels[i].hw_value;
  4003. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4004. if (!is_channel_valid(ch_info)) {
  4005. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4006. scan_ch->channel);
  4007. continue;
  4008. }
  4009. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4010. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4011. /* If passive , set up for auto-switch
  4012. * and use long active_dwell time.
  4013. */
  4014. if (!is_active || is_channel_passive(ch_info) ||
  4015. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  4016. scan_ch->type = 0; /* passive */
  4017. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  4018. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  4019. } else {
  4020. scan_ch->type = 1; /* active */
  4021. }
  4022. /* Set direct probe bits. These may be used both for active
  4023. * scan channels (probes gets sent right away),
  4024. * or for passive channels (probes get se sent only after
  4025. * hearing clear Rx packet).*/
  4026. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  4027. if (n_probes)
  4028. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4029. } else {
  4030. /* uCode v1 does not allow setting direct probe bits on
  4031. * passive channel. */
  4032. if ((scan_ch->type & 1) && n_probes)
  4033. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4034. }
  4035. /* Set txpower levels to defaults */
  4036. scan_ch->tpc.dsp_atten = 110;
  4037. /* scan_pwr_info->tpc.dsp_atten; */
  4038. /*scan_pwr_info->tpc.tx_gain; */
  4039. if (band == IEEE80211_BAND_5GHZ)
  4040. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4041. else {
  4042. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4043. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4044. * power level:
  4045. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4046. */
  4047. }
  4048. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4049. scan_ch->channel,
  4050. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4051. (scan_ch->type & 1) ?
  4052. active_dwell : passive_dwell);
  4053. scan_ch++;
  4054. added++;
  4055. }
  4056. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4057. return added;
  4058. }
  4059. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4060. struct ieee80211_rate *rates)
  4061. {
  4062. int i;
  4063. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4064. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4065. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4066. rates[i].hw_value_short = i;
  4067. rates[i].flags = 0;
  4068. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4069. /*
  4070. * If CCK != 1M then set short preamble rate flag.
  4071. */
  4072. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4073. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4074. }
  4075. }
  4076. }
  4077. /**
  4078. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4079. */
  4080. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4081. {
  4082. struct iwl3945_channel_info *ch;
  4083. struct ieee80211_supported_band *sband;
  4084. struct ieee80211_channel *channels;
  4085. struct ieee80211_channel *geo_ch;
  4086. struct ieee80211_rate *rates;
  4087. int i = 0;
  4088. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4089. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4090. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4091. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4092. return 0;
  4093. }
  4094. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4095. priv->channel_count, GFP_KERNEL);
  4096. if (!channels)
  4097. return -ENOMEM;
  4098. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4099. GFP_KERNEL);
  4100. if (!rates) {
  4101. kfree(channels);
  4102. return -ENOMEM;
  4103. }
  4104. /* 5.2GHz channels start after the 2.4GHz channels */
  4105. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4106. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4107. /* just OFDM */
  4108. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4109. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4110. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4111. sband->channels = channels;
  4112. /* OFDM & CCK */
  4113. sband->bitrates = rates;
  4114. sband->n_bitrates = IWL_RATE_COUNT;
  4115. priv->ieee_channels = channels;
  4116. priv->ieee_rates = rates;
  4117. iwl3945_init_hw_rates(priv, rates);
  4118. for (i = 0; i < priv->channel_count; i++) {
  4119. ch = &priv->channel_info[i];
  4120. /* FIXME: might be removed if scan is OK*/
  4121. if (!is_channel_valid(ch))
  4122. continue;
  4123. if (is_channel_a_band(ch))
  4124. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4125. else
  4126. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4127. geo_ch = &sband->channels[sband->n_channels++];
  4128. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4129. geo_ch->max_power = ch->max_power_avg;
  4130. geo_ch->max_antenna_gain = 0xff;
  4131. geo_ch->hw_value = ch->channel;
  4132. if (is_channel_valid(ch)) {
  4133. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4134. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4135. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4136. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4137. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4138. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4139. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4140. priv->max_channel_txpower_limit =
  4141. ch->max_power_avg;
  4142. } else {
  4143. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4144. }
  4145. /* Save flags for reg domain usage */
  4146. geo_ch->orig_flags = geo_ch->flags;
  4147. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4148. ch->channel, geo_ch->center_freq,
  4149. is_channel_a_band(ch) ? "5.2" : "2.4",
  4150. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4151. "restricted" : "valid",
  4152. geo_ch->flags);
  4153. }
  4154. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4155. priv->cfg->sku & IWL_SKU_A) {
  4156. printk(KERN_INFO DRV_NAME
  4157. ": Incorrectly detected BG card as ABG. Please send "
  4158. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4159. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4160. priv->cfg->sku &= ~IWL_SKU_A;
  4161. }
  4162. printk(KERN_INFO DRV_NAME
  4163. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4164. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4165. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4166. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4167. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4168. &priv->bands[IEEE80211_BAND_2GHZ];
  4169. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4170. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4171. &priv->bands[IEEE80211_BAND_5GHZ];
  4172. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4173. return 0;
  4174. }
  4175. /*
  4176. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4177. */
  4178. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4179. {
  4180. kfree(priv->ieee_channels);
  4181. kfree(priv->ieee_rates);
  4182. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4183. }
  4184. /******************************************************************************
  4185. *
  4186. * uCode download functions
  4187. *
  4188. ******************************************************************************/
  4189. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4190. {
  4191. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4192. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4193. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4194. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4195. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4196. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4197. }
  4198. /**
  4199. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4200. * looking at all data.
  4201. */
  4202. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4203. {
  4204. u32 val;
  4205. u32 save_len = len;
  4206. int rc = 0;
  4207. u32 errcnt;
  4208. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4209. rc = iwl3945_grab_nic_access(priv);
  4210. if (rc)
  4211. return rc;
  4212. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4213. errcnt = 0;
  4214. for (; len > 0; len -= sizeof(u32), image++) {
  4215. /* read data comes through single port, auto-incr addr */
  4216. /* NOTE: Use the debugless read so we don't flood kernel log
  4217. * if IWL_DL_IO is set */
  4218. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4219. if (val != le32_to_cpu(*image)) {
  4220. IWL_ERROR("uCode INST section is invalid at "
  4221. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4222. save_len - len, val, le32_to_cpu(*image));
  4223. rc = -EIO;
  4224. errcnt++;
  4225. if (errcnt >= 20)
  4226. break;
  4227. }
  4228. }
  4229. iwl3945_release_nic_access(priv);
  4230. if (!errcnt)
  4231. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4232. return rc;
  4233. }
  4234. /**
  4235. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4236. * using sample data 100 bytes apart. If these sample points are good,
  4237. * it's a pretty good bet that everything between them is good, too.
  4238. */
  4239. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4240. {
  4241. u32 val;
  4242. int rc = 0;
  4243. u32 errcnt = 0;
  4244. u32 i;
  4245. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4246. rc = iwl3945_grab_nic_access(priv);
  4247. if (rc)
  4248. return rc;
  4249. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4250. /* read data comes through single port, auto-incr addr */
  4251. /* NOTE: Use the debugless read so we don't flood kernel log
  4252. * if IWL_DL_IO is set */
  4253. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4254. i + RTC_INST_LOWER_BOUND);
  4255. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4256. if (val != le32_to_cpu(*image)) {
  4257. #if 0 /* Enable this if you want to see details */
  4258. IWL_ERROR("uCode INST section is invalid at "
  4259. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4260. i, val, *image);
  4261. #endif
  4262. rc = -EIO;
  4263. errcnt++;
  4264. if (errcnt >= 3)
  4265. break;
  4266. }
  4267. }
  4268. iwl3945_release_nic_access(priv);
  4269. return rc;
  4270. }
  4271. /**
  4272. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4273. * and verify its contents
  4274. */
  4275. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4276. {
  4277. __le32 *image;
  4278. u32 len;
  4279. int rc = 0;
  4280. /* Try bootstrap */
  4281. image = (__le32 *)priv->ucode_boot.v_addr;
  4282. len = priv->ucode_boot.len;
  4283. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4284. if (rc == 0) {
  4285. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4286. return 0;
  4287. }
  4288. /* Try initialize */
  4289. image = (__le32 *)priv->ucode_init.v_addr;
  4290. len = priv->ucode_init.len;
  4291. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4292. if (rc == 0) {
  4293. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4294. return 0;
  4295. }
  4296. /* Try runtime/protocol */
  4297. image = (__le32 *)priv->ucode_code.v_addr;
  4298. len = priv->ucode_code.len;
  4299. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4300. if (rc == 0) {
  4301. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4302. return 0;
  4303. }
  4304. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4305. /* Since nothing seems to match, show first several data entries in
  4306. * instruction SRAM, so maybe visual inspection will give a clue.
  4307. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4308. image = (__le32 *)priv->ucode_boot.v_addr;
  4309. len = priv->ucode_boot.len;
  4310. rc = iwl3945_verify_inst_full(priv, image, len);
  4311. return rc;
  4312. }
  4313. /* check contents of special bootstrap uCode SRAM */
  4314. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4315. {
  4316. __le32 *image = priv->ucode_boot.v_addr;
  4317. u32 len = priv->ucode_boot.len;
  4318. u32 reg;
  4319. u32 val;
  4320. IWL_DEBUG_INFO("Begin verify bsm\n");
  4321. /* verify BSM SRAM contents */
  4322. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4323. for (reg = BSM_SRAM_LOWER_BOUND;
  4324. reg < BSM_SRAM_LOWER_BOUND + len;
  4325. reg += sizeof(u32), image++) {
  4326. val = iwl3945_read_prph(priv, reg);
  4327. if (val != le32_to_cpu(*image)) {
  4328. IWL_ERROR("BSM uCode verification failed at "
  4329. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4330. BSM_SRAM_LOWER_BOUND,
  4331. reg - BSM_SRAM_LOWER_BOUND, len,
  4332. val, le32_to_cpu(*image));
  4333. return -EIO;
  4334. }
  4335. }
  4336. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4337. return 0;
  4338. }
  4339. /**
  4340. * iwl3945_load_bsm - Load bootstrap instructions
  4341. *
  4342. * BSM operation:
  4343. *
  4344. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4345. * in special SRAM that does not power down during RFKILL. When powering back
  4346. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4347. * the bootstrap program into the on-board processor, and starts it.
  4348. *
  4349. * The bootstrap program loads (via DMA) instructions and data for a new
  4350. * program from host DRAM locations indicated by the host driver in the
  4351. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4352. * automatically.
  4353. *
  4354. * When initializing the NIC, the host driver points the BSM to the
  4355. * "initialize" uCode image. This uCode sets up some internal data, then
  4356. * notifies host via "initialize alive" that it is complete.
  4357. *
  4358. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4359. * normal runtime uCode instructions and a backup uCode data cache buffer
  4360. * (filled initially with starting data values for the on-board processor),
  4361. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4362. * which begins normal operation.
  4363. *
  4364. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4365. * the backup data cache in DRAM before SRAM is powered down.
  4366. *
  4367. * When powering back up, the BSM loads the bootstrap program. This reloads
  4368. * the runtime uCode instructions and the backup data cache into SRAM,
  4369. * and re-launches the runtime uCode from where it left off.
  4370. */
  4371. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4372. {
  4373. __le32 *image = priv->ucode_boot.v_addr;
  4374. u32 len = priv->ucode_boot.len;
  4375. dma_addr_t pinst;
  4376. dma_addr_t pdata;
  4377. u32 inst_len;
  4378. u32 data_len;
  4379. int rc;
  4380. int i;
  4381. u32 done;
  4382. u32 reg_offset;
  4383. IWL_DEBUG_INFO("Begin load bsm\n");
  4384. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4385. if (len > IWL_MAX_BSM_SIZE)
  4386. return -EINVAL;
  4387. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4388. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4389. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4390. * after the "initialize" uCode has run, to point to
  4391. * runtime/protocol instructions and backup data cache. */
  4392. pinst = priv->ucode_init.p_addr;
  4393. pdata = priv->ucode_init_data.p_addr;
  4394. inst_len = priv->ucode_init.len;
  4395. data_len = priv->ucode_init_data.len;
  4396. rc = iwl3945_grab_nic_access(priv);
  4397. if (rc)
  4398. return rc;
  4399. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4400. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4401. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4402. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4403. /* Fill BSM memory with bootstrap instructions */
  4404. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4405. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4406. reg_offset += sizeof(u32), image++)
  4407. _iwl3945_write_prph(priv, reg_offset,
  4408. le32_to_cpu(*image));
  4409. rc = iwl3945_verify_bsm(priv);
  4410. if (rc) {
  4411. iwl3945_release_nic_access(priv);
  4412. return rc;
  4413. }
  4414. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4415. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4416. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4417. RTC_INST_LOWER_BOUND);
  4418. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4419. /* Load bootstrap code into instruction SRAM now,
  4420. * to prepare to load "initialize" uCode */
  4421. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4422. BSM_WR_CTRL_REG_BIT_START);
  4423. /* Wait for load of bootstrap uCode to finish */
  4424. for (i = 0; i < 100; i++) {
  4425. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4426. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4427. break;
  4428. udelay(10);
  4429. }
  4430. if (i < 100)
  4431. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4432. else {
  4433. IWL_ERROR("BSM write did not complete!\n");
  4434. return -EIO;
  4435. }
  4436. /* Enable future boot loads whenever power management unit triggers it
  4437. * (e.g. when powering back up after power-save shutdown) */
  4438. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4439. BSM_WR_CTRL_REG_BIT_START_EN);
  4440. iwl3945_release_nic_access(priv);
  4441. return 0;
  4442. }
  4443. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4444. {
  4445. /* Remove all resets to allow NIC to operate */
  4446. iwl3945_write32(priv, CSR_RESET, 0);
  4447. }
  4448. /**
  4449. * iwl3945_read_ucode - Read uCode images from disk file.
  4450. *
  4451. * Copy into buffers for card to fetch via bus-mastering
  4452. */
  4453. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4454. {
  4455. struct iwl3945_ucode *ucode;
  4456. int ret = -EINVAL, index;
  4457. const struct firmware *ucode_raw;
  4458. /* firmware file name contains uCode/driver compatibility version */
  4459. const char *name_pre = priv->cfg->fw_name_pre;
  4460. const unsigned int api_max = priv->cfg->ucode_api_max;
  4461. const unsigned int api_min = priv->cfg->ucode_api_min;
  4462. char buf[25];
  4463. u8 *src;
  4464. size_t len;
  4465. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4466. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4467. * request_firmware() is synchronous, file is in memory on return. */
  4468. for (index = api_max; index >= api_min; index--) {
  4469. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4470. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4471. if (ret < 0) {
  4472. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4473. buf, ret);
  4474. if (ret == -ENOENT)
  4475. continue;
  4476. else
  4477. goto error;
  4478. } else {
  4479. if (index < api_max)
  4480. IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
  4481. buf, api_max);
  4482. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4483. buf, ucode_raw->size);
  4484. break;
  4485. }
  4486. }
  4487. if (ret < 0)
  4488. goto error;
  4489. /* Make sure that we got at least our header! */
  4490. if (ucode_raw->size < sizeof(*ucode)) {
  4491. IWL_ERROR("File size way too small!\n");
  4492. ret = -EINVAL;
  4493. goto err_release;
  4494. }
  4495. /* Data from ucode file: header followed by uCode images */
  4496. ucode = (void *)ucode_raw->data;
  4497. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4498. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4499. inst_size = le32_to_cpu(ucode->inst_size);
  4500. data_size = le32_to_cpu(ucode->data_size);
  4501. init_size = le32_to_cpu(ucode->init_size);
  4502. init_data_size = le32_to_cpu(ucode->init_data_size);
  4503. boot_size = le32_to_cpu(ucode->boot_size);
  4504. /* api_ver should match the api version forming part of the
  4505. * firmware filename ... but we don't check for that and only rely
  4506. * on the API version read from firware header from here on forward */
  4507. if (api_ver < api_min || api_ver > api_max) {
  4508. IWL_ERROR("Driver unable to support your firmware API. "
  4509. "Driver supports v%u, firmware is v%u.\n",
  4510. api_max, api_ver);
  4511. priv->ucode_ver = 0;
  4512. ret = -EINVAL;
  4513. goto err_release;
  4514. }
  4515. if (api_ver != api_max)
  4516. IWL_ERROR("Firmware has old API version. Expected %u, "
  4517. "got %u. New firmware can be obtained "
  4518. "from http://www.intellinuxwireless.org.\n",
  4519. api_max, api_ver);
  4520. printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n",
  4521. IWL_UCODE_MAJOR(priv->ucode_ver),
  4522. IWL_UCODE_MINOR(priv->ucode_ver),
  4523. IWL_UCODE_API(priv->ucode_ver),
  4524. IWL_UCODE_SERIAL(priv->ucode_ver));
  4525. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4526. priv->ucode_ver);
  4527. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4528. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4529. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4530. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4531. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4532. /* Verify size of file vs. image size info in file's header */
  4533. if (ucode_raw->size < sizeof(*ucode) +
  4534. inst_size + data_size + init_size +
  4535. init_data_size + boot_size) {
  4536. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4537. (int)ucode_raw->size);
  4538. ret = -EINVAL;
  4539. goto err_release;
  4540. }
  4541. /* Verify that uCode images will fit in card's SRAM */
  4542. if (inst_size > IWL_MAX_INST_SIZE) {
  4543. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4544. inst_size);
  4545. ret = -EINVAL;
  4546. goto err_release;
  4547. }
  4548. if (data_size > IWL_MAX_DATA_SIZE) {
  4549. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4550. data_size);
  4551. ret = -EINVAL;
  4552. goto err_release;
  4553. }
  4554. if (init_size > IWL_MAX_INST_SIZE) {
  4555. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4556. init_size);
  4557. ret = -EINVAL;
  4558. goto err_release;
  4559. }
  4560. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4561. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4562. init_data_size);
  4563. ret = -EINVAL;
  4564. goto err_release;
  4565. }
  4566. if (boot_size > IWL_MAX_BSM_SIZE) {
  4567. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4568. boot_size);
  4569. ret = -EINVAL;
  4570. goto err_release;
  4571. }
  4572. /* Allocate ucode buffers for card's bus-master loading ... */
  4573. /* Runtime instructions and 2 copies of data:
  4574. * 1) unmodified from disk
  4575. * 2) backup cache for save/restore during power-downs */
  4576. priv->ucode_code.len = inst_size;
  4577. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4578. priv->ucode_data.len = data_size;
  4579. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4580. priv->ucode_data_backup.len = data_size;
  4581. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4582. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4583. !priv->ucode_data_backup.v_addr)
  4584. goto err_pci_alloc;
  4585. /* Initialization instructions and data */
  4586. if (init_size && init_data_size) {
  4587. priv->ucode_init.len = init_size;
  4588. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4589. priv->ucode_init_data.len = init_data_size;
  4590. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4591. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4592. goto err_pci_alloc;
  4593. }
  4594. /* Bootstrap (instructions only, no data) */
  4595. if (boot_size) {
  4596. priv->ucode_boot.len = boot_size;
  4597. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4598. if (!priv->ucode_boot.v_addr)
  4599. goto err_pci_alloc;
  4600. }
  4601. /* Copy images into buffers for card's bus-master reads ... */
  4602. /* Runtime instructions (first block of data in file) */
  4603. src = &ucode->data[0];
  4604. len = priv->ucode_code.len;
  4605. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4606. memcpy(priv->ucode_code.v_addr, src, len);
  4607. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4608. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4609. /* Runtime data (2nd block)
  4610. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4611. src = &ucode->data[inst_size];
  4612. len = priv->ucode_data.len;
  4613. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4614. memcpy(priv->ucode_data.v_addr, src, len);
  4615. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4616. /* Initialization instructions (3rd block) */
  4617. if (init_size) {
  4618. src = &ucode->data[inst_size + data_size];
  4619. len = priv->ucode_init.len;
  4620. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4621. len);
  4622. memcpy(priv->ucode_init.v_addr, src, len);
  4623. }
  4624. /* Initialization data (4th block) */
  4625. if (init_data_size) {
  4626. src = &ucode->data[inst_size + data_size + init_size];
  4627. len = priv->ucode_init_data.len;
  4628. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4629. (int)len);
  4630. memcpy(priv->ucode_init_data.v_addr, src, len);
  4631. }
  4632. /* Bootstrap instructions (5th block) */
  4633. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4634. len = priv->ucode_boot.len;
  4635. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4636. (int)len);
  4637. memcpy(priv->ucode_boot.v_addr, src, len);
  4638. /* We have our copies now, allow OS release its copies */
  4639. release_firmware(ucode_raw);
  4640. return 0;
  4641. err_pci_alloc:
  4642. IWL_ERROR("failed to allocate pci memory\n");
  4643. ret = -ENOMEM;
  4644. iwl3945_dealloc_ucode_pci(priv);
  4645. err_release:
  4646. release_firmware(ucode_raw);
  4647. error:
  4648. return ret;
  4649. }
  4650. /**
  4651. * iwl3945_set_ucode_ptrs - Set uCode address location
  4652. *
  4653. * Tell initialization uCode where to find runtime uCode.
  4654. *
  4655. * BSM registers initially contain pointers to initialization uCode.
  4656. * We need to replace them to load runtime uCode inst and data,
  4657. * and to save runtime data when powering down.
  4658. */
  4659. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4660. {
  4661. dma_addr_t pinst;
  4662. dma_addr_t pdata;
  4663. int rc = 0;
  4664. unsigned long flags;
  4665. /* bits 31:0 for 3945 */
  4666. pinst = priv->ucode_code.p_addr;
  4667. pdata = priv->ucode_data_backup.p_addr;
  4668. spin_lock_irqsave(&priv->lock, flags);
  4669. rc = iwl3945_grab_nic_access(priv);
  4670. if (rc) {
  4671. spin_unlock_irqrestore(&priv->lock, flags);
  4672. return rc;
  4673. }
  4674. /* Tell bootstrap uCode where to find image to load */
  4675. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4676. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4677. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4678. priv->ucode_data.len);
  4679. /* Inst byte count must be last to set up, bit 31 signals uCode
  4680. * that all new ptr/size info is in place */
  4681. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4682. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4683. iwl3945_release_nic_access(priv);
  4684. spin_unlock_irqrestore(&priv->lock, flags);
  4685. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4686. return rc;
  4687. }
  4688. /**
  4689. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4690. *
  4691. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4692. *
  4693. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4694. */
  4695. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4696. {
  4697. /* Check alive response for "valid" sign from uCode */
  4698. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4699. /* We had an error bringing up the hardware, so take it
  4700. * all the way back down so we can try again */
  4701. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4702. goto restart;
  4703. }
  4704. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4705. * This is a paranoid check, because we would not have gotten the
  4706. * "initialize" alive if code weren't properly loaded. */
  4707. if (iwl3945_verify_ucode(priv)) {
  4708. /* Runtime instruction load was bad;
  4709. * take it all the way back down so we can try again */
  4710. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4711. goto restart;
  4712. }
  4713. /* Send pointers to protocol/runtime uCode image ... init code will
  4714. * load and launch runtime uCode, which will send us another "Alive"
  4715. * notification. */
  4716. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4717. if (iwl3945_set_ucode_ptrs(priv)) {
  4718. /* Runtime instruction load won't happen;
  4719. * take it all the way back down so we can try again */
  4720. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4721. goto restart;
  4722. }
  4723. return;
  4724. restart:
  4725. queue_work(priv->workqueue, &priv->restart);
  4726. }
  4727. /* temporary */
  4728. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4729. struct sk_buff *skb);
  4730. /**
  4731. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4732. * from protocol/runtime uCode (initialization uCode's
  4733. * Alive gets handled by iwl3945_init_alive_start()).
  4734. */
  4735. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4736. {
  4737. int rc = 0;
  4738. int thermal_spin = 0;
  4739. u32 rfkill;
  4740. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4741. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4742. /* We had an error bringing up the hardware, so take it
  4743. * all the way back down so we can try again */
  4744. IWL_DEBUG_INFO("Alive failed.\n");
  4745. goto restart;
  4746. }
  4747. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4748. * This is a paranoid check, because we would not have gotten the
  4749. * "runtime" alive if code weren't properly loaded. */
  4750. if (iwl3945_verify_ucode(priv)) {
  4751. /* Runtime instruction load was bad;
  4752. * take it all the way back down so we can try again */
  4753. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4754. goto restart;
  4755. }
  4756. iwl3945_clear_stations_table(priv);
  4757. rc = iwl3945_grab_nic_access(priv);
  4758. if (rc) {
  4759. IWL_WARNING("Can not read RFKILL status from adapter\n");
  4760. return;
  4761. }
  4762. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4763. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4764. iwl3945_release_nic_access(priv);
  4765. if (rfkill & 0x1) {
  4766. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4767. /* if RFKILL is not on, then wait for thermal
  4768. * sensor in adapter to kick in */
  4769. while (iwl3945_hw_get_temperature(priv) == 0) {
  4770. thermal_spin++;
  4771. udelay(10);
  4772. }
  4773. if (thermal_spin)
  4774. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4775. thermal_spin * 10);
  4776. } else
  4777. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4778. /* After the ALIVE response, we can send commands to 3945 uCode */
  4779. set_bit(STATUS_ALIVE, &priv->status);
  4780. /* Clear out the uCode error bit if it is set */
  4781. clear_bit(STATUS_FW_ERROR, &priv->status);
  4782. if (iwl3945_is_rfkill(priv))
  4783. return;
  4784. ieee80211_wake_queues(priv->hw);
  4785. priv->active_rate = priv->rates_mask;
  4786. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4787. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4788. if (iwl3945_is_associated(priv)) {
  4789. struct iwl3945_rxon_cmd *active_rxon =
  4790. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4791. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4792. sizeof(priv->staging_rxon));
  4793. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4794. } else {
  4795. /* Initialize our rx_config data */
  4796. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4797. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4798. }
  4799. /* Configure Bluetooth device coexistence support */
  4800. iwl3945_send_bt_config(priv);
  4801. /* Configure the adapter for unassociated operation */
  4802. iwl3945_commit_rxon(priv);
  4803. iwl3945_reg_txpower_periodic(priv);
  4804. iwl3945_led_register(priv);
  4805. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4806. set_bit(STATUS_READY, &priv->status);
  4807. wake_up_interruptible(&priv->wait_command_queue);
  4808. if (priv->error_recovering)
  4809. iwl3945_error_recovery(priv);
  4810. /* reassociate for ADHOC mode */
  4811. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4812. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4813. priv->vif);
  4814. if (beacon)
  4815. iwl3945_mac_beacon_update(priv->hw, beacon);
  4816. }
  4817. return;
  4818. restart:
  4819. queue_work(priv->workqueue, &priv->restart);
  4820. }
  4821. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4822. static void __iwl3945_down(struct iwl3945_priv *priv)
  4823. {
  4824. unsigned long flags;
  4825. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4826. struct ieee80211_conf *conf = NULL;
  4827. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4828. conf = ieee80211_get_hw_conf(priv->hw);
  4829. if (!exit_pending)
  4830. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4831. iwl3945_led_unregister(priv);
  4832. iwl3945_clear_stations_table(priv);
  4833. /* Unblock any waiting calls */
  4834. wake_up_interruptible_all(&priv->wait_command_queue);
  4835. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4836. * exiting the module */
  4837. if (!exit_pending)
  4838. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4839. /* stop and reset the on-board processor */
  4840. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4841. /* tell the device to stop sending interrupts */
  4842. spin_lock_irqsave(&priv->lock, flags);
  4843. iwl3945_disable_interrupts(priv);
  4844. spin_unlock_irqrestore(&priv->lock, flags);
  4845. iwl_synchronize_irq(priv);
  4846. if (priv->mac80211_registered)
  4847. ieee80211_stop_queues(priv->hw);
  4848. /* If we have not previously called iwl3945_init() then
  4849. * clear all bits but the RF Kill and SUSPEND bits and return */
  4850. if (!iwl3945_is_init(priv)) {
  4851. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4852. STATUS_RF_KILL_HW |
  4853. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4854. STATUS_RF_KILL_SW |
  4855. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4856. STATUS_GEO_CONFIGURED |
  4857. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4858. STATUS_IN_SUSPEND |
  4859. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4860. STATUS_EXIT_PENDING;
  4861. goto exit;
  4862. }
  4863. /* ...otherwise clear out all the status bits but the RF Kill and
  4864. * SUSPEND bits and continue taking the NIC down. */
  4865. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4866. STATUS_RF_KILL_HW |
  4867. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4868. STATUS_RF_KILL_SW |
  4869. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4870. STATUS_GEO_CONFIGURED |
  4871. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4872. STATUS_IN_SUSPEND |
  4873. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4874. STATUS_FW_ERROR |
  4875. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4876. STATUS_EXIT_PENDING;
  4877. spin_lock_irqsave(&priv->lock, flags);
  4878. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4879. spin_unlock_irqrestore(&priv->lock, flags);
  4880. iwl3945_hw_txq_ctx_stop(priv);
  4881. iwl3945_hw_rxq_stop(priv);
  4882. spin_lock_irqsave(&priv->lock, flags);
  4883. if (!iwl3945_grab_nic_access(priv)) {
  4884. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4885. APMG_CLK_VAL_DMA_CLK_RQT);
  4886. iwl3945_release_nic_access(priv);
  4887. }
  4888. spin_unlock_irqrestore(&priv->lock, flags);
  4889. udelay(5);
  4890. iwl3945_hw_nic_stop_master(priv);
  4891. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4892. iwl3945_hw_nic_reset(priv);
  4893. exit:
  4894. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4895. if (priv->ibss_beacon)
  4896. dev_kfree_skb(priv->ibss_beacon);
  4897. priv->ibss_beacon = NULL;
  4898. /* clear out any free frames */
  4899. iwl3945_clear_free_frames(priv);
  4900. }
  4901. static void iwl3945_down(struct iwl3945_priv *priv)
  4902. {
  4903. mutex_lock(&priv->mutex);
  4904. __iwl3945_down(priv);
  4905. mutex_unlock(&priv->mutex);
  4906. iwl3945_cancel_deferred_work(priv);
  4907. }
  4908. #define MAX_HW_RESTARTS 5
  4909. static int __iwl3945_up(struct iwl3945_priv *priv)
  4910. {
  4911. int rc, i;
  4912. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4913. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4914. return -EIO;
  4915. }
  4916. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4917. IWL_WARNING("Radio disabled by SW RF kill (module "
  4918. "parameter)\n");
  4919. return -ENODEV;
  4920. }
  4921. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4922. IWL_ERROR("ucode not available for device bring up\n");
  4923. return -EIO;
  4924. }
  4925. /* If platform's RF_KILL switch is NOT set to KILL */
  4926. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  4927. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4928. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4929. else {
  4930. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4931. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4932. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4933. return -ENODEV;
  4934. }
  4935. }
  4936. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4937. rc = iwl3945_hw_nic_init(priv);
  4938. if (rc) {
  4939. IWL_ERROR("Unable to int nic\n");
  4940. return rc;
  4941. }
  4942. /* make sure rfkill handshake bits are cleared */
  4943. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4944. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4945. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4946. /* clear (again), then enable host interrupts */
  4947. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4948. iwl3945_enable_interrupts(priv);
  4949. /* really make sure rfkill handshake bits are cleared */
  4950. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4951. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4952. /* Copy original ucode data image from disk into backup cache.
  4953. * This will be used to initialize the on-board processor's
  4954. * data SRAM for a clean start when the runtime program first loads. */
  4955. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4956. priv->ucode_data.len);
  4957. /* We return success when we resume from suspend and rf_kill is on. */
  4958. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4959. return 0;
  4960. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4961. iwl3945_clear_stations_table(priv);
  4962. /* load bootstrap state machine,
  4963. * load bootstrap program into processor's memory,
  4964. * prepare to load the "initialize" uCode */
  4965. rc = iwl3945_load_bsm(priv);
  4966. if (rc) {
  4967. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4968. continue;
  4969. }
  4970. /* start card; "initialize" will load runtime ucode */
  4971. iwl3945_nic_start(priv);
  4972. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4973. return 0;
  4974. }
  4975. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4976. __iwl3945_down(priv);
  4977. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4978. /* tried to restart and config the device for as long as our
  4979. * patience could withstand */
  4980. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4981. return -EIO;
  4982. }
  4983. /*****************************************************************************
  4984. *
  4985. * Workqueue callbacks
  4986. *
  4987. *****************************************************************************/
  4988. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4989. {
  4990. struct iwl3945_priv *priv =
  4991. container_of(data, struct iwl3945_priv, init_alive_start.work);
  4992. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4993. return;
  4994. mutex_lock(&priv->mutex);
  4995. iwl3945_init_alive_start(priv);
  4996. mutex_unlock(&priv->mutex);
  4997. }
  4998. static void iwl3945_bg_alive_start(struct work_struct *data)
  4999. {
  5000. struct iwl3945_priv *priv =
  5001. container_of(data, struct iwl3945_priv, alive_start.work);
  5002. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5003. return;
  5004. mutex_lock(&priv->mutex);
  5005. iwl3945_alive_start(priv);
  5006. mutex_unlock(&priv->mutex);
  5007. }
  5008. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5009. {
  5010. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5011. wake_up_interruptible(&priv->wait_command_queue);
  5012. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5013. return;
  5014. mutex_lock(&priv->mutex);
  5015. if (!iwl3945_is_rfkill(priv)) {
  5016. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5017. "HW and/or SW RF Kill no longer active, restarting "
  5018. "device\n");
  5019. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5020. queue_work(priv->workqueue, &priv->restart);
  5021. } else {
  5022. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5023. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5024. "disabled by SW switch\n");
  5025. else
  5026. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5027. "Kill switch must be turned off for "
  5028. "wireless networking to work.\n");
  5029. }
  5030. mutex_unlock(&priv->mutex);
  5031. iwl3945_rfkill_set_hw_state(priv);
  5032. }
  5033. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5034. static void iwl3945_bg_scan_check(struct work_struct *data)
  5035. {
  5036. struct iwl3945_priv *priv =
  5037. container_of(data, struct iwl3945_priv, scan_check.work);
  5038. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5039. return;
  5040. mutex_lock(&priv->mutex);
  5041. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5042. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5043. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5044. "Scan completion watchdog resetting adapter (%dms)\n",
  5045. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5046. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5047. iwl3945_send_scan_abort(priv);
  5048. }
  5049. mutex_unlock(&priv->mutex);
  5050. }
  5051. static void iwl3945_bg_request_scan(struct work_struct *data)
  5052. {
  5053. struct iwl3945_priv *priv =
  5054. container_of(data, struct iwl3945_priv, request_scan);
  5055. struct iwl3945_host_cmd cmd = {
  5056. .id = REPLY_SCAN_CMD,
  5057. .len = sizeof(struct iwl3945_scan_cmd),
  5058. .meta.flags = CMD_SIZE_HUGE,
  5059. };
  5060. int rc = 0;
  5061. struct iwl3945_scan_cmd *scan;
  5062. struct ieee80211_conf *conf = NULL;
  5063. u8 n_probes = 2;
  5064. enum ieee80211_band band;
  5065. DECLARE_SSID_BUF(ssid);
  5066. conf = ieee80211_get_hw_conf(priv->hw);
  5067. mutex_lock(&priv->mutex);
  5068. if (!iwl3945_is_ready(priv)) {
  5069. IWL_WARNING("request scan called when driver not ready.\n");
  5070. goto done;
  5071. }
  5072. /* Make sure the scan wasn't canceled before this queued work
  5073. * was given the chance to run... */
  5074. if (!test_bit(STATUS_SCANNING, &priv->status))
  5075. goto done;
  5076. /* This should never be called or scheduled if there is currently
  5077. * a scan active in the hardware. */
  5078. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5079. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5080. "Ignoring second request.\n");
  5081. rc = -EIO;
  5082. goto done;
  5083. }
  5084. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5085. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5086. goto done;
  5087. }
  5088. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5089. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5090. goto done;
  5091. }
  5092. if (iwl3945_is_rfkill(priv)) {
  5093. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5094. goto done;
  5095. }
  5096. if (!test_bit(STATUS_READY, &priv->status)) {
  5097. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5098. goto done;
  5099. }
  5100. if (!priv->scan_bands) {
  5101. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5102. goto done;
  5103. }
  5104. if (!priv->scan) {
  5105. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5106. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5107. if (!priv->scan) {
  5108. rc = -ENOMEM;
  5109. goto done;
  5110. }
  5111. }
  5112. scan = priv->scan;
  5113. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5114. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5115. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5116. if (iwl3945_is_associated(priv)) {
  5117. u16 interval = 0;
  5118. u32 extra;
  5119. u32 suspend_time = 100;
  5120. u32 scan_suspend_time = 100;
  5121. unsigned long flags;
  5122. IWL_DEBUG_INFO("Scanning while associated...\n");
  5123. spin_lock_irqsave(&priv->lock, flags);
  5124. interval = priv->beacon_int;
  5125. spin_unlock_irqrestore(&priv->lock, flags);
  5126. scan->suspend_time = 0;
  5127. scan->max_out_time = cpu_to_le32(200 * 1024);
  5128. if (!interval)
  5129. interval = suspend_time;
  5130. /*
  5131. * suspend time format:
  5132. * 0-19: beacon interval in usec (time before exec.)
  5133. * 20-23: 0
  5134. * 24-31: number of beacons (suspend between channels)
  5135. */
  5136. extra = (suspend_time / interval) << 24;
  5137. scan_suspend_time = 0xFF0FFFFF &
  5138. (extra | ((suspend_time % interval) * 1024));
  5139. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5140. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5141. scan_suspend_time, interval);
  5142. }
  5143. /* We should add the ability for user to lock to PASSIVE ONLY */
  5144. if (priv->one_direct_scan) {
  5145. IWL_DEBUG_SCAN
  5146. ("Kicking off one direct scan for '%s'\n",
  5147. print_ssid(ssid, priv->direct_ssid,
  5148. priv->direct_ssid_len));
  5149. scan->direct_scan[0].id = WLAN_EID_SSID;
  5150. scan->direct_scan[0].len = priv->direct_ssid_len;
  5151. memcpy(scan->direct_scan[0].ssid,
  5152. priv->direct_ssid, priv->direct_ssid_len);
  5153. n_probes++;
  5154. } else
  5155. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5156. /* We don't build a direct scan probe request; the uCode will do
  5157. * that based on the direct_mask added to each channel entry */
  5158. scan->tx_cmd.len = cpu_to_le16(
  5159. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5160. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  5161. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5162. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5163. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5164. /* flags + rate selection */
  5165. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5166. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5167. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5168. scan->good_CRC_th = 0;
  5169. band = IEEE80211_BAND_2GHZ;
  5170. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5171. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5172. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5173. band = IEEE80211_BAND_5GHZ;
  5174. } else {
  5175. IWL_WARNING("Invalid scan band count\n");
  5176. goto done;
  5177. }
  5178. /* select Rx antennas */
  5179. scan->flags |= iwl3945_get_antenna_flags(priv);
  5180. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  5181. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5182. scan->channel_count =
  5183. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  5184. n_probes,
  5185. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5186. if (scan->channel_count == 0) {
  5187. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  5188. goto done;
  5189. }
  5190. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5191. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5192. cmd.data = scan;
  5193. scan->len = cpu_to_le16(cmd.len);
  5194. set_bit(STATUS_SCAN_HW, &priv->status);
  5195. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5196. if (rc)
  5197. goto done;
  5198. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5199. IWL_SCAN_CHECK_WATCHDOG);
  5200. mutex_unlock(&priv->mutex);
  5201. return;
  5202. done:
  5203. /* can not perform scan make sure we clear scanning
  5204. * bits from status so next scan request can be performed.
  5205. * if we dont clear scanning status bit here all next scan
  5206. * will fail
  5207. */
  5208. clear_bit(STATUS_SCAN_HW, &priv->status);
  5209. clear_bit(STATUS_SCANNING, &priv->status);
  5210. /* inform mac80211 scan aborted */
  5211. queue_work(priv->workqueue, &priv->scan_completed);
  5212. mutex_unlock(&priv->mutex);
  5213. }
  5214. static void iwl3945_bg_up(struct work_struct *data)
  5215. {
  5216. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5217. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5218. return;
  5219. mutex_lock(&priv->mutex);
  5220. __iwl3945_up(priv);
  5221. mutex_unlock(&priv->mutex);
  5222. iwl3945_rfkill_set_hw_state(priv);
  5223. }
  5224. static void iwl3945_bg_restart(struct work_struct *data)
  5225. {
  5226. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5227. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5228. return;
  5229. iwl3945_down(priv);
  5230. queue_work(priv->workqueue, &priv->up);
  5231. }
  5232. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5233. {
  5234. struct iwl3945_priv *priv =
  5235. container_of(data, struct iwl3945_priv, rx_replenish);
  5236. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5237. return;
  5238. mutex_lock(&priv->mutex);
  5239. iwl3945_rx_replenish(priv);
  5240. mutex_unlock(&priv->mutex);
  5241. }
  5242. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5243. static void iwl3945_post_associate(struct iwl3945_priv *priv)
  5244. {
  5245. int rc = 0;
  5246. struct ieee80211_conf *conf = NULL;
  5247. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5248. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5249. return;
  5250. }
  5251. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  5252. priv->assoc_id, priv->active_rxon.bssid_addr);
  5253. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5254. return;
  5255. if (!priv->vif || !priv->is_open)
  5256. return;
  5257. iwl3945_scan_cancel_timeout(priv, 200);
  5258. conf = ieee80211_get_hw_conf(priv->hw);
  5259. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5260. iwl3945_commit_rxon(priv);
  5261. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5262. iwl3945_setup_rxon_timing(priv);
  5263. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5264. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5265. if (rc)
  5266. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5267. "Attempting to continue.\n");
  5268. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5269. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5270. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5271. priv->assoc_id, priv->beacon_int);
  5272. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5273. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5274. else
  5275. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5276. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5277. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5278. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5279. else
  5280. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5281. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5282. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5283. }
  5284. iwl3945_commit_rxon(priv);
  5285. switch (priv->iw_mode) {
  5286. case NL80211_IFTYPE_STATION:
  5287. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5288. break;
  5289. case NL80211_IFTYPE_ADHOC:
  5290. priv->assoc_id = 1;
  5291. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5292. iwl3945_sync_sta(priv, IWL_STA_ID,
  5293. (priv->band == IEEE80211_BAND_5GHZ) ?
  5294. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5295. CMD_ASYNC);
  5296. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5297. iwl3945_send_beacon_cmd(priv);
  5298. break;
  5299. default:
  5300. IWL_ERROR("%s Should not be called in %d mode\n",
  5301. __func__, priv->iw_mode);
  5302. break;
  5303. }
  5304. iwl3945_activate_qos(priv, 0);
  5305. /* we have just associated, don't start scan too early */
  5306. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5307. }
  5308. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5309. {
  5310. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5311. if (!iwl3945_is_ready(priv))
  5312. return;
  5313. mutex_lock(&priv->mutex);
  5314. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5315. iwl3945_send_scan_abort(priv);
  5316. mutex_unlock(&priv->mutex);
  5317. }
  5318. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5319. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5320. {
  5321. struct iwl3945_priv *priv =
  5322. container_of(work, struct iwl3945_priv, scan_completed);
  5323. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5324. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5325. return;
  5326. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5327. iwl3945_mac_config(priv->hw, 0);
  5328. ieee80211_scan_completed(priv->hw);
  5329. /* Since setting the TXPOWER may have been deferred while
  5330. * performing the scan, fire one off */
  5331. mutex_lock(&priv->mutex);
  5332. iwl3945_hw_reg_send_txpower(priv);
  5333. mutex_unlock(&priv->mutex);
  5334. }
  5335. /*****************************************************************************
  5336. *
  5337. * mac80211 entry point functions
  5338. *
  5339. *****************************************************************************/
  5340. #define UCODE_READY_TIMEOUT (2 * HZ)
  5341. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5342. {
  5343. struct iwl3945_priv *priv = hw->priv;
  5344. int ret;
  5345. IWL_DEBUG_MAC80211("enter\n");
  5346. if (pci_enable_device(priv->pci_dev)) {
  5347. IWL_ERROR("Fail to pci_enable_device\n");
  5348. return -ENODEV;
  5349. }
  5350. pci_restore_state(priv->pci_dev);
  5351. pci_enable_msi(priv->pci_dev);
  5352. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5353. DRV_NAME, priv);
  5354. if (ret) {
  5355. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5356. goto out_disable_msi;
  5357. }
  5358. /* we should be verifying the device is ready to be opened */
  5359. mutex_lock(&priv->mutex);
  5360. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5361. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5362. * ucode filename and max sizes are card-specific. */
  5363. if (!priv->ucode_code.len) {
  5364. ret = iwl3945_read_ucode(priv);
  5365. if (ret) {
  5366. IWL_ERROR("Could not read microcode: %d\n", ret);
  5367. mutex_unlock(&priv->mutex);
  5368. goto out_release_irq;
  5369. }
  5370. }
  5371. ret = __iwl3945_up(priv);
  5372. mutex_unlock(&priv->mutex);
  5373. iwl3945_rfkill_set_hw_state(priv);
  5374. if (ret)
  5375. goto out_release_irq;
  5376. IWL_DEBUG_INFO("Start UP work.\n");
  5377. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5378. return 0;
  5379. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5380. * mac80211 will not be run successfully. */
  5381. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5382. test_bit(STATUS_READY, &priv->status),
  5383. UCODE_READY_TIMEOUT);
  5384. if (!ret) {
  5385. if (!test_bit(STATUS_READY, &priv->status)) {
  5386. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5387. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5388. ret = -ETIMEDOUT;
  5389. goto out_release_irq;
  5390. }
  5391. }
  5392. priv->is_open = 1;
  5393. IWL_DEBUG_MAC80211("leave\n");
  5394. return 0;
  5395. out_release_irq:
  5396. free_irq(priv->pci_dev->irq, priv);
  5397. out_disable_msi:
  5398. pci_disable_msi(priv->pci_dev);
  5399. pci_disable_device(priv->pci_dev);
  5400. priv->is_open = 0;
  5401. IWL_DEBUG_MAC80211("leave - failed\n");
  5402. return ret;
  5403. }
  5404. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5405. {
  5406. struct iwl3945_priv *priv = hw->priv;
  5407. IWL_DEBUG_MAC80211("enter\n");
  5408. if (!priv->is_open) {
  5409. IWL_DEBUG_MAC80211("leave - skip\n");
  5410. return;
  5411. }
  5412. priv->is_open = 0;
  5413. if (iwl3945_is_ready_rf(priv)) {
  5414. /* stop mac, cancel any scan request and clear
  5415. * RXON_FILTER_ASSOC_MSK BIT
  5416. */
  5417. mutex_lock(&priv->mutex);
  5418. iwl3945_scan_cancel_timeout(priv, 100);
  5419. mutex_unlock(&priv->mutex);
  5420. }
  5421. iwl3945_down(priv);
  5422. flush_workqueue(priv->workqueue);
  5423. free_irq(priv->pci_dev->irq, priv);
  5424. pci_disable_msi(priv->pci_dev);
  5425. pci_save_state(priv->pci_dev);
  5426. pci_disable_device(priv->pci_dev);
  5427. IWL_DEBUG_MAC80211("leave\n");
  5428. }
  5429. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5430. {
  5431. struct iwl3945_priv *priv = hw->priv;
  5432. IWL_DEBUG_MAC80211("enter\n");
  5433. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5434. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5435. if (iwl3945_tx_skb(priv, skb))
  5436. dev_kfree_skb_any(skb);
  5437. IWL_DEBUG_MAC80211("leave\n");
  5438. return NETDEV_TX_OK;
  5439. }
  5440. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5441. struct ieee80211_if_init_conf *conf)
  5442. {
  5443. struct iwl3945_priv *priv = hw->priv;
  5444. unsigned long flags;
  5445. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5446. if (priv->vif) {
  5447. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5448. return -EOPNOTSUPP;
  5449. }
  5450. spin_lock_irqsave(&priv->lock, flags);
  5451. priv->vif = conf->vif;
  5452. priv->iw_mode = conf->type;
  5453. spin_unlock_irqrestore(&priv->lock, flags);
  5454. mutex_lock(&priv->mutex);
  5455. if (conf->mac_addr) {
  5456. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5457. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5458. }
  5459. if (iwl3945_is_ready(priv))
  5460. iwl3945_set_mode(priv, conf->type);
  5461. mutex_unlock(&priv->mutex);
  5462. IWL_DEBUG_MAC80211("leave\n");
  5463. return 0;
  5464. }
  5465. /**
  5466. * iwl3945_mac_config - mac80211 config callback
  5467. *
  5468. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5469. * be set inappropriately and the driver currently sets the hardware up to
  5470. * use it whenever needed.
  5471. */
  5472. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5473. {
  5474. struct iwl3945_priv *priv = hw->priv;
  5475. const struct iwl3945_channel_info *ch_info;
  5476. struct ieee80211_conf *conf = &hw->conf;
  5477. unsigned long flags;
  5478. int ret = 0;
  5479. mutex_lock(&priv->mutex);
  5480. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5481. if (!iwl3945_is_ready(priv)) {
  5482. IWL_DEBUG_MAC80211("leave - not ready\n");
  5483. ret = -EIO;
  5484. goto out;
  5485. }
  5486. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5487. test_bit(STATUS_SCANNING, &priv->status))) {
  5488. IWL_DEBUG_MAC80211("leave - scanning\n");
  5489. set_bit(STATUS_CONF_PENDING, &priv->status);
  5490. mutex_unlock(&priv->mutex);
  5491. return 0;
  5492. }
  5493. spin_lock_irqsave(&priv->lock, flags);
  5494. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5495. conf->channel->hw_value);
  5496. if (!is_channel_valid(ch_info)) {
  5497. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5498. conf->channel->hw_value, conf->channel->band);
  5499. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5500. spin_unlock_irqrestore(&priv->lock, flags);
  5501. ret = -EINVAL;
  5502. goto out;
  5503. }
  5504. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5505. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5506. /* The list of supported rates and rate mask can be different
  5507. * for each phymode; since the phymode may have changed, reset
  5508. * the rate mask to what mac80211 lists */
  5509. iwl3945_set_rate(priv);
  5510. spin_unlock_irqrestore(&priv->lock, flags);
  5511. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5512. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5513. iwl3945_hw_channel_switch(priv, conf->channel);
  5514. goto out;
  5515. }
  5516. #endif
  5517. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5518. if (!conf->radio_enabled) {
  5519. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5520. goto out;
  5521. }
  5522. if (iwl3945_is_rfkill(priv)) {
  5523. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5524. ret = -EIO;
  5525. goto out;
  5526. }
  5527. iwl3945_set_rate(priv);
  5528. if (memcmp(&priv->active_rxon,
  5529. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5530. iwl3945_commit_rxon(priv);
  5531. else
  5532. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5533. IWL_DEBUG_MAC80211("leave\n");
  5534. out:
  5535. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5536. mutex_unlock(&priv->mutex);
  5537. return ret;
  5538. }
  5539. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5540. {
  5541. int rc = 0;
  5542. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5543. return;
  5544. /* The following should be done only at AP bring up */
  5545. if (!(iwl3945_is_associated(priv))) {
  5546. /* RXON - unassoc (to set timing command) */
  5547. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5548. iwl3945_commit_rxon(priv);
  5549. /* RXON Timing */
  5550. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5551. iwl3945_setup_rxon_timing(priv);
  5552. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5553. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5554. if (rc)
  5555. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5556. "Attempting to continue.\n");
  5557. /* FIXME: what should be the assoc_id for AP? */
  5558. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5559. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5560. priv->staging_rxon.flags |=
  5561. RXON_FLG_SHORT_PREAMBLE_MSK;
  5562. else
  5563. priv->staging_rxon.flags &=
  5564. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5565. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5566. if (priv->assoc_capability &
  5567. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5568. priv->staging_rxon.flags |=
  5569. RXON_FLG_SHORT_SLOT_MSK;
  5570. else
  5571. priv->staging_rxon.flags &=
  5572. ~RXON_FLG_SHORT_SLOT_MSK;
  5573. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5574. priv->staging_rxon.flags &=
  5575. ~RXON_FLG_SHORT_SLOT_MSK;
  5576. }
  5577. /* restore RXON assoc */
  5578. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5579. iwl3945_commit_rxon(priv);
  5580. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5581. }
  5582. iwl3945_send_beacon_cmd(priv);
  5583. /* FIXME - we need to add code here to detect a totally new
  5584. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5585. * clear sta table, add BCAST sta... */
  5586. }
  5587. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5588. struct ieee80211_vif *vif,
  5589. struct ieee80211_if_conf *conf)
  5590. {
  5591. struct iwl3945_priv *priv = hw->priv;
  5592. int rc;
  5593. if (conf == NULL)
  5594. return -EIO;
  5595. if (priv->vif != vif) {
  5596. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5597. return 0;
  5598. }
  5599. /* handle this temporarily here */
  5600. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5601. conf->changed & IEEE80211_IFCC_BEACON) {
  5602. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5603. if (!beacon)
  5604. return -ENOMEM;
  5605. mutex_lock(&priv->mutex);
  5606. rc = iwl3945_mac_beacon_update(hw, beacon);
  5607. mutex_unlock(&priv->mutex);
  5608. if (rc)
  5609. return rc;
  5610. }
  5611. if (!iwl3945_is_alive(priv))
  5612. return -EAGAIN;
  5613. mutex_lock(&priv->mutex);
  5614. if (conf->bssid)
  5615. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5616. /*
  5617. * very dubious code was here; the probe filtering flag is never set:
  5618. *
  5619. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5620. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5621. */
  5622. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5623. if (!conf->bssid) {
  5624. conf->bssid = priv->mac_addr;
  5625. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5626. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5627. conf->bssid);
  5628. }
  5629. if (priv->ibss_beacon)
  5630. dev_kfree_skb(priv->ibss_beacon);
  5631. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5632. }
  5633. if (iwl3945_is_rfkill(priv))
  5634. goto done;
  5635. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5636. !is_multicast_ether_addr(conf->bssid)) {
  5637. /* If there is currently a HW scan going on in the background
  5638. * then we need to cancel it else the RXON below will fail. */
  5639. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5640. IWL_WARNING("Aborted scan still in progress "
  5641. "after 100ms\n");
  5642. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5643. mutex_unlock(&priv->mutex);
  5644. return -EAGAIN;
  5645. }
  5646. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5647. /* TODO: Audit driver for usage of these members and see
  5648. * if mac80211 deprecates them (priv->bssid looks like it
  5649. * shouldn't be there, but I haven't scanned the IBSS code
  5650. * to verify) - jpk */
  5651. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5652. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5653. iwl3945_config_ap(priv);
  5654. else {
  5655. rc = iwl3945_commit_rxon(priv);
  5656. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5657. iwl3945_add_station(priv,
  5658. priv->active_rxon.bssid_addr, 1, 0);
  5659. }
  5660. } else {
  5661. iwl3945_scan_cancel_timeout(priv, 100);
  5662. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5663. iwl3945_commit_rxon(priv);
  5664. }
  5665. done:
  5666. IWL_DEBUG_MAC80211("leave\n");
  5667. mutex_unlock(&priv->mutex);
  5668. return 0;
  5669. }
  5670. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5671. unsigned int changed_flags,
  5672. unsigned int *total_flags,
  5673. int mc_count, struct dev_addr_list *mc_list)
  5674. {
  5675. struct iwl3945_priv *priv = hw->priv;
  5676. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  5677. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5678. changed_flags, *total_flags);
  5679. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5680. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5681. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5682. else
  5683. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5684. }
  5685. if (changed_flags & FIF_ALLMULTI) {
  5686. if (*total_flags & FIF_ALLMULTI)
  5687. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5688. else
  5689. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5690. }
  5691. if (changed_flags & FIF_CONTROL) {
  5692. if (*total_flags & FIF_CONTROL)
  5693. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5694. else
  5695. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5696. }
  5697. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5698. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5699. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5700. else
  5701. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5702. }
  5703. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5704. * since mac80211 will call ieee80211_hw_config immediately.
  5705. * (mc_list is not supported at this time). Otherwise, we need to
  5706. * queue a background iwl_commit_rxon work.
  5707. */
  5708. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5709. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5710. }
  5711. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5712. struct ieee80211_if_init_conf *conf)
  5713. {
  5714. struct iwl3945_priv *priv = hw->priv;
  5715. IWL_DEBUG_MAC80211("enter\n");
  5716. mutex_lock(&priv->mutex);
  5717. if (iwl3945_is_ready_rf(priv)) {
  5718. iwl3945_scan_cancel_timeout(priv, 100);
  5719. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5720. iwl3945_commit_rxon(priv);
  5721. }
  5722. if (priv->vif == conf->vif) {
  5723. priv->vif = NULL;
  5724. memset(priv->bssid, 0, ETH_ALEN);
  5725. }
  5726. mutex_unlock(&priv->mutex);
  5727. IWL_DEBUG_MAC80211("leave\n");
  5728. }
  5729. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5730. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5731. struct ieee80211_vif *vif,
  5732. struct ieee80211_bss_conf *bss_conf,
  5733. u32 changes)
  5734. {
  5735. struct iwl3945_priv *priv = hw->priv;
  5736. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5737. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5738. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5739. bss_conf->use_short_preamble);
  5740. if (bss_conf->use_short_preamble)
  5741. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5742. else
  5743. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5744. }
  5745. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5746. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5747. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5748. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5749. else
  5750. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5751. }
  5752. if (changes & BSS_CHANGED_ASSOC) {
  5753. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5754. /* This should never happen as this function should
  5755. * never be called from interrupt context. */
  5756. if (WARN_ON_ONCE(in_interrupt()))
  5757. return;
  5758. if (bss_conf->assoc) {
  5759. priv->assoc_id = bss_conf->aid;
  5760. priv->beacon_int = bss_conf->beacon_int;
  5761. priv->timestamp = bss_conf->timestamp;
  5762. priv->assoc_capability = bss_conf->assoc_capability;
  5763. priv->next_scan_jiffies = jiffies +
  5764. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5765. mutex_lock(&priv->mutex);
  5766. iwl3945_post_associate(priv);
  5767. mutex_unlock(&priv->mutex);
  5768. } else {
  5769. priv->assoc_id = 0;
  5770. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5771. }
  5772. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5773. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5774. iwl3945_send_rxon_assoc(priv);
  5775. }
  5776. }
  5777. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5778. {
  5779. int rc = 0;
  5780. unsigned long flags;
  5781. struct iwl3945_priv *priv = hw->priv;
  5782. DECLARE_SSID_BUF(ssid_buf);
  5783. IWL_DEBUG_MAC80211("enter\n");
  5784. mutex_lock(&priv->mutex);
  5785. spin_lock_irqsave(&priv->lock, flags);
  5786. if (!iwl3945_is_ready_rf(priv)) {
  5787. rc = -EIO;
  5788. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5789. goto out_unlock;
  5790. }
  5791. /* we don't schedule scan within next_scan_jiffies period */
  5792. if (priv->next_scan_jiffies &&
  5793. time_after(priv->next_scan_jiffies, jiffies)) {
  5794. rc = -EAGAIN;
  5795. goto out_unlock;
  5796. }
  5797. /* if we just finished scan ask for delay for a broadcast scan */
  5798. if ((len == 0) && priv->last_scan_jiffies &&
  5799. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5800. jiffies)) {
  5801. rc = -EAGAIN;
  5802. goto out_unlock;
  5803. }
  5804. if (len) {
  5805. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5806. print_ssid(ssid_buf, ssid, len), (int)len);
  5807. priv->one_direct_scan = 1;
  5808. priv->direct_ssid_len = (u8)
  5809. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5810. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5811. } else
  5812. priv->one_direct_scan = 0;
  5813. rc = iwl3945_scan_initiate(priv);
  5814. IWL_DEBUG_MAC80211("leave\n");
  5815. out_unlock:
  5816. spin_unlock_irqrestore(&priv->lock, flags);
  5817. mutex_unlock(&priv->mutex);
  5818. return rc;
  5819. }
  5820. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5821. const u8 *local_addr, const u8 *addr,
  5822. struct ieee80211_key_conf *key)
  5823. {
  5824. struct iwl3945_priv *priv = hw->priv;
  5825. int rc = 0;
  5826. u8 sta_id;
  5827. IWL_DEBUG_MAC80211("enter\n");
  5828. if (!iwl3945_param_hwcrypto) {
  5829. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5830. return -EOPNOTSUPP;
  5831. }
  5832. if (is_zero_ether_addr(addr))
  5833. /* only support pairwise keys */
  5834. return -EOPNOTSUPP;
  5835. sta_id = iwl3945_hw_find_station(priv, addr);
  5836. if (sta_id == IWL_INVALID_STATION) {
  5837. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5838. addr);
  5839. return -EINVAL;
  5840. }
  5841. mutex_lock(&priv->mutex);
  5842. iwl3945_scan_cancel_timeout(priv, 100);
  5843. switch (cmd) {
  5844. case SET_KEY:
  5845. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5846. if (!rc) {
  5847. iwl3945_set_rxon_hwcrypto(priv, 1);
  5848. iwl3945_commit_rxon(priv);
  5849. key->hw_key_idx = sta_id;
  5850. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5851. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5852. }
  5853. break;
  5854. case DISABLE_KEY:
  5855. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5856. if (!rc) {
  5857. iwl3945_set_rxon_hwcrypto(priv, 0);
  5858. iwl3945_commit_rxon(priv);
  5859. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5860. }
  5861. break;
  5862. default:
  5863. rc = -EINVAL;
  5864. }
  5865. IWL_DEBUG_MAC80211("leave\n");
  5866. mutex_unlock(&priv->mutex);
  5867. return rc;
  5868. }
  5869. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5870. const struct ieee80211_tx_queue_params *params)
  5871. {
  5872. struct iwl3945_priv *priv = hw->priv;
  5873. unsigned long flags;
  5874. int q;
  5875. IWL_DEBUG_MAC80211("enter\n");
  5876. if (!iwl3945_is_ready_rf(priv)) {
  5877. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5878. return -EIO;
  5879. }
  5880. if (queue >= AC_NUM) {
  5881. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5882. return 0;
  5883. }
  5884. q = AC_NUM - 1 - queue;
  5885. spin_lock_irqsave(&priv->lock, flags);
  5886. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5887. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5888. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5889. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5890. cpu_to_le16((params->txop * 32));
  5891. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5892. priv->qos_data.qos_active = 1;
  5893. spin_unlock_irqrestore(&priv->lock, flags);
  5894. mutex_lock(&priv->mutex);
  5895. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5896. iwl3945_activate_qos(priv, 1);
  5897. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5898. iwl3945_activate_qos(priv, 0);
  5899. mutex_unlock(&priv->mutex);
  5900. IWL_DEBUG_MAC80211("leave\n");
  5901. return 0;
  5902. }
  5903. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5904. struct ieee80211_tx_queue_stats *stats)
  5905. {
  5906. struct iwl3945_priv *priv = hw->priv;
  5907. int i, avail;
  5908. struct iwl3945_tx_queue *txq;
  5909. struct iwl3945_queue *q;
  5910. unsigned long flags;
  5911. IWL_DEBUG_MAC80211("enter\n");
  5912. if (!iwl3945_is_ready_rf(priv)) {
  5913. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5914. return -EIO;
  5915. }
  5916. spin_lock_irqsave(&priv->lock, flags);
  5917. for (i = 0; i < AC_NUM; i++) {
  5918. txq = &priv->txq[i];
  5919. q = &txq->q;
  5920. avail = iwl3945_queue_space(q);
  5921. stats[i].len = q->n_window - avail;
  5922. stats[i].limit = q->n_window - q->high_mark;
  5923. stats[i].count = q->n_window;
  5924. }
  5925. spin_unlock_irqrestore(&priv->lock, flags);
  5926. IWL_DEBUG_MAC80211("leave\n");
  5927. return 0;
  5928. }
  5929. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  5930. struct ieee80211_low_level_stats *stats)
  5931. {
  5932. return 0;
  5933. }
  5934. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5935. {
  5936. struct iwl3945_priv *priv = hw->priv;
  5937. unsigned long flags;
  5938. mutex_lock(&priv->mutex);
  5939. IWL_DEBUG_MAC80211("enter\n");
  5940. iwl3945_reset_qos(priv);
  5941. spin_lock_irqsave(&priv->lock, flags);
  5942. priv->assoc_id = 0;
  5943. priv->assoc_capability = 0;
  5944. priv->call_post_assoc_from_beacon = 0;
  5945. /* new association get rid of ibss beacon skb */
  5946. if (priv->ibss_beacon)
  5947. dev_kfree_skb(priv->ibss_beacon);
  5948. priv->ibss_beacon = NULL;
  5949. priv->beacon_int = priv->hw->conf.beacon_int;
  5950. priv->timestamp = 0;
  5951. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5952. priv->beacon_int = 0;
  5953. spin_unlock_irqrestore(&priv->lock, flags);
  5954. if (!iwl3945_is_ready_rf(priv)) {
  5955. IWL_DEBUG_MAC80211("leave - not ready\n");
  5956. mutex_unlock(&priv->mutex);
  5957. return;
  5958. }
  5959. /* we are restarting association process
  5960. * clear RXON_FILTER_ASSOC_MSK bit
  5961. */
  5962. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5963. iwl3945_scan_cancel_timeout(priv, 100);
  5964. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5965. iwl3945_commit_rxon(priv);
  5966. }
  5967. /* Per mac80211.h: This is only used in IBSS mode... */
  5968. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5969. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5970. mutex_unlock(&priv->mutex);
  5971. return;
  5972. }
  5973. iwl3945_set_rate(priv);
  5974. mutex_unlock(&priv->mutex);
  5975. IWL_DEBUG_MAC80211("leave\n");
  5976. }
  5977. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5978. {
  5979. struct iwl3945_priv *priv = hw->priv;
  5980. unsigned long flags;
  5981. IWL_DEBUG_MAC80211("enter\n");
  5982. if (!iwl3945_is_ready_rf(priv)) {
  5983. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5984. return -EIO;
  5985. }
  5986. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5987. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5988. return -EIO;
  5989. }
  5990. spin_lock_irqsave(&priv->lock, flags);
  5991. if (priv->ibss_beacon)
  5992. dev_kfree_skb(priv->ibss_beacon);
  5993. priv->ibss_beacon = skb;
  5994. priv->assoc_id = 0;
  5995. IWL_DEBUG_MAC80211("leave\n");
  5996. spin_unlock_irqrestore(&priv->lock, flags);
  5997. iwl3945_reset_qos(priv);
  5998. iwl3945_post_associate(priv);
  5999. return 0;
  6000. }
  6001. /*****************************************************************************
  6002. *
  6003. * sysfs attributes
  6004. *
  6005. *****************************************************************************/
  6006. #ifdef CONFIG_IWL3945_DEBUG
  6007. /*
  6008. * The following adds a new attribute to the sysfs representation
  6009. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6010. * used for controlling the debug level.
  6011. *
  6012. * See the level definitions in iwl for details.
  6013. */
  6014. static ssize_t show_debug_level(struct device *d,
  6015. struct device_attribute *attr, char *buf)
  6016. {
  6017. struct iwl3945_priv *priv = d->driver_data;
  6018. return sprintf(buf, "0x%08X\n", priv->debug_level);
  6019. }
  6020. static ssize_t store_debug_level(struct device *d,
  6021. struct device_attribute *attr,
  6022. const char *buf, size_t count)
  6023. {
  6024. struct iwl3945_priv *priv = d->driver_data;
  6025. unsigned long val;
  6026. int ret;
  6027. ret = strict_strtoul(buf, 0, &val);
  6028. if (ret)
  6029. printk(KERN_INFO DRV_NAME
  6030. ": %s is not in hex or decimal form.\n", buf);
  6031. else
  6032. priv->debug_level = val;
  6033. return strnlen(buf, count);
  6034. }
  6035. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6036. show_debug_level, store_debug_level);
  6037. #endif /* CONFIG_IWL3945_DEBUG */
  6038. static ssize_t show_temperature(struct device *d,
  6039. struct device_attribute *attr, char *buf)
  6040. {
  6041. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6042. if (!iwl3945_is_alive(priv))
  6043. return -EAGAIN;
  6044. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6045. }
  6046. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6047. static ssize_t show_tx_power(struct device *d,
  6048. struct device_attribute *attr, char *buf)
  6049. {
  6050. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6051. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6052. }
  6053. static ssize_t store_tx_power(struct device *d,
  6054. struct device_attribute *attr,
  6055. const char *buf, size_t count)
  6056. {
  6057. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6058. char *p = (char *)buf;
  6059. u32 val;
  6060. val = simple_strtoul(p, &p, 10);
  6061. if (p == buf)
  6062. printk(KERN_INFO DRV_NAME
  6063. ": %s is not in decimal form.\n", buf);
  6064. else
  6065. iwl3945_hw_reg_set_txpower(priv, val);
  6066. return count;
  6067. }
  6068. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6069. static ssize_t show_flags(struct device *d,
  6070. struct device_attribute *attr, char *buf)
  6071. {
  6072. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6073. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6074. }
  6075. static ssize_t store_flags(struct device *d,
  6076. struct device_attribute *attr,
  6077. const char *buf, size_t count)
  6078. {
  6079. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6080. u32 flags = simple_strtoul(buf, NULL, 0);
  6081. mutex_lock(&priv->mutex);
  6082. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6083. /* Cancel any currently running scans... */
  6084. if (iwl3945_scan_cancel_timeout(priv, 100))
  6085. IWL_WARNING("Could not cancel scan.\n");
  6086. else {
  6087. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6088. flags);
  6089. priv->staging_rxon.flags = cpu_to_le32(flags);
  6090. iwl3945_commit_rxon(priv);
  6091. }
  6092. }
  6093. mutex_unlock(&priv->mutex);
  6094. return count;
  6095. }
  6096. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6097. static ssize_t show_filter_flags(struct device *d,
  6098. struct device_attribute *attr, char *buf)
  6099. {
  6100. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6101. return sprintf(buf, "0x%04X\n",
  6102. le32_to_cpu(priv->active_rxon.filter_flags));
  6103. }
  6104. static ssize_t store_filter_flags(struct device *d,
  6105. struct device_attribute *attr,
  6106. const char *buf, size_t count)
  6107. {
  6108. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6109. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6110. mutex_lock(&priv->mutex);
  6111. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6112. /* Cancel any currently running scans... */
  6113. if (iwl3945_scan_cancel_timeout(priv, 100))
  6114. IWL_WARNING("Could not cancel scan.\n");
  6115. else {
  6116. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6117. "0x%04X\n", filter_flags);
  6118. priv->staging_rxon.filter_flags =
  6119. cpu_to_le32(filter_flags);
  6120. iwl3945_commit_rxon(priv);
  6121. }
  6122. }
  6123. mutex_unlock(&priv->mutex);
  6124. return count;
  6125. }
  6126. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6127. store_filter_flags);
  6128. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6129. static ssize_t show_measurement(struct device *d,
  6130. struct device_attribute *attr, char *buf)
  6131. {
  6132. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6133. struct iwl_spectrum_notification measure_report;
  6134. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6135. u8 *data = (u8 *)&measure_report;
  6136. unsigned long flags;
  6137. spin_lock_irqsave(&priv->lock, flags);
  6138. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6139. spin_unlock_irqrestore(&priv->lock, flags);
  6140. return 0;
  6141. }
  6142. memcpy(&measure_report, &priv->measure_report, size);
  6143. priv->measurement_status = 0;
  6144. spin_unlock_irqrestore(&priv->lock, flags);
  6145. while (size && (PAGE_SIZE - len)) {
  6146. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6147. PAGE_SIZE - len, 1);
  6148. len = strlen(buf);
  6149. if (PAGE_SIZE - len)
  6150. buf[len++] = '\n';
  6151. ofs += 16;
  6152. size -= min(size, 16U);
  6153. }
  6154. return len;
  6155. }
  6156. static ssize_t store_measurement(struct device *d,
  6157. struct device_attribute *attr,
  6158. const char *buf, size_t count)
  6159. {
  6160. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6161. struct ieee80211_measurement_params params = {
  6162. .channel = le16_to_cpu(priv->active_rxon.channel),
  6163. .start_time = cpu_to_le64(priv->last_tsf),
  6164. .duration = cpu_to_le16(1),
  6165. };
  6166. u8 type = IWL_MEASURE_BASIC;
  6167. u8 buffer[32];
  6168. u8 channel;
  6169. if (count) {
  6170. char *p = buffer;
  6171. strncpy(buffer, buf, min(sizeof(buffer), count));
  6172. channel = simple_strtoul(p, NULL, 0);
  6173. if (channel)
  6174. params.channel = channel;
  6175. p = buffer;
  6176. while (*p && *p != ' ')
  6177. p++;
  6178. if (*p)
  6179. type = simple_strtoul(p + 1, NULL, 0);
  6180. }
  6181. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6182. "channel %d (for '%s')\n", type, params.channel, buf);
  6183. iwl3945_get_measurement(priv, &params, type);
  6184. return count;
  6185. }
  6186. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6187. show_measurement, store_measurement);
  6188. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6189. static ssize_t store_retry_rate(struct device *d,
  6190. struct device_attribute *attr,
  6191. const char *buf, size_t count)
  6192. {
  6193. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6194. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6195. if (priv->retry_rate <= 0)
  6196. priv->retry_rate = 1;
  6197. return count;
  6198. }
  6199. static ssize_t show_retry_rate(struct device *d,
  6200. struct device_attribute *attr, char *buf)
  6201. {
  6202. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6203. return sprintf(buf, "%d", priv->retry_rate);
  6204. }
  6205. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6206. store_retry_rate);
  6207. static ssize_t store_power_level(struct device *d,
  6208. struct device_attribute *attr,
  6209. const char *buf, size_t count)
  6210. {
  6211. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6212. int rc;
  6213. int mode;
  6214. mode = simple_strtoul(buf, NULL, 0);
  6215. mutex_lock(&priv->mutex);
  6216. if (!iwl3945_is_ready(priv)) {
  6217. rc = -EAGAIN;
  6218. goto out;
  6219. }
  6220. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6221. mode = IWL_POWER_AC;
  6222. else
  6223. mode |= IWL_POWER_ENABLED;
  6224. if (mode != priv->power_mode) {
  6225. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6226. if (rc) {
  6227. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6228. goto out;
  6229. }
  6230. priv->power_mode = mode;
  6231. }
  6232. rc = count;
  6233. out:
  6234. mutex_unlock(&priv->mutex);
  6235. return rc;
  6236. }
  6237. #define MAX_WX_STRING 80
  6238. /* Values are in microsecond */
  6239. static const s32 timeout_duration[] = {
  6240. 350000,
  6241. 250000,
  6242. 75000,
  6243. 37000,
  6244. 25000,
  6245. };
  6246. static const s32 period_duration[] = {
  6247. 400000,
  6248. 700000,
  6249. 1000000,
  6250. 1000000,
  6251. 1000000
  6252. };
  6253. static ssize_t show_power_level(struct device *d,
  6254. struct device_attribute *attr, char *buf)
  6255. {
  6256. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6257. int level = IWL_POWER_LEVEL(priv->power_mode);
  6258. char *p = buf;
  6259. p += sprintf(p, "%d ", level);
  6260. switch (level) {
  6261. case IWL_POWER_MODE_CAM:
  6262. case IWL_POWER_AC:
  6263. p += sprintf(p, "(AC)");
  6264. break;
  6265. case IWL_POWER_BATTERY:
  6266. p += sprintf(p, "(BATTERY)");
  6267. break;
  6268. default:
  6269. p += sprintf(p,
  6270. "(Timeout %dms, Period %dms)",
  6271. timeout_duration[level - 1] / 1000,
  6272. period_duration[level - 1] / 1000);
  6273. }
  6274. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6275. p += sprintf(p, " OFF\n");
  6276. else
  6277. p += sprintf(p, " \n");
  6278. return p - buf + 1;
  6279. }
  6280. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6281. store_power_level);
  6282. static ssize_t show_channels(struct device *d,
  6283. struct device_attribute *attr, char *buf)
  6284. {
  6285. /* all this shit doesn't belong into sysfs anyway */
  6286. return 0;
  6287. }
  6288. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6289. static ssize_t show_statistics(struct device *d,
  6290. struct device_attribute *attr, char *buf)
  6291. {
  6292. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6293. u32 size = sizeof(struct iwl3945_notif_statistics);
  6294. u32 len = 0, ofs = 0;
  6295. u8 *data = (u8 *)&priv->statistics;
  6296. int rc = 0;
  6297. if (!iwl3945_is_alive(priv))
  6298. return -EAGAIN;
  6299. mutex_lock(&priv->mutex);
  6300. rc = iwl3945_send_statistics_request(priv);
  6301. mutex_unlock(&priv->mutex);
  6302. if (rc) {
  6303. len = sprintf(buf,
  6304. "Error sending statistics request: 0x%08X\n", rc);
  6305. return len;
  6306. }
  6307. while (size && (PAGE_SIZE - len)) {
  6308. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6309. PAGE_SIZE - len, 1);
  6310. len = strlen(buf);
  6311. if (PAGE_SIZE - len)
  6312. buf[len++] = '\n';
  6313. ofs += 16;
  6314. size -= min(size, 16U);
  6315. }
  6316. return len;
  6317. }
  6318. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6319. static ssize_t show_antenna(struct device *d,
  6320. struct device_attribute *attr, char *buf)
  6321. {
  6322. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6323. if (!iwl3945_is_alive(priv))
  6324. return -EAGAIN;
  6325. return sprintf(buf, "%d\n", priv->antenna);
  6326. }
  6327. static ssize_t store_antenna(struct device *d,
  6328. struct device_attribute *attr,
  6329. const char *buf, size_t count)
  6330. {
  6331. int ant;
  6332. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6333. if (count == 0)
  6334. return 0;
  6335. if (sscanf(buf, "%1i", &ant) != 1) {
  6336. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6337. return count;
  6338. }
  6339. if ((ant >= 0) && (ant <= 2)) {
  6340. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6341. priv->antenna = (enum iwl3945_antenna)ant;
  6342. } else
  6343. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6344. return count;
  6345. }
  6346. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6347. static ssize_t show_status(struct device *d,
  6348. struct device_attribute *attr, char *buf)
  6349. {
  6350. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6351. if (!iwl3945_is_alive(priv))
  6352. return -EAGAIN;
  6353. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6354. }
  6355. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6356. static ssize_t dump_error_log(struct device *d,
  6357. struct device_attribute *attr,
  6358. const char *buf, size_t count)
  6359. {
  6360. char *p = (char *)buf;
  6361. if (p[0] == '1')
  6362. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6363. return strnlen(buf, count);
  6364. }
  6365. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6366. static ssize_t dump_event_log(struct device *d,
  6367. struct device_attribute *attr,
  6368. const char *buf, size_t count)
  6369. {
  6370. char *p = (char *)buf;
  6371. if (p[0] == '1')
  6372. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6373. return strnlen(buf, count);
  6374. }
  6375. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6376. /*****************************************************************************
  6377. *
  6378. * driver setup and tear down
  6379. *
  6380. *****************************************************************************/
  6381. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6382. {
  6383. priv->workqueue = create_workqueue(DRV_NAME);
  6384. init_waitqueue_head(&priv->wait_command_queue);
  6385. INIT_WORK(&priv->up, iwl3945_bg_up);
  6386. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6387. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6388. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6389. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6390. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6391. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6392. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6393. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6394. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6395. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6396. iwl3945_hw_setup_deferred_work(priv);
  6397. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6398. iwl3945_irq_tasklet, (unsigned long)priv);
  6399. }
  6400. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6401. {
  6402. iwl3945_hw_cancel_deferred_work(priv);
  6403. cancel_delayed_work_sync(&priv->init_alive_start);
  6404. cancel_delayed_work(&priv->scan_check);
  6405. cancel_delayed_work(&priv->alive_start);
  6406. cancel_work_sync(&priv->beacon_update);
  6407. }
  6408. static struct attribute *iwl3945_sysfs_entries[] = {
  6409. &dev_attr_antenna.attr,
  6410. &dev_attr_channels.attr,
  6411. &dev_attr_dump_errors.attr,
  6412. &dev_attr_dump_events.attr,
  6413. &dev_attr_flags.attr,
  6414. &dev_attr_filter_flags.attr,
  6415. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6416. &dev_attr_measurement.attr,
  6417. #endif
  6418. &dev_attr_power_level.attr,
  6419. &dev_attr_retry_rate.attr,
  6420. &dev_attr_statistics.attr,
  6421. &dev_attr_status.attr,
  6422. &dev_attr_temperature.attr,
  6423. &dev_attr_tx_power.attr,
  6424. #ifdef CONFIG_IWL3945_DEBUG
  6425. &dev_attr_debug_level.attr,
  6426. #endif
  6427. NULL
  6428. };
  6429. static struct attribute_group iwl3945_attribute_group = {
  6430. .name = NULL, /* put in device directory */
  6431. .attrs = iwl3945_sysfs_entries,
  6432. };
  6433. static struct ieee80211_ops iwl3945_hw_ops = {
  6434. .tx = iwl3945_mac_tx,
  6435. .start = iwl3945_mac_start,
  6436. .stop = iwl3945_mac_stop,
  6437. .add_interface = iwl3945_mac_add_interface,
  6438. .remove_interface = iwl3945_mac_remove_interface,
  6439. .config = iwl3945_mac_config,
  6440. .config_interface = iwl3945_mac_config_interface,
  6441. .configure_filter = iwl3945_configure_filter,
  6442. .set_key = iwl3945_mac_set_key,
  6443. .get_stats = iwl3945_mac_get_stats,
  6444. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6445. .conf_tx = iwl3945_mac_conf_tx,
  6446. .reset_tsf = iwl3945_mac_reset_tsf,
  6447. .bss_info_changed = iwl3945_bss_info_changed,
  6448. .hw_scan = iwl3945_mac_hw_scan
  6449. };
  6450. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6451. {
  6452. int err = 0;
  6453. struct iwl3945_priv *priv;
  6454. struct ieee80211_hw *hw;
  6455. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6456. unsigned long flags;
  6457. /***********************
  6458. * 1. Allocating HW data
  6459. * ********************/
  6460. /* mac80211 allocates memory for this device instance, including
  6461. * space for this driver's private structure */
  6462. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6463. if (hw == NULL) {
  6464. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6465. err = -ENOMEM;
  6466. goto out;
  6467. }
  6468. SET_IEEE80211_DEV(hw, &pdev->dev);
  6469. priv = hw->priv;
  6470. priv->hw = hw;
  6471. priv->pci_dev = pdev;
  6472. priv->cfg = cfg;
  6473. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6474. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6475. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6476. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6477. err = -EINVAL;
  6478. goto out;
  6479. }
  6480. /* Disabling hardware scan means that mac80211 will perform scans
  6481. * "the hard way", rather than using device's scan. */
  6482. if (iwl3945_param_disable_hw_scan) {
  6483. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6484. iwl3945_hw_ops.hw_scan = NULL;
  6485. }
  6486. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6487. hw->rate_control_algorithm = "iwl-3945-rs";
  6488. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6489. /* Select antenna (may be helpful if only one antenna is connected) */
  6490. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6491. #ifdef CONFIG_IWL3945_DEBUG
  6492. priv->debug_level = iwl3945_param_debug;
  6493. atomic_set(&priv->restrict_refcnt, 0);
  6494. #endif
  6495. /* Tell mac80211 our characteristics */
  6496. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6497. IEEE80211_HW_NOISE_DBM;
  6498. hw->wiphy->interface_modes =
  6499. BIT(NL80211_IFTYPE_STATION) |
  6500. BIT(NL80211_IFTYPE_ADHOC);
  6501. hw->wiphy->fw_handles_regulatory = true;
  6502. /* 4 EDCA QOS priorities */
  6503. hw->queues = 4;
  6504. /***************************
  6505. * 2. Initializing PCI bus
  6506. * *************************/
  6507. if (pci_enable_device(pdev)) {
  6508. err = -ENODEV;
  6509. goto out_ieee80211_free_hw;
  6510. }
  6511. pci_set_master(pdev);
  6512. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6513. if (!err)
  6514. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6515. if (err) {
  6516. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6517. goto out_pci_disable_device;
  6518. }
  6519. pci_set_drvdata(pdev, priv);
  6520. err = pci_request_regions(pdev, DRV_NAME);
  6521. if (err)
  6522. goto out_pci_disable_device;
  6523. /***********************
  6524. * 3. Read REV Register
  6525. * ********************/
  6526. priv->hw_base = pci_iomap(pdev, 0, 0);
  6527. if (!priv->hw_base) {
  6528. err = -ENODEV;
  6529. goto out_pci_release_regions;
  6530. }
  6531. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6532. (unsigned long long) pci_resource_len(pdev, 0));
  6533. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6534. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6535. * PCI Tx retries from interfering with C3 CPU state */
  6536. pci_write_config_byte(pdev, 0x41, 0x00);
  6537. /* nic init */
  6538. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6539. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6540. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6541. err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
  6542. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6543. if (err < 0) {
  6544. IWL_DEBUG_INFO("Failed to init the card\n");
  6545. goto out_remove_sysfs;
  6546. }
  6547. /***********************
  6548. * 4. Read EEPROM
  6549. * ********************/
  6550. /* Read the EEPROM */
  6551. err = iwl3945_eeprom_init(priv);
  6552. if (err) {
  6553. IWL_ERROR("Unable to init EEPROM\n");
  6554. goto out_remove_sysfs;
  6555. }
  6556. /* MAC Address location in EEPROM same for 3945/4965 */
  6557. get_eeprom_mac(priv, priv->mac_addr);
  6558. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6559. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6560. /***********************
  6561. * 5. Setup HW Constants
  6562. * ********************/
  6563. /* Device-specific setup */
  6564. if (iwl3945_hw_set_hw_setting(priv)) {
  6565. IWL_ERROR("failed to set hw settings\n");
  6566. goto out_iounmap;
  6567. }
  6568. /***********************
  6569. * 6. Setup priv
  6570. * ********************/
  6571. priv->retry_rate = 1;
  6572. priv->ibss_beacon = NULL;
  6573. spin_lock_init(&priv->lock);
  6574. spin_lock_init(&priv->power_data.lock);
  6575. spin_lock_init(&priv->sta_lock);
  6576. spin_lock_init(&priv->hcmd_lock);
  6577. INIT_LIST_HEAD(&priv->free_frames);
  6578. mutex_init(&priv->mutex);
  6579. /* Clear the driver's (not device's) station table */
  6580. iwl3945_clear_stations_table(priv);
  6581. priv->data_retry_limit = -1;
  6582. priv->ieee_channels = NULL;
  6583. priv->ieee_rates = NULL;
  6584. priv->band = IEEE80211_BAND_2GHZ;
  6585. priv->iw_mode = NL80211_IFTYPE_STATION;
  6586. iwl3945_reset_qos(priv);
  6587. priv->qos_data.qos_active = 0;
  6588. priv->qos_data.qos_cap.val = 0;
  6589. priv->rates_mask = IWL_RATES_MASK;
  6590. /* If power management is turned on, default to AC mode */
  6591. priv->power_mode = IWL_POWER_AC;
  6592. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6593. err = iwl3945_init_channel_map(priv);
  6594. if (err) {
  6595. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6596. goto out_release_irq;
  6597. }
  6598. err = iwl3945_init_geos(priv);
  6599. if (err) {
  6600. IWL_ERROR("initializing geos failed: %d\n", err);
  6601. goto out_free_channel_map;
  6602. }
  6603. printk(KERN_INFO DRV_NAME
  6604. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6605. /***********************************
  6606. * 7. Initialize Module Parameters
  6607. * **********************************/
  6608. /* Initialize module parameter values here */
  6609. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6610. if (iwl3945_param_disable) {
  6611. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6612. IWL_DEBUG_INFO("Radio disabled.\n");
  6613. }
  6614. /***********************
  6615. * 8. Setup Services
  6616. * ********************/
  6617. spin_lock_irqsave(&priv->lock, flags);
  6618. iwl3945_disable_interrupts(priv);
  6619. spin_unlock_irqrestore(&priv->lock, flags);
  6620. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6621. if (err) {
  6622. IWL_ERROR("failed to create sysfs device attributes\n");
  6623. goto out_free_geos;
  6624. }
  6625. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6626. iwl3945_setup_deferred_work(priv);
  6627. iwl3945_setup_rx_handlers(priv);
  6628. /***********************
  6629. * 9. Conclude
  6630. * ********************/
  6631. pci_save_state(pdev);
  6632. pci_disable_device(pdev);
  6633. /*********************************
  6634. * 10. Setup and Register mac80211
  6635. * *******************************/
  6636. err = ieee80211_register_hw(priv->hw);
  6637. if (err) {
  6638. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6639. goto out_remove_sysfs;
  6640. }
  6641. priv->hw->conf.beacon_int = 100;
  6642. priv->mac80211_registered = 1;
  6643. err = iwl3945_rfkill_init(priv);
  6644. if (err)
  6645. IWL_ERROR("Unable to initialize RFKILL system. "
  6646. "Ignoring error: %d\n", err);
  6647. return 0;
  6648. out_remove_sysfs:
  6649. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6650. out_free_geos:
  6651. iwl3945_free_geos(priv);
  6652. out_free_channel_map:
  6653. iwl3945_free_channel_map(priv);
  6654. out_release_irq:
  6655. destroy_workqueue(priv->workqueue);
  6656. priv->workqueue = NULL;
  6657. iwl3945_unset_hw_setting(priv);
  6658. out_iounmap:
  6659. pci_iounmap(pdev, priv->hw_base);
  6660. out_pci_release_regions:
  6661. pci_release_regions(pdev);
  6662. out_pci_disable_device:
  6663. pci_disable_device(pdev);
  6664. pci_set_drvdata(pdev, NULL);
  6665. out_ieee80211_free_hw:
  6666. ieee80211_free_hw(priv->hw);
  6667. out:
  6668. return err;
  6669. }
  6670. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6671. {
  6672. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6673. unsigned long flags;
  6674. if (!priv)
  6675. return;
  6676. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6677. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6678. iwl3945_down(priv);
  6679. /* make sure we flush any pending irq or
  6680. * tasklet for the driver
  6681. */
  6682. spin_lock_irqsave(&priv->lock, flags);
  6683. iwl3945_disable_interrupts(priv);
  6684. spin_unlock_irqrestore(&priv->lock, flags);
  6685. iwl_synchronize_irq(priv);
  6686. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6687. iwl3945_rfkill_unregister(priv);
  6688. iwl3945_dealloc_ucode_pci(priv);
  6689. if (priv->rxq.bd)
  6690. iwl3945_rx_queue_free(priv, &priv->rxq);
  6691. iwl3945_hw_txq_ctx_free(priv);
  6692. iwl3945_unset_hw_setting(priv);
  6693. iwl3945_clear_stations_table(priv);
  6694. if (priv->mac80211_registered)
  6695. ieee80211_unregister_hw(priv->hw);
  6696. /*netif_stop_queue(dev); */
  6697. flush_workqueue(priv->workqueue);
  6698. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6699. * priv->workqueue... so we can't take down the workqueue
  6700. * until now... */
  6701. destroy_workqueue(priv->workqueue);
  6702. priv->workqueue = NULL;
  6703. pci_iounmap(pdev, priv->hw_base);
  6704. pci_release_regions(pdev);
  6705. pci_disable_device(pdev);
  6706. pci_set_drvdata(pdev, NULL);
  6707. iwl3945_free_channel_map(priv);
  6708. iwl3945_free_geos(priv);
  6709. kfree(priv->scan);
  6710. if (priv->ibss_beacon)
  6711. dev_kfree_skb(priv->ibss_beacon);
  6712. ieee80211_free_hw(priv->hw);
  6713. }
  6714. #ifdef CONFIG_PM
  6715. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6716. {
  6717. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6718. if (priv->is_open) {
  6719. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6720. iwl3945_mac_stop(priv->hw);
  6721. priv->is_open = 1;
  6722. }
  6723. pci_set_power_state(pdev, PCI_D3hot);
  6724. return 0;
  6725. }
  6726. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6727. {
  6728. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6729. pci_set_power_state(pdev, PCI_D0);
  6730. if (priv->is_open)
  6731. iwl3945_mac_start(priv->hw);
  6732. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6733. return 0;
  6734. }
  6735. #endif /* CONFIG_PM */
  6736. /*************** RFKILL FUNCTIONS **********/
  6737. #ifdef CONFIG_IWL3945_RFKILL
  6738. /* software rf-kill from user */
  6739. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6740. {
  6741. struct iwl3945_priv *priv = data;
  6742. int err = 0;
  6743. if (!priv->rfkill)
  6744. return 0;
  6745. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6746. return 0;
  6747. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6748. mutex_lock(&priv->mutex);
  6749. switch (state) {
  6750. case RFKILL_STATE_UNBLOCKED:
  6751. if (iwl3945_is_rfkill_hw(priv)) {
  6752. err = -EBUSY;
  6753. goto out_unlock;
  6754. }
  6755. iwl3945_radio_kill_sw(priv, 0);
  6756. break;
  6757. case RFKILL_STATE_SOFT_BLOCKED:
  6758. iwl3945_radio_kill_sw(priv, 1);
  6759. break;
  6760. default:
  6761. IWL_WARNING("we received unexpected RFKILL state %d\n", state);
  6762. break;
  6763. }
  6764. out_unlock:
  6765. mutex_unlock(&priv->mutex);
  6766. return err;
  6767. }
  6768. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6769. {
  6770. struct device *device = wiphy_dev(priv->hw->wiphy);
  6771. int ret = 0;
  6772. BUG_ON(device == NULL);
  6773. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6774. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6775. if (!priv->rfkill) {
  6776. IWL_ERROR("Unable to allocate rfkill device.\n");
  6777. ret = -ENOMEM;
  6778. goto error;
  6779. }
  6780. priv->rfkill->name = priv->cfg->name;
  6781. priv->rfkill->data = priv;
  6782. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6783. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6784. priv->rfkill->user_claim_unsupported = 1;
  6785. priv->rfkill->dev.class->suspend = NULL;
  6786. priv->rfkill->dev.class->resume = NULL;
  6787. ret = rfkill_register(priv->rfkill);
  6788. if (ret) {
  6789. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6790. goto freed_rfkill;
  6791. }
  6792. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6793. return ret;
  6794. freed_rfkill:
  6795. if (priv->rfkill != NULL)
  6796. rfkill_free(priv->rfkill);
  6797. priv->rfkill = NULL;
  6798. error:
  6799. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6800. return ret;
  6801. }
  6802. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6803. {
  6804. if (priv->rfkill)
  6805. rfkill_unregister(priv->rfkill);
  6806. priv->rfkill = NULL;
  6807. }
  6808. /* set rf-kill to the right state. */
  6809. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6810. {
  6811. if (!priv->rfkill)
  6812. return;
  6813. if (iwl3945_is_rfkill_hw(priv)) {
  6814. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6815. return;
  6816. }
  6817. if (!iwl3945_is_rfkill_sw(priv))
  6818. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6819. else
  6820. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6821. }
  6822. #endif
  6823. /*****************************************************************************
  6824. *
  6825. * driver and module entry point
  6826. *
  6827. *****************************************************************************/
  6828. static struct pci_driver iwl3945_driver = {
  6829. .name = DRV_NAME,
  6830. .id_table = iwl3945_hw_card_ids,
  6831. .probe = iwl3945_pci_probe,
  6832. .remove = __devexit_p(iwl3945_pci_remove),
  6833. #ifdef CONFIG_PM
  6834. .suspend = iwl3945_pci_suspend,
  6835. .resume = iwl3945_pci_resume,
  6836. #endif
  6837. };
  6838. static int __init iwl3945_init(void)
  6839. {
  6840. int ret;
  6841. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6842. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6843. ret = iwl3945_rate_control_register();
  6844. if (ret) {
  6845. printk(KERN_ERR DRV_NAME
  6846. "Unable to register rate control algorithm: %d\n", ret);
  6847. return ret;
  6848. }
  6849. ret = pci_register_driver(&iwl3945_driver);
  6850. if (ret) {
  6851. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6852. goto error_register;
  6853. }
  6854. return ret;
  6855. error_register:
  6856. iwl3945_rate_control_unregister();
  6857. return ret;
  6858. }
  6859. static void __exit iwl3945_exit(void)
  6860. {
  6861. pci_unregister_driver(&iwl3945_driver);
  6862. iwl3945_rate_control_unregister();
  6863. }
  6864. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6865. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6866. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6867. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6868. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6869. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6870. MODULE_PARM_DESC(hwcrypto,
  6871. "using hardware crypto engine (default 0 [software])\n");
  6872. module_param_named(debug, iwl3945_param_debug, uint, 0444);
  6873. MODULE_PARM_DESC(debug, "debug output mask");
  6874. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6875. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6876. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6877. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6878. module_exit(iwl3945_exit);
  6879. module_init(iwl3945_init);