cx23885.h 21 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/pci.h>
  22. #include <linux/i2c.h>
  23. #include <linux/kdev_t.h>
  24. #include <linux/slab.h>
  25. #include <media/v4l2-device.h>
  26. #include <media/tuner.h>
  27. #include <media/tveeprom.h>
  28. #include <media/videobuf-dma-sg.h>
  29. #include <media/videobuf-dvb.h>
  30. #include <media/rc-core.h>
  31. #include "btcx-risc.h"
  32. #include "cx23885-reg.h"
  33. #include "media/cx2341x.h"
  34. #include <linux/mutex.h>
  35. #define CX23885_VERSION "0.0.3"
  36. #define UNSET (-1U)
  37. #define CX23885_MAXBOARDS 8
  38. /* Max number of inputs by card */
  39. #define MAX_CX23885_INPUT 8
  40. #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
  41. #define RESOURCE_OVERLAY 1
  42. #define RESOURCE_VIDEO 2
  43. #define RESOURCE_VBI 4
  44. #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
  45. #define CX23885_BOARD_NOAUTO UNSET
  46. #define CX23885_BOARD_UNKNOWN 0
  47. #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
  48. #define CX23885_BOARD_HAUPPAUGE_HVR1800 2
  49. #define CX23885_BOARD_HAUPPAUGE_HVR1250 3
  50. #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
  51. #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
  52. #define CX23885_BOARD_HAUPPAUGE_HVR1500 6
  53. #define CX23885_BOARD_HAUPPAUGE_HVR1200 7
  54. #define CX23885_BOARD_HAUPPAUGE_HVR1700 8
  55. #define CX23885_BOARD_HAUPPAUGE_HVR1400 9
  56. #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
  57. #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
  58. #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
  59. #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
  60. #define CX23885_BOARD_TBS_6920 14
  61. #define CX23885_BOARD_TEVII_S470 15
  62. #define CX23885_BOARD_DVBWORLD_2005 16
  63. #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
  64. #define CX23885_BOARD_HAUPPAUGE_HVR1270 18
  65. #define CX23885_BOARD_HAUPPAUGE_HVR1275 19
  66. #define CX23885_BOARD_HAUPPAUGE_HVR1255 20
  67. #define CX23885_BOARD_HAUPPAUGE_HVR1210 21
  68. #define CX23885_BOARD_MYGICA_X8506 22
  69. #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
  70. #define CX23885_BOARD_HAUPPAUGE_HVR1850 24
  71. #define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
  72. #define CX23885_BOARD_HAUPPAUGE_HVR1290 26
  73. #define CX23885_BOARD_MYGICA_X8558PRO 27
  74. #define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
  75. #define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
  76. #define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
  77. #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
  78. #define CX23885_BOARD_MPX885 32
  79. #define CX23885_BOARD_MYGICA_X8507 33
  80. #define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
  81. #define CX23885_BOARD_TEVII_S471 35
  82. #define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
  83. #define CX23885_BOARD_PROF_8000 37
  84. #define CX23885_BOARD_HAUPPAUGE_HVR4400 38
  85. #define CX23885_BOARD_AVERMEDIA_HC81R 39
  86. #define CX23885_BOARD_TBS_6981 40
  87. #define CX23885_BOARD_TBS_6980 41
  88. #define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
  89. #define GPIO_0 0x00000001
  90. #define GPIO_1 0x00000002
  91. #define GPIO_2 0x00000004
  92. #define GPIO_3 0x00000008
  93. #define GPIO_4 0x00000010
  94. #define GPIO_5 0x00000020
  95. #define GPIO_6 0x00000040
  96. #define GPIO_7 0x00000080
  97. #define GPIO_8 0x00000100
  98. #define GPIO_9 0x00000200
  99. #define GPIO_10 0x00000400
  100. #define GPIO_11 0x00000800
  101. #define GPIO_12 0x00001000
  102. #define GPIO_13 0x00002000
  103. #define GPIO_14 0x00004000
  104. #define GPIO_15 0x00008000
  105. /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
  106. #define CX23885_NORMS (\
  107. V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
  108. V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
  109. V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
  110. V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
  111. struct cx23885_fmt {
  112. char *name;
  113. u32 fourcc; /* v4l2 format id */
  114. int depth;
  115. int flags;
  116. u32 cxformat;
  117. };
  118. struct cx23885_ctrl {
  119. struct v4l2_queryctrl v;
  120. u32 off;
  121. u32 reg;
  122. u32 mask;
  123. u32 shift;
  124. };
  125. struct cx23885_tvnorm {
  126. char *name;
  127. v4l2_std_id id;
  128. u32 cxiformat;
  129. u32 cxoformat;
  130. };
  131. struct cx23885_fh {
  132. struct cx23885_dev *dev;
  133. enum v4l2_buf_type type;
  134. int radio;
  135. u32 resources;
  136. /* video overlay */
  137. struct v4l2_window win;
  138. struct v4l2_clip *clips;
  139. unsigned int nclips;
  140. /* video capture */
  141. struct cx23885_fmt *fmt;
  142. unsigned int width, height;
  143. /* vbi capture */
  144. struct videobuf_queue vidq;
  145. struct videobuf_queue vbiq;
  146. /* MPEG Encoder specifics ONLY */
  147. struct videobuf_queue mpegq;
  148. atomic_t v4l_reading;
  149. };
  150. enum cx23885_itype {
  151. CX23885_VMUX_COMPOSITE1 = 1,
  152. CX23885_VMUX_COMPOSITE2,
  153. CX23885_VMUX_COMPOSITE3,
  154. CX23885_VMUX_COMPOSITE4,
  155. CX23885_VMUX_SVIDEO,
  156. CX23885_VMUX_COMPONENT,
  157. CX23885_VMUX_TELEVISION,
  158. CX23885_VMUX_CABLE,
  159. CX23885_VMUX_DVB,
  160. CX23885_VMUX_DEBUG,
  161. CX23885_RADIO,
  162. };
  163. enum cx23885_src_sel_type {
  164. CX23885_SRC_SEL_EXT_656_VIDEO = 0,
  165. CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
  166. };
  167. /* buffer for one video frame */
  168. struct cx23885_buffer {
  169. /* common v4l buffer stuff -- must be first */
  170. struct videobuf_buffer vb;
  171. /* cx23885 specific */
  172. unsigned int bpl;
  173. struct btcx_riscmem risc;
  174. struct cx23885_fmt *fmt;
  175. u32 count;
  176. };
  177. struct cx23885_input {
  178. enum cx23885_itype type;
  179. unsigned int vmux;
  180. unsigned int amux;
  181. u32 gpio0, gpio1, gpio2, gpio3;
  182. };
  183. typedef enum {
  184. CX23885_MPEG_UNDEFINED = 0,
  185. CX23885_MPEG_DVB,
  186. CX23885_ANALOG_VIDEO,
  187. CX23885_MPEG_ENCODER,
  188. } port_t;
  189. struct cx23885_board {
  190. char *name;
  191. port_t porta, portb, portc;
  192. int num_fds_portb, num_fds_portc;
  193. unsigned int tuner_type;
  194. unsigned int radio_type;
  195. unsigned char tuner_addr;
  196. unsigned char radio_addr;
  197. unsigned int tuner_bus;
  198. /* Vendors can and do run the PCIe bridge at different
  199. * clock rates, driven physically by crystals on the PCBs.
  200. * The core has to accommodate this. This allows the user
  201. * to add new boards with new frequencys. The value is
  202. * expressed in Hz.
  203. *
  204. * The core framework will default this value based on
  205. * current designs, but it can vary.
  206. */
  207. u32 clk_freq;
  208. struct cx23885_input input[MAX_CX23885_INPUT];
  209. int ci_type; /* for NetUP */
  210. /* Force bottom field first during DMA (888 workaround) */
  211. u32 force_bff;
  212. };
  213. struct cx23885_subid {
  214. u16 subvendor;
  215. u16 subdevice;
  216. u32 card;
  217. };
  218. struct cx23885_i2c {
  219. struct cx23885_dev *dev;
  220. int nr;
  221. /* i2c i/o */
  222. struct i2c_adapter i2c_adap;
  223. struct i2c_client i2c_client;
  224. u32 i2c_rc;
  225. /* 885 registers used for raw addess */
  226. u32 i2c_period;
  227. u32 reg_ctrl;
  228. u32 reg_stat;
  229. u32 reg_addr;
  230. u32 reg_rdata;
  231. u32 reg_wdata;
  232. };
  233. struct cx23885_dmaqueue {
  234. struct list_head active;
  235. struct list_head queued;
  236. struct timer_list timeout;
  237. struct btcx_riscmem stopper;
  238. u32 count;
  239. };
  240. struct cx23885_tsport {
  241. struct cx23885_dev *dev;
  242. int nr;
  243. int sram_chno;
  244. struct videobuf_dvb_frontends frontends;
  245. /* dma queues */
  246. struct cx23885_dmaqueue mpegq;
  247. u32 ts_packet_size;
  248. u32 ts_packet_count;
  249. int width;
  250. int height;
  251. spinlock_t slock;
  252. /* registers */
  253. u32 reg_gpcnt;
  254. u32 reg_gpcnt_ctl;
  255. u32 reg_dma_ctl;
  256. u32 reg_lngth;
  257. u32 reg_hw_sop_ctrl;
  258. u32 reg_gen_ctrl;
  259. u32 reg_bd_pkt_status;
  260. u32 reg_sop_status;
  261. u32 reg_fifo_ovfl_stat;
  262. u32 reg_vld_misc;
  263. u32 reg_ts_clk_en;
  264. u32 reg_ts_int_msk;
  265. u32 reg_ts_int_stat;
  266. u32 reg_src_sel;
  267. /* Default register vals */
  268. int pci_irqmask;
  269. u32 dma_ctl_val;
  270. u32 ts_int_msk_val;
  271. u32 gen_ctrl_val;
  272. u32 ts_clk_en_val;
  273. u32 src_sel_val;
  274. u32 vld_misc_val;
  275. u32 hw_sop_ctrl_val;
  276. /* Allow a single tsport to have multiple frontends */
  277. u32 num_frontends;
  278. void (*gate_ctrl)(struct cx23885_tsport *port, int open);
  279. void *port_priv;
  280. /* Workaround for a temp dvb_frontend that the tuner can attached to */
  281. struct dvb_frontend analog_fe;
  282. int (*set_frontend)(struct dvb_frontend *fe);
  283. };
  284. struct cx23885_kernel_ir {
  285. struct cx23885_dev *cx;
  286. char *name;
  287. char *phys;
  288. struct rc_dev *rc;
  289. };
  290. struct cx23885_audio_buffer {
  291. unsigned int bpl;
  292. struct btcx_riscmem risc;
  293. struct videobuf_dmabuf dma;
  294. };
  295. struct cx23885_audio_dev {
  296. struct cx23885_dev *dev;
  297. struct pci_dev *pci;
  298. struct snd_card *card;
  299. spinlock_t lock;
  300. atomic_t count;
  301. unsigned int dma_size;
  302. unsigned int period_size;
  303. unsigned int num_periods;
  304. struct videobuf_dmabuf *dma_risc;
  305. struct cx23885_audio_buffer *buf;
  306. struct snd_pcm_substream *substream;
  307. };
  308. struct cx23885_dev {
  309. atomic_t refcount;
  310. struct v4l2_device v4l2_dev;
  311. /* pci stuff */
  312. struct pci_dev *pci;
  313. unsigned char pci_rev, pci_lat;
  314. int pci_bus, pci_slot;
  315. u32 __iomem *lmmio;
  316. u8 __iomem *bmmio;
  317. int pci_irqmask;
  318. spinlock_t pci_irqmask_lock; /* protects mask reg too */
  319. int hwrevision;
  320. /* This valud is board specific and is used to configure the
  321. * AV core so we see nice clean and stable video and audio. */
  322. u32 clk_freq;
  323. /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
  324. struct cx23885_i2c i2c_bus[3];
  325. int nr;
  326. struct mutex lock;
  327. struct mutex gpio_lock;
  328. /* board details */
  329. unsigned int board;
  330. char name[32];
  331. struct cx23885_tsport ts1, ts2;
  332. /* sram configuration */
  333. struct sram_channel *sram_channels;
  334. enum {
  335. CX23885_BRIDGE_UNDEFINED = 0,
  336. CX23885_BRIDGE_885 = 885,
  337. CX23885_BRIDGE_887 = 887,
  338. CX23885_BRIDGE_888 = 888,
  339. } bridge;
  340. /* Analog video */
  341. u32 resources;
  342. unsigned int input;
  343. unsigned int audinput; /* Selectable audio input */
  344. u32 tvaudio;
  345. v4l2_std_id tvnorm;
  346. unsigned int tuner_type;
  347. unsigned char tuner_addr;
  348. unsigned int tuner_bus;
  349. unsigned int radio_type;
  350. unsigned char radio_addr;
  351. unsigned int has_radio;
  352. struct v4l2_subdev *sd_cx25840;
  353. struct work_struct cx25840_work;
  354. /* Infrared */
  355. struct v4l2_subdev *sd_ir;
  356. struct work_struct ir_rx_work;
  357. unsigned long ir_rx_notifications;
  358. struct work_struct ir_tx_work;
  359. unsigned long ir_tx_notifications;
  360. struct cx23885_kernel_ir *kernel_ir;
  361. atomic_t ir_input_stopping;
  362. /* V4l */
  363. u32 freq;
  364. struct video_device *video_dev;
  365. struct video_device *vbi_dev;
  366. struct video_device *radio_dev;
  367. struct cx23885_dmaqueue vidq;
  368. struct cx23885_dmaqueue vbiq;
  369. spinlock_t slock;
  370. /* MPEG Encoder ONLY settings */
  371. u32 cx23417_mailbox;
  372. struct cx2341x_mpeg_params mpeg_params;
  373. struct video_device *v4l_device;
  374. atomic_t v4l_reader_count;
  375. struct cx23885_tvnorm encodernorm;
  376. /* Analog raw audio */
  377. struct cx23885_audio_dev *audio_dev;
  378. };
  379. static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
  380. {
  381. return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
  382. }
  383. #define call_all(dev, o, f, args...) \
  384. v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
  385. #define CX23885_HW_888_IR (1 << 0)
  386. #define CX23885_HW_AV_CORE (1 << 1)
  387. #define call_hw(dev, grpid, o, f, args...) \
  388. v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
  389. extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
  390. #define SRAM_CH01 0 /* Video A */
  391. #define SRAM_CH02 1 /* VBI A */
  392. #define SRAM_CH03 2 /* Video B */
  393. #define SRAM_CH04 3 /* Transport via B */
  394. #define SRAM_CH05 4 /* VBI B */
  395. #define SRAM_CH06 5 /* Video C */
  396. #define SRAM_CH07 6 /* Transport via C */
  397. #define SRAM_CH08 7 /* Audio Internal A */
  398. #define SRAM_CH09 8 /* Audio Internal B */
  399. #define SRAM_CH10 9 /* Audio External */
  400. #define SRAM_CH11 10 /* COMB_3D_N */
  401. #define SRAM_CH12 11 /* Comb 3D N1 */
  402. #define SRAM_CH13 12 /* Comb 3D N2 */
  403. #define SRAM_CH14 13 /* MOE Vid */
  404. #define SRAM_CH15 14 /* MOE RSLT */
  405. struct sram_channel {
  406. char *name;
  407. u32 cmds_start;
  408. u32 ctrl_start;
  409. u32 cdt;
  410. u32 fifo_start;
  411. u32 fifo_size;
  412. u32 ptr1_reg;
  413. u32 ptr2_reg;
  414. u32 cnt1_reg;
  415. u32 cnt2_reg;
  416. u32 jumponly;
  417. };
  418. /* ----------------------------------------------------------- */
  419. #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
  420. #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
  421. #define cx_andor(reg, mask, value) \
  422. writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
  423. ((value) & (mask)), dev->lmmio+((reg)>>2))
  424. #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
  425. #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
  426. /* ----------------------------------------------------------- */
  427. /* cx23885-core.c */
  428. extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
  429. struct sram_channel *ch,
  430. unsigned int bpl, u32 risc);
  431. extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
  432. struct sram_channel *ch);
  433. extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
  434. u32 reg, u32 mask, u32 value);
  435. extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
  436. struct scatterlist *sglist,
  437. unsigned int top_offset, unsigned int bottom_offset,
  438. unsigned int bpl, unsigned int padding, unsigned int lines);
  439. extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
  440. struct btcx_riscmem *risc, struct scatterlist *sglist,
  441. unsigned int top_offset, unsigned int bottom_offset,
  442. unsigned int bpl, unsigned int padding, unsigned int lines);
  443. void cx23885_cancel_buffers(struct cx23885_tsport *port);
  444. extern int cx23885_restart_queue(struct cx23885_tsport *port,
  445. struct cx23885_dmaqueue *q);
  446. extern void cx23885_wakeup(struct cx23885_tsport *port,
  447. struct cx23885_dmaqueue *q, u32 count);
  448. extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
  449. extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
  450. extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
  451. extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
  452. int asoutput);
  453. extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
  454. extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
  455. extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
  456. extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
  457. /* ----------------------------------------------------------- */
  458. /* cx23885-cards.c */
  459. extern struct cx23885_board cx23885_boards[];
  460. extern const unsigned int cx23885_bcount;
  461. extern struct cx23885_subid cx23885_subids[];
  462. extern const unsigned int cx23885_idcount;
  463. extern int cx23885_tuner_callback(void *priv, int component,
  464. int command, int arg);
  465. extern void cx23885_card_list(struct cx23885_dev *dev);
  466. extern int cx23885_ir_init(struct cx23885_dev *dev);
  467. extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
  468. extern void cx23885_ir_fini(struct cx23885_dev *dev);
  469. extern void cx23885_gpio_setup(struct cx23885_dev *dev);
  470. extern void cx23885_card_setup(struct cx23885_dev *dev);
  471. extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
  472. extern int cx23885_dvb_register(struct cx23885_tsport *port);
  473. extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
  474. extern int cx23885_buf_prepare(struct videobuf_queue *q,
  475. struct cx23885_tsport *port,
  476. struct cx23885_buffer *buf,
  477. enum v4l2_field field);
  478. extern void cx23885_buf_queue(struct cx23885_tsport *port,
  479. struct cx23885_buffer *buf);
  480. extern void cx23885_free_buffer(struct videobuf_queue *q,
  481. struct cx23885_buffer *buf);
  482. /* ----------------------------------------------------------- */
  483. /* cx23885-video.c */
  484. /* Video */
  485. extern int cx23885_video_register(struct cx23885_dev *dev);
  486. extern void cx23885_video_unregister(struct cx23885_dev *dev);
  487. extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
  488. extern void cx23885_video_wakeup(struct cx23885_dev *dev,
  489. struct cx23885_dmaqueue *q, u32 count);
  490. int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
  491. int cx23885_set_input(struct file *file, void *priv, unsigned int i);
  492. int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
  493. int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
  494. int cx23885_set_control(struct cx23885_dev *dev, struct v4l2_control *ctl);
  495. int cx23885_get_control(struct cx23885_dev *dev, struct v4l2_control *ctl);
  496. int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
  497. /* ----------------------------------------------------------- */
  498. /* cx23885-vbi.c */
  499. extern int cx23885_vbi_fmt(struct file *file, void *priv,
  500. struct v4l2_format *f);
  501. extern void cx23885_vbi_timeout(unsigned long data);
  502. extern struct videobuf_queue_ops cx23885_vbi_qops;
  503. extern int cx23885_restart_vbi_queue(struct cx23885_dev *dev,
  504. struct cx23885_dmaqueue *q);
  505. extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
  506. /* cx23885-i2c.c */
  507. extern int cx23885_i2c_register(struct cx23885_i2c *bus);
  508. extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
  509. extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
  510. /* ----------------------------------------------------------- */
  511. /* cx23885-417.c */
  512. extern int cx23885_417_register(struct cx23885_dev *dev);
  513. extern void cx23885_417_unregister(struct cx23885_dev *dev);
  514. extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
  515. extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
  516. extern void cx23885_mc417_init(struct cx23885_dev *dev);
  517. extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
  518. extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
  519. extern int mc417_register_read(struct cx23885_dev *dev,
  520. u16 address, u32 *value);
  521. extern int mc417_register_write(struct cx23885_dev *dev,
  522. u16 address, u32 value);
  523. extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
  524. extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
  525. extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
  526. /* ----------------------------------------------------------- */
  527. /* cx23885-alsa.c */
  528. extern struct cx23885_audio_dev *cx23885_audio_register(
  529. struct cx23885_dev *dev);
  530. extern void cx23885_audio_unregister(struct cx23885_dev *dev);
  531. extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
  532. extern int cx23885_risc_databuffer(struct pci_dev *pci,
  533. struct btcx_riscmem *risc,
  534. struct scatterlist *sglist,
  535. unsigned int bpl,
  536. unsigned int lines,
  537. unsigned int lpi);
  538. /* ----------------------------------------------------------- */
  539. /* tv norms */
  540. static inline unsigned int norm_maxw(v4l2_std_id norm)
  541. {
  542. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
  543. }
  544. static inline unsigned int norm_maxh(v4l2_std_id norm)
  545. {
  546. return (norm & V4L2_STD_625_50) ? 576 : 480;
  547. }
  548. static inline unsigned int norm_swidth(v4l2_std_id norm)
  549. {
  550. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
  551. }