smsc911x.c 56 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. ***************************************************************************
  21. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  22. * Partly uses io macros from smc91x.c by Nicolas Pitre
  23. *
  24. * Supported devices:
  25. * LAN9115, LAN9116, LAN9117, LAN9118
  26. * LAN9215, LAN9216, LAN9217, LAN9218
  27. * LAN9210, LAN9211
  28. * LAN9220, LAN9221
  29. *
  30. */
  31. #include <linux/crc32.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/ethtool.h>
  36. #include <linux/init.h>
  37. #include <linux/ioport.h>
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/sched.h>
  43. #include <linux/slab.h>
  44. #include <linux/timer.h>
  45. #include <linux/version.h>
  46. #include <linux/bug.h>
  47. #include <linux/bitops.h>
  48. #include <linux/irq.h>
  49. #include <linux/io.h>
  50. #include <linux/phy.h>
  51. #include <linux/smsc911x.h>
  52. #include "smsc911x.h"
  53. #define SMSC_CHIPNAME "smsc911x"
  54. #define SMSC_MDIONAME "smsc911x-mdio"
  55. #define SMSC_DRV_VERSION "2008-10-21"
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(SMSC_DRV_VERSION);
  58. #if USE_DEBUG > 0
  59. static int debug = 16;
  60. #else
  61. static int debug = 3;
  62. #endif
  63. module_param(debug, int, 0);
  64. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  65. struct smsc911x_data {
  66. void __iomem *ioaddr;
  67. unsigned int idrev;
  68. /* used to decide which workarounds apply */
  69. unsigned int generation;
  70. /* device configuration (copied from platform_data during probe) */
  71. struct smsc911x_platform_config config;
  72. /* This needs to be acquired before calling any of below:
  73. * smsc911x_mac_read(), smsc911x_mac_write()
  74. */
  75. spinlock_t mac_lock;
  76. /* spinlock to ensure 16-bit accesses are serialised.
  77. * unused with a 32-bit bus */
  78. spinlock_t dev_lock;
  79. struct phy_device *phy_dev;
  80. struct mii_bus *mii_bus;
  81. int phy_irq[PHY_MAX_ADDR];
  82. unsigned int using_extphy;
  83. int last_duplex;
  84. int last_carrier;
  85. u32 msg_enable;
  86. unsigned int gpio_setting;
  87. unsigned int gpio_orig_setting;
  88. struct net_device *dev;
  89. struct napi_struct napi;
  90. unsigned int software_irq_signal;
  91. #ifdef USE_PHY_WORK_AROUND
  92. #define MIN_PACKET_SIZE (64)
  93. char loopback_tx_pkt[MIN_PACKET_SIZE];
  94. char loopback_rx_pkt[MIN_PACKET_SIZE];
  95. unsigned int resetcount;
  96. #endif
  97. /* Members for Multicast filter workaround */
  98. unsigned int multicast_update_pending;
  99. unsigned int set_bits_mask;
  100. unsigned int clear_bits_mask;
  101. unsigned int hashhi;
  102. unsigned int hashlo;
  103. };
  104. /* The 16-bit access functions are significantly slower, due to the locking
  105. * necessary. If your bus hardware can be configured to do this for you
  106. * (in response to a single 32-bit operation from software), you should use
  107. * the 32-bit access functions instead. */
  108. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  109. {
  110. if (pdata->config.flags & SMSC911X_USE_32BIT)
  111. return readl(pdata->ioaddr + reg);
  112. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  113. u32 data;
  114. unsigned long flags;
  115. /* these two 16-bit reads must be performed consecutively, so
  116. * must not be interrupted by our own ISR (which would start
  117. * another read operation) */
  118. spin_lock_irqsave(&pdata->dev_lock, flags);
  119. data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  120. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  121. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  122. return data;
  123. }
  124. BUG();
  125. return 0;
  126. }
  127. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  128. u32 val)
  129. {
  130. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  131. writel(val, pdata->ioaddr + reg);
  132. return;
  133. }
  134. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  135. unsigned long flags;
  136. /* these two 16-bit writes must be performed consecutively, so
  137. * must not be interrupted by our own ISR (which would start
  138. * another read operation) */
  139. spin_lock_irqsave(&pdata->dev_lock, flags);
  140. writew(val & 0xFFFF, pdata->ioaddr + reg);
  141. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  142. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  143. return;
  144. }
  145. BUG();
  146. }
  147. /* Writes a packet to the TX_DATA_FIFO */
  148. static inline void
  149. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  150. unsigned int wordcount)
  151. {
  152. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  153. writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  154. return;
  155. }
  156. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  157. while (wordcount--)
  158. smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  159. return;
  160. }
  161. BUG();
  162. }
  163. /* Reads a packet out of the RX_DATA_FIFO */
  164. static inline void
  165. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  166. unsigned int wordcount)
  167. {
  168. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  169. readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  170. return;
  171. }
  172. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  173. while (wordcount--)
  174. *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  175. return;
  176. }
  177. BUG();
  178. }
  179. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  180. * and smsc911x_mac_write, so assumes mac_lock is held */
  181. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  182. {
  183. int i;
  184. u32 val;
  185. SMSC_ASSERT_MAC_LOCK(pdata);
  186. for (i = 0; i < 40; i++) {
  187. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  188. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  189. return 0;
  190. }
  191. SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
  192. "MAC_CSR_CMD: 0x%08X", val);
  193. return -EIO;
  194. }
  195. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  196. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  197. {
  198. unsigned int temp;
  199. SMSC_ASSERT_MAC_LOCK(pdata);
  200. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  201. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  202. SMSC_WARNING(HW, "MAC busy at entry");
  203. return 0xFFFFFFFF;
  204. }
  205. /* Send the MAC cmd */
  206. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  207. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  208. /* Workaround for hardware read-after-write restriction */
  209. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  210. /* Wait for the read to complete */
  211. if (likely(smsc911x_mac_complete(pdata) == 0))
  212. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  213. SMSC_WARNING(HW, "MAC busy after read");
  214. return 0xFFFFFFFF;
  215. }
  216. /* Set a mac register, mac_lock must be acquired before calling */
  217. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  218. unsigned int offset, u32 val)
  219. {
  220. unsigned int temp;
  221. SMSC_ASSERT_MAC_LOCK(pdata);
  222. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  223. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  224. SMSC_WARNING(HW,
  225. "smsc911x_mac_write failed, MAC busy at entry");
  226. return;
  227. }
  228. /* Send data to write */
  229. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  230. /* Write the actual data */
  231. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  232. MAC_CSR_CMD_CSR_BUSY_));
  233. /* Workaround for hardware read-after-write restriction */
  234. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  235. /* Wait for the write to complete */
  236. if (likely(smsc911x_mac_complete(pdata) == 0))
  237. return;
  238. SMSC_WARNING(HW,
  239. "smsc911x_mac_write failed, MAC busy after write");
  240. }
  241. /* Get a phy register */
  242. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  243. {
  244. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  245. unsigned long flags;
  246. unsigned int addr;
  247. int i, reg;
  248. spin_lock_irqsave(&pdata->mac_lock, flags);
  249. /* Confirm MII not busy */
  250. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  251. SMSC_WARNING(HW,
  252. "MII is busy in smsc911x_mii_read???");
  253. reg = -EIO;
  254. goto out;
  255. }
  256. /* Set the address, index & direction (read from PHY) */
  257. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  258. smsc911x_mac_write(pdata, MII_ACC, addr);
  259. /* Wait for read to complete w/ timeout */
  260. for (i = 0; i < 100; i++)
  261. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  262. reg = smsc911x_mac_read(pdata, MII_DATA);
  263. goto out;
  264. }
  265. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  266. reg = -EIO;
  267. out:
  268. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  269. return reg;
  270. }
  271. /* Set a phy register */
  272. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  273. u16 val)
  274. {
  275. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  276. unsigned long flags;
  277. unsigned int addr;
  278. int i, reg;
  279. spin_lock_irqsave(&pdata->mac_lock, flags);
  280. /* Confirm MII not busy */
  281. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  282. SMSC_WARNING(HW,
  283. "MII is busy in smsc911x_mii_write???");
  284. reg = -EIO;
  285. goto out;
  286. }
  287. /* Put the data to write in the MAC */
  288. smsc911x_mac_write(pdata, MII_DATA, val);
  289. /* Set the address, index & direction (write to PHY) */
  290. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  291. MII_ACC_MII_WRITE_;
  292. smsc911x_mac_write(pdata, MII_ACC, addr);
  293. /* Wait for write to complete w/ timeout */
  294. for (i = 0; i < 100; i++)
  295. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  296. reg = 0;
  297. goto out;
  298. }
  299. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  300. reg = -EIO;
  301. out:
  302. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  303. return reg;
  304. }
  305. /* Switch to external phy. Assumes tx and rx are stopped. */
  306. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  307. {
  308. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  309. /* Disable phy clocks to the MAC */
  310. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  311. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  312. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  313. udelay(10); /* Enough time for clocks to stop */
  314. /* Switch to external phy */
  315. hwcfg |= HW_CFG_EXT_PHY_EN_;
  316. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  317. /* Enable phy clocks to the MAC */
  318. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  319. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  320. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  321. udelay(10); /* Enough time for clocks to restart */
  322. hwcfg |= HW_CFG_SMI_SEL_;
  323. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  324. }
  325. /* Autodetects and enables external phy if present on supported chips.
  326. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  327. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  328. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  329. {
  330. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  331. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  332. SMSC_TRACE(HW, "Forcing internal PHY");
  333. pdata->using_extphy = 0;
  334. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  335. SMSC_TRACE(HW, "Forcing external PHY");
  336. smsc911x_phy_enable_external(pdata);
  337. pdata->using_extphy = 1;
  338. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  339. SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
  340. smsc911x_phy_enable_external(pdata);
  341. pdata->using_extphy = 1;
  342. } else {
  343. SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
  344. pdata->using_extphy = 0;
  345. }
  346. }
  347. /* Fetches a tx status out of the status fifo */
  348. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  349. {
  350. unsigned int result =
  351. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  352. if (result != 0)
  353. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  354. return result;
  355. }
  356. /* Fetches the next rx status */
  357. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  358. {
  359. unsigned int result =
  360. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  361. if (result != 0)
  362. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  363. return result;
  364. }
  365. #ifdef USE_PHY_WORK_AROUND
  366. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  367. {
  368. unsigned int tries;
  369. u32 wrsz;
  370. u32 rdsz;
  371. ulong bufp;
  372. for (tries = 0; tries < 10; tries++) {
  373. unsigned int txcmd_a;
  374. unsigned int txcmd_b;
  375. unsigned int status;
  376. unsigned int pktlength;
  377. unsigned int i;
  378. /* Zero-out rx packet memory */
  379. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  380. /* Write tx packet to 118 */
  381. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  382. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  383. txcmd_a |= MIN_PACKET_SIZE;
  384. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  385. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  386. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  387. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  388. wrsz = MIN_PACKET_SIZE + 3;
  389. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  390. wrsz >>= 2;
  391. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  392. /* Wait till transmit is done */
  393. i = 60;
  394. do {
  395. udelay(5);
  396. status = smsc911x_tx_get_txstatus(pdata);
  397. } while ((i--) && (!status));
  398. if (!status) {
  399. SMSC_WARNING(HW, "Failed to transmit "
  400. "during loopback test");
  401. continue;
  402. }
  403. if (status & TX_STS_ES_) {
  404. SMSC_WARNING(HW, "Transmit encountered "
  405. "errors during loopback test");
  406. continue;
  407. }
  408. /* Wait till receive is done */
  409. i = 60;
  410. do {
  411. udelay(5);
  412. status = smsc911x_rx_get_rxstatus(pdata);
  413. } while ((i--) && (!status));
  414. if (!status) {
  415. SMSC_WARNING(HW,
  416. "Failed to receive during loopback test");
  417. continue;
  418. }
  419. if (status & RX_STS_ES_) {
  420. SMSC_WARNING(HW, "Receive encountered "
  421. "errors during loopback test");
  422. continue;
  423. }
  424. pktlength = ((status & 0x3FFF0000UL) >> 16);
  425. bufp = (ulong)pdata->loopback_rx_pkt;
  426. rdsz = pktlength + 3;
  427. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  428. rdsz >>= 2;
  429. smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  430. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  431. SMSC_WARNING(HW, "Unexpected packet size "
  432. "during loop back test, size=%d, will retry",
  433. pktlength);
  434. } else {
  435. unsigned int j;
  436. int mismatch = 0;
  437. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  438. if (pdata->loopback_tx_pkt[j]
  439. != pdata->loopback_rx_pkt[j]) {
  440. mismatch = 1;
  441. break;
  442. }
  443. }
  444. if (!mismatch) {
  445. SMSC_TRACE(HW, "Successfully verified "
  446. "loopback packet");
  447. return 0;
  448. } else {
  449. SMSC_WARNING(HW, "Data mismatch "
  450. "during loop back test, will retry");
  451. }
  452. }
  453. }
  454. return -EIO;
  455. }
  456. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  457. {
  458. struct phy_device *phy_dev = pdata->phy_dev;
  459. unsigned int temp;
  460. unsigned int i = 100000;
  461. BUG_ON(!phy_dev);
  462. BUG_ON(!phy_dev->bus);
  463. SMSC_TRACE(HW, "Performing PHY BCR Reset");
  464. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  465. do {
  466. msleep(1);
  467. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  468. MII_BMCR);
  469. } while ((i--) && (temp & BMCR_RESET));
  470. if (temp & BMCR_RESET) {
  471. SMSC_WARNING(HW, "PHY reset failed to complete.");
  472. return -EIO;
  473. }
  474. /* Extra delay required because the phy may not be completed with
  475. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  476. * enough delay but using 1ms here to be safe */
  477. msleep(1);
  478. return 0;
  479. }
  480. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  481. {
  482. struct smsc911x_data *pdata = netdev_priv(dev);
  483. struct phy_device *phy_dev = pdata->phy_dev;
  484. int result = -EIO;
  485. unsigned int i, val;
  486. unsigned long flags;
  487. /* Initialise tx packet using broadcast destination address */
  488. memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
  489. /* Use incrementing source address */
  490. for (i = 6; i < 12; i++)
  491. pdata->loopback_tx_pkt[i] = (char)i;
  492. /* Set length type field */
  493. pdata->loopback_tx_pkt[12] = 0x00;
  494. pdata->loopback_tx_pkt[13] = 0x00;
  495. for (i = 14; i < MIN_PACKET_SIZE; i++)
  496. pdata->loopback_tx_pkt[i] = (char)i;
  497. val = smsc911x_reg_read(pdata, HW_CFG);
  498. val &= HW_CFG_TX_FIF_SZ_;
  499. val |= HW_CFG_SF_;
  500. smsc911x_reg_write(pdata, HW_CFG, val);
  501. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  502. smsc911x_reg_write(pdata, RX_CFG,
  503. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  504. for (i = 0; i < 10; i++) {
  505. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  506. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  507. BMCR_LOOPBACK | BMCR_FULLDPLX);
  508. /* Enable MAC tx/rx, FD */
  509. spin_lock_irqsave(&pdata->mac_lock, flags);
  510. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  511. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  512. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  513. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  514. result = 0;
  515. break;
  516. }
  517. pdata->resetcount++;
  518. /* Disable MAC rx */
  519. spin_lock_irqsave(&pdata->mac_lock, flags);
  520. smsc911x_mac_write(pdata, MAC_CR, 0);
  521. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  522. smsc911x_phy_reset(pdata);
  523. }
  524. /* Disable MAC */
  525. spin_lock_irqsave(&pdata->mac_lock, flags);
  526. smsc911x_mac_write(pdata, MAC_CR, 0);
  527. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  528. /* Cancel PHY loopback mode */
  529. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  530. smsc911x_reg_write(pdata, TX_CFG, 0);
  531. smsc911x_reg_write(pdata, RX_CFG, 0);
  532. return result;
  533. }
  534. #endif /* USE_PHY_WORK_AROUND */
  535. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  536. {
  537. struct phy_device *phy_dev = pdata->phy_dev;
  538. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  539. u32 flow;
  540. unsigned long flags;
  541. if (phy_dev->duplex == DUPLEX_FULL) {
  542. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  543. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  544. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  545. if (cap & FLOW_CTRL_RX)
  546. flow = 0xFFFF0002;
  547. else
  548. flow = 0;
  549. if (cap & FLOW_CTRL_TX)
  550. afc |= 0xF;
  551. else
  552. afc &= ~0xF;
  553. SMSC_TRACE(HW, "rx pause %s, tx pause %s",
  554. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  555. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  556. } else {
  557. SMSC_TRACE(HW, "half duplex");
  558. flow = 0;
  559. afc |= 0xF;
  560. }
  561. spin_lock_irqsave(&pdata->mac_lock, flags);
  562. smsc911x_mac_write(pdata, FLOW, flow);
  563. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  564. smsc911x_reg_write(pdata, AFC_CFG, afc);
  565. }
  566. /* Update link mode if anything has changed. Called periodically when the
  567. * PHY is in polling mode, even if nothing has changed. */
  568. static void smsc911x_phy_adjust_link(struct net_device *dev)
  569. {
  570. struct smsc911x_data *pdata = netdev_priv(dev);
  571. struct phy_device *phy_dev = pdata->phy_dev;
  572. unsigned long flags;
  573. int carrier;
  574. if (phy_dev->duplex != pdata->last_duplex) {
  575. unsigned int mac_cr;
  576. SMSC_TRACE(HW, "duplex state has changed");
  577. spin_lock_irqsave(&pdata->mac_lock, flags);
  578. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  579. if (phy_dev->duplex) {
  580. SMSC_TRACE(HW,
  581. "configuring for full duplex mode");
  582. mac_cr |= MAC_CR_FDPX_;
  583. } else {
  584. SMSC_TRACE(HW,
  585. "configuring for half duplex mode");
  586. mac_cr &= ~MAC_CR_FDPX_;
  587. }
  588. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  589. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  590. smsc911x_phy_update_flowcontrol(pdata);
  591. pdata->last_duplex = phy_dev->duplex;
  592. }
  593. carrier = netif_carrier_ok(dev);
  594. if (carrier != pdata->last_carrier) {
  595. SMSC_TRACE(HW, "carrier state has changed");
  596. if (carrier) {
  597. SMSC_TRACE(HW, "configuring for carrier OK");
  598. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  599. (!pdata->using_extphy)) {
  600. /* Restore orginal GPIO configuration */
  601. pdata->gpio_setting = pdata->gpio_orig_setting;
  602. smsc911x_reg_write(pdata, GPIO_CFG,
  603. pdata->gpio_setting);
  604. }
  605. } else {
  606. SMSC_TRACE(HW, "configuring for no carrier");
  607. /* Check global setting that LED1
  608. * usage is 10/100 indicator */
  609. pdata->gpio_setting = smsc911x_reg_read(pdata,
  610. GPIO_CFG);
  611. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
  612. && (!pdata->using_extphy)) {
  613. /* Force 10/100 LED off, after saving
  614. * orginal GPIO configuration */
  615. pdata->gpio_orig_setting = pdata->gpio_setting;
  616. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  617. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  618. | GPIO_CFG_GPIODIR0_
  619. | GPIO_CFG_GPIOD0_);
  620. smsc911x_reg_write(pdata, GPIO_CFG,
  621. pdata->gpio_setting);
  622. }
  623. }
  624. pdata->last_carrier = carrier;
  625. }
  626. }
  627. static int smsc911x_mii_probe(struct net_device *dev)
  628. {
  629. struct smsc911x_data *pdata = netdev_priv(dev);
  630. struct phy_device *phydev = NULL;
  631. int phy_addr;
  632. /* find the first phy */
  633. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  634. if (pdata->mii_bus->phy_map[phy_addr]) {
  635. phydev = pdata->mii_bus->phy_map[phy_addr];
  636. SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
  637. phy_addr, phydev->addr, phydev->phy_id);
  638. break;
  639. }
  640. }
  641. if (!phydev) {
  642. pr_err("%s: no PHY found\n", dev->name);
  643. return -ENODEV;
  644. }
  645. phydev = phy_connect(dev, dev_name(&phydev->dev),
  646. &smsc911x_phy_adjust_link, 0, pdata->config.phy_interface);
  647. if (IS_ERR(phydev)) {
  648. pr_err("%s: Could not attach to PHY\n", dev->name);
  649. return PTR_ERR(phydev);
  650. }
  651. pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  652. dev->name, phydev->drv->name,
  653. dev_name(&phydev->dev), phydev->irq);
  654. /* mask with MAC supported features */
  655. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  656. SUPPORTED_Asym_Pause);
  657. phydev->advertising = phydev->supported;
  658. pdata->phy_dev = phydev;
  659. pdata->last_duplex = -1;
  660. pdata->last_carrier = -1;
  661. #ifdef USE_PHY_WORK_AROUND
  662. if (smsc911x_phy_loopbacktest(dev) < 0) {
  663. SMSC_WARNING(HW, "Failed Loop Back Test");
  664. return -ENODEV;
  665. }
  666. SMSC_TRACE(HW, "Passed Loop Back Test");
  667. #endif /* USE_PHY_WORK_AROUND */
  668. SMSC_TRACE(HW, "phy initialised succesfully");
  669. return 0;
  670. }
  671. static int __devinit smsc911x_mii_init(struct platform_device *pdev,
  672. struct net_device *dev)
  673. {
  674. struct smsc911x_data *pdata = netdev_priv(dev);
  675. int err = -ENXIO, i;
  676. pdata->mii_bus = mdiobus_alloc();
  677. if (!pdata->mii_bus) {
  678. err = -ENOMEM;
  679. goto err_out_1;
  680. }
  681. pdata->mii_bus->name = SMSC_MDIONAME;
  682. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
  683. pdata->mii_bus->priv = pdata;
  684. pdata->mii_bus->read = smsc911x_mii_read;
  685. pdata->mii_bus->write = smsc911x_mii_write;
  686. pdata->mii_bus->irq = pdata->phy_irq;
  687. for (i = 0; i < PHY_MAX_ADDR; ++i)
  688. pdata->mii_bus->irq[i] = PHY_POLL;
  689. pdata->mii_bus->parent = &pdev->dev;
  690. switch (pdata->idrev & 0xFFFF0000) {
  691. case 0x01170000:
  692. case 0x01150000:
  693. case 0x117A0000:
  694. case 0x115A0000:
  695. /* External PHY supported, try to autodetect */
  696. smsc911x_phy_initialise_external(pdata);
  697. break;
  698. default:
  699. SMSC_TRACE(HW, "External PHY is not supported, "
  700. "using internal PHY");
  701. pdata->using_extphy = 0;
  702. break;
  703. }
  704. if (!pdata->using_extphy) {
  705. /* Mask all PHYs except ID 1 (internal) */
  706. pdata->mii_bus->phy_mask = ~(1 << 1);
  707. }
  708. if (mdiobus_register(pdata->mii_bus)) {
  709. SMSC_WARNING(PROBE, "Error registering mii bus");
  710. goto err_out_free_bus_2;
  711. }
  712. if (smsc911x_mii_probe(dev) < 0) {
  713. SMSC_WARNING(PROBE, "Error registering mii bus");
  714. goto err_out_unregister_bus_3;
  715. }
  716. return 0;
  717. err_out_unregister_bus_3:
  718. mdiobus_unregister(pdata->mii_bus);
  719. err_out_free_bus_2:
  720. mdiobus_free(pdata->mii_bus);
  721. err_out_1:
  722. return err;
  723. }
  724. /* Gets the number of tx statuses in the fifo */
  725. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  726. {
  727. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  728. & TX_FIFO_INF_TSUSED_) >> 16;
  729. }
  730. /* Reads tx statuses and increments counters where necessary */
  731. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  732. {
  733. struct smsc911x_data *pdata = netdev_priv(dev);
  734. unsigned int tx_stat;
  735. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  736. if (unlikely(tx_stat & 0x80000000)) {
  737. /* In this driver the packet tag is used as the packet
  738. * length. Since a packet length can never reach the
  739. * size of 0x8000, this bit is reserved. It is worth
  740. * noting that the "reserved bit" in the warning above
  741. * does not reference a hardware defined reserved bit
  742. * but rather a driver defined one.
  743. */
  744. SMSC_WARNING(HW,
  745. "Packet tag reserved bit is high");
  746. } else {
  747. if (unlikely(tx_stat & TX_STS_ES_)) {
  748. dev->stats.tx_errors++;
  749. } else {
  750. dev->stats.tx_packets++;
  751. dev->stats.tx_bytes += (tx_stat >> 16);
  752. }
  753. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  754. dev->stats.collisions += 16;
  755. dev->stats.tx_aborted_errors += 1;
  756. } else {
  757. dev->stats.collisions +=
  758. ((tx_stat >> 3) & 0xF);
  759. }
  760. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  761. dev->stats.tx_carrier_errors += 1;
  762. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  763. dev->stats.collisions++;
  764. dev->stats.tx_aborted_errors++;
  765. }
  766. }
  767. }
  768. }
  769. /* Increments the Rx error counters */
  770. static void
  771. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  772. {
  773. int crc_err = 0;
  774. if (unlikely(rxstat & RX_STS_ES_)) {
  775. dev->stats.rx_errors++;
  776. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  777. dev->stats.rx_crc_errors++;
  778. crc_err = 1;
  779. }
  780. }
  781. if (likely(!crc_err)) {
  782. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  783. (rxstat & RX_STS_LENGTH_ERR_)))
  784. dev->stats.rx_length_errors++;
  785. if (rxstat & RX_STS_MCAST_)
  786. dev->stats.multicast++;
  787. }
  788. }
  789. /* Quickly dumps bad packets */
  790. static void
  791. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
  792. {
  793. unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
  794. if (likely(pktwords >= 4)) {
  795. unsigned int timeout = 500;
  796. unsigned int val;
  797. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  798. do {
  799. udelay(1);
  800. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  801. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  802. if (unlikely(timeout == 0))
  803. SMSC_WARNING(HW, "Timed out waiting for "
  804. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  805. } else {
  806. unsigned int temp;
  807. while (pktwords--)
  808. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  809. }
  810. }
  811. /* NAPI poll function */
  812. static int smsc911x_poll(struct napi_struct *napi, int budget)
  813. {
  814. struct smsc911x_data *pdata =
  815. container_of(napi, struct smsc911x_data, napi);
  816. struct net_device *dev = pdata->dev;
  817. int npackets = 0;
  818. while (likely(netif_running(dev)) && (npackets < budget)) {
  819. unsigned int pktlength;
  820. unsigned int pktwords;
  821. struct sk_buff *skb;
  822. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  823. if (!rxstat) {
  824. unsigned int temp;
  825. /* We processed all packets available. Tell NAPI it can
  826. * stop polling then re-enable rx interrupts */
  827. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  828. napi_complete(napi);
  829. temp = smsc911x_reg_read(pdata, INT_EN);
  830. temp |= INT_EN_RSFL_EN_;
  831. smsc911x_reg_write(pdata, INT_EN, temp);
  832. break;
  833. }
  834. /* Count packet for NAPI scheduling, even if it has an error.
  835. * Error packets still require cycles to discard */
  836. npackets++;
  837. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  838. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  839. smsc911x_rx_counterrors(dev, rxstat);
  840. if (unlikely(rxstat & RX_STS_ES_)) {
  841. SMSC_WARNING(RX_ERR,
  842. "Discarding packet with error bit set");
  843. /* Packet has an error, discard it and continue with
  844. * the next */
  845. smsc911x_rx_fastforward(pdata, pktwords);
  846. dev->stats.rx_dropped++;
  847. continue;
  848. }
  849. skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
  850. if (unlikely(!skb)) {
  851. SMSC_WARNING(RX_ERR,
  852. "Unable to allocate skb for rx packet");
  853. /* Drop the packet and stop this polling iteration */
  854. smsc911x_rx_fastforward(pdata, pktwords);
  855. dev->stats.rx_dropped++;
  856. break;
  857. }
  858. skb->data = skb->head;
  859. skb_reset_tail_pointer(skb);
  860. /* Align IP on 16B boundary */
  861. skb_reserve(skb, NET_IP_ALIGN);
  862. skb_put(skb, pktlength - 4);
  863. smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
  864. pktwords);
  865. skb->protocol = eth_type_trans(skb, dev);
  866. skb->ip_summed = CHECKSUM_NONE;
  867. netif_receive_skb(skb);
  868. /* Update counters */
  869. dev->stats.rx_packets++;
  870. dev->stats.rx_bytes += (pktlength - 4);
  871. dev->last_rx = jiffies;
  872. }
  873. /* Return total received packets */
  874. return npackets;
  875. }
  876. /* Returns hash bit number for given MAC address
  877. * Example:
  878. * 01 00 5E 00 00 01 -> returns bit number 31 */
  879. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  880. {
  881. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  882. }
  883. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  884. {
  885. /* Performs the multicast & mac_cr update. This is called when
  886. * safe on the current hardware, and with the mac_lock held */
  887. unsigned int mac_cr;
  888. SMSC_ASSERT_MAC_LOCK(pdata);
  889. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  890. mac_cr |= pdata->set_bits_mask;
  891. mac_cr &= ~(pdata->clear_bits_mask);
  892. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  893. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  894. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  895. SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  896. mac_cr, pdata->hashhi, pdata->hashlo);
  897. }
  898. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  899. {
  900. unsigned int mac_cr;
  901. /* This function is only called for older LAN911x devices
  902. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  903. * be modified during Rx - newer devices immediately update the
  904. * registers.
  905. *
  906. * This is called from interrupt context */
  907. spin_lock(&pdata->mac_lock);
  908. /* Check Rx has stopped */
  909. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  910. SMSC_WARNING(DRV, "Rx not stopped");
  911. /* Perform the update - safe to do now Rx has stopped */
  912. smsc911x_rx_multicast_update(pdata);
  913. /* Re-enable Rx */
  914. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  915. mac_cr |= MAC_CR_RXEN_;
  916. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  917. pdata->multicast_update_pending = 0;
  918. spin_unlock(&pdata->mac_lock);
  919. }
  920. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  921. {
  922. unsigned int timeout;
  923. unsigned int temp;
  924. /* Reset the LAN911x */
  925. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  926. timeout = 10;
  927. do {
  928. udelay(10);
  929. temp = smsc911x_reg_read(pdata, HW_CFG);
  930. } while ((--timeout) && (temp & HW_CFG_SRST_));
  931. if (unlikely(temp & HW_CFG_SRST_)) {
  932. SMSC_WARNING(DRV, "Failed to complete reset");
  933. return -EIO;
  934. }
  935. return 0;
  936. }
  937. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  938. static void
  939. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  940. {
  941. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  942. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  943. (dev_addr[1] << 8) | dev_addr[0];
  944. SMSC_ASSERT_MAC_LOCK(pdata);
  945. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  946. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  947. }
  948. static int smsc911x_open(struct net_device *dev)
  949. {
  950. struct smsc911x_data *pdata = netdev_priv(dev);
  951. unsigned int timeout;
  952. unsigned int temp;
  953. unsigned int intcfg;
  954. /* if the phy is not yet registered, retry later*/
  955. if (!pdata->phy_dev) {
  956. SMSC_WARNING(HW, "phy_dev is NULL");
  957. return -EAGAIN;
  958. }
  959. if (!is_valid_ether_addr(dev->dev_addr)) {
  960. SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
  961. return -EADDRNOTAVAIL;
  962. }
  963. /* Reset the LAN911x */
  964. if (smsc911x_soft_reset(pdata)) {
  965. SMSC_WARNING(HW, "soft reset failed");
  966. return -EIO;
  967. }
  968. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  969. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  970. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  971. timeout = 50;
  972. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  973. --timeout) {
  974. udelay(10);
  975. }
  976. if (unlikely(timeout == 0))
  977. SMSC_WARNING(IFUP,
  978. "Timed out waiting for EEPROM busy bit to clear");
  979. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  980. /* The soft reset above cleared the device's MAC address,
  981. * restore it from local copy (set in probe) */
  982. spin_lock_irq(&pdata->mac_lock);
  983. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  984. spin_unlock_irq(&pdata->mac_lock);
  985. /* Initialise irqs, but leave all sources disabled */
  986. smsc911x_reg_write(pdata, INT_EN, 0);
  987. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  988. /* Set interrupt deassertion to 100uS */
  989. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  990. if (pdata->config.irq_polarity) {
  991. SMSC_TRACE(IFUP, "irq polarity: active high");
  992. intcfg |= INT_CFG_IRQ_POL_;
  993. } else {
  994. SMSC_TRACE(IFUP, "irq polarity: active low");
  995. }
  996. if (pdata->config.irq_type) {
  997. SMSC_TRACE(IFUP, "irq type: push-pull");
  998. intcfg |= INT_CFG_IRQ_TYPE_;
  999. } else {
  1000. SMSC_TRACE(IFUP, "irq type: open drain");
  1001. }
  1002. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1003. SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
  1004. pdata->software_irq_signal = 0;
  1005. smp_wmb();
  1006. temp = smsc911x_reg_read(pdata, INT_EN);
  1007. temp |= INT_EN_SW_INT_EN_;
  1008. smsc911x_reg_write(pdata, INT_EN, temp);
  1009. timeout = 1000;
  1010. while (timeout--) {
  1011. if (pdata->software_irq_signal)
  1012. break;
  1013. msleep(1);
  1014. }
  1015. if (!pdata->software_irq_signal) {
  1016. dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
  1017. dev->irq);
  1018. return -ENODEV;
  1019. }
  1020. SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
  1021. dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1022. (unsigned long)pdata->ioaddr, dev->irq);
  1023. /* Reset the last known duplex and carrier */
  1024. pdata->last_duplex = -1;
  1025. pdata->last_carrier = -1;
  1026. /* Bring the PHY up */
  1027. phy_start(pdata->phy_dev);
  1028. temp = smsc911x_reg_read(pdata, HW_CFG);
  1029. /* Preserve TX FIFO size and external PHY configuration */
  1030. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1031. temp |= HW_CFG_SF_;
  1032. smsc911x_reg_write(pdata, HW_CFG, temp);
  1033. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1034. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1035. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1036. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1037. /* set RX Data offset to 2 bytes for alignment */
  1038. smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
  1039. /* enable NAPI polling before enabling RX interrupts */
  1040. napi_enable(&pdata->napi);
  1041. temp = smsc911x_reg_read(pdata, INT_EN);
  1042. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1043. smsc911x_reg_write(pdata, INT_EN, temp);
  1044. spin_lock_irq(&pdata->mac_lock);
  1045. temp = smsc911x_mac_read(pdata, MAC_CR);
  1046. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1047. smsc911x_mac_write(pdata, MAC_CR, temp);
  1048. spin_unlock_irq(&pdata->mac_lock);
  1049. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1050. netif_start_queue(dev);
  1051. return 0;
  1052. }
  1053. /* Entry point for stopping the interface */
  1054. static int smsc911x_stop(struct net_device *dev)
  1055. {
  1056. struct smsc911x_data *pdata = netdev_priv(dev);
  1057. unsigned int temp;
  1058. /* Disable all device interrupts */
  1059. temp = smsc911x_reg_read(pdata, INT_CFG);
  1060. temp &= ~INT_CFG_IRQ_EN_;
  1061. smsc911x_reg_write(pdata, INT_CFG, temp);
  1062. /* Stop Tx and Rx polling */
  1063. netif_stop_queue(dev);
  1064. napi_disable(&pdata->napi);
  1065. /* At this point all Rx and Tx activity is stopped */
  1066. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1067. smsc911x_tx_update_txcounters(dev);
  1068. /* Bring the PHY down */
  1069. if (pdata->phy_dev)
  1070. phy_stop(pdata->phy_dev);
  1071. SMSC_TRACE(IFDOWN, "Interface stopped");
  1072. return 0;
  1073. }
  1074. /* Entry point for transmitting a packet */
  1075. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1076. {
  1077. struct smsc911x_data *pdata = netdev_priv(dev);
  1078. unsigned int freespace;
  1079. unsigned int tx_cmd_a;
  1080. unsigned int tx_cmd_b;
  1081. unsigned int temp;
  1082. u32 wrsz;
  1083. ulong bufp;
  1084. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1085. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1086. SMSC_WARNING(TX_ERR,
  1087. "Tx data fifo low, space available: %d", freespace);
  1088. /* Word alignment adjustment */
  1089. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1090. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1091. tx_cmd_a |= (unsigned int)skb->len;
  1092. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1093. tx_cmd_b |= (unsigned int)skb->len;
  1094. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1095. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1096. bufp = (ulong)skb->data & (~0x3);
  1097. wrsz = (u32)skb->len + 3;
  1098. wrsz += (u32)((ulong)skb->data & 0x3);
  1099. wrsz >>= 2;
  1100. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1101. freespace -= (skb->len + 32);
  1102. dev_kfree_skb(skb);
  1103. dev->trans_start = jiffies;
  1104. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1105. smsc911x_tx_update_txcounters(dev);
  1106. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1107. netif_stop_queue(dev);
  1108. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1109. temp &= 0x00FFFFFF;
  1110. temp |= 0x32000000;
  1111. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1112. }
  1113. return NETDEV_TX_OK;
  1114. }
  1115. /* Entry point for getting status counters */
  1116. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1117. {
  1118. struct smsc911x_data *pdata = netdev_priv(dev);
  1119. smsc911x_tx_update_txcounters(dev);
  1120. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1121. return &dev->stats;
  1122. }
  1123. /* Entry point for setting addressing modes */
  1124. static void smsc911x_set_multicast_list(struct net_device *dev)
  1125. {
  1126. struct smsc911x_data *pdata = netdev_priv(dev);
  1127. unsigned long flags;
  1128. if (dev->flags & IFF_PROMISC) {
  1129. /* Enabling promiscuous mode */
  1130. pdata->set_bits_mask = MAC_CR_PRMS_;
  1131. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1132. pdata->hashhi = 0;
  1133. pdata->hashlo = 0;
  1134. } else if (dev->flags & IFF_ALLMULTI) {
  1135. /* Enabling all multicast mode */
  1136. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1137. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1138. pdata->hashhi = 0;
  1139. pdata->hashlo = 0;
  1140. } else if (dev->mc_count > 0) {
  1141. /* Enabling specific multicast addresses */
  1142. unsigned int hash_high = 0;
  1143. unsigned int hash_low = 0;
  1144. unsigned int count = 0;
  1145. struct dev_mc_list *mc_list = dev->mc_list;
  1146. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1147. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1148. while (mc_list) {
  1149. count++;
  1150. if ((mc_list->dmi_addrlen) == ETH_ALEN) {
  1151. unsigned int bitnum =
  1152. smsc911x_hash(mc_list->dmi_addr);
  1153. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1154. if (bitnum & 0x20)
  1155. hash_high |= mask;
  1156. else
  1157. hash_low |= mask;
  1158. } else {
  1159. SMSC_WARNING(DRV, "dmi_addrlen != 6");
  1160. }
  1161. mc_list = mc_list->next;
  1162. }
  1163. if (count != (unsigned int)dev->mc_count)
  1164. SMSC_WARNING(DRV, "mc_count != dev->mc_count");
  1165. pdata->hashhi = hash_high;
  1166. pdata->hashlo = hash_low;
  1167. } else {
  1168. /* Enabling local MAC address only */
  1169. pdata->set_bits_mask = 0;
  1170. pdata->clear_bits_mask =
  1171. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1172. pdata->hashhi = 0;
  1173. pdata->hashlo = 0;
  1174. }
  1175. spin_lock_irqsave(&pdata->mac_lock, flags);
  1176. if (pdata->generation <= 1) {
  1177. /* Older hardware revision - cannot change these flags while
  1178. * receiving data */
  1179. if (!pdata->multicast_update_pending) {
  1180. unsigned int temp;
  1181. SMSC_TRACE(HW, "scheduling mcast update");
  1182. pdata->multicast_update_pending = 1;
  1183. /* Request the hardware to stop, then perform the
  1184. * update when we get an RX_STOP interrupt */
  1185. temp = smsc911x_mac_read(pdata, MAC_CR);
  1186. temp &= ~(MAC_CR_RXEN_);
  1187. smsc911x_mac_write(pdata, MAC_CR, temp);
  1188. } else {
  1189. /* There is another update pending, this should now
  1190. * use the newer values */
  1191. }
  1192. } else {
  1193. /* Newer hardware revision - can write immediately */
  1194. smsc911x_rx_multicast_update(pdata);
  1195. }
  1196. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1197. }
  1198. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1199. {
  1200. struct net_device *dev = dev_id;
  1201. struct smsc911x_data *pdata = netdev_priv(dev);
  1202. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1203. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1204. int serviced = IRQ_NONE;
  1205. u32 temp;
  1206. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1207. temp = smsc911x_reg_read(pdata, INT_EN);
  1208. temp &= (~INT_EN_SW_INT_EN_);
  1209. smsc911x_reg_write(pdata, INT_EN, temp);
  1210. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1211. pdata->software_irq_signal = 1;
  1212. smp_wmb();
  1213. serviced = IRQ_HANDLED;
  1214. }
  1215. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1216. /* Called when there is a multicast update scheduled and
  1217. * it is now safe to complete the update */
  1218. SMSC_TRACE(INTR, "RX Stop interrupt");
  1219. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1220. if (pdata->multicast_update_pending)
  1221. smsc911x_rx_multicast_update_workaround(pdata);
  1222. serviced = IRQ_HANDLED;
  1223. }
  1224. if (intsts & inten & INT_STS_TDFA_) {
  1225. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1226. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1227. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1228. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1229. netif_wake_queue(dev);
  1230. serviced = IRQ_HANDLED;
  1231. }
  1232. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1233. SMSC_TRACE(INTR, "RX Error interrupt");
  1234. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1235. serviced = IRQ_HANDLED;
  1236. }
  1237. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1238. if (likely(napi_schedule_prep(&pdata->napi))) {
  1239. /* Disable Rx interrupts */
  1240. temp = smsc911x_reg_read(pdata, INT_EN);
  1241. temp &= (~INT_EN_RSFL_EN_);
  1242. smsc911x_reg_write(pdata, INT_EN, temp);
  1243. /* Schedule a NAPI poll */
  1244. __napi_schedule(&pdata->napi);
  1245. } else {
  1246. SMSC_WARNING(RX_ERR,
  1247. "napi_schedule_prep failed");
  1248. }
  1249. serviced = IRQ_HANDLED;
  1250. }
  1251. return serviced;
  1252. }
  1253. #ifdef CONFIG_NET_POLL_CONTROLLER
  1254. static void smsc911x_poll_controller(struct net_device *dev)
  1255. {
  1256. disable_irq(dev->irq);
  1257. smsc911x_irqhandler(0, dev);
  1258. enable_irq(dev->irq);
  1259. }
  1260. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1261. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1262. {
  1263. struct smsc911x_data *pdata = netdev_priv(dev);
  1264. struct sockaddr *addr = p;
  1265. /* On older hardware revisions we cannot change the mac address
  1266. * registers while receiving data. Newer devices can safely change
  1267. * this at any time. */
  1268. if (pdata->generation <= 1 && netif_running(dev))
  1269. return -EBUSY;
  1270. if (!is_valid_ether_addr(addr->sa_data))
  1271. return -EADDRNOTAVAIL;
  1272. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1273. spin_lock_irq(&pdata->mac_lock);
  1274. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1275. spin_unlock_irq(&pdata->mac_lock);
  1276. dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
  1277. return 0;
  1278. }
  1279. /* Standard ioctls for mii-tool */
  1280. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1281. {
  1282. struct smsc911x_data *pdata = netdev_priv(dev);
  1283. if (!netif_running(dev) || !pdata->phy_dev)
  1284. return -EINVAL;
  1285. return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
  1286. }
  1287. static int
  1288. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1289. {
  1290. struct smsc911x_data *pdata = netdev_priv(dev);
  1291. cmd->maxtxpkt = 1;
  1292. cmd->maxrxpkt = 1;
  1293. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1294. }
  1295. static int
  1296. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1297. {
  1298. struct smsc911x_data *pdata = netdev_priv(dev);
  1299. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1300. }
  1301. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1302. struct ethtool_drvinfo *info)
  1303. {
  1304. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1305. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1306. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1307. sizeof(info->bus_info));
  1308. }
  1309. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1310. {
  1311. struct smsc911x_data *pdata = netdev_priv(dev);
  1312. return phy_start_aneg(pdata->phy_dev);
  1313. }
  1314. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1315. {
  1316. struct smsc911x_data *pdata = netdev_priv(dev);
  1317. return pdata->msg_enable;
  1318. }
  1319. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1320. {
  1321. struct smsc911x_data *pdata = netdev_priv(dev);
  1322. pdata->msg_enable = level;
  1323. }
  1324. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1325. {
  1326. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1327. sizeof(u32);
  1328. }
  1329. static void
  1330. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1331. void *buf)
  1332. {
  1333. struct smsc911x_data *pdata = netdev_priv(dev);
  1334. struct phy_device *phy_dev = pdata->phy_dev;
  1335. unsigned long flags;
  1336. unsigned int i;
  1337. unsigned int j = 0;
  1338. u32 *data = buf;
  1339. regs->version = pdata->idrev;
  1340. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1341. data[j++] = smsc911x_reg_read(pdata, i);
  1342. for (i = MAC_CR; i <= WUCSR; i++) {
  1343. spin_lock_irqsave(&pdata->mac_lock, flags);
  1344. data[j++] = smsc911x_mac_read(pdata, i);
  1345. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1346. }
  1347. for (i = 0; i <= 31; i++)
  1348. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1349. }
  1350. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1351. {
  1352. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1353. temp &= ~GPIO_CFG_EEPR_EN_;
  1354. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1355. msleep(1);
  1356. }
  1357. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1358. {
  1359. int timeout = 100;
  1360. u32 e2cmd;
  1361. SMSC_TRACE(DRV, "op 0x%08x", op);
  1362. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1363. SMSC_WARNING(DRV, "Busy at start");
  1364. return -EBUSY;
  1365. }
  1366. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1367. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1368. do {
  1369. msleep(1);
  1370. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1371. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1372. if (!timeout) {
  1373. SMSC_TRACE(DRV, "TIMED OUT");
  1374. return -EAGAIN;
  1375. }
  1376. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1377. SMSC_TRACE(DRV, "Error occured during eeprom operation");
  1378. return -EINVAL;
  1379. }
  1380. return 0;
  1381. }
  1382. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1383. u8 address, u8 *data)
  1384. {
  1385. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1386. int ret;
  1387. SMSC_TRACE(DRV, "address 0x%x", address);
  1388. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1389. if (!ret)
  1390. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1391. return ret;
  1392. }
  1393. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1394. u8 address, u8 data)
  1395. {
  1396. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1397. u32 temp;
  1398. int ret;
  1399. SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
  1400. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1401. if (!ret) {
  1402. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1403. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1404. /* Workaround for hardware read-after-write restriction */
  1405. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1406. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1407. }
  1408. return ret;
  1409. }
  1410. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1411. {
  1412. return SMSC911X_EEPROM_SIZE;
  1413. }
  1414. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1415. struct ethtool_eeprom *eeprom, u8 *data)
  1416. {
  1417. struct smsc911x_data *pdata = netdev_priv(dev);
  1418. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1419. int len;
  1420. int i;
  1421. smsc911x_eeprom_enable_access(pdata);
  1422. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1423. for (i = 0; i < len; i++) {
  1424. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1425. if (ret < 0) {
  1426. eeprom->len = 0;
  1427. return ret;
  1428. }
  1429. }
  1430. memcpy(data, &eeprom_data[eeprom->offset], len);
  1431. eeprom->len = len;
  1432. return 0;
  1433. }
  1434. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1435. struct ethtool_eeprom *eeprom, u8 *data)
  1436. {
  1437. int ret;
  1438. struct smsc911x_data *pdata = netdev_priv(dev);
  1439. smsc911x_eeprom_enable_access(pdata);
  1440. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1441. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1442. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1443. /* Single byte write, according to man page */
  1444. eeprom->len = 1;
  1445. return ret;
  1446. }
  1447. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1448. .get_settings = smsc911x_ethtool_getsettings,
  1449. .set_settings = smsc911x_ethtool_setsettings,
  1450. .get_link = ethtool_op_get_link,
  1451. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1452. .nway_reset = smsc911x_ethtool_nwayreset,
  1453. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1454. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1455. .get_regs_len = smsc911x_ethtool_getregslen,
  1456. .get_regs = smsc911x_ethtool_getregs,
  1457. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1458. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1459. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1460. };
  1461. static const struct net_device_ops smsc911x_netdev_ops = {
  1462. .ndo_open = smsc911x_open,
  1463. .ndo_stop = smsc911x_stop,
  1464. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1465. .ndo_get_stats = smsc911x_get_stats,
  1466. .ndo_set_multicast_list = smsc911x_set_multicast_list,
  1467. .ndo_do_ioctl = smsc911x_do_ioctl,
  1468. .ndo_validate_addr = eth_validate_addr,
  1469. .ndo_set_mac_address = smsc911x_set_mac_address,
  1470. #ifdef CONFIG_NET_POLL_CONTROLLER
  1471. .ndo_poll_controller = smsc911x_poll_controller,
  1472. #endif
  1473. };
  1474. /* copies the current mac address from hardware to dev->dev_addr */
  1475. static void __devinit smsc911x_read_mac_address(struct net_device *dev)
  1476. {
  1477. struct smsc911x_data *pdata = netdev_priv(dev);
  1478. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1479. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1480. dev->dev_addr[0] = (u8)(mac_low32);
  1481. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1482. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1483. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1484. dev->dev_addr[4] = (u8)(mac_high16);
  1485. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1486. }
  1487. /* Initializing private device structures, only called from probe */
  1488. static int __devinit smsc911x_init(struct net_device *dev)
  1489. {
  1490. struct smsc911x_data *pdata = netdev_priv(dev);
  1491. unsigned int byte_test;
  1492. SMSC_TRACE(PROBE, "Driver Parameters:");
  1493. SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
  1494. (unsigned long)pdata->ioaddr);
  1495. SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
  1496. SMSC_TRACE(PROBE, "PHY will be autodetected.");
  1497. spin_lock_init(&pdata->dev_lock);
  1498. if (pdata->ioaddr == 0) {
  1499. SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
  1500. return -ENODEV;
  1501. }
  1502. /* Check byte ordering */
  1503. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1504. SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
  1505. if (byte_test == 0x43218765) {
  1506. SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
  1507. "applying WORD_SWAP");
  1508. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1509. /* 1 dummy read of BYTE_TEST is needed after a write to
  1510. * WORD_SWAP before its contents are valid */
  1511. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1512. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1513. }
  1514. if (byte_test != 0x87654321) {
  1515. SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
  1516. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1517. SMSC_WARNING(PROBE,
  1518. "top 16 bits equal to bottom 16 bits");
  1519. SMSC_TRACE(PROBE, "This may mean the chip is set "
  1520. "for 32 bit while the bus is reading 16 bit");
  1521. }
  1522. return -ENODEV;
  1523. }
  1524. /* Default generation to zero (all workarounds apply) */
  1525. pdata->generation = 0;
  1526. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1527. switch (pdata->idrev & 0xFFFF0000) {
  1528. case 0x01180000:
  1529. case 0x01170000:
  1530. case 0x01160000:
  1531. case 0x01150000:
  1532. /* LAN911[5678] family */
  1533. pdata->generation = pdata->idrev & 0x0000FFFF;
  1534. break;
  1535. case 0x118A0000:
  1536. case 0x117A0000:
  1537. case 0x116A0000:
  1538. case 0x115A0000:
  1539. /* LAN921[5678] family */
  1540. pdata->generation = 3;
  1541. break;
  1542. case 0x92100000:
  1543. case 0x92110000:
  1544. case 0x92200000:
  1545. case 0x92210000:
  1546. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1547. pdata->generation = 4;
  1548. break;
  1549. default:
  1550. SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
  1551. pdata->idrev);
  1552. return -ENODEV;
  1553. }
  1554. SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
  1555. pdata->idrev, pdata->generation);
  1556. if (pdata->generation == 0)
  1557. SMSC_WARNING(PROBE,
  1558. "This driver is not intended for this chip revision");
  1559. /* workaround for platforms without an eeprom, where the mac address
  1560. * is stored elsewhere and set by the bootloader. This saves the
  1561. * mac address before resetting the device */
  1562. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
  1563. smsc911x_read_mac_address(dev);
  1564. /* Reset the LAN911x */
  1565. if (smsc911x_soft_reset(pdata))
  1566. return -ENODEV;
  1567. /* Disable all interrupt sources until we bring the device up */
  1568. smsc911x_reg_write(pdata, INT_EN, 0);
  1569. ether_setup(dev);
  1570. dev->flags |= IFF_MULTICAST;
  1571. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1572. dev->netdev_ops = &smsc911x_netdev_ops;
  1573. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1574. return 0;
  1575. }
  1576. static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
  1577. {
  1578. struct net_device *dev;
  1579. struct smsc911x_data *pdata;
  1580. struct resource *res;
  1581. dev = platform_get_drvdata(pdev);
  1582. BUG_ON(!dev);
  1583. pdata = netdev_priv(dev);
  1584. BUG_ON(!pdata);
  1585. BUG_ON(!pdata->ioaddr);
  1586. BUG_ON(!pdata->phy_dev);
  1587. SMSC_TRACE(IFDOWN, "Stopping driver.");
  1588. phy_disconnect(pdata->phy_dev);
  1589. pdata->phy_dev = NULL;
  1590. mdiobus_unregister(pdata->mii_bus);
  1591. mdiobus_free(pdata->mii_bus);
  1592. platform_set_drvdata(pdev, NULL);
  1593. unregister_netdev(dev);
  1594. free_irq(dev->irq, dev);
  1595. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1596. "smsc911x-memory");
  1597. if (!res)
  1598. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1599. release_mem_region(res->start, res->end - res->start);
  1600. iounmap(pdata->ioaddr);
  1601. free_netdev(dev);
  1602. return 0;
  1603. }
  1604. static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
  1605. {
  1606. struct net_device *dev;
  1607. struct smsc911x_data *pdata;
  1608. struct smsc911x_platform_config *config = pdev->dev.platform_data;
  1609. struct resource *res, *irq_res;
  1610. unsigned int intcfg = 0;
  1611. int res_size, irq_flags;
  1612. int retval;
  1613. pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
  1614. /* platform data specifies irq & dynamic bus configuration */
  1615. if (!pdev->dev.platform_data) {
  1616. pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
  1617. retval = -ENODEV;
  1618. goto out_0;
  1619. }
  1620. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1621. "smsc911x-memory");
  1622. if (!res)
  1623. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1624. if (!res) {
  1625. pr_warning("%s: Could not allocate resource.\n",
  1626. SMSC_CHIPNAME);
  1627. retval = -ENODEV;
  1628. goto out_0;
  1629. }
  1630. res_size = res->end - res->start;
  1631. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1632. if (!irq_res) {
  1633. pr_warning("%s: Could not allocate irq resource.\n",
  1634. SMSC_CHIPNAME);
  1635. retval = -ENODEV;
  1636. goto out_0;
  1637. }
  1638. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  1639. retval = -EBUSY;
  1640. goto out_0;
  1641. }
  1642. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  1643. if (!dev) {
  1644. pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
  1645. retval = -ENOMEM;
  1646. goto out_release_io_1;
  1647. }
  1648. SET_NETDEV_DEV(dev, &pdev->dev);
  1649. pdata = netdev_priv(dev);
  1650. dev->irq = irq_res->start;
  1651. irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
  1652. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  1653. /* copy config parameters across to pdata */
  1654. memcpy(&pdata->config, config, sizeof(pdata->config));
  1655. pdata->dev = dev;
  1656. pdata->msg_enable = ((1 << debug) - 1);
  1657. if (pdata->ioaddr == NULL) {
  1658. SMSC_WARNING(PROBE,
  1659. "Error smsc911x base address invalid");
  1660. retval = -ENOMEM;
  1661. goto out_free_netdev_2;
  1662. }
  1663. retval = smsc911x_init(dev);
  1664. if (retval < 0)
  1665. goto out_unmap_io_3;
  1666. /* configure irq polarity and type before connecting isr */
  1667. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  1668. intcfg |= INT_CFG_IRQ_POL_;
  1669. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  1670. intcfg |= INT_CFG_IRQ_TYPE_;
  1671. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1672. /* Ensure interrupts are globally disabled before connecting ISR */
  1673. smsc911x_reg_write(pdata, INT_EN, 0);
  1674. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1675. retval = request_irq(dev->irq, smsc911x_irqhandler,
  1676. irq_flags | IRQF_SHARED, dev->name, dev);
  1677. if (retval) {
  1678. SMSC_WARNING(PROBE,
  1679. "Unable to claim requested irq: %d", dev->irq);
  1680. goto out_unmap_io_3;
  1681. }
  1682. platform_set_drvdata(pdev, dev);
  1683. retval = register_netdev(dev);
  1684. if (retval) {
  1685. SMSC_WARNING(PROBE,
  1686. "Error %i registering device", retval);
  1687. goto out_unset_drvdata_4;
  1688. } else {
  1689. SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
  1690. }
  1691. spin_lock_init(&pdata->mac_lock);
  1692. retval = smsc911x_mii_init(pdev, dev);
  1693. if (retval) {
  1694. SMSC_WARNING(PROBE,
  1695. "Error %i initialising mii", retval);
  1696. goto out_unregister_netdev_5;
  1697. }
  1698. spin_lock_irq(&pdata->mac_lock);
  1699. /* Check if mac address has been specified when bringing interface up */
  1700. if (is_valid_ether_addr(dev->dev_addr)) {
  1701. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1702. SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
  1703. } else {
  1704. /* Try reading mac address from device. if EEPROM is present
  1705. * it will already have been set */
  1706. smsc911x_read_mac_address(dev);
  1707. if (is_valid_ether_addr(dev->dev_addr)) {
  1708. /* eeprom values are valid so use them */
  1709. SMSC_TRACE(PROBE,
  1710. "Mac Address is read from LAN911x EEPROM");
  1711. } else {
  1712. /* eeprom values are invalid, generate random MAC */
  1713. random_ether_addr(dev->dev_addr);
  1714. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1715. SMSC_TRACE(PROBE,
  1716. "MAC Address is set to random_ether_addr");
  1717. }
  1718. }
  1719. spin_unlock_irq(&pdata->mac_lock);
  1720. dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
  1721. return 0;
  1722. out_unregister_netdev_5:
  1723. unregister_netdev(dev);
  1724. out_unset_drvdata_4:
  1725. platform_set_drvdata(pdev, NULL);
  1726. free_irq(dev->irq, dev);
  1727. out_unmap_io_3:
  1728. iounmap(pdata->ioaddr);
  1729. out_free_netdev_2:
  1730. free_netdev(dev);
  1731. out_release_io_1:
  1732. release_mem_region(res->start, res->end - res->start);
  1733. out_0:
  1734. return retval;
  1735. }
  1736. static struct platform_driver smsc911x_driver = {
  1737. .probe = smsc911x_drv_probe,
  1738. .remove = smsc911x_drv_remove,
  1739. .driver = {
  1740. .name = SMSC_CHIPNAME,
  1741. },
  1742. };
  1743. /* Entry point for loading the module */
  1744. static int __init smsc911x_init_module(void)
  1745. {
  1746. return platform_driver_register(&smsc911x_driver);
  1747. }
  1748. /* entry point for unloading the module */
  1749. static void __exit smsc911x_cleanup_module(void)
  1750. {
  1751. platform_driver_unregister(&smsc911x_driver);
  1752. }
  1753. module_init(smsc911x_init_module);
  1754. module_exit(smsc911x_cleanup_module);