cpu.c 4.3 KB

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  1. /* linux/arch/arm/mach-s5p64x0/cpu.c
  2. *
  3. * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/types.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/list.h>
  14. #include <linux/timer.h>
  15. #include <linux/init.h>
  16. #include <linux/clk.h>
  17. #include <linux/io.h>
  18. #include <linux/sysdev.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach/map.h>
  23. #include <asm/mach/irq.h>
  24. #include <asm/proc-fns.h>
  25. #include <asm/irq.h>
  26. #include <mach/hardware.h>
  27. #include <mach/map.h>
  28. #include <mach/regs-clock.h>
  29. #include <plat/regs-serial.h>
  30. #include <plat/cpu.h>
  31. #include <plat/devs.h>
  32. #include <plat/clock.h>
  33. #include <plat/s5p6440.h>
  34. #include <plat/s5p6450.h>
  35. #include <plat/adc-core.h>
  36. /* Initial IO mappings */
  37. static struct map_desc s5p64x0_iodesc[] __initdata = {
  38. {
  39. .virtual = (unsigned long)S5P_VA_GPIO,
  40. .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
  41. .length = SZ_4K,
  42. .type = MT_DEVICE,
  43. }, {
  44. .virtual = (unsigned long)VA_VIC0,
  45. .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
  46. .length = SZ_16K,
  47. .type = MT_DEVICE,
  48. }, {
  49. .virtual = (unsigned long)VA_VIC1,
  50. .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
  51. .length = SZ_16K,
  52. .type = MT_DEVICE,
  53. },
  54. };
  55. static struct map_desc s5p6440_iodesc[] __initdata = {
  56. {
  57. .virtual = (unsigned long)S3C_VA_UART,
  58. .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
  59. .length = SZ_4K,
  60. .type = MT_DEVICE,
  61. },
  62. };
  63. static struct map_desc s5p6450_iodesc[] __initdata = {
  64. {
  65. .virtual = (unsigned long)S3C_VA_UART,
  66. .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
  67. .length = SZ_512K,
  68. .type = MT_DEVICE,
  69. }, {
  70. .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
  71. .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
  72. .length = SZ_4K,
  73. .type = MT_DEVICE,
  74. },
  75. };
  76. static void s5p64x0_idle(void)
  77. {
  78. unsigned long val;
  79. if (!need_resched()) {
  80. val = __raw_readl(S5P64X0_PWR_CFG);
  81. val &= ~(0x3 << 5);
  82. val |= (0x1 << 5);
  83. __raw_writel(val, S5P64X0_PWR_CFG);
  84. cpu_do_idle();
  85. }
  86. local_irq_enable();
  87. }
  88. /*
  89. * s5p64x0_map_io
  90. *
  91. * register the standard CPU IO areas
  92. */
  93. void __init s5p6440_map_io(void)
  94. {
  95. /* initialize any device information early */
  96. s3c_adc_setname("s3c64x0-adc");
  97. iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
  98. iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
  99. }
  100. void __init s5p6450_map_io(void)
  101. {
  102. /* initialize any device information early */
  103. s3c_adc_setname("s3c64x0-adc");
  104. iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
  105. iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
  106. }
  107. /*
  108. * s5p64x0_init_clocks
  109. *
  110. * register and setup the CPU clocks
  111. */
  112. void __init s5p6440_init_clocks(int xtal)
  113. {
  114. printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
  115. s3c24xx_register_baseclocks(xtal);
  116. s5p_register_clocks(xtal);
  117. s5p6440_register_clocks();
  118. s5p6440_setup_clocks();
  119. }
  120. void __init s5p6450_init_clocks(int xtal)
  121. {
  122. printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
  123. s3c24xx_register_baseclocks(xtal);
  124. s5p_register_clocks(xtal);
  125. s5p6450_register_clocks();
  126. s5p6450_setup_clocks();
  127. }
  128. /*
  129. * s5p64x0_init_irq
  130. *
  131. * register the CPU interrupts
  132. */
  133. void __init s5p6440_init_irq(void)
  134. {
  135. /* S5P6440 supports 2 VIC */
  136. u32 vic[2];
  137. /*
  138. * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
  139. * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
  140. */
  141. vic[0] = 0xff800ae7;
  142. vic[1] = 0xffbf23e5;
  143. s5p_init_irq(vic, ARRAY_SIZE(vic));
  144. }
  145. void __init s5p6450_init_irq(void)
  146. {
  147. /* S5P6450 supports only 2 VIC */
  148. u32 vic[2];
  149. /*
  150. * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
  151. * VIC1 is missing IRQ VIC1[12, 14, 23]
  152. */
  153. vic[0] = 0xff9f1fff;
  154. vic[1] = 0xff7fafff;
  155. s5p_init_irq(vic, ARRAY_SIZE(vic));
  156. }
  157. struct sysdev_class s5p64x0_sysclass = {
  158. .name = "s5p64x0-core",
  159. };
  160. static struct sys_device s5p64x0_sysdev = {
  161. .cls = &s5p64x0_sysclass,
  162. };
  163. static int __init s5p64x0_core_init(void)
  164. {
  165. return sysdev_class_register(&s5p64x0_sysclass);
  166. }
  167. core_initcall(s5p64x0_core_init);
  168. int __init s5p64x0_init(void)
  169. {
  170. printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
  171. /* set idle function */
  172. pm_idle = s5p64x0_idle;
  173. return sysdev_register(&s5p64x0_sysdev);
  174. }