omap_hwmod_33xx_data.c 79 KB

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  1. /*
  2. * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
  3. *
  4. * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is automatically generated from the AM33XX hardware databases.
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <plat/omap_hwmod.h>
  17. #include <plat/cpu.h>
  18. #include <plat/gpio.h>
  19. #include <plat/dma.h>
  20. #include <plat/mmc.h>
  21. #include <plat/mcspi.h>
  22. #include <plat/i2c.h>
  23. #include "omap_hwmod_common_data.h"
  24. #include "control.h"
  25. #include "cm33xx.h"
  26. #include "prm33xx.h"
  27. #include "prm-regbits-33xx.h"
  28. /* XXX Remove this during the sparseirq conversion */
  29. #define OMAP_INTC_START 0
  30. /*
  31. * IP blocks
  32. */
  33. /*
  34. * 'emif_fw' class
  35. * instance(s): emif_fw
  36. */
  37. static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
  38. .name = "emif_fw",
  39. };
  40. /* emif_fw */
  41. static struct omap_hwmod am33xx_emif_fw_hwmod = {
  42. .name = "emif_fw",
  43. .class = &am33xx_emif_fw_hwmod_class,
  44. .clkdm_name = "l4fw_clkdm",
  45. .main_clk = "l4fw_gclk",
  46. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  47. .prcm = {
  48. .omap4 = {
  49. .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
  50. .modulemode = MODULEMODE_SWCTRL,
  51. },
  52. },
  53. };
  54. /*
  55. * 'emif' class
  56. * instance(s): emif
  57. */
  58. static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
  59. .rev_offs = 0x0000,
  60. };
  61. static struct omap_hwmod_class am33xx_emif_hwmod_class = {
  62. .name = "emif",
  63. .sysc = &am33xx_emif_sysc,
  64. };
  65. static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
  66. { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
  67. { .irq = -1 },
  68. };
  69. /* emif */
  70. static struct omap_hwmod am33xx_emif_hwmod = {
  71. .name = "emif",
  72. .class = &am33xx_emif_hwmod_class,
  73. .clkdm_name = "l3_clkdm",
  74. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  75. .mpu_irqs = am33xx_emif_irqs,
  76. .main_clk = "dpll_ddr_m2_div2_ck",
  77. .prcm = {
  78. .omap4 = {
  79. .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  80. .modulemode = MODULEMODE_SWCTRL,
  81. },
  82. },
  83. };
  84. /*
  85. * 'l3' class
  86. * instance(s): l3_main, l3_s, l3_instr
  87. */
  88. static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  89. .name = "l3",
  90. };
  91. /* l3_main (l3_fast) */
  92. static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
  93. { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
  94. { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
  95. { .irq = -1 },
  96. };
  97. static struct omap_hwmod am33xx_l3_main_hwmod = {
  98. .name = "l3_main",
  99. .class = &am33xx_l3_hwmod_class,
  100. .clkdm_name = "l3_clkdm",
  101. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  102. .mpu_irqs = am33xx_l3_main_irqs,
  103. .main_clk = "l3_gclk",
  104. .prcm = {
  105. .omap4 = {
  106. .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
  107. .modulemode = MODULEMODE_SWCTRL,
  108. },
  109. },
  110. };
  111. /* l3_s */
  112. static struct omap_hwmod am33xx_l3_s_hwmod = {
  113. .name = "l3_s",
  114. .class = &am33xx_l3_hwmod_class,
  115. .clkdm_name = "l3s_clkdm",
  116. };
  117. /* l3_instr */
  118. static struct omap_hwmod am33xx_l3_instr_hwmod = {
  119. .name = "l3_instr",
  120. .class = &am33xx_l3_hwmod_class,
  121. .clkdm_name = "l3_clkdm",
  122. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  123. .main_clk = "l3_gclk",
  124. .prcm = {
  125. .omap4 = {
  126. .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
  127. .modulemode = MODULEMODE_SWCTRL,
  128. },
  129. },
  130. };
  131. /*
  132. * 'l4' class
  133. * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  134. */
  135. static struct omap_hwmod_class am33xx_l4_hwmod_class = {
  136. .name = "l4",
  137. };
  138. /* l4_ls */
  139. static struct omap_hwmod am33xx_l4_ls_hwmod = {
  140. .name = "l4_ls",
  141. .class = &am33xx_l4_hwmod_class,
  142. .clkdm_name = "l4ls_clkdm",
  143. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  144. .main_clk = "l4ls_gclk",
  145. .prcm = {
  146. .omap4 = {
  147. .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
  148. .modulemode = MODULEMODE_SWCTRL,
  149. },
  150. },
  151. };
  152. /* l4_hs */
  153. static struct omap_hwmod am33xx_l4_hs_hwmod = {
  154. .name = "l4_hs",
  155. .class = &am33xx_l4_hwmod_class,
  156. .clkdm_name = "l4hs_clkdm",
  157. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  158. .main_clk = "l4hs_gclk",
  159. .prcm = {
  160. .omap4 = {
  161. .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  162. .modulemode = MODULEMODE_SWCTRL,
  163. },
  164. },
  165. };
  166. /* l4_wkup */
  167. static struct omap_hwmod am33xx_l4_wkup_hwmod = {
  168. .name = "l4_wkup",
  169. .class = &am33xx_l4_hwmod_class,
  170. .clkdm_name = "l4_wkup_clkdm",
  171. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  172. .prcm = {
  173. .omap4 = {
  174. .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
  175. .modulemode = MODULEMODE_SWCTRL,
  176. },
  177. },
  178. };
  179. /* l4_fw */
  180. static struct omap_hwmod am33xx_l4_fw_hwmod = {
  181. .name = "l4_fw",
  182. .class = &am33xx_l4_hwmod_class,
  183. .clkdm_name = "l4fw_clkdm",
  184. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  185. .prcm = {
  186. .omap4 = {
  187. .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
  188. .modulemode = MODULEMODE_SWCTRL,
  189. },
  190. },
  191. };
  192. /*
  193. * 'mpu' class
  194. */
  195. static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
  196. .name = "mpu",
  197. };
  198. /* mpu */
  199. static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
  200. { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
  201. { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
  202. { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
  203. { .name = "bench", .irq = 3 + OMAP_INTC_START, },
  204. { .irq = -1 },
  205. };
  206. static struct omap_hwmod am33xx_mpu_hwmod = {
  207. .name = "mpu",
  208. .class = &am33xx_mpu_hwmod_class,
  209. .clkdm_name = "mpu_clkdm",
  210. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  211. .mpu_irqs = am33xx_mpu_irqs,
  212. .main_clk = "dpll_mpu_m2_ck",
  213. .prcm = {
  214. .omap4 = {
  215. .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
  216. .modulemode = MODULEMODE_SWCTRL,
  217. },
  218. },
  219. };
  220. /*
  221. * 'wakeup m3' class
  222. * Wakeup controller sub-system under wakeup domain
  223. */
  224. static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
  225. .name = "wkup_m3",
  226. };
  227. static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  228. { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  229. };
  230. static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
  231. { .name = "txev", .irq = 78 + OMAP_INTC_START, },
  232. { .irq = -1 },
  233. };
  234. /* wkup_m3 */
  235. static struct omap_hwmod am33xx_wkup_m3_hwmod = {
  236. .name = "wkup_m3",
  237. .class = &am33xx_wkup_m3_hwmod_class,
  238. .clkdm_name = "l4_wkup_aon_clkdm",
  239. .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
  240. .mpu_irqs = am33xx_wkup_m3_irqs,
  241. .main_clk = "dpll_core_m4_div2_ck",
  242. .prcm = {
  243. .omap4 = {
  244. .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  245. .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
  246. .modulemode = MODULEMODE_SWCTRL,
  247. },
  248. },
  249. .rst_lines = am33xx_wkup_m3_resets,
  250. .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
  251. };
  252. /*
  253. * 'pru-icss' class
  254. * Programmable Real-Time Unit and Industrial Communication Subsystem
  255. */
  256. static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
  257. .name = "pruss",
  258. };
  259. static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
  260. { .name = "pruss", .rst_shift = 1 },
  261. };
  262. static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
  263. { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
  264. { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
  265. { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
  266. { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
  267. { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
  268. { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
  269. { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
  270. { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
  271. { .irq = -1 },
  272. };
  273. /* pru-icss */
  274. /* Pseudo hwmod for reset control purpose only */
  275. static struct omap_hwmod am33xx_pruss_hwmod = {
  276. .name = "pruss",
  277. .class = &am33xx_pruss_hwmod_class,
  278. .clkdm_name = "pruss_ocp_clkdm",
  279. .mpu_irqs = am33xx_pruss_irqs,
  280. .main_clk = "pruss_ocp_gclk",
  281. .prcm = {
  282. .omap4 = {
  283. .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
  284. .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
  285. .modulemode = MODULEMODE_SWCTRL,
  286. },
  287. },
  288. .rst_lines = am33xx_pruss_resets,
  289. .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
  290. };
  291. /* gfx */
  292. /* Pseudo hwmod for reset control purpose only */
  293. static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
  294. .name = "gfx",
  295. };
  296. static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
  297. { .name = "gfx", .rst_shift = 0 },
  298. };
  299. static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
  300. { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
  301. { .irq = -1 },
  302. };
  303. static struct omap_hwmod am33xx_gfx_hwmod = {
  304. .name = "gfx",
  305. .class = &am33xx_gfx_hwmod_class,
  306. .clkdm_name = "gfx_l3_clkdm",
  307. .mpu_irqs = am33xx_gfx_irqs,
  308. .main_clk = "gfx_fck_div_ck",
  309. .prcm = {
  310. .omap4 = {
  311. .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
  312. .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
  313. .modulemode = MODULEMODE_SWCTRL,
  314. },
  315. },
  316. .rst_lines = am33xx_gfx_resets,
  317. .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
  318. };
  319. /*
  320. * 'prcm' class
  321. * power and reset manager (whole prcm infrastructure)
  322. */
  323. static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
  324. .name = "prcm",
  325. };
  326. /* prcm */
  327. static struct omap_hwmod am33xx_prcm_hwmod = {
  328. .name = "prcm",
  329. .class = &am33xx_prcm_hwmod_class,
  330. .clkdm_name = "l4_wkup_clkdm",
  331. };
  332. /*
  333. * 'adc/tsc' class
  334. * TouchScreen Controller (Anolog-To-Digital Converter)
  335. */
  336. static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
  337. .rev_offs = 0x00,
  338. .sysc_offs = 0x10,
  339. .sysc_flags = SYSC_HAS_SIDLEMODE,
  340. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  341. SIDLE_SMART_WKUP),
  342. .sysc_fields = &omap_hwmod_sysc_type2,
  343. };
  344. static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
  345. .name = "adc_tsc",
  346. .sysc = &am33xx_adc_tsc_sysc,
  347. };
  348. static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
  349. { .irq = 16 + OMAP_INTC_START, },
  350. { .irq = -1 },
  351. };
  352. static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  353. .name = "adc_tsc",
  354. .class = &am33xx_adc_tsc_hwmod_class,
  355. .clkdm_name = "l4_wkup_clkdm",
  356. .mpu_irqs = am33xx_adc_tsc_irqs,
  357. .main_clk = "adc_tsc_fck",
  358. .prcm = {
  359. .omap4 = {
  360. .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
  361. .modulemode = MODULEMODE_SWCTRL,
  362. },
  363. },
  364. };
  365. /*
  366. * Modules omap_hwmod structures
  367. *
  368. * The following IPs are excluded for the moment because:
  369. * - They do not need an explicit SW control using omap_hwmod API.
  370. * - They still need to be validated with the driver
  371. * properly adapted to omap_hwmod / omap_device
  372. *
  373. * - cEFUSE (doesn't fall under any ocp_if)
  374. * - clkdiv32k
  375. * - debugss
  376. * - ocmc ram
  377. * - ocp watch point
  378. * - aes0
  379. * - sha0
  380. */
  381. #if 0
  382. /*
  383. * 'cefuse' class
  384. */
  385. static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
  386. .name = "cefuse",
  387. };
  388. static struct omap_hwmod am33xx_cefuse_hwmod = {
  389. .name = "cefuse",
  390. .class = &am33xx_cefuse_hwmod_class,
  391. .clkdm_name = "l4_cefuse_clkdm",
  392. .main_clk = "cefuse_fck",
  393. .prcm = {
  394. .omap4 = {
  395. .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
  396. .modulemode = MODULEMODE_SWCTRL,
  397. },
  398. },
  399. };
  400. /*
  401. * 'clkdiv32k' class
  402. */
  403. static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
  404. .name = "clkdiv32k",
  405. };
  406. static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
  407. .name = "clkdiv32k",
  408. .class = &am33xx_clkdiv32k_hwmod_class,
  409. .clkdm_name = "clk_24mhz_clkdm",
  410. .main_clk = "clkdiv32k_ick",
  411. .prcm = {
  412. .omap4 = {
  413. .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
  414. .modulemode = MODULEMODE_SWCTRL,
  415. },
  416. },
  417. };
  418. /*
  419. * 'debugss' class
  420. * debug sub system
  421. */
  422. static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
  423. .name = "debugss",
  424. };
  425. static struct omap_hwmod am33xx_debugss_hwmod = {
  426. .name = "debugss",
  427. .class = &am33xx_debugss_hwmod_class,
  428. .clkdm_name = "l3_aon_clkdm",
  429. .main_clk = "debugss_ick",
  430. .prcm = {
  431. .omap4 = {
  432. .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
  433. .modulemode = MODULEMODE_SWCTRL,
  434. },
  435. },
  436. };
  437. /* ocmcram */
  438. static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
  439. .name = "ocmcram",
  440. };
  441. static struct omap_hwmod am33xx_ocmcram_hwmod = {
  442. .name = "ocmcram",
  443. .class = &am33xx_ocmcram_hwmod_class,
  444. .clkdm_name = "l3_clkdm",
  445. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  446. .main_clk = "l3_gclk",
  447. .prcm = {
  448. .omap4 = {
  449. .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
  450. .modulemode = MODULEMODE_SWCTRL,
  451. },
  452. },
  453. };
  454. /* ocpwp */
  455. static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
  456. .name = "ocpwp",
  457. };
  458. static struct omap_hwmod am33xx_ocpwp_hwmod = {
  459. .name = "ocpwp",
  460. .class = &am33xx_ocpwp_hwmod_class,
  461. .clkdm_name = "l4ls_clkdm",
  462. .main_clk = "l4ls_gclk",
  463. .prcm = {
  464. .omap4 = {
  465. .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
  466. .modulemode = MODULEMODE_SWCTRL,
  467. },
  468. },
  469. };
  470. /*
  471. * 'aes' class
  472. */
  473. static struct omap_hwmod_class am33xx_aes_hwmod_class = {
  474. .name = "aes",
  475. };
  476. static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
  477. { .irq = 102 + OMAP_INTC_START, },
  478. { .irq = -1 },
  479. };
  480. static struct omap_hwmod am33xx_aes0_hwmod = {
  481. .name = "aes0",
  482. .class = &am33xx_aes_hwmod_class,
  483. .clkdm_name = "l3_clkdm",
  484. .mpu_irqs = am33xx_aes0_irqs,
  485. .main_clk = "l3_gclk",
  486. .prcm = {
  487. .omap4 = {
  488. .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
  489. .modulemode = MODULEMODE_SWCTRL,
  490. },
  491. },
  492. };
  493. /* sha0 */
  494. static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
  495. .name = "sha0",
  496. };
  497. static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
  498. { .irq = 108 + OMAP_INTC_START, },
  499. { .irq = -1 },
  500. };
  501. static struct omap_hwmod am33xx_sha0_hwmod = {
  502. .name = "sha0",
  503. .class = &am33xx_sha0_hwmod_class,
  504. .clkdm_name = "l3_clkdm",
  505. .mpu_irqs = am33xx_sha0_irqs,
  506. .main_clk = "l3_gclk",
  507. .prcm = {
  508. .omap4 = {
  509. .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
  510. .modulemode = MODULEMODE_SWCTRL,
  511. },
  512. },
  513. };
  514. #endif
  515. /* 'smartreflex' class */
  516. static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
  517. .name = "smartreflex",
  518. };
  519. /* smartreflex0 */
  520. static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
  521. { .irq = 120 + OMAP_INTC_START, },
  522. { .irq = -1 },
  523. };
  524. static struct omap_hwmod am33xx_smartreflex0_hwmod = {
  525. .name = "smartreflex0",
  526. .class = &am33xx_smartreflex_hwmod_class,
  527. .clkdm_name = "l4_wkup_clkdm",
  528. .mpu_irqs = am33xx_smartreflex0_irqs,
  529. .main_clk = "smartreflex0_fck",
  530. .prcm = {
  531. .omap4 = {
  532. .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
  533. .modulemode = MODULEMODE_SWCTRL,
  534. },
  535. },
  536. };
  537. /* smartreflex1 */
  538. static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
  539. { .irq = 121 + OMAP_INTC_START, },
  540. { .irq = -1 },
  541. };
  542. static struct omap_hwmod am33xx_smartreflex1_hwmod = {
  543. .name = "smartreflex1",
  544. .class = &am33xx_smartreflex_hwmod_class,
  545. .clkdm_name = "l4_wkup_clkdm",
  546. .mpu_irqs = am33xx_smartreflex1_irqs,
  547. .main_clk = "smartreflex1_fck",
  548. .prcm = {
  549. .omap4 = {
  550. .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
  551. .modulemode = MODULEMODE_SWCTRL,
  552. },
  553. },
  554. };
  555. /*
  556. * 'control' module class
  557. */
  558. static struct omap_hwmod_class am33xx_control_hwmod_class = {
  559. .name = "control",
  560. };
  561. static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
  562. { .irq = 8 + OMAP_INTC_START, },
  563. { .irq = -1 },
  564. };
  565. static struct omap_hwmod am33xx_control_hwmod = {
  566. .name = "control",
  567. .class = &am33xx_control_hwmod_class,
  568. .clkdm_name = "l4_wkup_clkdm",
  569. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  570. .mpu_irqs = am33xx_control_irqs,
  571. .main_clk = "dpll_core_m4_div2_ck",
  572. .prcm = {
  573. .omap4 = {
  574. .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  575. .modulemode = MODULEMODE_SWCTRL,
  576. },
  577. },
  578. };
  579. /*
  580. * 'cpgmac' class
  581. * cpsw/cpgmac sub system
  582. */
  583. static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
  584. .rev_offs = 0x0,
  585. .sysc_offs = 0x8,
  586. .syss_offs = 0x4,
  587. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  588. SYSS_HAS_RESET_STATUS),
  589. .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
  590. MSTANDBY_NO),
  591. .sysc_fields = &omap_hwmod_sysc_type3,
  592. };
  593. static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
  594. .name = "cpgmac0",
  595. .sysc = &am33xx_cpgmac_sysc,
  596. };
  597. static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
  598. { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
  599. { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
  600. { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
  601. { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
  602. { .irq = -1 },
  603. };
  604. static struct omap_hwmod am33xx_cpgmac0_hwmod = {
  605. .name = "cpgmac0",
  606. .class = &am33xx_cpgmac0_hwmod_class,
  607. .clkdm_name = "cpsw_125mhz_clkdm",
  608. .mpu_irqs = am33xx_cpgmac0_irqs,
  609. .main_clk = "cpsw_125mhz_gclk",
  610. .prcm = {
  611. .omap4 = {
  612. .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
  613. .modulemode = MODULEMODE_SWCTRL,
  614. },
  615. },
  616. };
  617. /*
  618. * dcan class
  619. */
  620. static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
  621. .name = "d_can",
  622. };
  623. /* dcan0 */
  624. static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
  625. { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
  626. { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
  627. { .irq = -1 },
  628. };
  629. static struct omap_hwmod am33xx_dcan0_hwmod = {
  630. .name = "d_can0",
  631. .class = &am33xx_dcan_hwmod_class,
  632. .clkdm_name = "l4ls_clkdm",
  633. .mpu_irqs = am33xx_dcan0_irqs,
  634. .main_clk = "dcan0_fck",
  635. .prcm = {
  636. .omap4 = {
  637. .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
  638. .modulemode = MODULEMODE_SWCTRL,
  639. },
  640. },
  641. };
  642. /* dcan1 */
  643. static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
  644. { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
  645. { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
  646. { .irq = -1 },
  647. };
  648. static struct omap_hwmod am33xx_dcan1_hwmod = {
  649. .name = "d_can1",
  650. .class = &am33xx_dcan_hwmod_class,
  651. .clkdm_name = "l4ls_clkdm",
  652. .mpu_irqs = am33xx_dcan1_irqs,
  653. .main_clk = "dcan1_fck",
  654. .prcm = {
  655. .omap4 = {
  656. .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
  657. .modulemode = MODULEMODE_SWCTRL,
  658. },
  659. },
  660. };
  661. /* elm */
  662. static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
  663. .rev_offs = 0x0000,
  664. .sysc_offs = 0x0010,
  665. .syss_offs = 0x0014,
  666. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  667. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  668. SYSS_HAS_RESET_STATUS),
  669. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  670. .sysc_fields = &omap_hwmod_sysc_type1,
  671. };
  672. static struct omap_hwmod_class am33xx_elm_hwmod_class = {
  673. .name = "elm",
  674. .sysc = &am33xx_elm_sysc,
  675. };
  676. static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
  677. { .irq = 4 + OMAP_INTC_START, },
  678. { .irq = -1 },
  679. };
  680. static struct omap_hwmod am33xx_elm_hwmod = {
  681. .name = "elm",
  682. .class = &am33xx_elm_hwmod_class,
  683. .clkdm_name = "l4ls_clkdm",
  684. .mpu_irqs = am33xx_elm_irqs,
  685. .main_clk = "l4ls_gclk",
  686. .prcm = {
  687. .omap4 = {
  688. .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
  689. .modulemode = MODULEMODE_SWCTRL,
  690. },
  691. },
  692. };
  693. /*
  694. * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
  695. */
  696. static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
  697. .rev_offs = 0x0,
  698. .sysc_offs = 0x4,
  699. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
  700. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  701. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  702. MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
  703. .sysc_fields = &omap_hwmod_sysc_type2,
  704. };
  705. static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
  706. .name = "epwmss",
  707. .sysc = &am33xx_epwmss_sysc,
  708. };
  709. /* ehrpwm0 */
  710. static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
  711. { .name = "int", .irq = 86 + OMAP_INTC_START, },
  712. { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
  713. { .irq = -1 },
  714. };
  715. static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
  716. .name = "ehrpwm0",
  717. .class = &am33xx_epwmss_hwmod_class,
  718. .clkdm_name = "l4ls_clkdm",
  719. .mpu_irqs = am33xx_ehrpwm0_irqs,
  720. .main_clk = "l4ls_gclk",
  721. .prcm = {
  722. .omap4 = {
  723. .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
  724. .modulemode = MODULEMODE_SWCTRL,
  725. },
  726. },
  727. };
  728. /* ehrpwm1 */
  729. static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
  730. { .name = "int", .irq = 87 + OMAP_INTC_START, },
  731. { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
  732. { .irq = -1 },
  733. };
  734. static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
  735. .name = "ehrpwm1",
  736. .class = &am33xx_epwmss_hwmod_class,
  737. .clkdm_name = "l4ls_clkdm",
  738. .mpu_irqs = am33xx_ehrpwm1_irqs,
  739. .main_clk = "l4ls_gclk",
  740. .prcm = {
  741. .omap4 = {
  742. .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
  743. .modulemode = MODULEMODE_SWCTRL,
  744. },
  745. },
  746. };
  747. /* ehrpwm2 */
  748. static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
  749. { .name = "int", .irq = 39 + OMAP_INTC_START, },
  750. { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
  751. { .irq = -1 },
  752. };
  753. static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
  754. .name = "ehrpwm2",
  755. .class = &am33xx_epwmss_hwmod_class,
  756. .clkdm_name = "l4ls_clkdm",
  757. .mpu_irqs = am33xx_ehrpwm2_irqs,
  758. .main_clk = "l4ls_gclk",
  759. .prcm = {
  760. .omap4 = {
  761. .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
  762. .modulemode = MODULEMODE_SWCTRL,
  763. },
  764. },
  765. };
  766. /* ecap0 */
  767. static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
  768. { .irq = 31 + OMAP_INTC_START, },
  769. { .irq = -1 },
  770. };
  771. static struct omap_hwmod am33xx_ecap0_hwmod = {
  772. .name = "ecap0",
  773. .class = &am33xx_epwmss_hwmod_class,
  774. .clkdm_name = "l4ls_clkdm",
  775. .mpu_irqs = am33xx_ecap0_irqs,
  776. .main_clk = "l4ls_gclk",
  777. .prcm = {
  778. .omap4 = {
  779. .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
  780. .modulemode = MODULEMODE_SWCTRL,
  781. },
  782. },
  783. };
  784. /* ecap1 */
  785. static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
  786. { .irq = 47 + OMAP_INTC_START, },
  787. { .irq = -1 },
  788. };
  789. static struct omap_hwmod am33xx_ecap1_hwmod = {
  790. .name = "ecap1",
  791. .class = &am33xx_epwmss_hwmod_class,
  792. .clkdm_name = "l4ls_clkdm",
  793. .mpu_irqs = am33xx_ecap1_irqs,
  794. .main_clk = "l4ls_gclk",
  795. .prcm = {
  796. .omap4 = {
  797. .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
  798. .modulemode = MODULEMODE_SWCTRL,
  799. },
  800. },
  801. };
  802. /* ecap2 */
  803. static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
  804. { .irq = 61 + OMAP_INTC_START, },
  805. { .irq = -1 },
  806. };
  807. static struct omap_hwmod am33xx_ecap2_hwmod = {
  808. .name = "ecap2",
  809. .mpu_irqs = am33xx_ecap2_irqs,
  810. .class = &am33xx_epwmss_hwmod_class,
  811. .clkdm_name = "l4ls_clkdm",
  812. .main_clk = "l4ls_gclk",
  813. .prcm = {
  814. .omap4 = {
  815. .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
  816. .modulemode = MODULEMODE_SWCTRL,
  817. },
  818. },
  819. };
  820. /*
  821. * 'gpio' class: for gpio 0,1,2,3
  822. */
  823. static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
  824. .rev_offs = 0x0000,
  825. .sysc_offs = 0x0010,
  826. .syss_offs = 0x0114,
  827. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
  828. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  829. SYSS_HAS_RESET_STATUS),
  830. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  831. SIDLE_SMART_WKUP),
  832. .sysc_fields = &omap_hwmod_sysc_type1,
  833. };
  834. static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
  835. .name = "gpio",
  836. .sysc = &am33xx_gpio_sysc,
  837. .rev = 2,
  838. };
  839. static struct omap_gpio_dev_attr gpio_dev_attr = {
  840. .bank_width = 32,
  841. .dbck_flag = true,
  842. };
  843. /* gpio0 */
  844. static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
  845. { .role = "dbclk", .clk = "gpio0_dbclk" },
  846. };
  847. static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
  848. { .irq = 96 + OMAP_INTC_START, },
  849. { .irq = -1 },
  850. };
  851. static struct omap_hwmod am33xx_gpio0_hwmod = {
  852. .name = "gpio1",
  853. .class = &am33xx_gpio_hwmod_class,
  854. .clkdm_name = "l4_wkup_clkdm",
  855. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  856. .mpu_irqs = am33xx_gpio0_irqs,
  857. .main_clk = "dpll_core_m4_div2_ck",
  858. .prcm = {
  859. .omap4 = {
  860. .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
  861. .modulemode = MODULEMODE_SWCTRL,
  862. },
  863. },
  864. .opt_clks = gpio0_opt_clks,
  865. .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
  866. .dev_attr = &gpio_dev_attr,
  867. };
  868. /* gpio1 */
  869. static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
  870. { .irq = 98 + OMAP_INTC_START, },
  871. { .irq = -1 },
  872. };
  873. static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
  874. { .role = "dbclk", .clk = "gpio1_dbclk" },
  875. };
  876. static struct omap_hwmod am33xx_gpio1_hwmod = {
  877. .name = "gpio2",
  878. .class = &am33xx_gpio_hwmod_class,
  879. .clkdm_name = "l4ls_clkdm",
  880. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  881. .mpu_irqs = am33xx_gpio1_irqs,
  882. .main_clk = "l4ls_gclk",
  883. .prcm = {
  884. .omap4 = {
  885. .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
  886. .modulemode = MODULEMODE_SWCTRL,
  887. },
  888. },
  889. .opt_clks = gpio1_opt_clks,
  890. .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  891. .dev_attr = &gpio_dev_attr,
  892. };
  893. /* gpio2 */
  894. static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
  895. { .irq = 32 + OMAP_INTC_START, },
  896. { .irq = -1 },
  897. };
  898. static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
  899. { .role = "dbclk", .clk = "gpio2_dbclk" },
  900. };
  901. static struct omap_hwmod am33xx_gpio2_hwmod = {
  902. .name = "gpio3",
  903. .class = &am33xx_gpio_hwmod_class,
  904. .clkdm_name = "l4ls_clkdm",
  905. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  906. .mpu_irqs = am33xx_gpio2_irqs,
  907. .main_clk = "l4ls_gclk",
  908. .prcm = {
  909. .omap4 = {
  910. .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
  911. .modulemode = MODULEMODE_SWCTRL,
  912. },
  913. },
  914. .opt_clks = gpio2_opt_clks,
  915. .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
  916. .dev_attr = &gpio_dev_attr,
  917. };
  918. /* gpio3 */
  919. static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
  920. { .irq = 62 + OMAP_INTC_START, },
  921. { .irq = -1 },
  922. };
  923. static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
  924. { .role = "dbclk", .clk = "gpio3_dbclk" },
  925. };
  926. static struct omap_hwmod am33xx_gpio3_hwmod = {
  927. .name = "gpio4",
  928. .class = &am33xx_gpio_hwmod_class,
  929. .clkdm_name = "l4ls_clkdm",
  930. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  931. .mpu_irqs = am33xx_gpio3_irqs,
  932. .main_clk = "l4ls_gclk",
  933. .prcm = {
  934. .omap4 = {
  935. .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
  936. .modulemode = MODULEMODE_SWCTRL,
  937. },
  938. },
  939. .opt_clks = gpio3_opt_clks,
  940. .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
  941. .dev_attr = &gpio_dev_attr,
  942. };
  943. /* gpmc */
  944. static struct omap_hwmod_class_sysconfig gpmc_sysc = {
  945. .rev_offs = 0x0,
  946. .sysc_offs = 0x10,
  947. .syss_offs = 0x14,
  948. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
  949. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  950. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  951. .sysc_fields = &omap_hwmod_sysc_type1,
  952. };
  953. static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
  954. .name = "gpmc",
  955. .sysc = &gpmc_sysc,
  956. };
  957. static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
  958. { .irq = 100 + OMAP_INTC_START, },
  959. { .irq = -1 },
  960. };
  961. static struct omap_hwmod am33xx_gpmc_hwmod = {
  962. .name = "gpmc",
  963. .class = &am33xx_gpmc_hwmod_class,
  964. .clkdm_name = "l3s_clkdm",
  965. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  966. .mpu_irqs = am33xx_gpmc_irqs,
  967. .main_clk = "l3s_gclk",
  968. .prcm = {
  969. .omap4 = {
  970. .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
  971. .modulemode = MODULEMODE_SWCTRL,
  972. },
  973. },
  974. };
  975. /* 'i2c' class */
  976. static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
  977. .sysc_offs = 0x0010,
  978. .syss_offs = 0x0090,
  979. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  980. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  981. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  982. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  983. SIDLE_SMART_WKUP),
  984. .sysc_fields = &omap_hwmod_sysc_type1,
  985. };
  986. static struct omap_hwmod_class i2c_class = {
  987. .name = "i2c",
  988. .sysc = &am33xx_i2c_sysc,
  989. .rev = OMAP_I2C_IP_VERSION_2,
  990. .reset = &omap_i2c_reset,
  991. };
  992. static struct omap_i2c_dev_attr i2c_dev_attr = {
  993. .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
  994. OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
  995. };
  996. /* i2c1 */
  997. static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
  998. { .irq = 70 + OMAP_INTC_START, },
  999. { .irq = -1 },
  1000. };
  1001. static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
  1002. { .name = "tx", .dma_req = 0, },
  1003. { .name = "rx", .dma_req = 0, },
  1004. { .dma_req = -1 }
  1005. };
  1006. static struct omap_hwmod am33xx_i2c1_hwmod = {
  1007. .name = "i2c1",
  1008. .class = &i2c_class,
  1009. .clkdm_name = "l4_wkup_clkdm",
  1010. .mpu_irqs = i2c1_mpu_irqs,
  1011. .sdma_reqs = i2c1_edma_reqs,
  1012. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1013. .main_clk = "dpll_per_m2_div4_wkupdm_ck",
  1014. .prcm = {
  1015. .omap4 = {
  1016. .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
  1017. .modulemode = MODULEMODE_SWCTRL,
  1018. },
  1019. },
  1020. .dev_attr = &i2c_dev_attr,
  1021. };
  1022. /* i2c1 */
  1023. static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
  1024. { .irq = 71 + OMAP_INTC_START, },
  1025. { .irq = -1 },
  1026. };
  1027. static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
  1028. { .name = "tx", .dma_req = 0, },
  1029. { .name = "rx", .dma_req = 0, },
  1030. { .dma_req = -1 }
  1031. };
  1032. static struct omap_hwmod am33xx_i2c2_hwmod = {
  1033. .name = "i2c2",
  1034. .class = &i2c_class,
  1035. .clkdm_name = "l4ls_clkdm",
  1036. .mpu_irqs = i2c2_mpu_irqs,
  1037. .sdma_reqs = i2c2_edma_reqs,
  1038. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1039. .main_clk = "dpll_per_m2_div4_ck",
  1040. .prcm = {
  1041. .omap4 = {
  1042. .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
  1043. .modulemode = MODULEMODE_SWCTRL,
  1044. },
  1045. },
  1046. .dev_attr = &i2c_dev_attr,
  1047. };
  1048. /* i2c3 */
  1049. static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
  1050. { .name = "tx", .dma_req = 0, },
  1051. { .name = "rx", .dma_req = 0, },
  1052. { .dma_req = -1 }
  1053. };
  1054. static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
  1055. { .irq = 30 + OMAP_INTC_START, },
  1056. { .irq = -1 },
  1057. };
  1058. static struct omap_hwmod am33xx_i2c3_hwmod = {
  1059. .name = "i2c3",
  1060. .class = &i2c_class,
  1061. .clkdm_name = "l4ls_clkdm",
  1062. .mpu_irqs = i2c3_mpu_irqs,
  1063. .sdma_reqs = i2c3_edma_reqs,
  1064. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1065. .main_clk = "dpll_per_m2_div4_ck",
  1066. .prcm = {
  1067. .omap4 = {
  1068. .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
  1069. .modulemode = MODULEMODE_SWCTRL,
  1070. },
  1071. },
  1072. .dev_attr = &i2c_dev_attr,
  1073. };
  1074. /* lcdc */
  1075. static struct omap_hwmod_class_sysconfig lcdc_sysc = {
  1076. .rev_offs = 0x0,
  1077. .sysc_offs = 0x54,
  1078. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
  1079. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1080. .sysc_fields = &omap_hwmod_sysc_type2,
  1081. };
  1082. static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
  1083. .name = "lcdc",
  1084. .sysc = &lcdc_sysc,
  1085. };
  1086. static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
  1087. { .irq = 36 + OMAP_INTC_START, },
  1088. { .irq = -1 },
  1089. };
  1090. static struct omap_hwmod am33xx_lcdc_hwmod = {
  1091. .name = "lcdc",
  1092. .class = &am33xx_lcdc_hwmod_class,
  1093. .clkdm_name = "lcdc_clkdm",
  1094. .mpu_irqs = am33xx_lcdc_irqs,
  1095. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
  1096. .main_clk = "lcd_gclk",
  1097. .prcm = {
  1098. .omap4 = {
  1099. .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
  1100. .modulemode = MODULEMODE_SWCTRL,
  1101. },
  1102. },
  1103. };
  1104. /*
  1105. * 'mailbox' class
  1106. * mailbox module allowing communication between the on-chip processors using a
  1107. * queued mailbox-interrupt mechanism.
  1108. */
  1109. static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
  1110. .rev_offs = 0x0000,
  1111. .sysc_offs = 0x0010,
  1112. .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
  1113. SYSC_HAS_SOFTRESET),
  1114. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1115. .sysc_fields = &omap_hwmod_sysc_type2,
  1116. };
  1117. static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
  1118. .name = "mailbox",
  1119. .sysc = &am33xx_mailbox_sysc,
  1120. };
  1121. static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
  1122. { .irq = 77 + OMAP_INTC_START, },
  1123. { .irq = -1 },
  1124. };
  1125. static struct omap_hwmod am33xx_mailbox_hwmod = {
  1126. .name = "mailbox",
  1127. .class = &am33xx_mailbox_hwmod_class,
  1128. .clkdm_name = "l4ls_clkdm",
  1129. .mpu_irqs = am33xx_mailbox_irqs,
  1130. .main_clk = "l4ls_gclk",
  1131. .prcm = {
  1132. .omap4 = {
  1133. .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
  1134. .modulemode = MODULEMODE_SWCTRL,
  1135. },
  1136. },
  1137. };
  1138. /*
  1139. * 'mcasp' class
  1140. */
  1141. static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
  1142. .rev_offs = 0x0,
  1143. .sysc_offs = 0x4,
  1144. .sysc_flags = SYSC_HAS_SIDLEMODE,
  1145. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1146. .sysc_fields = &omap_hwmod_sysc_type3,
  1147. };
  1148. static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
  1149. .name = "mcasp",
  1150. .sysc = &am33xx_mcasp_sysc,
  1151. };
  1152. /* mcasp0 */
  1153. static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
  1154. { .name = "ax", .irq = 80 + OMAP_INTC_START, },
  1155. { .name = "ar", .irq = 81 + OMAP_INTC_START, },
  1156. { .irq = -1 },
  1157. };
  1158. static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
  1159. { .name = "tx", .dma_req = 8, },
  1160. { .name = "rx", .dma_req = 9, },
  1161. { .dma_req = -1 }
  1162. };
  1163. static struct omap_hwmod am33xx_mcasp0_hwmod = {
  1164. .name = "mcasp0",
  1165. .class = &am33xx_mcasp_hwmod_class,
  1166. .clkdm_name = "l3s_clkdm",
  1167. .mpu_irqs = am33xx_mcasp0_irqs,
  1168. .sdma_reqs = am33xx_mcasp0_edma_reqs,
  1169. .main_clk = "mcasp0_fck",
  1170. .prcm = {
  1171. .omap4 = {
  1172. .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
  1173. .modulemode = MODULEMODE_SWCTRL,
  1174. },
  1175. },
  1176. };
  1177. /* mcasp1 */
  1178. static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
  1179. { .name = "ax", .irq = 82 + OMAP_INTC_START, },
  1180. { .name = "ar", .irq = 83 + OMAP_INTC_START, },
  1181. { .irq = -1 },
  1182. };
  1183. static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
  1184. { .name = "tx", .dma_req = 10, },
  1185. { .name = "rx", .dma_req = 11, },
  1186. { .dma_req = -1 }
  1187. };
  1188. static struct omap_hwmod am33xx_mcasp1_hwmod = {
  1189. .name = "mcasp1",
  1190. .class = &am33xx_mcasp_hwmod_class,
  1191. .clkdm_name = "l3s_clkdm",
  1192. .mpu_irqs = am33xx_mcasp1_irqs,
  1193. .sdma_reqs = am33xx_mcasp1_edma_reqs,
  1194. .main_clk = "mcasp1_fck",
  1195. .prcm = {
  1196. .omap4 = {
  1197. .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
  1198. .modulemode = MODULEMODE_SWCTRL,
  1199. },
  1200. },
  1201. };
  1202. /* 'mmc' class */
  1203. static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
  1204. .rev_offs = 0x1fc,
  1205. .sysc_offs = 0x10,
  1206. .syss_offs = 0x14,
  1207. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1208. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  1209. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  1210. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1211. .sysc_fields = &omap_hwmod_sysc_type1,
  1212. };
  1213. static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
  1214. .name = "mmc",
  1215. .sysc = &am33xx_mmc_sysc,
  1216. };
  1217. /* mmc0 */
  1218. static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
  1219. { .irq = 64 + OMAP_INTC_START, },
  1220. { .irq = -1 },
  1221. };
  1222. static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
  1223. { .name = "tx", .dma_req = 24, },
  1224. { .name = "rx", .dma_req = 25, },
  1225. { .dma_req = -1 }
  1226. };
  1227. static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
  1228. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1229. };
  1230. static struct omap_hwmod am33xx_mmc0_hwmod = {
  1231. .name = "mmc1",
  1232. .class = &am33xx_mmc_hwmod_class,
  1233. .clkdm_name = "l4ls_clkdm",
  1234. .mpu_irqs = am33xx_mmc0_irqs,
  1235. .sdma_reqs = am33xx_mmc0_edma_reqs,
  1236. .main_clk = "mmc_clk",
  1237. .prcm = {
  1238. .omap4 = {
  1239. .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
  1240. .modulemode = MODULEMODE_SWCTRL,
  1241. },
  1242. },
  1243. .dev_attr = &am33xx_mmc0_dev_attr,
  1244. };
  1245. /* mmc1 */
  1246. static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
  1247. { .irq = 28 + OMAP_INTC_START, },
  1248. { .irq = -1 },
  1249. };
  1250. static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
  1251. { .name = "tx", .dma_req = 2, },
  1252. { .name = "rx", .dma_req = 3, },
  1253. { .dma_req = -1 }
  1254. };
  1255. static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
  1256. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1257. };
  1258. static struct omap_hwmod am33xx_mmc1_hwmod = {
  1259. .name = "mmc2",
  1260. .class = &am33xx_mmc_hwmod_class,
  1261. .clkdm_name = "l4ls_clkdm",
  1262. .mpu_irqs = am33xx_mmc1_irqs,
  1263. .sdma_reqs = am33xx_mmc1_edma_reqs,
  1264. .main_clk = "mmc_clk",
  1265. .prcm = {
  1266. .omap4 = {
  1267. .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
  1268. .modulemode = MODULEMODE_SWCTRL,
  1269. },
  1270. },
  1271. .dev_attr = &am33xx_mmc1_dev_attr,
  1272. };
  1273. /* mmc2 */
  1274. static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
  1275. { .irq = 29 + OMAP_INTC_START, },
  1276. { .irq = -1 },
  1277. };
  1278. static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
  1279. { .name = "tx", .dma_req = 64, },
  1280. { .name = "rx", .dma_req = 65, },
  1281. { .dma_req = -1 }
  1282. };
  1283. static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
  1284. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1285. };
  1286. static struct omap_hwmod am33xx_mmc2_hwmod = {
  1287. .name = "mmc3",
  1288. .class = &am33xx_mmc_hwmod_class,
  1289. .clkdm_name = "l3s_clkdm",
  1290. .mpu_irqs = am33xx_mmc2_irqs,
  1291. .sdma_reqs = am33xx_mmc2_edma_reqs,
  1292. .main_clk = "mmc_clk",
  1293. .prcm = {
  1294. .omap4 = {
  1295. .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
  1296. .modulemode = MODULEMODE_SWCTRL,
  1297. },
  1298. },
  1299. .dev_attr = &am33xx_mmc2_dev_attr,
  1300. };
  1301. /*
  1302. * 'rtc' class
  1303. * rtc subsystem
  1304. */
  1305. static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
  1306. .rev_offs = 0x0074,
  1307. .sysc_offs = 0x0078,
  1308. .sysc_flags = SYSC_HAS_SIDLEMODE,
  1309. .idlemodes = (SIDLE_FORCE | SIDLE_NO |
  1310. SIDLE_SMART | SIDLE_SMART_WKUP),
  1311. .sysc_fields = &omap_hwmod_sysc_type3,
  1312. };
  1313. static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
  1314. .name = "rtc",
  1315. .sysc = &am33xx_rtc_sysc,
  1316. };
  1317. static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
  1318. { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
  1319. { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
  1320. { .irq = -1 },
  1321. };
  1322. static struct omap_hwmod am33xx_rtc_hwmod = {
  1323. .name = "rtc",
  1324. .class = &am33xx_rtc_hwmod_class,
  1325. .clkdm_name = "l4_rtc_clkdm",
  1326. .mpu_irqs = am33xx_rtc_irqs,
  1327. .main_clk = "clk_32768_ck",
  1328. .prcm = {
  1329. .omap4 = {
  1330. .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
  1331. .modulemode = MODULEMODE_SWCTRL,
  1332. },
  1333. },
  1334. };
  1335. /* 'spi' class */
  1336. static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
  1337. .rev_offs = 0x0000,
  1338. .sysc_offs = 0x0110,
  1339. .syss_offs = 0x0114,
  1340. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1341. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  1342. SYSS_HAS_RESET_STATUS),
  1343. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1344. .sysc_fields = &omap_hwmod_sysc_type1,
  1345. };
  1346. static struct omap_hwmod_class am33xx_spi_hwmod_class = {
  1347. .name = "mcspi",
  1348. .sysc = &am33xx_mcspi_sysc,
  1349. .rev = OMAP4_MCSPI_REV,
  1350. };
  1351. /* spi0 */
  1352. static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
  1353. { .irq = 65 + OMAP_INTC_START, },
  1354. { .irq = -1 },
  1355. };
  1356. static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
  1357. { .name = "rx0", .dma_req = 17 },
  1358. { .name = "tx0", .dma_req = 16 },
  1359. { .name = "rx1", .dma_req = 19 },
  1360. { .name = "tx1", .dma_req = 18 },
  1361. { .dma_req = -1 }
  1362. };
  1363. static struct omap2_mcspi_dev_attr mcspi_attrib = {
  1364. .num_chipselect = 2,
  1365. };
  1366. static struct omap_hwmod am33xx_spi0_hwmod = {
  1367. .name = "spi0",
  1368. .class = &am33xx_spi_hwmod_class,
  1369. .clkdm_name = "l4ls_clkdm",
  1370. .mpu_irqs = am33xx_spi0_irqs,
  1371. .sdma_reqs = am33xx_mcspi0_edma_reqs,
  1372. .main_clk = "dpll_per_m2_div4_ck",
  1373. .prcm = {
  1374. .omap4 = {
  1375. .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
  1376. .modulemode = MODULEMODE_SWCTRL,
  1377. },
  1378. },
  1379. .dev_attr = &mcspi_attrib,
  1380. };
  1381. /* spi1 */
  1382. static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
  1383. { .irq = 125 + OMAP_INTC_START, },
  1384. { .irq = -1 },
  1385. };
  1386. static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
  1387. { .name = "rx0", .dma_req = 43 },
  1388. { .name = "tx0", .dma_req = 42 },
  1389. { .name = "rx1", .dma_req = 45 },
  1390. { .name = "tx1", .dma_req = 44 },
  1391. { .dma_req = -1 }
  1392. };
  1393. static struct omap_hwmod am33xx_spi1_hwmod = {
  1394. .name = "spi1",
  1395. .class = &am33xx_spi_hwmod_class,
  1396. .clkdm_name = "l4ls_clkdm",
  1397. .mpu_irqs = am33xx_spi1_irqs,
  1398. .sdma_reqs = am33xx_mcspi1_edma_reqs,
  1399. .main_clk = "dpll_per_m2_div4_ck",
  1400. .prcm = {
  1401. .omap4 = {
  1402. .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
  1403. .modulemode = MODULEMODE_SWCTRL,
  1404. },
  1405. },
  1406. .dev_attr = &mcspi_attrib,
  1407. };
  1408. /*
  1409. * 'spinlock' class
  1410. * spinlock provides hardware assistance for synchronizing the
  1411. * processes running on multiple processors
  1412. */
  1413. static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
  1414. .name = "spinlock",
  1415. };
  1416. static struct omap_hwmod am33xx_spinlock_hwmod = {
  1417. .name = "spinlock",
  1418. .class = &am33xx_spinlock_hwmod_class,
  1419. .clkdm_name = "l4ls_clkdm",
  1420. .main_clk = "l4ls_gclk",
  1421. .prcm = {
  1422. .omap4 = {
  1423. .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
  1424. .modulemode = MODULEMODE_SWCTRL,
  1425. },
  1426. },
  1427. };
  1428. /* 'timer 2-7' class */
  1429. static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
  1430. .rev_offs = 0x0000,
  1431. .sysc_offs = 0x0010,
  1432. .syss_offs = 0x0014,
  1433. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1434. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1435. SIDLE_SMART_WKUP),
  1436. .sysc_fields = &omap_hwmod_sysc_type2,
  1437. };
  1438. static struct omap_hwmod_class am33xx_timer_hwmod_class = {
  1439. .name = "timer",
  1440. .sysc = &am33xx_timer_sysc,
  1441. };
  1442. /* timer1 1ms */
  1443. static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
  1444. .rev_offs = 0x0000,
  1445. .sysc_offs = 0x0010,
  1446. .syss_offs = 0x0014,
  1447. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1448. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  1449. SYSS_HAS_RESET_STATUS),
  1450. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1451. .sysc_fields = &omap_hwmod_sysc_type1,
  1452. };
  1453. static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
  1454. .name = "timer",
  1455. .sysc = &am33xx_timer1ms_sysc,
  1456. };
  1457. static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
  1458. { .irq = 67 + OMAP_INTC_START, },
  1459. { .irq = -1 },
  1460. };
  1461. static struct omap_hwmod am33xx_timer1_hwmod = {
  1462. .name = "timer1",
  1463. .class = &am33xx_timer1ms_hwmod_class,
  1464. .clkdm_name = "l4_wkup_clkdm",
  1465. .mpu_irqs = am33xx_timer1_irqs,
  1466. .main_clk = "timer1_fck",
  1467. .prcm = {
  1468. .omap4 = {
  1469. .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
  1470. .modulemode = MODULEMODE_SWCTRL,
  1471. },
  1472. },
  1473. };
  1474. static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
  1475. { .irq = 68 + OMAP_INTC_START, },
  1476. { .irq = -1 },
  1477. };
  1478. static struct omap_hwmod am33xx_timer2_hwmod = {
  1479. .name = "timer2",
  1480. .class = &am33xx_timer_hwmod_class,
  1481. .clkdm_name = "l4ls_clkdm",
  1482. .mpu_irqs = am33xx_timer2_irqs,
  1483. .main_clk = "timer2_fck",
  1484. .prcm = {
  1485. .omap4 = {
  1486. .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
  1487. .modulemode = MODULEMODE_SWCTRL,
  1488. },
  1489. },
  1490. };
  1491. static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
  1492. { .irq = 69 + OMAP_INTC_START, },
  1493. { .irq = -1 },
  1494. };
  1495. static struct omap_hwmod am33xx_timer3_hwmod = {
  1496. .name = "timer3",
  1497. .class = &am33xx_timer_hwmod_class,
  1498. .clkdm_name = "l4ls_clkdm",
  1499. .mpu_irqs = am33xx_timer3_irqs,
  1500. .main_clk = "timer3_fck",
  1501. .prcm = {
  1502. .omap4 = {
  1503. .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
  1504. .modulemode = MODULEMODE_SWCTRL,
  1505. },
  1506. },
  1507. };
  1508. static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
  1509. { .irq = 92 + OMAP_INTC_START, },
  1510. { .irq = -1 },
  1511. };
  1512. static struct omap_hwmod am33xx_timer4_hwmod = {
  1513. .name = "timer4",
  1514. .class = &am33xx_timer_hwmod_class,
  1515. .clkdm_name = "l4ls_clkdm",
  1516. .mpu_irqs = am33xx_timer4_irqs,
  1517. .main_clk = "timer4_fck",
  1518. .prcm = {
  1519. .omap4 = {
  1520. .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
  1521. .modulemode = MODULEMODE_SWCTRL,
  1522. },
  1523. },
  1524. };
  1525. static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
  1526. { .irq = 93 + OMAP_INTC_START, },
  1527. { .irq = -1 },
  1528. };
  1529. static struct omap_hwmod am33xx_timer5_hwmod = {
  1530. .name = "timer5",
  1531. .class = &am33xx_timer_hwmod_class,
  1532. .clkdm_name = "l4ls_clkdm",
  1533. .mpu_irqs = am33xx_timer5_irqs,
  1534. .main_clk = "timer5_fck",
  1535. .prcm = {
  1536. .omap4 = {
  1537. .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
  1538. .modulemode = MODULEMODE_SWCTRL,
  1539. },
  1540. },
  1541. };
  1542. static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
  1543. { .irq = 94 + OMAP_INTC_START, },
  1544. { .irq = -1 },
  1545. };
  1546. static struct omap_hwmod am33xx_timer6_hwmod = {
  1547. .name = "timer6",
  1548. .class = &am33xx_timer_hwmod_class,
  1549. .clkdm_name = "l4ls_clkdm",
  1550. .mpu_irqs = am33xx_timer6_irqs,
  1551. .main_clk = "timer6_fck",
  1552. .prcm = {
  1553. .omap4 = {
  1554. .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
  1555. .modulemode = MODULEMODE_SWCTRL,
  1556. },
  1557. },
  1558. };
  1559. static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
  1560. { .irq = 95 + OMAP_INTC_START, },
  1561. { .irq = -1 },
  1562. };
  1563. static struct omap_hwmod am33xx_timer7_hwmod = {
  1564. .name = "timer7",
  1565. .class = &am33xx_timer_hwmod_class,
  1566. .clkdm_name = "l4ls_clkdm",
  1567. .mpu_irqs = am33xx_timer7_irqs,
  1568. .main_clk = "timer7_fck",
  1569. .prcm = {
  1570. .omap4 = {
  1571. .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
  1572. .modulemode = MODULEMODE_SWCTRL,
  1573. },
  1574. },
  1575. };
  1576. /* tpcc */
  1577. static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
  1578. .name = "tpcc",
  1579. };
  1580. static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
  1581. { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
  1582. { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
  1583. { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
  1584. { .irq = -1 },
  1585. };
  1586. static struct omap_hwmod am33xx_tpcc_hwmod = {
  1587. .name = "tpcc",
  1588. .class = &am33xx_tpcc_hwmod_class,
  1589. .clkdm_name = "l3_clkdm",
  1590. .mpu_irqs = am33xx_tpcc_irqs,
  1591. .main_clk = "l3_gclk",
  1592. .prcm = {
  1593. .omap4 = {
  1594. .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
  1595. .modulemode = MODULEMODE_SWCTRL,
  1596. },
  1597. },
  1598. };
  1599. static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
  1600. .rev_offs = 0x0,
  1601. .sysc_offs = 0x10,
  1602. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  1603. SYSC_HAS_MIDLEMODE),
  1604. .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
  1605. .sysc_fields = &omap_hwmod_sysc_type2,
  1606. };
  1607. /* 'tptc' class */
  1608. static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
  1609. .name = "tptc",
  1610. .sysc = &am33xx_tptc_sysc,
  1611. };
  1612. /* tptc0 */
  1613. static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
  1614. { .irq = 112 + OMAP_INTC_START, },
  1615. { .irq = -1 },
  1616. };
  1617. static struct omap_hwmod am33xx_tptc0_hwmod = {
  1618. .name = "tptc0",
  1619. .class = &am33xx_tptc_hwmod_class,
  1620. .clkdm_name = "l3_clkdm",
  1621. .mpu_irqs = am33xx_tptc0_irqs,
  1622. .main_clk = "l3_gclk",
  1623. .prcm = {
  1624. .omap4 = {
  1625. .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
  1626. .modulemode = MODULEMODE_SWCTRL,
  1627. },
  1628. },
  1629. };
  1630. /* tptc1 */
  1631. static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
  1632. { .irq = 113 + OMAP_INTC_START, },
  1633. { .irq = -1 },
  1634. };
  1635. static struct omap_hwmod am33xx_tptc1_hwmod = {
  1636. .name = "tptc1",
  1637. .class = &am33xx_tptc_hwmod_class,
  1638. .clkdm_name = "l3_clkdm",
  1639. .mpu_irqs = am33xx_tptc1_irqs,
  1640. .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
  1641. .main_clk = "l3_gclk",
  1642. .prcm = {
  1643. .omap4 = {
  1644. .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
  1645. .modulemode = MODULEMODE_SWCTRL,
  1646. },
  1647. },
  1648. };
  1649. /* tptc2 */
  1650. static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
  1651. { .irq = 114 + OMAP_INTC_START, },
  1652. { .irq = -1 },
  1653. };
  1654. static struct omap_hwmod am33xx_tptc2_hwmod = {
  1655. .name = "tptc2",
  1656. .class = &am33xx_tptc_hwmod_class,
  1657. .clkdm_name = "l3_clkdm",
  1658. .mpu_irqs = am33xx_tptc2_irqs,
  1659. .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
  1660. .main_clk = "l3_gclk",
  1661. .prcm = {
  1662. .omap4 = {
  1663. .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
  1664. .modulemode = MODULEMODE_SWCTRL,
  1665. },
  1666. },
  1667. };
  1668. /* 'uart' class */
  1669. static struct omap_hwmod_class_sysconfig uart_sysc = {
  1670. .rev_offs = 0x50,
  1671. .sysc_offs = 0x54,
  1672. .syss_offs = 0x58,
  1673. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
  1674. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1675. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1676. SIDLE_SMART_WKUP),
  1677. .sysc_fields = &omap_hwmod_sysc_type1,
  1678. };
  1679. static struct omap_hwmod_class uart_class = {
  1680. .name = "uart",
  1681. .sysc = &uart_sysc,
  1682. };
  1683. /* uart1 */
  1684. static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
  1685. { .name = "tx", .dma_req = 26, },
  1686. { .name = "rx", .dma_req = 27, },
  1687. { .dma_req = -1 }
  1688. };
  1689. static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
  1690. { .irq = 72 + OMAP_INTC_START, },
  1691. { .irq = -1 },
  1692. };
  1693. static struct omap_hwmod am33xx_uart1_hwmod = {
  1694. .name = "uart1",
  1695. .class = &uart_class,
  1696. .clkdm_name = "l4_wkup_clkdm",
  1697. .mpu_irqs = am33xx_uart1_irqs,
  1698. .sdma_reqs = uart1_edma_reqs,
  1699. .main_clk = "dpll_per_m2_div4_wkupdm_ck",
  1700. .prcm = {
  1701. .omap4 = {
  1702. .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
  1703. .modulemode = MODULEMODE_SWCTRL,
  1704. },
  1705. },
  1706. };
  1707. static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
  1708. { .irq = 73 + OMAP_INTC_START, },
  1709. { .irq = -1 },
  1710. };
  1711. static struct omap_hwmod am33xx_uart2_hwmod = {
  1712. .name = "uart2",
  1713. .class = &uart_class,
  1714. .clkdm_name = "l4ls_clkdm",
  1715. .mpu_irqs = am33xx_uart2_irqs,
  1716. .sdma_reqs = uart1_edma_reqs,
  1717. .main_clk = "dpll_per_m2_div4_ck",
  1718. .prcm = {
  1719. .omap4 = {
  1720. .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
  1721. .modulemode = MODULEMODE_SWCTRL,
  1722. },
  1723. },
  1724. };
  1725. /* uart3 */
  1726. static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
  1727. { .name = "tx", .dma_req = 30, },
  1728. { .name = "rx", .dma_req = 31, },
  1729. { .dma_req = -1 }
  1730. };
  1731. static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
  1732. { .irq = 74 + OMAP_INTC_START, },
  1733. { .irq = -1 },
  1734. };
  1735. static struct omap_hwmod am33xx_uart3_hwmod = {
  1736. .name = "uart3",
  1737. .class = &uart_class,
  1738. .clkdm_name = "l4ls_clkdm",
  1739. .mpu_irqs = am33xx_uart3_irqs,
  1740. .sdma_reqs = uart3_edma_reqs,
  1741. .main_clk = "dpll_per_m2_div4_ck",
  1742. .prcm = {
  1743. .omap4 = {
  1744. .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
  1745. .modulemode = MODULEMODE_SWCTRL,
  1746. },
  1747. },
  1748. };
  1749. static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
  1750. { .irq = 44 + OMAP_INTC_START, },
  1751. { .irq = -1 },
  1752. };
  1753. static struct omap_hwmod am33xx_uart4_hwmod = {
  1754. .name = "uart4",
  1755. .class = &uart_class,
  1756. .clkdm_name = "l4ls_clkdm",
  1757. .mpu_irqs = am33xx_uart4_irqs,
  1758. .sdma_reqs = uart1_edma_reqs,
  1759. .main_clk = "dpll_per_m2_div4_ck",
  1760. .prcm = {
  1761. .omap4 = {
  1762. .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
  1763. .modulemode = MODULEMODE_SWCTRL,
  1764. },
  1765. },
  1766. };
  1767. static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
  1768. { .irq = 45 + OMAP_INTC_START, },
  1769. { .irq = -1 },
  1770. };
  1771. static struct omap_hwmod am33xx_uart5_hwmod = {
  1772. .name = "uart5",
  1773. .class = &uart_class,
  1774. .clkdm_name = "l4ls_clkdm",
  1775. .mpu_irqs = am33xx_uart5_irqs,
  1776. .sdma_reqs = uart1_edma_reqs,
  1777. .main_clk = "dpll_per_m2_div4_ck",
  1778. .prcm = {
  1779. .omap4 = {
  1780. .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
  1781. .modulemode = MODULEMODE_SWCTRL,
  1782. },
  1783. },
  1784. };
  1785. static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
  1786. { .irq = 46 + OMAP_INTC_START, },
  1787. { .irq = -1 },
  1788. };
  1789. static struct omap_hwmod am33xx_uart6_hwmod = {
  1790. .name = "uart6",
  1791. .class = &uart_class,
  1792. .clkdm_name = "l4ls_clkdm",
  1793. .mpu_irqs = am33xx_uart6_irqs,
  1794. .sdma_reqs = uart1_edma_reqs,
  1795. .main_clk = "dpll_per_m2_div4_ck",
  1796. .prcm = {
  1797. .omap4 = {
  1798. .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
  1799. .modulemode = MODULEMODE_SWCTRL,
  1800. },
  1801. },
  1802. };
  1803. /* 'wd_timer' class */
  1804. static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
  1805. .name = "wd_timer",
  1806. };
  1807. /*
  1808. * XXX: device.c file uses hardcoded name for watchdog timer
  1809. * driver "wd_timer2, so we are also using same name as of now...
  1810. */
  1811. static struct omap_hwmod am33xx_wd_timer1_hwmod = {
  1812. .name = "wd_timer2",
  1813. .class = &am33xx_wd_timer_hwmod_class,
  1814. .clkdm_name = "l4_wkup_clkdm",
  1815. .main_clk = "wdt1_fck",
  1816. .prcm = {
  1817. .omap4 = {
  1818. .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
  1819. .modulemode = MODULEMODE_SWCTRL,
  1820. },
  1821. },
  1822. };
  1823. /*
  1824. * 'usb_otg' class
  1825. * high-speed on-the-go universal serial bus (usb_otg) controller
  1826. */
  1827. static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
  1828. .rev_offs = 0x0,
  1829. .sysc_offs = 0x10,
  1830. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
  1831. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1832. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  1833. .sysc_fields = &omap_hwmod_sysc_type2,
  1834. };
  1835. static struct omap_hwmod_class am33xx_usbotg_class = {
  1836. .name = "usbotg",
  1837. .sysc = &am33xx_usbhsotg_sysc,
  1838. };
  1839. static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
  1840. { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
  1841. { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
  1842. { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
  1843. { .irq = -1 + OMAP_INTC_START, },
  1844. };
  1845. static struct omap_hwmod am33xx_usbss_hwmod = {
  1846. .name = "usb_otg_hs",
  1847. .class = &am33xx_usbotg_class,
  1848. .clkdm_name = "l3s_clkdm",
  1849. .mpu_irqs = am33xx_usbss_mpu_irqs,
  1850. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
  1851. .main_clk = "usbotg_fck",
  1852. .prcm = {
  1853. .omap4 = {
  1854. .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
  1855. .modulemode = MODULEMODE_SWCTRL,
  1856. },
  1857. },
  1858. };
  1859. /*
  1860. * Interfaces
  1861. */
  1862. /* l4 fw -> emif fw */
  1863. static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
  1864. .master = &am33xx_l4_fw_hwmod,
  1865. .slave = &am33xx_emif_fw_hwmod,
  1866. .clk = "l4fw_gclk",
  1867. .user = OCP_USER_MPU,
  1868. };
  1869. static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
  1870. {
  1871. .pa_start = 0x4c000000,
  1872. .pa_end = 0x4c000fff,
  1873. .flags = ADDR_TYPE_RT
  1874. },
  1875. { }
  1876. };
  1877. /* l3 main -> emif */
  1878. static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
  1879. .master = &am33xx_l3_main_hwmod,
  1880. .slave = &am33xx_emif_hwmod,
  1881. .clk = "dpll_core_m4_ck",
  1882. .addr = am33xx_emif_addrs,
  1883. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1884. };
  1885. /* mpu -> l3 main */
  1886. static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
  1887. .master = &am33xx_mpu_hwmod,
  1888. .slave = &am33xx_l3_main_hwmod,
  1889. .clk = "dpll_mpu_m2_ck",
  1890. .user = OCP_USER_MPU,
  1891. };
  1892. /* l3 main -> l4 hs */
  1893. static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
  1894. .master = &am33xx_l3_main_hwmod,
  1895. .slave = &am33xx_l4_hs_hwmod,
  1896. .clk = "l3s_gclk",
  1897. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1898. };
  1899. /* l3 main -> l3 s */
  1900. static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
  1901. .master = &am33xx_l3_main_hwmod,
  1902. .slave = &am33xx_l3_s_hwmod,
  1903. .clk = "l3s_gclk",
  1904. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1905. };
  1906. /* l3 s -> l4 per/ls */
  1907. static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
  1908. .master = &am33xx_l3_s_hwmod,
  1909. .slave = &am33xx_l4_ls_hwmod,
  1910. .clk = "l3s_gclk",
  1911. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1912. };
  1913. /* l3 s -> l4 wkup */
  1914. static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
  1915. .master = &am33xx_l3_s_hwmod,
  1916. .slave = &am33xx_l4_wkup_hwmod,
  1917. .clk = "l3s_gclk",
  1918. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1919. };
  1920. /* l3 s -> l4 fw */
  1921. static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
  1922. .master = &am33xx_l3_s_hwmod,
  1923. .slave = &am33xx_l4_fw_hwmod,
  1924. .clk = "l3s_gclk",
  1925. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1926. };
  1927. /* l3 main -> l3 instr */
  1928. static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
  1929. .master = &am33xx_l3_main_hwmod,
  1930. .slave = &am33xx_l3_instr_hwmod,
  1931. .clk = "l3s_gclk",
  1932. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1933. };
  1934. /* mpu -> prcm */
  1935. static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
  1936. .master = &am33xx_mpu_hwmod,
  1937. .slave = &am33xx_prcm_hwmod,
  1938. .clk = "dpll_mpu_m2_ck",
  1939. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1940. };
  1941. /* l3 s -> l3 main*/
  1942. static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
  1943. .master = &am33xx_l3_s_hwmod,
  1944. .slave = &am33xx_l3_main_hwmod,
  1945. .clk = "l3s_gclk",
  1946. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1947. };
  1948. /* pru-icss -> l3 main */
  1949. static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
  1950. .master = &am33xx_pruss_hwmod,
  1951. .slave = &am33xx_l3_main_hwmod,
  1952. .clk = "l3_gclk",
  1953. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1954. };
  1955. /* wkup m3 -> l4 wkup */
  1956. static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
  1957. .master = &am33xx_wkup_m3_hwmod,
  1958. .slave = &am33xx_l4_wkup_hwmod,
  1959. .clk = "dpll_core_m4_div2_ck",
  1960. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1961. };
  1962. /* gfx -> l3 main */
  1963. static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
  1964. .master = &am33xx_gfx_hwmod,
  1965. .slave = &am33xx_l3_main_hwmod,
  1966. .clk = "dpll_core_m4_ck",
  1967. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1968. };
  1969. /* l4 wkup -> wkup m3 */
  1970. static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
  1971. {
  1972. .name = "umem",
  1973. .pa_start = 0x44d00000,
  1974. .pa_end = 0x44d00000 + SZ_16K - 1,
  1975. .flags = ADDR_TYPE_RT
  1976. },
  1977. {
  1978. .name = "dmem",
  1979. .pa_start = 0x44d80000,
  1980. .pa_end = 0x44d80000 + SZ_8K - 1,
  1981. .flags = ADDR_TYPE_RT
  1982. },
  1983. { }
  1984. };
  1985. static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
  1986. .master = &am33xx_l4_wkup_hwmod,
  1987. .slave = &am33xx_wkup_m3_hwmod,
  1988. .clk = "dpll_core_m4_div2_ck",
  1989. .addr = am33xx_wkup_m3_addrs,
  1990. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1991. };
  1992. /* l4 hs -> pru-icss */
  1993. static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
  1994. {
  1995. .pa_start = 0x4a300000,
  1996. .pa_end = 0x4a300000 + SZ_512K - 1,
  1997. .flags = ADDR_TYPE_RT
  1998. },
  1999. { }
  2000. };
  2001. static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
  2002. .master = &am33xx_l4_hs_hwmod,
  2003. .slave = &am33xx_pruss_hwmod,
  2004. .clk = "dpll_core_m4_ck",
  2005. .addr = am33xx_pruss_addrs,
  2006. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2007. };
  2008. /* l3 main -> gfx */
  2009. static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
  2010. {
  2011. .pa_start = 0x56000000,
  2012. .pa_end = 0x56000000 + SZ_16M - 1,
  2013. .flags = ADDR_TYPE_RT
  2014. },
  2015. { }
  2016. };
  2017. static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
  2018. .master = &am33xx_l3_main_hwmod,
  2019. .slave = &am33xx_gfx_hwmod,
  2020. .clk = "dpll_core_m4_ck",
  2021. .addr = am33xx_gfx_addrs,
  2022. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2023. };
  2024. /* l4 wkup -> smartreflex0 */
  2025. static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
  2026. {
  2027. .pa_start = 0x44e37000,
  2028. .pa_end = 0x44e37000 + SZ_4K - 1,
  2029. .flags = ADDR_TYPE_RT
  2030. },
  2031. { }
  2032. };
  2033. static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
  2034. .master = &am33xx_l4_wkup_hwmod,
  2035. .slave = &am33xx_smartreflex0_hwmod,
  2036. .clk = "dpll_core_m4_div2_ck",
  2037. .addr = am33xx_smartreflex0_addrs,
  2038. .user = OCP_USER_MPU,
  2039. };
  2040. /* l4 wkup -> smartreflex1 */
  2041. static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
  2042. {
  2043. .pa_start = 0x44e39000,
  2044. .pa_end = 0x44e39000 + SZ_4K - 1,
  2045. .flags = ADDR_TYPE_RT
  2046. },
  2047. { }
  2048. };
  2049. static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
  2050. .master = &am33xx_l4_wkup_hwmod,
  2051. .slave = &am33xx_smartreflex1_hwmod,
  2052. .clk = "dpll_core_m4_div2_ck",
  2053. .addr = am33xx_smartreflex1_addrs,
  2054. .user = OCP_USER_MPU,
  2055. };
  2056. /* l4 wkup -> control */
  2057. static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
  2058. {
  2059. .pa_start = 0x44e10000,
  2060. .pa_end = 0x44e10000 + SZ_8K - 1,
  2061. .flags = ADDR_TYPE_RT
  2062. },
  2063. { }
  2064. };
  2065. static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
  2066. .master = &am33xx_l4_wkup_hwmod,
  2067. .slave = &am33xx_control_hwmod,
  2068. .clk = "dpll_core_m4_div2_ck",
  2069. .addr = am33xx_control_addrs,
  2070. .user = OCP_USER_MPU,
  2071. };
  2072. /* l4 wkup -> rtc */
  2073. static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
  2074. {
  2075. .pa_start = 0x44e3e000,
  2076. .pa_end = 0x44e3e000 + SZ_4K - 1,
  2077. .flags = ADDR_TYPE_RT
  2078. },
  2079. { }
  2080. };
  2081. static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
  2082. .master = &am33xx_l4_wkup_hwmod,
  2083. .slave = &am33xx_rtc_hwmod,
  2084. .clk = "clkdiv32k_ick",
  2085. .addr = am33xx_rtc_addrs,
  2086. .user = OCP_USER_MPU,
  2087. };
  2088. /* l4 per/ls -> DCAN0 */
  2089. static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
  2090. {
  2091. .pa_start = 0x481CC000,
  2092. .pa_end = 0x481CC000 + SZ_4K - 1,
  2093. .flags = ADDR_TYPE_RT
  2094. },
  2095. { }
  2096. };
  2097. static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
  2098. .master = &am33xx_l4_ls_hwmod,
  2099. .slave = &am33xx_dcan0_hwmod,
  2100. .clk = "l4ls_gclk",
  2101. .addr = am33xx_dcan0_addrs,
  2102. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2103. };
  2104. /* l4 per/ls -> DCAN1 */
  2105. static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
  2106. {
  2107. .pa_start = 0x481D0000,
  2108. .pa_end = 0x481D0000 + SZ_4K - 1,
  2109. .flags = ADDR_TYPE_RT
  2110. },
  2111. { }
  2112. };
  2113. static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
  2114. .master = &am33xx_l4_ls_hwmod,
  2115. .slave = &am33xx_dcan1_hwmod,
  2116. .clk = "l4ls_gclk",
  2117. .addr = am33xx_dcan1_addrs,
  2118. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2119. };
  2120. /* l4 per/ls -> GPIO2 */
  2121. static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
  2122. {
  2123. .pa_start = 0x4804C000,
  2124. .pa_end = 0x4804C000 + SZ_4K - 1,
  2125. .flags = ADDR_TYPE_RT,
  2126. },
  2127. { }
  2128. };
  2129. static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
  2130. .master = &am33xx_l4_ls_hwmod,
  2131. .slave = &am33xx_gpio1_hwmod,
  2132. .clk = "l4ls_gclk",
  2133. .addr = am33xx_gpio1_addrs,
  2134. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2135. };
  2136. /* l4 per/ls -> gpio3 */
  2137. static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
  2138. {
  2139. .pa_start = 0x481AC000,
  2140. .pa_end = 0x481AC000 + SZ_4K - 1,
  2141. .flags = ADDR_TYPE_RT,
  2142. },
  2143. { }
  2144. };
  2145. static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
  2146. .master = &am33xx_l4_ls_hwmod,
  2147. .slave = &am33xx_gpio2_hwmod,
  2148. .clk = "l4ls_gclk",
  2149. .addr = am33xx_gpio2_addrs,
  2150. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2151. };
  2152. /* l4 per/ls -> gpio4 */
  2153. static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
  2154. {
  2155. .pa_start = 0x481AE000,
  2156. .pa_end = 0x481AE000 + SZ_4K - 1,
  2157. .flags = ADDR_TYPE_RT,
  2158. },
  2159. { }
  2160. };
  2161. static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
  2162. .master = &am33xx_l4_ls_hwmod,
  2163. .slave = &am33xx_gpio3_hwmod,
  2164. .clk = "l4ls_gclk",
  2165. .addr = am33xx_gpio3_addrs,
  2166. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2167. };
  2168. /* L4 WKUP -> I2C1 */
  2169. static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
  2170. {
  2171. .pa_start = 0x44E0B000,
  2172. .pa_end = 0x44E0B000 + SZ_4K - 1,
  2173. .flags = ADDR_TYPE_RT,
  2174. },
  2175. { }
  2176. };
  2177. static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
  2178. .master = &am33xx_l4_wkup_hwmod,
  2179. .slave = &am33xx_i2c1_hwmod,
  2180. .clk = "dpll_core_m4_div2_ck",
  2181. .addr = am33xx_i2c1_addr_space,
  2182. .user = OCP_USER_MPU,
  2183. };
  2184. /* L4 WKUP -> GPIO1 */
  2185. static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
  2186. {
  2187. .pa_start = 0x44E07000,
  2188. .pa_end = 0x44E07000 + SZ_4K - 1,
  2189. .flags = ADDR_TYPE_RT,
  2190. },
  2191. { }
  2192. };
  2193. static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
  2194. .master = &am33xx_l4_wkup_hwmod,
  2195. .slave = &am33xx_gpio0_hwmod,
  2196. .clk = "dpll_core_m4_div2_ck",
  2197. .addr = am33xx_gpio0_addrs,
  2198. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2199. };
  2200. /* L4 WKUP -> ADC_TSC */
  2201. static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
  2202. {
  2203. .pa_start = 0x44E0D000,
  2204. .pa_end = 0x44E0D000 + SZ_8K - 1,
  2205. .flags = ADDR_TYPE_RT
  2206. },
  2207. { }
  2208. };
  2209. static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
  2210. .master = &am33xx_l4_wkup_hwmod,
  2211. .slave = &am33xx_adc_tsc_hwmod,
  2212. .clk = "dpll_core_m4_div2_ck",
  2213. .addr = am33xx_adc_tsc_addrs,
  2214. .user = OCP_USER_MPU,
  2215. };
  2216. static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
  2217. /* cpsw ss */
  2218. {
  2219. .pa_start = 0x4a100000,
  2220. .pa_end = 0x4a100000 + SZ_2K - 1,
  2221. .flags = ADDR_TYPE_RT,
  2222. },
  2223. /* cpsw wr */
  2224. {
  2225. .pa_start = 0x4a101200,
  2226. .pa_end = 0x4a101200 + SZ_256 - 1,
  2227. .flags = ADDR_TYPE_RT,
  2228. },
  2229. { }
  2230. };
  2231. static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
  2232. .master = &am33xx_l4_hs_hwmod,
  2233. .slave = &am33xx_cpgmac0_hwmod,
  2234. .clk = "cpsw_125mhz_gclk",
  2235. .addr = am33xx_cpgmac0_addr_space,
  2236. .user = OCP_USER_MPU,
  2237. };
  2238. static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
  2239. {
  2240. .pa_start = 0x48080000,
  2241. .pa_end = 0x48080000 + SZ_8K - 1,
  2242. .flags = ADDR_TYPE_RT
  2243. },
  2244. { }
  2245. };
  2246. static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
  2247. .master = &am33xx_l4_ls_hwmod,
  2248. .slave = &am33xx_elm_hwmod,
  2249. .clk = "l4ls_gclk",
  2250. .addr = am33xx_elm_addr_space,
  2251. .user = OCP_USER_MPU,
  2252. };
  2253. /*
  2254. * Splitting the resources to handle access of PWMSS config space
  2255. * and module specific part independently
  2256. */
  2257. static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
  2258. {
  2259. .pa_start = 0x48300000,
  2260. .pa_end = 0x48300000 + SZ_16 - 1,
  2261. .flags = ADDR_TYPE_RT
  2262. },
  2263. {
  2264. .pa_start = 0x48300200,
  2265. .pa_end = 0x48300200 + SZ_256 - 1,
  2266. .flags = ADDR_TYPE_RT
  2267. },
  2268. { }
  2269. };
  2270. static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
  2271. .master = &am33xx_l4_ls_hwmod,
  2272. .slave = &am33xx_ehrpwm0_hwmod,
  2273. .clk = "l4ls_gclk",
  2274. .addr = am33xx_ehrpwm0_addr_space,
  2275. .user = OCP_USER_MPU,
  2276. };
  2277. /*
  2278. * Splitting the resources to handle access of PWMSS config space
  2279. * and module specific part independently
  2280. */
  2281. static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
  2282. {
  2283. .pa_start = 0x48302000,
  2284. .pa_end = 0x48302000 + SZ_16 - 1,
  2285. .flags = ADDR_TYPE_RT
  2286. },
  2287. {
  2288. .pa_start = 0x48302200,
  2289. .pa_end = 0x48302200 + SZ_256 - 1,
  2290. .flags = ADDR_TYPE_RT
  2291. },
  2292. { }
  2293. };
  2294. static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
  2295. .master = &am33xx_l4_ls_hwmod,
  2296. .slave = &am33xx_ehrpwm1_hwmod,
  2297. .clk = "l4ls_gclk",
  2298. .addr = am33xx_ehrpwm1_addr_space,
  2299. .user = OCP_USER_MPU,
  2300. };
  2301. /*
  2302. * Splitting the resources to handle access of PWMSS config space
  2303. * and module specific part independently
  2304. */
  2305. static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
  2306. {
  2307. .pa_start = 0x48304000,
  2308. .pa_end = 0x48304000 + SZ_16 - 1,
  2309. .flags = ADDR_TYPE_RT
  2310. },
  2311. {
  2312. .pa_start = 0x48304200,
  2313. .pa_end = 0x48304200 + SZ_256 - 1,
  2314. .flags = ADDR_TYPE_RT
  2315. },
  2316. { }
  2317. };
  2318. static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
  2319. .master = &am33xx_l4_ls_hwmod,
  2320. .slave = &am33xx_ehrpwm2_hwmod,
  2321. .clk = "l4ls_gclk",
  2322. .addr = am33xx_ehrpwm2_addr_space,
  2323. .user = OCP_USER_MPU,
  2324. };
  2325. /*
  2326. * Splitting the resources to handle access of PWMSS config space
  2327. * and module specific part independently
  2328. */
  2329. static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
  2330. {
  2331. .pa_start = 0x48300000,
  2332. .pa_end = 0x48300000 + SZ_16 - 1,
  2333. .flags = ADDR_TYPE_RT
  2334. },
  2335. {
  2336. .pa_start = 0x48300100,
  2337. .pa_end = 0x48300100 + SZ_256 - 1,
  2338. .flags = ADDR_TYPE_RT
  2339. },
  2340. { }
  2341. };
  2342. static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
  2343. .master = &am33xx_l4_ls_hwmod,
  2344. .slave = &am33xx_ecap0_hwmod,
  2345. .clk = "l4ls_gclk",
  2346. .addr = am33xx_ecap0_addr_space,
  2347. .user = OCP_USER_MPU,
  2348. };
  2349. /*
  2350. * Splitting the resources to handle access of PWMSS config space
  2351. * and module specific part independently
  2352. */
  2353. static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
  2354. {
  2355. .pa_start = 0x48302000,
  2356. .pa_end = 0x48302000 + SZ_16 - 1,
  2357. .flags = ADDR_TYPE_RT
  2358. },
  2359. {
  2360. .pa_start = 0x48302100,
  2361. .pa_end = 0x48302100 + SZ_256 - 1,
  2362. .flags = ADDR_TYPE_RT
  2363. },
  2364. { }
  2365. };
  2366. static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
  2367. .master = &am33xx_l4_ls_hwmod,
  2368. .slave = &am33xx_ecap1_hwmod,
  2369. .clk = "l4ls_gclk",
  2370. .addr = am33xx_ecap1_addr_space,
  2371. .user = OCP_USER_MPU,
  2372. };
  2373. /*
  2374. * Splitting the resources to handle access of PWMSS config space
  2375. * and module specific part independently
  2376. */
  2377. static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
  2378. {
  2379. .pa_start = 0x48304000,
  2380. .pa_end = 0x48304000 + SZ_16 - 1,
  2381. .flags = ADDR_TYPE_RT
  2382. },
  2383. {
  2384. .pa_start = 0x48304100,
  2385. .pa_end = 0x48304100 + SZ_256 - 1,
  2386. .flags = ADDR_TYPE_RT
  2387. },
  2388. { }
  2389. };
  2390. static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
  2391. .master = &am33xx_l4_ls_hwmod,
  2392. .slave = &am33xx_ecap2_hwmod,
  2393. .clk = "l4ls_gclk",
  2394. .addr = am33xx_ecap2_addr_space,
  2395. .user = OCP_USER_MPU,
  2396. };
  2397. /* l3s cfg -> gpmc */
  2398. static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
  2399. {
  2400. .pa_start = 0x50000000,
  2401. .pa_end = 0x50000000 + SZ_8K - 1,
  2402. .flags = ADDR_TYPE_RT,
  2403. },
  2404. { }
  2405. };
  2406. static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
  2407. .master = &am33xx_l3_s_hwmod,
  2408. .slave = &am33xx_gpmc_hwmod,
  2409. .clk = "l3s_gclk",
  2410. .addr = am33xx_gpmc_addr_space,
  2411. .user = OCP_USER_MPU,
  2412. };
  2413. /* i2c2 */
  2414. static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
  2415. {
  2416. .pa_start = 0x4802A000,
  2417. .pa_end = 0x4802A000 + SZ_4K - 1,
  2418. .flags = ADDR_TYPE_RT,
  2419. },
  2420. { }
  2421. };
  2422. static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
  2423. .master = &am33xx_l4_ls_hwmod,
  2424. .slave = &am33xx_i2c2_hwmod,
  2425. .clk = "l4ls_gclk",
  2426. .addr = am33xx_i2c2_addr_space,
  2427. .user = OCP_USER_MPU,
  2428. };
  2429. static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
  2430. {
  2431. .pa_start = 0x4819C000,
  2432. .pa_end = 0x4819C000 + SZ_4K - 1,
  2433. .flags = ADDR_TYPE_RT
  2434. },
  2435. { }
  2436. };
  2437. static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
  2438. .master = &am33xx_l4_ls_hwmod,
  2439. .slave = &am33xx_i2c3_hwmod,
  2440. .clk = "l4ls_gclk",
  2441. .addr = am33xx_i2c3_addr_space,
  2442. .user = OCP_USER_MPU,
  2443. };
  2444. static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
  2445. {
  2446. .pa_start = 0x4830E000,
  2447. .pa_end = 0x4830E000 + SZ_8K - 1,
  2448. .flags = ADDR_TYPE_RT,
  2449. },
  2450. { }
  2451. };
  2452. static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
  2453. .master = &am33xx_l3_main_hwmod,
  2454. .slave = &am33xx_lcdc_hwmod,
  2455. .clk = "dpll_core_m4_ck",
  2456. .addr = am33xx_lcdc_addr_space,
  2457. .user = OCP_USER_MPU,
  2458. };
  2459. static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
  2460. {
  2461. .pa_start = 0x480C8000,
  2462. .pa_end = 0x480C8000 + (SZ_4K - 1),
  2463. .flags = ADDR_TYPE_RT
  2464. },
  2465. { }
  2466. };
  2467. /* l4 ls -> mailbox */
  2468. static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
  2469. .master = &am33xx_l4_ls_hwmod,
  2470. .slave = &am33xx_mailbox_hwmod,
  2471. .clk = "l4ls_gclk",
  2472. .addr = am33xx_mailbox_addrs,
  2473. .user = OCP_USER_MPU,
  2474. };
  2475. /* l4 ls -> spinlock */
  2476. static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
  2477. {
  2478. .pa_start = 0x480Ca000,
  2479. .pa_end = 0x480Ca000 + SZ_4K - 1,
  2480. .flags = ADDR_TYPE_RT
  2481. },
  2482. { }
  2483. };
  2484. static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
  2485. .master = &am33xx_l4_ls_hwmod,
  2486. .slave = &am33xx_spinlock_hwmod,
  2487. .clk = "l4ls_gclk",
  2488. .addr = am33xx_spinlock_addrs,
  2489. .user = OCP_USER_MPU,
  2490. };
  2491. /* l4 ls -> mcasp0 */
  2492. static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
  2493. {
  2494. .pa_start = 0x48038000,
  2495. .pa_end = 0x48038000 + SZ_8K - 1,
  2496. .flags = ADDR_TYPE_RT
  2497. },
  2498. { }
  2499. };
  2500. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
  2501. .master = &am33xx_l4_ls_hwmod,
  2502. .slave = &am33xx_mcasp0_hwmod,
  2503. .clk = "l4ls_gclk",
  2504. .addr = am33xx_mcasp0_addr_space,
  2505. .user = OCP_USER_MPU,
  2506. };
  2507. /* l3 s -> mcasp0 data */
  2508. static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
  2509. {
  2510. .pa_start = 0x46000000,
  2511. .pa_end = 0x46000000 + SZ_4M - 1,
  2512. .flags = ADDR_TYPE_RT
  2513. },
  2514. { }
  2515. };
  2516. static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
  2517. .master = &am33xx_l3_s_hwmod,
  2518. .slave = &am33xx_mcasp0_hwmod,
  2519. .clk = "l3s_gclk",
  2520. .addr = am33xx_mcasp0_data_addr_space,
  2521. .user = OCP_USER_SDMA,
  2522. };
  2523. /* l4 ls -> mcasp1 */
  2524. static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
  2525. {
  2526. .pa_start = 0x4803C000,
  2527. .pa_end = 0x4803C000 + SZ_8K - 1,
  2528. .flags = ADDR_TYPE_RT
  2529. },
  2530. { }
  2531. };
  2532. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
  2533. .master = &am33xx_l4_ls_hwmod,
  2534. .slave = &am33xx_mcasp1_hwmod,
  2535. .clk = "l4ls_gclk",
  2536. .addr = am33xx_mcasp1_addr_space,
  2537. .user = OCP_USER_MPU,
  2538. };
  2539. /* l3 s -> mcasp1 data */
  2540. static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
  2541. {
  2542. .pa_start = 0x46400000,
  2543. .pa_end = 0x46400000 + SZ_4M - 1,
  2544. .flags = ADDR_TYPE_RT
  2545. },
  2546. { }
  2547. };
  2548. static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
  2549. .master = &am33xx_l3_s_hwmod,
  2550. .slave = &am33xx_mcasp1_hwmod,
  2551. .clk = "l3s_gclk",
  2552. .addr = am33xx_mcasp1_data_addr_space,
  2553. .user = OCP_USER_SDMA,
  2554. };
  2555. /* l4 ls -> mmc0 */
  2556. static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
  2557. {
  2558. .pa_start = 0x48060100,
  2559. .pa_end = 0x48060100 + SZ_4K - 1,
  2560. .flags = ADDR_TYPE_RT,
  2561. },
  2562. { }
  2563. };
  2564. static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
  2565. .master = &am33xx_l4_ls_hwmod,
  2566. .slave = &am33xx_mmc0_hwmod,
  2567. .clk = "l4ls_gclk",
  2568. .addr = am33xx_mmc0_addr_space,
  2569. .user = OCP_USER_MPU,
  2570. };
  2571. /* l4 ls -> mmc1 */
  2572. static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
  2573. {
  2574. .pa_start = 0x481d8100,
  2575. .pa_end = 0x481d8100 + SZ_4K - 1,
  2576. .flags = ADDR_TYPE_RT,
  2577. },
  2578. { }
  2579. };
  2580. static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
  2581. .master = &am33xx_l4_ls_hwmod,
  2582. .slave = &am33xx_mmc1_hwmod,
  2583. .clk = "l4ls_gclk",
  2584. .addr = am33xx_mmc1_addr_space,
  2585. .user = OCP_USER_MPU,
  2586. };
  2587. /* l3 s -> mmc2 */
  2588. static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
  2589. {
  2590. .pa_start = 0x47810100,
  2591. .pa_end = 0x47810100 + SZ_64K - 1,
  2592. .flags = ADDR_TYPE_RT,
  2593. },
  2594. { }
  2595. };
  2596. static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
  2597. .master = &am33xx_l3_s_hwmod,
  2598. .slave = &am33xx_mmc2_hwmod,
  2599. .clk = "l3s_gclk",
  2600. .addr = am33xx_mmc2_addr_space,
  2601. .user = OCP_USER_MPU,
  2602. };
  2603. /* l4 ls -> mcspi0 */
  2604. static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
  2605. {
  2606. .pa_start = 0x48030000,
  2607. .pa_end = 0x48030000 + SZ_1K - 1,
  2608. .flags = ADDR_TYPE_RT,
  2609. },
  2610. { }
  2611. };
  2612. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
  2613. .master = &am33xx_l4_ls_hwmod,
  2614. .slave = &am33xx_spi0_hwmod,
  2615. .clk = "l4ls_gclk",
  2616. .addr = am33xx_mcspi0_addr_space,
  2617. .user = OCP_USER_MPU,
  2618. };
  2619. /* l4 ls -> mcspi1 */
  2620. static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
  2621. {
  2622. .pa_start = 0x481A0000,
  2623. .pa_end = 0x481A0000 + SZ_1K - 1,
  2624. .flags = ADDR_TYPE_RT,
  2625. },
  2626. { }
  2627. };
  2628. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
  2629. .master = &am33xx_l4_ls_hwmod,
  2630. .slave = &am33xx_spi1_hwmod,
  2631. .clk = "l4ls_gclk",
  2632. .addr = am33xx_mcspi1_addr_space,
  2633. .user = OCP_USER_MPU,
  2634. };
  2635. /* l4 wkup -> timer1 */
  2636. static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
  2637. {
  2638. .pa_start = 0x44E31000,
  2639. .pa_end = 0x44E31000 + SZ_1K - 1,
  2640. .flags = ADDR_TYPE_RT
  2641. },
  2642. { }
  2643. };
  2644. static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
  2645. .master = &am33xx_l4_wkup_hwmod,
  2646. .slave = &am33xx_timer1_hwmod,
  2647. .clk = "dpll_core_m4_div2_ck",
  2648. .addr = am33xx_timer1_addr_space,
  2649. .user = OCP_USER_MPU,
  2650. };
  2651. /* l4 per -> timer2 */
  2652. static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
  2653. {
  2654. .pa_start = 0x48040000,
  2655. .pa_end = 0x48040000 + SZ_1K - 1,
  2656. .flags = ADDR_TYPE_RT
  2657. },
  2658. { }
  2659. };
  2660. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
  2661. .master = &am33xx_l4_ls_hwmod,
  2662. .slave = &am33xx_timer2_hwmod,
  2663. .clk = "l4ls_gclk",
  2664. .addr = am33xx_timer2_addr_space,
  2665. .user = OCP_USER_MPU,
  2666. };
  2667. /* l4 per -> timer3 */
  2668. static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
  2669. {
  2670. .pa_start = 0x48042000,
  2671. .pa_end = 0x48042000 + SZ_1K - 1,
  2672. .flags = ADDR_TYPE_RT
  2673. },
  2674. { }
  2675. };
  2676. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
  2677. .master = &am33xx_l4_ls_hwmod,
  2678. .slave = &am33xx_timer3_hwmod,
  2679. .clk = "l4ls_gclk",
  2680. .addr = am33xx_timer3_addr_space,
  2681. .user = OCP_USER_MPU,
  2682. };
  2683. /* l4 per -> timer4 */
  2684. static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
  2685. {
  2686. .pa_start = 0x48044000,
  2687. .pa_end = 0x48044000 + SZ_1K - 1,
  2688. .flags = ADDR_TYPE_RT
  2689. },
  2690. { }
  2691. };
  2692. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
  2693. .master = &am33xx_l4_ls_hwmod,
  2694. .slave = &am33xx_timer4_hwmod,
  2695. .clk = "l4ls_gclk",
  2696. .addr = am33xx_timer4_addr_space,
  2697. .user = OCP_USER_MPU,
  2698. };
  2699. /* l4 per -> timer5 */
  2700. static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
  2701. {
  2702. .pa_start = 0x48046000,
  2703. .pa_end = 0x48046000 + SZ_1K - 1,
  2704. .flags = ADDR_TYPE_RT
  2705. },
  2706. { }
  2707. };
  2708. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
  2709. .master = &am33xx_l4_ls_hwmod,
  2710. .slave = &am33xx_timer5_hwmod,
  2711. .clk = "l4ls_gclk",
  2712. .addr = am33xx_timer5_addr_space,
  2713. .user = OCP_USER_MPU,
  2714. };
  2715. /* l4 per -> timer6 */
  2716. static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
  2717. {
  2718. .pa_start = 0x48048000,
  2719. .pa_end = 0x48048000 + SZ_1K - 1,
  2720. .flags = ADDR_TYPE_RT
  2721. },
  2722. { }
  2723. };
  2724. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
  2725. .master = &am33xx_l4_ls_hwmod,
  2726. .slave = &am33xx_timer6_hwmod,
  2727. .clk = "l4ls_gclk",
  2728. .addr = am33xx_timer6_addr_space,
  2729. .user = OCP_USER_MPU,
  2730. };
  2731. /* l4 per -> timer7 */
  2732. static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
  2733. {
  2734. .pa_start = 0x4804A000,
  2735. .pa_end = 0x4804A000 + SZ_1K - 1,
  2736. .flags = ADDR_TYPE_RT
  2737. },
  2738. { }
  2739. };
  2740. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
  2741. .master = &am33xx_l4_ls_hwmod,
  2742. .slave = &am33xx_timer7_hwmod,
  2743. .clk = "l4ls_gclk",
  2744. .addr = am33xx_timer7_addr_space,
  2745. .user = OCP_USER_MPU,
  2746. };
  2747. /* l3 main -> tpcc */
  2748. static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
  2749. {
  2750. .pa_start = 0x49000000,
  2751. .pa_end = 0x49000000 + SZ_32K - 1,
  2752. .flags = ADDR_TYPE_RT
  2753. },
  2754. { }
  2755. };
  2756. static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
  2757. .master = &am33xx_l3_main_hwmod,
  2758. .slave = &am33xx_tpcc_hwmod,
  2759. .clk = "l3_gclk",
  2760. .addr = am33xx_tpcc_addr_space,
  2761. .user = OCP_USER_MPU,
  2762. };
  2763. /* l3 main -> tpcc0 */
  2764. static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
  2765. {
  2766. .pa_start = 0x49800000,
  2767. .pa_end = 0x49800000 + SZ_8K - 1,
  2768. .flags = ADDR_TYPE_RT,
  2769. },
  2770. { }
  2771. };
  2772. static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
  2773. .master = &am33xx_l3_main_hwmod,
  2774. .slave = &am33xx_tptc0_hwmod,
  2775. .clk = "l3_gclk",
  2776. .addr = am33xx_tptc0_addr_space,
  2777. .user = OCP_USER_MPU,
  2778. };
  2779. /* l3 main -> tpcc1 */
  2780. static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
  2781. {
  2782. .pa_start = 0x49900000,
  2783. .pa_end = 0x49900000 + SZ_8K - 1,
  2784. .flags = ADDR_TYPE_RT,
  2785. },
  2786. { }
  2787. };
  2788. static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
  2789. .master = &am33xx_l3_main_hwmod,
  2790. .slave = &am33xx_tptc1_hwmod,
  2791. .clk = "l3_gclk",
  2792. .addr = am33xx_tptc1_addr_space,
  2793. .user = OCP_USER_MPU,
  2794. };
  2795. /* l3 main -> tpcc2 */
  2796. static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
  2797. {
  2798. .pa_start = 0x49a00000,
  2799. .pa_end = 0x49a00000 + SZ_8K - 1,
  2800. .flags = ADDR_TYPE_RT,
  2801. },
  2802. { }
  2803. };
  2804. static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
  2805. .master = &am33xx_l3_main_hwmod,
  2806. .slave = &am33xx_tptc2_hwmod,
  2807. .clk = "l3_gclk",
  2808. .addr = am33xx_tptc2_addr_space,
  2809. .user = OCP_USER_MPU,
  2810. };
  2811. /* l4 wkup -> uart1 */
  2812. static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
  2813. {
  2814. .pa_start = 0x44E09000,
  2815. .pa_end = 0x44E09000 + SZ_8K - 1,
  2816. .flags = ADDR_TYPE_RT,
  2817. },
  2818. { }
  2819. };
  2820. static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
  2821. .master = &am33xx_l4_wkup_hwmod,
  2822. .slave = &am33xx_uart1_hwmod,
  2823. .clk = "dpll_core_m4_div2_ck",
  2824. .addr = am33xx_uart1_addr_space,
  2825. .user = OCP_USER_MPU,
  2826. };
  2827. /* l4 ls -> uart2 */
  2828. static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
  2829. {
  2830. .pa_start = 0x48022000,
  2831. .pa_end = 0x48022000 + SZ_8K - 1,
  2832. .flags = ADDR_TYPE_RT,
  2833. },
  2834. { }
  2835. };
  2836. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
  2837. .master = &am33xx_l4_ls_hwmod,
  2838. .slave = &am33xx_uart2_hwmod,
  2839. .clk = "l4ls_gclk",
  2840. .addr = am33xx_uart2_addr_space,
  2841. .user = OCP_USER_MPU,
  2842. };
  2843. /* l4 ls -> uart3 */
  2844. static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
  2845. {
  2846. .pa_start = 0x48024000,
  2847. .pa_end = 0x48024000 + SZ_8K - 1,
  2848. .flags = ADDR_TYPE_RT,
  2849. },
  2850. { }
  2851. };
  2852. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
  2853. .master = &am33xx_l4_ls_hwmod,
  2854. .slave = &am33xx_uart3_hwmod,
  2855. .clk = "l4ls_gclk",
  2856. .addr = am33xx_uart3_addr_space,
  2857. .user = OCP_USER_MPU,
  2858. };
  2859. /* l4 ls -> uart4 */
  2860. static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
  2861. {
  2862. .pa_start = 0x481A6000,
  2863. .pa_end = 0x481A6000 + SZ_8K - 1,
  2864. .flags = ADDR_TYPE_RT,
  2865. },
  2866. { }
  2867. };
  2868. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
  2869. .master = &am33xx_l4_ls_hwmod,
  2870. .slave = &am33xx_uart4_hwmod,
  2871. .clk = "l4ls_gclk",
  2872. .addr = am33xx_uart4_addr_space,
  2873. .user = OCP_USER_MPU,
  2874. };
  2875. /* l4 ls -> uart5 */
  2876. static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
  2877. {
  2878. .pa_start = 0x481A8000,
  2879. .pa_end = 0x481A8000 + SZ_8K - 1,
  2880. .flags = ADDR_TYPE_RT,
  2881. },
  2882. { }
  2883. };
  2884. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
  2885. .master = &am33xx_l4_ls_hwmod,
  2886. .slave = &am33xx_uart5_hwmod,
  2887. .clk = "l4ls_gclk",
  2888. .addr = am33xx_uart5_addr_space,
  2889. .user = OCP_USER_MPU,
  2890. };
  2891. /* l4 ls -> uart6 */
  2892. static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
  2893. {
  2894. .pa_start = 0x481aa000,
  2895. .pa_end = 0x481aa000 + SZ_8K - 1,
  2896. .flags = ADDR_TYPE_RT,
  2897. },
  2898. { }
  2899. };
  2900. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
  2901. .master = &am33xx_l4_ls_hwmod,
  2902. .slave = &am33xx_uart6_hwmod,
  2903. .clk = "l4ls_gclk",
  2904. .addr = am33xx_uart6_addr_space,
  2905. .user = OCP_USER_MPU,
  2906. };
  2907. /* l4 wkup -> wd_timer1 */
  2908. static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
  2909. {
  2910. .pa_start = 0x44e35000,
  2911. .pa_end = 0x44e35000 + SZ_4K - 1,
  2912. .flags = ADDR_TYPE_RT
  2913. },
  2914. { }
  2915. };
  2916. static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
  2917. .master = &am33xx_l4_wkup_hwmod,
  2918. .slave = &am33xx_wd_timer1_hwmod,
  2919. .clk = "dpll_core_m4_div2_ck",
  2920. .addr = am33xx_wd_timer1_addrs,
  2921. .user = OCP_USER_MPU,
  2922. };
  2923. /* usbss */
  2924. /* l3 s -> USBSS interface */
  2925. static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
  2926. {
  2927. .name = "usbss",
  2928. .pa_start = 0x47400000,
  2929. .pa_end = 0x47400000 + SZ_4K - 1,
  2930. .flags = ADDR_TYPE_RT
  2931. },
  2932. {
  2933. .name = "musb0",
  2934. .pa_start = 0x47401000,
  2935. .pa_end = 0x47401000 + SZ_2K - 1,
  2936. .flags = ADDR_TYPE_RT
  2937. },
  2938. {
  2939. .name = "musb1",
  2940. .pa_start = 0x47401800,
  2941. .pa_end = 0x47401800 + SZ_2K - 1,
  2942. .flags = ADDR_TYPE_RT
  2943. },
  2944. { }
  2945. };
  2946. static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
  2947. .master = &am33xx_l3_s_hwmod,
  2948. .slave = &am33xx_usbss_hwmod,
  2949. .clk = "l3s_gclk",
  2950. .addr = am33xx_usbss_addr_space,
  2951. .user = OCP_USER_MPU,
  2952. .flags = OCPIF_SWSUP_IDLE,
  2953. };
  2954. static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
  2955. &am33xx_l4_fw__emif_fw,
  2956. &am33xx_l3_main__emif,
  2957. &am33xx_mpu__l3_main,
  2958. &am33xx_mpu__prcm,
  2959. &am33xx_l3_s__l4_ls,
  2960. &am33xx_l3_s__l4_wkup,
  2961. &am33xx_l3_s__l4_fw,
  2962. &am33xx_l3_main__l4_hs,
  2963. &am33xx_l3_main__l3_s,
  2964. &am33xx_l3_main__l3_instr,
  2965. &am33xx_l3_main__gfx,
  2966. &am33xx_l3_s__l3_main,
  2967. &am33xx_pruss__l3_main,
  2968. &am33xx_wkup_m3__l4_wkup,
  2969. &am33xx_gfx__l3_main,
  2970. &am33xx_l4_wkup__wkup_m3,
  2971. &am33xx_l4_wkup__control,
  2972. &am33xx_l4_wkup__smartreflex0,
  2973. &am33xx_l4_wkup__smartreflex1,
  2974. &am33xx_l4_wkup__uart1,
  2975. &am33xx_l4_wkup__timer1,
  2976. &am33xx_l4_wkup__rtc,
  2977. &am33xx_l4_wkup__i2c1,
  2978. &am33xx_l4_wkup__gpio0,
  2979. &am33xx_l4_wkup__adc_tsc,
  2980. &am33xx_l4_wkup__wd_timer1,
  2981. &am33xx_l4_hs__pruss,
  2982. &am33xx_l4_per__dcan0,
  2983. &am33xx_l4_per__dcan1,
  2984. &am33xx_l4_per__gpio1,
  2985. &am33xx_l4_per__gpio2,
  2986. &am33xx_l4_per__gpio3,
  2987. &am33xx_l4_per__i2c2,
  2988. &am33xx_l4_per__i2c3,
  2989. &am33xx_l4_per__mailbox,
  2990. &am33xx_l4_ls__mcasp0,
  2991. &am33xx_l3_s__mcasp0_data,
  2992. &am33xx_l4_ls__mcasp1,
  2993. &am33xx_l3_s__mcasp1_data,
  2994. &am33xx_l4_ls__mmc0,
  2995. &am33xx_l4_ls__mmc1,
  2996. &am33xx_l3_s__mmc2,
  2997. &am33xx_l4_ls__timer2,
  2998. &am33xx_l4_ls__timer3,
  2999. &am33xx_l4_ls__timer4,
  3000. &am33xx_l4_ls__timer5,
  3001. &am33xx_l4_ls__timer6,
  3002. &am33xx_l4_ls__timer7,
  3003. &am33xx_l3_main__tpcc,
  3004. &am33xx_l4_ls__uart2,
  3005. &am33xx_l4_ls__uart3,
  3006. &am33xx_l4_ls__uart4,
  3007. &am33xx_l4_ls__uart5,
  3008. &am33xx_l4_ls__uart6,
  3009. &am33xx_l4_ls__spinlock,
  3010. &am33xx_l4_ls__elm,
  3011. &am33xx_l4_ls__ehrpwm0,
  3012. &am33xx_l4_ls__ehrpwm1,
  3013. &am33xx_l4_ls__ehrpwm2,
  3014. &am33xx_l4_ls__ecap0,
  3015. &am33xx_l4_ls__ecap1,
  3016. &am33xx_l4_ls__ecap2,
  3017. &am33xx_l3_s__gpmc,
  3018. &am33xx_l3_main__lcdc,
  3019. &am33xx_l4_ls__mcspi0,
  3020. &am33xx_l4_ls__mcspi1,
  3021. &am33xx_l3_main__tptc0,
  3022. &am33xx_l3_main__tptc1,
  3023. &am33xx_l3_main__tptc2,
  3024. &am33xx_l3_s__usbss,
  3025. &am33xx_l4_hs__cpgmac0,
  3026. NULL,
  3027. };
  3028. int __init am33xx_hwmod_init(void)
  3029. {
  3030. omap_hwmod_init();
  3031. return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
  3032. }