cnic.c 121 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static void cnic_shutdown_rings(struct cnic_dev *);
  72. static void cnic_init_rings(struct cnic_dev *);
  73. static int cnic_cm_set_pg(struct cnic_sock *);
  74. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  75. {
  76. struct cnic_dev *dev = uinfo->priv;
  77. struct cnic_local *cp = dev->cnic_priv;
  78. if (!capable(CAP_NET_ADMIN))
  79. return -EPERM;
  80. if (cp->uio_dev != -1)
  81. return -EBUSY;
  82. rtnl_lock();
  83. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  84. rtnl_unlock();
  85. return -ENODEV;
  86. }
  87. cp->uio_dev = iminor(inode);
  88. cnic_init_rings(dev);
  89. rtnl_unlock();
  90. return 0;
  91. }
  92. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  93. {
  94. struct cnic_dev *dev = uinfo->priv;
  95. struct cnic_local *cp = dev->cnic_priv;
  96. cnic_shutdown_rings(dev);
  97. cp->uio_dev = -1;
  98. return 0;
  99. }
  100. static inline void cnic_hold(struct cnic_dev *dev)
  101. {
  102. atomic_inc(&dev->ref_count);
  103. }
  104. static inline void cnic_put(struct cnic_dev *dev)
  105. {
  106. atomic_dec(&dev->ref_count);
  107. }
  108. static inline void csk_hold(struct cnic_sock *csk)
  109. {
  110. atomic_inc(&csk->ref_count);
  111. }
  112. static inline void csk_put(struct cnic_sock *csk)
  113. {
  114. atomic_dec(&csk->ref_count);
  115. }
  116. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  117. {
  118. struct cnic_dev *cdev;
  119. read_lock(&cnic_dev_lock);
  120. list_for_each_entry(cdev, &cnic_dev_list, list) {
  121. if (netdev == cdev->netdev) {
  122. cnic_hold(cdev);
  123. read_unlock(&cnic_dev_lock);
  124. return cdev;
  125. }
  126. }
  127. read_unlock(&cnic_dev_lock);
  128. return NULL;
  129. }
  130. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  131. {
  132. atomic_inc(&ulp_ops->ref_count);
  133. }
  134. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  135. {
  136. atomic_dec(&ulp_ops->ref_count);
  137. }
  138. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  139. {
  140. struct cnic_local *cp = dev->cnic_priv;
  141. struct cnic_eth_dev *ethdev = cp->ethdev;
  142. struct drv_ctl_info info;
  143. struct drv_ctl_io *io = &info.data.io;
  144. info.cmd = DRV_CTL_CTX_WR_CMD;
  145. io->cid_addr = cid_addr;
  146. io->offset = off;
  147. io->data = val;
  148. ethdev->drv_ctl(dev->netdev, &info);
  149. }
  150. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  157. io->offset = off;
  158. io->dma_addr = addr;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_l2_ring *ring = &info.data.ring;
  167. if (start)
  168. info.cmd = DRV_CTL_START_L2_CMD;
  169. else
  170. info.cmd = DRV_CTL_STOP_L2_CMD;
  171. ring->cid = cid;
  172. ring->client_id = cl_id;
  173. ethdev->drv_ctl(dev->netdev, &info);
  174. }
  175. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  176. {
  177. struct cnic_local *cp = dev->cnic_priv;
  178. struct cnic_eth_dev *ethdev = cp->ethdev;
  179. struct drv_ctl_info info;
  180. struct drv_ctl_io *io = &info.data.io;
  181. info.cmd = DRV_CTL_IO_WR_CMD;
  182. io->offset = off;
  183. io->data = val;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_RD_CMD;
  193. io->offset = off;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. return io->data;
  196. }
  197. static int cnic_in_use(struct cnic_sock *csk)
  198. {
  199. return test_bit(SK_F_INUSE, &csk->flags);
  200. }
  201. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  202. {
  203. struct cnic_local *cp = dev->cnic_priv;
  204. struct cnic_eth_dev *ethdev = cp->ethdev;
  205. struct drv_ctl_info info;
  206. info.cmd = cmd;
  207. info.data.credit.credit_count = count;
  208. ethdev->drv_ctl(dev->netdev, &info);
  209. }
  210. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  211. {
  212. u32 i;
  213. for (i = 0; i < cp->max_cid_space; i++) {
  214. if (cp->ctx_tbl[i].cid == cid) {
  215. *l5_cid = i;
  216. return 0;
  217. }
  218. }
  219. return -EINVAL;
  220. }
  221. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  222. struct cnic_sock *csk)
  223. {
  224. struct iscsi_path path_req;
  225. char *buf = NULL;
  226. u16 len = 0;
  227. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  228. struct cnic_ulp_ops *ulp_ops;
  229. if (cp->uio_dev == -1)
  230. return -ENODEV;
  231. if (csk) {
  232. len = sizeof(path_req);
  233. buf = (char *) &path_req;
  234. memset(&path_req, 0, len);
  235. msg_type = ISCSI_KEVENT_PATH_REQ;
  236. path_req.handle = (u64) csk->l5_cid;
  237. if (test_bit(SK_F_IPV6, &csk->flags)) {
  238. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  239. sizeof(struct in6_addr));
  240. path_req.ip_addr_len = 16;
  241. } else {
  242. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  243. sizeof(struct in_addr));
  244. path_req.ip_addr_len = 4;
  245. }
  246. path_req.vlan_id = csk->vlan_id;
  247. path_req.pmtu = csk->mtu;
  248. }
  249. rcu_read_lock();
  250. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  251. if (ulp_ops)
  252. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  253. rcu_read_unlock();
  254. return 0;
  255. }
  256. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  257. char *buf, u16 len)
  258. {
  259. int rc = -EINVAL;
  260. switch (msg_type) {
  261. case ISCSI_UEVENT_PATH_UPDATE: {
  262. struct cnic_local *cp;
  263. u32 l5_cid;
  264. struct cnic_sock *csk;
  265. struct iscsi_path *path_resp;
  266. if (len < sizeof(*path_resp))
  267. break;
  268. path_resp = (struct iscsi_path *) buf;
  269. cp = dev->cnic_priv;
  270. l5_cid = (u32) path_resp->handle;
  271. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  272. break;
  273. rcu_read_lock();
  274. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  275. rc = -ENODEV;
  276. rcu_read_unlock();
  277. break;
  278. }
  279. csk = &cp->csk_tbl[l5_cid];
  280. csk_hold(csk);
  281. if (cnic_in_use(csk)) {
  282. memcpy(csk->ha, path_resp->mac_addr, 6);
  283. if (test_bit(SK_F_IPV6, &csk->flags))
  284. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  285. sizeof(struct in6_addr));
  286. else
  287. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  288. sizeof(struct in_addr));
  289. if (is_valid_ether_addr(csk->ha))
  290. cnic_cm_set_pg(csk);
  291. }
  292. csk_put(csk);
  293. rcu_read_unlock();
  294. rc = 0;
  295. }
  296. }
  297. return rc;
  298. }
  299. static int cnic_offld_prep(struct cnic_sock *csk)
  300. {
  301. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  302. return 0;
  303. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  304. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  305. return 0;
  306. }
  307. return 1;
  308. }
  309. static int cnic_close_prep(struct cnic_sock *csk)
  310. {
  311. clear_bit(SK_F_CONNECT_START, &csk->flags);
  312. smp_mb__after_clear_bit();
  313. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  314. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  315. msleep(1);
  316. return 1;
  317. }
  318. return 0;
  319. }
  320. static int cnic_abort_prep(struct cnic_sock *csk)
  321. {
  322. clear_bit(SK_F_CONNECT_START, &csk->flags);
  323. smp_mb__after_clear_bit();
  324. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  325. msleep(1);
  326. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  327. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  328. return 1;
  329. }
  330. return 0;
  331. }
  332. static void cnic_uio_stop(void)
  333. {
  334. struct cnic_dev *dev;
  335. read_lock(&cnic_dev_lock);
  336. list_for_each_entry(dev, &cnic_dev_list, list) {
  337. struct cnic_local *cp = dev->cnic_priv;
  338. if (cp->cnic_uinfo)
  339. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  340. }
  341. read_unlock(&cnic_dev_lock);
  342. }
  343. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  344. {
  345. struct cnic_dev *dev;
  346. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  347. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  348. return -EINVAL;
  349. }
  350. mutex_lock(&cnic_lock);
  351. if (cnic_ulp_tbl[ulp_type]) {
  352. pr_err("%s: Type %d has already been registered\n",
  353. __func__, ulp_type);
  354. mutex_unlock(&cnic_lock);
  355. return -EBUSY;
  356. }
  357. read_lock(&cnic_dev_lock);
  358. list_for_each_entry(dev, &cnic_dev_list, list) {
  359. struct cnic_local *cp = dev->cnic_priv;
  360. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  361. }
  362. read_unlock(&cnic_dev_lock);
  363. atomic_set(&ulp_ops->ref_count, 0);
  364. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  365. mutex_unlock(&cnic_lock);
  366. /* Prevent race conditions with netdev_event */
  367. rtnl_lock();
  368. read_lock(&cnic_dev_lock);
  369. list_for_each_entry(dev, &cnic_dev_list, list) {
  370. struct cnic_local *cp = dev->cnic_priv;
  371. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  372. ulp_ops->cnic_init(dev);
  373. }
  374. read_unlock(&cnic_dev_lock);
  375. rtnl_unlock();
  376. return 0;
  377. }
  378. int cnic_unregister_driver(int ulp_type)
  379. {
  380. struct cnic_dev *dev;
  381. struct cnic_ulp_ops *ulp_ops;
  382. int i = 0;
  383. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  384. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  385. return -EINVAL;
  386. }
  387. mutex_lock(&cnic_lock);
  388. ulp_ops = cnic_ulp_tbl[ulp_type];
  389. if (!ulp_ops) {
  390. pr_err("%s: Type %d has not been registered\n",
  391. __func__, ulp_type);
  392. goto out_unlock;
  393. }
  394. read_lock(&cnic_dev_lock);
  395. list_for_each_entry(dev, &cnic_dev_list, list) {
  396. struct cnic_local *cp = dev->cnic_priv;
  397. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  398. pr_err("%s: Type %d still has devices registered\n",
  399. __func__, ulp_type);
  400. read_unlock(&cnic_dev_lock);
  401. goto out_unlock;
  402. }
  403. }
  404. read_unlock(&cnic_dev_lock);
  405. if (ulp_type == CNIC_ULP_ISCSI)
  406. cnic_uio_stop();
  407. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  408. mutex_unlock(&cnic_lock);
  409. synchronize_rcu();
  410. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  411. msleep(100);
  412. i++;
  413. }
  414. if (atomic_read(&ulp_ops->ref_count) != 0)
  415. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  416. return 0;
  417. out_unlock:
  418. mutex_unlock(&cnic_lock);
  419. return -EINVAL;
  420. }
  421. static int cnic_start_hw(struct cnic_dev *);
  422. static void cnic_stop_hw(struct cnic_dev *);
  423. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  424. void *ulp_ctx)
  425. {
  426. struct cnic_local *cp = dev->cnic_priv;
  427. struct cnic_ulp_ops *ulp_ops;
  428. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  429. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  430. return -EINVAL;
  431. }
  432. mutex_lock(&cnic_lock);
  433. if (cnic_ulp_tbl[ulp_type] == NULL) {
  434. pr_err("%s: Driver with type %d has not been registered\n",
  435. __func__, ulp_type);
  436. mutex_unlock(&cnic_lock);
  437. return -EAGAIN;
  438. }
  439. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  440. pr_err("%s: Type %d has already been registered to this device\n",
  441. __func__, ulp_type);
  442. mutex_unlock(&cnic_lock);
  443. return -EBUSY;
  444. }
  445. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  446. cp->ulp_handle[ulp_type] = ulp_ctx;
  447. ulp_ops = cnic_ulp_tbl[ulp_type];
  448. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  449. cnic_hold(dev);
  450. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  451. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  452. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  453. mutex_unlock(&cnic_lock);
  454. return 0;
  455. }
  456. EXPORT_SYMBOL(cnic_register_driver);
  457. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  458. {
  459. struct cnic_local *cp = dev->cnic_priv;
  460. int i = 0;
  461. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  462. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  463. return -EINVAL;
  464. }
  465. mutex_lock(&cnic_lock);
  466. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  467. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  468. cnic_put(dev);
  469. } else {
  470. pr_err("%s: device not registered to this ulp type %d\n",
  471. __func__, ulp_type);
  472. mutex_unlock(&cnic_lock);
  473. return -EINVAL;
  474. }
  475. mutex_unlock(&cnic_lock);
  476. synchronize_rcu();
  477. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  478. i < 20) {
  479. msleep(100);
  480. i++;
  481. }
  482. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  483. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  484. return 0;
  485. }
  486. EXPORT_SYMBOL(cnic_unregister_driver);
  487. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  488. {
  489. id_tbl->start = start_id;
  490. id_tbl->max = size;
  491. id_tbl->next = 0;
  492. spin_lock_init(&id_tbl->lock);
  493. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  494. if (!id_tbl->table)
  495. return -ENOMEM;
  496. return 0;
  497. }
  498. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  499. {
  500. kfree(id_tbl->table);
  501. id_tbl->table = NULL;
  502. }
  503. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  504. {
  505. int ret = -1;
  506. id -= id_tbl->start;
  507. if (id >= id_tbl->max)
  508. return ret;
  509. spin_lock(&id_tbl->lock);
  510. if (!test_bit(id, id_tbl->table)) {
  511. set_bit(id, id_tbl->table);
  512. ret = 0;
  513. }
  514. spin_unlock(&id_tbl->lock);
  515. return ret;
  516. }
  517. /* Returns -1 if not successful */
  518. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  519. {
  520. u32 id;
  521. spin_lock(&id_tbl->lock);
  522. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  523. if (id >= id_tbl->max) {
  524. id = -1;
  525. if (id_tbl->next != 0) {
  526. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  527. if (id >= id_tbl->next)
  528. id = -1;
  529. }
  530. }
  531. if (id < id_tbl->max) {
  532. set_bit(id, id_tbl->table);
  533. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  534. id += id_tbl->start;
  535. }
  536. spin_unlock(&id_tbl->lock);
  537. return id;
  538. }
  539. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  540. {
  541. if (id == -1)
  542. return;
  543. id -= id_tbl->start;
  544. if (id >= id_tbl->max)
  545. return;
  546. clear_bit(id, id_tbl->table);
  547. }
  548. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  549. {
  550. int i;
  551. if (!dma->pg_arr)
  552. return;
  553. for (i = 0; i < dma->num_pages; i++) {
  554. if (dma->pg_arr[i]) {
  555. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  556. dma->pg_arr[i], dma->pg_map_arr[i]);
  557. dma->pg_arr[i] = NULL;
  558. }
  559. }
  560. if (dma->pgtbl) {
  561. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  562. dma->pgtbl, dma->pgtbl_map);
  563. dma->pgtbl = NULL;
  564. }
  565. kfree(dma->pg_arr);
  566. dma->pg_arr = NULL;
  567. dma->num_pages = 0;
  568. }
  569. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  570. {
  571. int i;
  572. u32 *page_table = dma->pgtbl;
  573. for (i = 0; i < dma->num_pages; i++) {
  574. /* Each entry needs to be in big endian format. */
  575. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  576. page_table++;
  577. *page_table = (u32) dma->pg_map_arr[i];
  578. page_table++;
  579. }
  580. }
  581. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  582. {
  583. int i;
  584. u32 *page_table = dma->pgtbl;
  585. for (i = 0; i < dma->num_pages; i++) {
  586. /* Each entry needs to be in little endian format. */
  587. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  588. page_table++;
  589. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  590. page_table++;
  591. }
  592. }
  593. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  594. int pages, int use_pg_tbl)
  595. {
  596. int i, size;
  597. struct cnic_local *cp = dev->cnic_priv;
  598. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  599. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  600. if (dma->pg_arr == NULL)
  601. return -ENOMEM;
  602. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  603. dma->num_pages = pages;
  604. for (i = 0; i < pages; i++) {
  605. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  606. BCM_PAGE_SIZE,
  607. &dma->pg_map_arr[i],
  608. GFP_ATOMIC);
  609. if (dma->pg_arr[i] == NULL)
  610. goto error;
  611. }
  612. if (!use_pg_tbl)
  613. return 0;
  614. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  615. ~(BCM_PAGE_SIZE - 1);
  616. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  617. &dma->pgtbl_map, GFP_ATOMIC);
  618. if (dma->pgtbl == NULL)
  619. goto error;
  620. cp->setup_pgtbl(dev, dma);
  621. return 0;
  622. error:
  623. cnic_free_dma(dev, dma);
  624. return -ENOMEM;
  625. }
  626. static void cnic_free_context(struct cnic_dev *dev)
  627. {
  628. struct cnic_local *cp = dev->cnic_priv;
  629. int i;
  630. for (i = 0; i < cp->ctx_blks; i++) {
  631. if (cp->ctx_arr[i].ctx) {
  632. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  633. cp->ctx_arr[i].ctx,
  634. cp->ctx_arr[i].mapping);
  635. cp->ctx_arr[i].ctx = NULL;
  636. }
  637. }
  638. }
  639. static void cnic_free_resc(struct cnic_dev *dev)
  640. {
  641. struct cnic_local *cp = dev->cnic_priv;
  642. int i = 0;
  643. if (cp->cnic_uinfo) {
  644. while (cp->uio_dev != -1 && i < 15) {
  645. msleep(100);
  646. i++;
  647. }
  648. uio_unregister_device(cp->cnic_uinfo);
  649. kfree(cp->cnic_uinfo);
  650. cp->cnic_uinfo = NULL;
  651. }
  652. if (cp->l2_buf) {
  653. dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  654. cp->l2_buf, cp->l2_buf_map);
  655. cp->l2_buf = NULL;
  656. }
  657. if (cp->l2_ring) {
  658. dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  659. cp->l2_ring, cp->l2_ring_map);
  660. cp->l2_ring = NULL;
  661. }
  662. cnic_free_context(dev);
  663. kfree(cp->ctx_arr);
  664. cp->ctx_arr = NULL;
  665. cp->ctx_blks = 0;
  666. cnic_free_dma(dev, &cp->gbl_buf_info);
  667. cnic_free_dma(dev, &cp->conn_buf_info);
  668. cnic_free_dma(dev, &cp->kwq_info);
  669. cnic_free_dma(dev, &cp->kwq_16_data_info);
  670. cnic_free_dma(dev, &cp->kcq1.dma);
  671. kfree(cp->iscsi_tbl);
  672. cp->iscsi_tbl = NULL;
  673. kfree(cp->ctx_tbl);
  674. cp->ctx_tbl = NULL;
  675. cnic_free_id_tbl(&cp->cid_tbl);
  676. }
  677. static int cnic_alloc_context(struct cnic_dev *dev)
  678. {
  679. struct cnic_local *cp = dev->cnic_priv;
  680. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  681. int i, k, arr_size;
  682. cp->ctx_blk_size = BCM_PAGE_SIZE;
  683. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  684. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  685. sizeof(struct cnic_ctx);
  686. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  687. if (cp->ctx_arr == NULL)
  688. return -ENOMEM;
  689. k = 0;
  690. for (i = 0; i < 2; i++) {
  691. u32 j, reg, off, lo, hi;
  692. if (i == 0)
  693. off = BNX2_PG_CTX_MAP;
  694. else
  695. off = BNX2_ISCSI_CTX_MAP;
  696. reg = cnic_reg_rd_ind(dev, off);
  697. lo = reg >> 16;
  698. hi = reg & 0xffff;
  699. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  700. cp->ctx_arr[k].cid = j;
  701. }
  702. cp->ctx_blks = k;
  703. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  704. cp->ctx_blks = 0;
  705. return -ENOMEM;
  706. }
  707. for (i = 0; i < cp->ctx_blks; i++) {
  708. cp->ctx_arr[i].ctx =
  709. dma_alloc_coherent(&dev->pcidev->dev,
  710. BCM_PAGE_SIZE,
  711. &cp->ctx_arr[i].mapping,
  712. GFP_KERNEL);
  713. if (cp->ctx_arr[i].ctx == NULL)
  714. return -ENOMEM;
  715. }
  716. }
  717. return 0;
  718. }
  719. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  720. {
  721. int err, i, is_bnx2 = 0;
  722. struct kcqe **kcq;
  723. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  724. is_bnx2 = 1;
  725. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  726. if (err)
  727. return err;
  728. kcq = (struct kcqe **) info->dma.pg_arr;
  729. info->kcq = kcq;
  730. if (is_bnx2)
  731. return 0;
  732. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  733. struct bnx2x_bd_chain_next *next =
  734. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  735. int j = i + 1;
  736. if (j >= KCQ_PAGE_CNT)
  737. j = 0;
  738. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  739. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  740. }
  741. return 0;
  742. }
  743. static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
  744. {
  745. struct cnic_local *cp = dev->cnic_priv;
  746. cp->l2_ring_size = pages * BCM_PAGE_SIZE;
  747. cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  748. &cp->l2_ring_map,
  749. GFP_KERNEL | __GFP_COMP);
  750. if (!cp->l2_ring)
  751. return -ENOMEM;
  752. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  753. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  754. cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  755. &cp->l2_buf_map,
  756. GFP_KERNEL | __GFP_COMP);
  757. if (!cp->l2_buf)
  758. return -ENOMEM;
  759. return 0;
  760. }
  761. static int cnic_alloc_uio(struct cnic_dev *dev) {
  762. struct cnic_local *cp = dev->cnic_priv;
  763. struct uio_info *uinfo;
  764. int ret;
  765. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  766. if (!uinfo)
  767. return -ENOMEM;
  768. uinfo->mem[0].addr = dev->netdev->base_addr;
  769. uinfo->mem[0].internal_addr = dev->regview;
  770. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  771. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  772. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  773. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  774. PAGE_MASK;
  775. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  776. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  777. else
  778. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  779. uinfo->name = "bnx2_cnic";
  780. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  781. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  782. PAGE_MASK;
  783. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  784. uinfo->name = "bnx2x_cnic";
  785. }
  786. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  787. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  788. uinfo->mem[2].size = cp->l2_ring_size;
  789. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  790. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  791. uinfo->mem[3].size = cp->l2_buf_size;
  792. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  793. uinfo->version = CNIC_MODULE_VERSION;
  794. uinfo->irq = UIO_IRQ_CUSTOM;
  795. uinfo->open = cnic_uio_open;
  796. uinfo->release = cnic_uio_close;
  797. uinfo->priv = dev;
  798. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  799. if (ret) {
  800. kfree(uinfo);
  801. return ret;
  802. }
  803. cp->cnic_uinfo = uinfo;
  804. return 0;
  805. }
  806. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  807. {
  808. struct cnic_local *cp = dev->cnic_priv;
  809. int ret;
  810. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  811. if (ret)
  812. goto error;
  813. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  814. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  815. if (ret)
  816. goto error;
  817. ret = cnic_alloc_context(dev);
  818. if (ret)
  819. goto error;
  820. ret = cnic_alloc_l2_rings(dev, 2);
  821. if (ret)
  822. goto error;
  823. ret = cnic_alloc_uio(dev);
  824. if (ret)
  825. goto error;
  826. return 0;
  827. error:
  828. cnic_free_resc(dev);
  829. return ret;
  830. }
  831. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  832. {
  833. struct cnic_local *cp = dev->cnic_priv;
  834. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  835. int total_mem, blks, i;
  836. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  837. blks = total_mem / ctx_blk_size;
  838. if (total_mem % ctx_blk_size)
  839. blks++;
  840. if (blks > cp->ethdev->ctx_tbl_len)
  841. return -ENOMEM;
  842. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  843. if (cp->ctx_arr == NULL)
  844. return -ENOMEM;
  845. cp->ctx_blks = blks;
  846. cp->ctx_blk_size = ctx_blk_size;
  847. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  848. cp->ctx_align = 0;
  849. else
  850. cp->ctx_align = ctx_blk_size;
  851. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  852. for (i = 0; i < blks; i++) {
  853. cp->ctx_arr[i].ctx =
  854. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  855. &cp->ctx_arr[i].mapping,
  856. GFP_KERNEL);
  857. if (cp->ctx_arr[i].ctx == NULL)
  858. return -ENOMEM;
  859. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  860. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  861. cnic_free_context(dev);
  862. cp->ctx_blk_size += cp->ctx_align;
  863. i = -1;
  864. continue;
  865. }
  866. }
  867. }
  868. return 0;
  869. }
  870. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  871. {
  872. struct cnic_local *cp = dev->cnic_priv;
  873. struct cnic_eth_dev *ethdev = cp->ethdev;
  874. u32 start_cid = ethdev->starting_cid;
  875. int i, j, n, ret, pages;
  876. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  877. cp->iro_arr = ethdev->iro_arr;
  878. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  879. cp->iscsi_start_cid = start_cid;
  880. if (start_cid < BNX2X_ISCSI_START_CID) {
  881. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  882. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  883. cp->max_cid_space += delta;
  884. }
  885. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  886. GFP_KERNEL);
  887. if (!cp->iscsi_tbl)
  888. goto error;
  889. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  890. cp->max_cid_space, GFP_KERNEL);
  891. if (!cp->ctx_tbl)
  892. goto error;
  893. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  894. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  895. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  896. }
  897. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  898. PAGE_SIZE;
  899. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  900. if (ret)
  901. return -ENOMEM;
  902. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  903. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  904. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  905. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  906. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  907. off;
  908. if ((i % n) == (n - 1))
  909. j++;
  910. }
  911. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  912. if (ret)
  913. goto error;
  914. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  915. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  916. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  917. if (ret)
  918. goto error;
  919. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  920. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  921. if (ret)
  922. goto error;
  923. ret = cnic_alloc_bnx2x_context(dev);
  924. if (ret)
  925. goto error;
  926. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  927. cp->l2_rx_ring_size = 15;
  928. ret = cnic_alloc_l2_rings(dev, 4);
  929. if (ret)
  930. goto error;
  931. ret = cnic_alloc_uio(dev);
  932. if (ret)
  933. goto error;
  934. return 0;
  935. error:
  936. cnic_free_resc(dev);
  937. return -ENOMEM;
  938. }
  939. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  940. {
  941. return cp->max_kwq_idx -
  942. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  943. }
  944. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  945. u32 num_wqes)
  946. {
  947. struct cnic_local *cp = dev->cnic_priv;
  948. struct kwqe *prod_qe;
  949. u16 prod, sw_prod, i;
  950. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  951. return -EAGAIN; /* bnx2 is down */
  952. spin_lock_bh(&cp->cnic_ulp_lock);
  953. if (num_wqes > cnic_kwq_avail(cp) &&
  954. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  955. spin_unlock_bh(&cp->cnic_ulp_lock);
  956. return -EAGAIN;
  957. }
  958. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  959. prod = cp->kwq_prod_idx;
  960. sw_prod = prod & MAX_KWQ_IDX;
  961. for (i = 0; i < num_wqes; i++) {
  962. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  963. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  964. prod++;
  965. sw_prod = prod & MAX_KWQ_IDX;
  966. }
  967. cp->kwq_prod_idx = prod;
  968. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  969. spin_unlock_bh(&cp->cnic_ulp_lock);
  970. return 0;
  971. }
  972. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  973. union l5cm_specific_data *l5_data)
  974. {
  975. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  976. dma_addr_t map;
  977. map = ctx->kwqe_data_mapping;
  978. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  979. l5_data->phy_address.hi = (u64) map >> 32;
  980. return ctx->kwqe_data;
  981. }
  982. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  983. u32 type, union l5cm_specific_data *l5_data)
  984. {
  985. struct cnic_local *cp = dev->cnic_priv;
  986. struct l5cm_spe kwqe;
  987. struct kwqe_16 *kwq[1];
  988. int ret;
  989. kwqe.hdr.conn_and_cmd_data =
  990. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  991. BNX2X_HW_CID(cp, cid)));
  992. kwqe.hdr.type = cpu_to_le16(type);
  993. kwqe.hdr.reserved1 = 0;
  994. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  995. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  996. kwq[0] = (struct kwqe_16 *) &kwqe;
  997. spin_lock_bh(&cp->cnic_ulp_lock);
  998. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  999. spin_unlock_bh(&cp->cnic_ulp_lock);
  1000. if (ret == 1)
  1001. return 0;
  1002. return -EBUSY;
  1003. }
  1004. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1005. struct kcqe *cqes[], u32 num_cqes)
  1006. {
  1007. struct cnic_local *cp = dev->cnic_priv;
  1008. struct cnic_ulp_ops *ulp_ops;
  1009. rcu_read_lock();
  1010. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1011. if (likely(ulp_ops)) {
  1012. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1013. cqes, num_cqes);
  1014. }
  1015. rcu_read_unlock();
  1016. }
  1017. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1018. {
  1019. struct cnic_local *cp = dev->cnic_priv;
  1020. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1021. int hq_bds, pages;
  1022. u32 pfid = cp->pfid;
  1023. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1024. cp->num_ccells = req1->num_ccells_per_conn;
  1025. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1026. cp->num_iscsi_tasks;
  1027. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1028. BNX2X_ISCSI_R2TQE_SIZE;
  1029. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1030. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1031. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1032. cp->num_cqs = req1->num_cqs;
  1033. if (!dev->max_iscsi_conn)
  1034. return 0;
  1035. /* init Tstorm RAM */
  1036. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1037. req1->rq_num_wqes);
  1038. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1039. PAGE_SIZE);
  1040. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1041. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1042. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1043. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1044. req1->num_tasks_per_conn);
  1045. /* init Ustorm RAM */
  1046. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1047. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1048. req1->rq_buffer_size);
  1049. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1050. PAGE_SIZE);
  1051. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1052. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1053. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1054. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1055. req1->num_tasks_per_conn);
  1056. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1057. req1->rq_num_wqes);
  1058. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1059. req1->cq_num_wqes);
  1060. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1061. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1062. /* init Xstorm RAM */
  1063. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1064. PAGE_SIZE);
  1065. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1066. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1067. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1068. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1069. req1->num_tasks_per_conn);
  1070. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1071. hq_bds);
  1072. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1073. req1->num_tasks_per_conn);
  1074. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1075. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1076. /* init Cstorm RAM */
  1077. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1078. PAGE_SIZE);
  1079. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1080. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1081. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1082. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1083. req1->num_tasks_per_conn);
  1084. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1085. req1->cq_num_wqes);
  1086. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1087. hq_bds);
  1088. return 0;
  1089. }
  1090. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1091. {
  1092. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1093. struct cnic_local *cp = dev->cnic_priv;
  1094. u32 pfid = cp->pfid;
  1095. struct iscsi_kcqe kcqe;
  1096. struct kcqe *cqes[1];
  1097. memset(&kcqe, 0, sizeof(kcqe));
  1098. if (!dev->max_iscsi_conn) {
  1099. kcqe.completion_status =
  1100. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1101. goto done;
  1102. }
  1103. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1104. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1105. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1106. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1107. req2->error_bit_map[1]);
  1108. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1109. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1110. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1111. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1112. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1113. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1114. req2->error_bit_map[1]);
  1115. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1116. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1117. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1118. done:
  1119. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1120. cqes[0] = (struct kcqe *) &kcqe;
  1121. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1122. return 0;
  1123. }
  1124. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1125. {
  1126. struct cnic_local *cp = dev->cnic_priv;
  1127. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1128. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1129. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1130. cnic_free_dma(dev, &iscsi->hq_info);
  1131. cnic_free_dma(dev, &iscsi->r2tq_info);
  1132. cnic_free_dma(dev, &iscsi->task_array_info);
  1133. }
  1134. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1135. ctx->cid = 0;
  1136. }
  1137. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1138. {
  1139. u32 cid;
  1140. int ret, pages;
  1141. struct cnic_local *cp = dev->cnic_priv;
  1142. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1143. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1144. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1145. if (cid == -1) {
  1146. ret = -ENOMEM;
  1147. goto error;
  1148. }
  1149. ctx->cid = cid;
  1150. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1151. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1152. if (ret)
  1153. goto error;
  1154. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1155. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1156. if (ret)
  1157. goto error;
  1158. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1159. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1160. if (ret)
  1161. goto error;
  1162. return 0;
  1163. error:
  1164. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1165. return ret;
  1166. }
  1167. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1168. struct regpair *ctx_addr)
  1169. {
  1170. struct cnic_local *cp = dev->cnic_priv;
  1171. struct cnic_eth_dev *ethdev = cp->ethdev;
  1172. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1173. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1174. unsigned long align_off = 0;
  1175. dma_addr_t ctx_map;
  1176. void *ctx;
  1177. if (cp->ctx_align) {
  1178. unsigned long mask = cp->ctx_align - 1;
  1179. if (cp->ctx_arr[blk].mapping & mask)
  1180. align_off = cp->ctx_align -
  1181. (cp->ctx_arr[blk].mapping & mask);
  1182. }
  1183. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1184. (off * BNX2X_CONTEXT_MEM_SIZE);
  1185. ctx = cp->ctx_arr[blk].ctx + align_off +
  1186. (off * BNX2X_CONTEXT_MEM_SIZE);
  1187. if (init)
  1188. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1189. ctx_addr->lo = ctx_map & 0xffffffff;
  1190. ctx_addr->hi = (u64) ctx_map >> 32;
  1191. return ctx;
  1192. }
  1193. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1194. u32 num)
  1195. {
  1196. struct cnic_local *cp = dev->cnic_priv;
  1197. struct iscsi_kwqe_conn_offload1 *req1 =
  1198. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1199. struct iscsi_kwqe_conn_offload2 *req2 =
  1200. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1201. struct iscsi_kwqe_conn_offload3 *req3;
  1202. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1203. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1204. u32 cid = ctx->cid;
  1205. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1206. struct iscsi_context *ictx;
  1207. struct regpair context_addr;
  1208. int i, j, n = 2, n_max;
  1209. ctx->ctx_flags = 0;
  1210. if (!req2->num_additional_wqes)
  1211. return -EINVAL;
  1212. n_max = req2->num_additional_wqes + 2;
  1213. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1214. if (ictx == NULL)
  1215. return -ENOMEM;
  1216. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1217. ictx->xstorm_ag_context.hq_prod = 1;
  1218. ictx->xstorm_st_context.iscsi.first_burst_length =
  1219. ISCSI_DEF_FIRST_BURST_LEN;
  1220. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1221. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1222. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1223. req1->sq_page_table_addr_lo;
  1224. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1225. req1->sq_page_table_addr_hi;
  1226. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1227. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1228. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1229. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1230. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1231. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1232. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1233. iscsi->hq_info.pgtbl[0];
  1234. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1235. iscsi->hq_info.pgtbl[1];
  1236. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1237. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1238. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1239. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1240. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1241. iscsi->r2tq_info.pgtbl[0];
  1242. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1243. iscsi->r2tq_info.pgtbl[1];
  1244. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1245. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1246. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1247. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1248. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1249. BNX2X_ISCSI_PBL_NOT_CACHED;
  1250. ictx->xstorm_st_context.iscsi.flags.flags |=
  1251. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1252. ictx->xstorm_st_context.iscsi.flags.flags |=
  1253. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1254. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1255. /* TSTORM requires the base address of RQ DB & not PTE */
  1256. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1257. req2->rq_page_table_addr_lo & PAGE_MASK;
  1258. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1259. req2->rq_page_table_addr_hi;
  1260. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1261. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1262. ictx->tstorm_st_context.tcp.flags2 |=
  1263. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1264. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1265. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1266. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1267. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1268. req2->rq_page_table_addr_lo;
  1269. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1270. req2->rq_page_table_addr_hi;
  1271. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1272. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1273. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1274. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1275. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1276. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1277. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1278. iscsi->r2tq_info.pgtbl[0];
  1279. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1280. iscsi->r2tq_info.pgtbl[1];
  1281. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1282. req1->cq_page_table_addr_lo;
  1283. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1284. req1->cq_page_table_addr_hi;
  1285. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1286. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1287. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1288. ictx->ustorm_st_context.task_pbe_cache_index =
  1289. BNX2X_ISCSI_PBL_NOT_CACHED;
  1290. ictx->ustorm_st_context.task_pdu_cache_index =
  1291. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1292. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1293. if (j == 3) {
  1294. if (n >= n_max)
  1295. break;
  1296. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1297. j = 0;
  1298. }
  1299. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1300. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1301. req3->qp_first_pte[j].hi;
  1302. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1303. req3->qp_first_pte[j].lo;
  1304. }
  1305. ictx->ustorm_st_context.task_pbl_base.lo =
  1306. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1307. ictx->ustorm_st_context.task_pbl_base.hi =
  1308. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1309. ictx->ustorm_st_context.tce_phy_addr.lo =
  1310. iscsi->task_array_info.pgtbl[0];
  1311. ictx->ustorm_st_context.tce_phy_addr.hi =
  1312. iscsi->task_array_info.pgtbl[1];
  1313. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1314. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1315. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1316. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1317. ISCSI_DEF_MAX_BURST_LEN;
  1318. ictx->ustorm_st_context.negotiated_rx |=
  1319. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1320. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1321. ictx->cstorm_st_context.hq_pbl_base.lo =
  1322. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1323. ictx->cstorm_st_context.hq_pbl_base.hi =
  1324. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1325. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1326. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1327. ictx->cstorm_st_context.task_pbl_base.lo =
  1328. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1329. ictx->cstorm_st_context.task_pbl_base.hi =
  1330. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1331. /* CSTORM and USTORM initialization is different, CSTORM requires
  1332. * CQ DB base & not PTE addr */
  1333. ictx->cstorm_st_context.cq_db_base.lo =
  1334. req1->cq_page_table_addr_lo & PAGE_MASK;
  1335. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1336. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1337. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1338. for (i = 0; i < cp->num_cqs; i++) {
  1339. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1340. ISCSI_INITIAL_SN;
  1341. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1342. ISCSI_INITIAL_SN;
  1343. }
  1344. ictx->xstorm_ag_context.cdu_reserved =
  1345. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1346. ISCSI_CONNECTION_TYPE);
  1347. ictx->ustorm_ag_context.cdu_usage =
  1348. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1349. ISCSI_CONNECTION_TYPE);
  1350. return 0;
  1351. }
  1352. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1353. u32 num, int *work)
  1354. {
  1355. struct iscsi_kwqe_conn_offload1 *req1;
  1356. struct iscsi_kwqe_conn_offload2 *req2;
  1357. struct cnic_local *cp = dev->cnic_priv;
  1358. struct iscsi_kcqe kcqe;
  1359. struct kcqe *cqes[1];
  1360. u32 l5_cid;
  1361. int ret;
  1362. if (num < 2) {
  1363. *work = num;
  1364. return -EINVAL;
  1365. }
  1366. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1367. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1368. if ((num - 2) < req2->num_additional_wqes) {
  1369. *work = num;
  1370. return -EINVAL;
  1371. }
  1372. *work = 2 + req2->num_additional_wqes;;
  1373. l5_cid = req1->iscsi_conn_id;
  1374. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1375. return -EINVAL;
  1376. memset(&kcqe, 0, sizeof(kcqe));
  1377. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1378. kcqe.iscsi_conn_id = l5_cid;
  1379. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1380. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1381. atomic_dec(&cp->iscsi_conn);
  1382. ret = 0;
  1383. goto done;
  1384. }
  1385. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1386. if (ret) {
  1387. atomic_dec(&cp->iscsi_conn);
  1388. ret = 0;
  1389. goto done;
  1390. }
  1391. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1392. if (ret < 0) {
  1393. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1394. atomic_dec(&cp->iscsi_conn);
  1395. goto done;
  1396. }
  1397. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1398. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1399. done:
  1400. cqes[0] = (struct kcqe *) &kcqe;
  1401. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1402. return ret;
  1403. }
  1404. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1405. {
  1406. struct cnic_local *cp = dev->cnic_priv;
  1407. struct iscsi_kwqe_conn_update *req =
  1408. (struct iscsi_kwqe_conn_update *) kwqe;
  1409. void *data;
  1410. union l5cm_specific_data l5_data;
  1411. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1412. int ret;
  1413. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1414. return -EINVAL;
  1415. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1416. if (!data)
  1417. return -ENOMEM;
  1418. memcpy(data, kwqe, sizeof(struct kwqe));
  1419. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1420. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1421. return ret;
  1422. }
  1423. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1424. {
  1425. struct cnic_local *cp = dev->cnic_priv;
  1426. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1427. union l5cm_specific_data l5_data;
  1428. int ret;
  1429. u32 hw_cid, type;
  1430. init_waitqueue_head(&ctx->waitq);
  1431. ctx->wait_cond = 0;
  1432. memset(&l5_data, 0, sizeof(l5_data));
  1433. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1434. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  1435. & SPE_HDR_CONN_TYPE;
  1436. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1437. SPE_HDR_FUNCTION_ID);
  1438. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1439. hw_cid, type, &l5_data);
  1440. if (ret == 0)
  1441. wait_event(ctx->waitq, ctx->wait_cond);
  1442. return ret;
  1443. }
  1444. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1445. {
  1446. struct cnic_local *cp = dev->cnic_priv;
  1447. struct iscsi_kwqe_conn_destroy *req =
  1448. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1449. u32 l5_cid = req->reserved0;
  1450. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1451. int ret = 0;
  1452. struct iscsi_kcqe kcqe;
  1453. struct kcqe *cqes[1];
  1454. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1455. goto skip_cfc_delete;
  1456. while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
  1457. msleep(250);
  1458. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1459. skip_cfc_delete:
  1460. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1461. atomic_dec(&cp->iscsi_conn);
  1462. memset(&kcqe, 0, sizeof(kcqe));
  1463. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1464. kcqe.iscsi_conn_id = l5_cid;
  1465. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1466. kcqe.iscsi_conn_context_id = req->context_id;
  1467. cqes[0] = (struct kcqe *) &kcqe;
  1468. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1469. return ret;
  1470. }
  1471. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1472. struct l4_kwq_connect_req1 *kwqe1,
  1473. struct l4_kwq_connect_req3 *kwqe3,
  1474. struct l5cm_active_conn_buffer *conn_buf)
  1475. {
  1476. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1477. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1478. &conn_buf->xstorm_conn_buffer;
  1479. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1480. &conn_buf->tstorm_conn_buffer;
  1481. struct regpair context_addr;
  1482. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1483. struct in6_addr src_ip, dst_ip;
  1484. int i;
  1485. u32 *addrp;
  1486. addrp = (u32 *) &conn_addr->local_ip_addr;
  1487. for (i = 0; i < 4; i++, addrp++)
  1488. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1489. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1490. for (i = 0; i < 4; i++, addrp++)
  1491. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1492. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1493. xstorm_buf->context_addr.hi = context_addr.hi;
  1494. xstorm_buf->context_addr.lo = context_addr.lo;
  1495. xstorm_buf->mss = 0xffff;
  1496. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1497. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1498. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1499. xstorm_buf->pseudo_header_checksum =
  1500. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1501. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1502. tstorm_buf->params |=
  1503. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1504. if (kwqe3->ka_timeout) {
  1505. tstorm_buf->ka_enable = 1;
  1506. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1507. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1508. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1509. }
  1510. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1511. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1512. tstorm_buf->max_rt_time = 0xffffffff;
  1513. }
  1514. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1515. {
  1516. struct cnic_local *cp = dev->cnic_priv;
  1517. u32 pfid = cp->pfid;
  1518. u8 *mac = dev->mac_addr;
  1519. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1520. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1521. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1522. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1523. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1524. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1525. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1526. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1527. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1528. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1529. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1530. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1531. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1532. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1533. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1534. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1535. mac[4]);
  1536. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1537. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1538. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1539. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1540. mac[2]);
  1541. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1542. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1543. mac[1]);
  1544. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1545. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1546. mac[0]);
  1547. }
  1548. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1549. {
  1550. struct cnic_local *cp = dev->cnic_priv;
  1551. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1552. u16 tstorm_flags = 0;
  1553. if (tcp_ts) {
  1554. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1555. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1556. }
  1557. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1558. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1559. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1560. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1561. }
  1562. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1563. u32 num, int *work)
  1564. {
  1565. struct cnic_local *cp = dev->cnic_priv;
  1566. struct l4_kwq_connect_req1 *kwqe1 =
  1567. (struct l4_kwq_connect_req1 *) wqes[0];
  1568. struct l4_kwq_connect_req3 *kwqe3;
  1569. struct l5cm_active_conn_buffer *conn_buf;
  1570. struct l5cm_conn_addr_params *conn_addr;
  1571. union l5cm_specific_data l5_data;
  1572. u32 l5_cid = kwqe1->pg_cid;
  1573. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1574. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1575. int ret;
  1576. if (num < 2) {
  1577. *work = num;
  1578. return -EINVAL;
  1579. }
  1580. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1581. *work = 3;
  1582. else
  1583. *work = 2;
  1584. if (num < *work) {
  1585. *work = num;
  1586. return -EINVAL;
  1587. }
  1588. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1589. netdev_err(dev->netdev, "conn_buf size too big\n");
  1590. return -ENOMEM;
  1591. }
  1592. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1593. if (!conn_buf)
  1594. return -ENOMEM;
  1595. memset(conn_buf, 0, sizeof(*conn_buf));
  1596. conn_addr = &conn_buf->conn_addr_buf;
  1597. conn_addr->remote_addr_0 = csk->ha[0];
  1598. conn_addr->remote_addr_1 = csk->ha[1];
  1599. conn_addr->remote_addr_2 = csk->ha[2];
  1600. conn_addr->remote_addr_3 = csk->ha[3];
  1601. conn_addr->remote_addr_4 = csk->ha[4];
  1602. conn_addr->remote_addr_5 = csk->ha[5];
  1603. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1604. struct l4_kwq_connect_req2 *kwqe2 =
  1605. (struct l4_kwq_connect_req2 *) wqes[1];
  1606. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1607. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1608. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1609. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1610. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1611. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1612. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1613. }
  1614. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1615. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1616. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1617. conn_addr->local_tcp_port = kwqe1->src_port;
  1618. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1619. conn_addr->pmtu = kwqe3->pmtu;
  1620. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1621. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1622. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1623. cnic_bnx2x_set_tcp_timestamp(dev,
  1624. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1625. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1626. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1627. if (!ret)
  1628. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1629. return ret;
  1630. }
  1631. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1632. {
  1633. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1634. union l5cm_specific_data l5_data;
  1635. int ret;
  1636. memset(&l5_data, 0, sizeof(l5_data));
  1637. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1638. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1639. return ret;
  1640. }
  1641. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1642. {
  1643. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1644. union l5cm_specific_data l5_data;
  1645. int ret;
  1646. memset(&l5_data, 0, sizeof(l5_data));
  1647. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1648. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1649. return ret;
  1650. }
  1651. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1652. {
  1653. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1654. struct l4_kcq kcqe;
  1655. struct kcqe *cqes[1];
  1656. memset(&kcqe, 0, sizeof(kcqe));
  1657. kcqe.pg_host_opaque = req->host_opaque;
  1658. kcqe.pg_cid = req->host_opaque;
  1659. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1660. cqes[0] = (struct kcqe *) &kcqe;
  1661. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1662. return 0;
  1663. }
  1664. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1665. {
  1666. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1667. struct l4_kcq kcqe;
  1668. struct kcqe *cqes[1];
  1669. memset(&kcqe, 0, sizeof(kcqe));
  1670. kcqe.pg_host_opaque = req->pg_host_opaque;
  1671. kcqe.pg_cid = req->pg_cid;
  1672. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1673. cqes[0] = (struct kcqe *) &kcqe;
  1674. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1675. return 0;
  1676. }
  1677. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1678. u32 num_wqes)
  1679. {
  1680. int i, work, ret;
  1681. u32 opcode;
  1682. struct kwqe *kwqe;
  1683. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1684. return -EAGAIN; /* bnx2 is down */
  1685. for (i = 0; i < num_wqes; ) {
  1686. kwqe = wqes[i];
  1687. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1688. work = 1;
  1689. switch (opcode) {
  1690. case ISCSI_KWQE_OPCODE_INIT1:
  1691. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1692. break;
  1693. case ISCSI_KWQE_OPCODE_INIT2:
  1694. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1695. break;
  1696. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1697. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1698. num_wqes - i, &work);
  1699. break;
  1700. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1701. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1702. break;
  1703. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1704. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1705. break;
  1706. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1707. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1708. &work);
  1709. break;
  1710. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1711. ret = cnic_bnx2x_close(dev, kwqe);
  1712. break;
  1713. case L4_KWQE_OPCODE_VALUE_RESET:
  1714. ret = cnic_bnx2x_reset(dev, kwqe);
  1715. break;
  1716. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1717. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1718. break;
  1719. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1720. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1721. break;
  1722. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1723. ret = 0;
  1724. break;
  1725. default:
  1726. ret = 0;
  1727. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1728. opcode);
  1729. break;
  1730. }
  1731. if (ret < 0)
  1732. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1733. opcode);
  1734. i += work;
  1735. }
  1736. return 0;
  1737. }
  1738. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1739. {
  1740. struct cnic_local *cp = dev->cnic_priv;
  1741. int i, j, comp = 0;
  1742. i = 0;
  1743. j = 1;
  1744. while (num_cqes) {
  1745. struct cnic_ulp_ops *ulp_ops;
  1746. int ulp_type;
  1747. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1748. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1749. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1750. comp++;
  1751. while (j < num_cqes) {
  1752. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1753. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1754. break;
  1755. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1756. comp++;
  1757. j++;
  1758. }
  1759. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1760. ulp_type = CNIC_ULP_RDMA;
  1761. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1762. ulp_type = CNIC_ULP_ISCSI;
  1763. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1764. ulp_type = CNIC_ULP_L4;
  1765. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1766. goto end;
  1767. else {
  1768. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1769. kcqe_op_flag);
  1770. goto end;
  1771. }
  1772. rcu_read_lock();
  1773. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1774. if (likely(ulp_ops)) {
  1775. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1776. cp->completed_kcq + i, j);
  1777. }
  1778. rcu_read_unlock();
  1779. end:
  1780. num_cqes -= j;
  1781. i += j;
  1782. j = 1;
  1783. }
  1784. if (unlikely(comp))
  1785. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  1786. }
  1787. static u16 cnic_bnx2_next_idx(u16 idx)
  1788. {
  1789. return idx + 1;
  1790. }
  1791. static u16 cnic_bnx2_hw_idx(u16 idx)
  1792. {
  1793. return idx;
  1794. }
  1795. static u16 cnic_bnx2x_next_idx(u16 idx)
  1796. {
  1797. idx++;
  1798. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1799. idx++;
  1800. return idx;
  1801. }
  1802. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1803. {
  1804. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1805. idx++;
  1806. return idx;
  1807. }
  1808. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  1809. {
  1810. struct cnic_local *cp = dev->cnic_priv;
  1811. u16 i, ri, hw_prod, last;
  1812. struct kcqe *kcqe;
  1813. int kcqe_cnt = 0, last_cnt = 0;
  1814. i = ri = last = info->sw_prod_idx;
  1815. ri &= MAX_KCQ_IDX;
  1816. hw_prod = *info->hw_prod_idx_ptr;
  1817. hw_prod = cp->hw_idx(hw_prod);
  1818. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1819. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1820. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1821. i = cp->next_idx(i);
  1822. ri = i & MAX_KCQ_IDX;
  1823. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1824. last_cnt = kcqe_cnt;
  1825. last = i;
  1826. }
  1827. }
  1828. info->sw_prod_idx = last;
  1829. return last_cnt;
  1830. }
  1831. static int cnic_l2_completion(struct cnic_local *cp)
  1832. {
  1833. u16 hw_cons, sw_cons;
  1834. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1835. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  1836. u32 cmd;
  1837. int comp = 0;
  1838. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1839. return 0;
  1840. hw_cons = *cp->rx_cons_ptr;
  1841. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1842. hw_cons++;
  1843. sw_cons = cp->rx_cons;
  1844. while (sw_cons != hw_cons) {
  1845. u8 cqe_fp_flags;
  1846. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1847. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1848. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1849. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1850. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1851. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1852. cmd == RAMROD_CMD_ID_ETH_HALT)
  1853. comp++;
  1854. }
  1855. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1856. }
  1857. return comp;
  1858. }
  1859. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1860. {
  1861. u16 rx_cons, tx_cons;
  1862. int comp = 0;
  1863. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  1864. return;
  1865. rx_cons = *cp->rx_cons_ptr;
  1866. tx_cons = *cp->tx_cons_ptr;
  1867. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1868. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1869. comp = cnic_l2_completion(cp);
  1870. cp->tx_cons = tx_cons;
  1871. cp->rx_cons = rx_cons;
  1872. uio_event_notify(cp->cnic_uinfo);
  1873. }
  1874. if (comp)
  1875. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1876. }
  1877. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  1878. {
  1879. struct cnic_local *cp = dev->cnic_priv;
  1880. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1881. int kcqe_cnt;
  1882. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1883. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  1884. service_kcqes(dev, kcqe_cnt);
  1885. /* Tell compiler that status_blk fields can change. */
  1886. barrier();
  1887. if (status_idx != *cp->kcq1.status_idx_ptr) {
  1888. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1889. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1890. } else
  1891. break;
  1892. }
  1893. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  1894. cnic_chk_pkt_rings(cp);
  1895. return status_idx;
  1896. }
  1897. static int cnic_service_bnx2(void *data, void *status_blk)
  1898. {
  1899. struct cnic_dev *dev = data;
  1900. struct cnic_local *cp = dev->cnic_priv;
  1901. u32 status_idx = *cp->kcq1.status_idx_ptr;
  1902. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1903. return status_idx;
  1904. return cnic_service_bnx2_queues(dev);
  1905. }
  1906. static void cnic_service_bnx2_msix(unsigned long data)
  1907. {
  1908. struct cnic_dev *dev = (struct cnic_dev *) data;
  1909. struct cnic_local *cp = dev->cnic_priv;
  1910. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  1911. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1912. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1913. }
  1914. static void cnic_doirq(struct cnic_dev *dev)
  1915. {
  1916. struct cnic_local *cp = dev->cnic_priv;
  1917. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  1918. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1919. prefetch(cp->status_blk.gen);
  1920. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1921. tasklet_schedule(&cp->cnic_irq_task);
  1922. }
  1923. }
  1924. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1925. {
  1926. struct cnic_dev *dev = dev_instance;
  1927. struct cnic_local *cp = dev->cnic_priv;
  1928. if (cp->ack_int)
  1929. cp->ack_int(dev);
  1930. cnic_doirq(dev);
  1931. return IRQ_HANDLED;
  1932. }
  1933. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1934. u16 index, u8 op, u8 update)
  1935. {
  1936. struct cnic_local *cp = dev->cnic_priv;
  1937. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1938. COMMAND_REG_INT_ACK);
  1939. struct igu_ack_register igu_ack;
  1940. igu_ack.status_block_index = index;
  1941. igu_ack.sb_id_and_flags =
  1942. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1943. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1944. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1945. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1946. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1947. }
  1948. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1949. {
  1950. struct cnic_local *cp = dev->cnic_priv;
  1951. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  1952. IGU_INT_DISABLE, 0);
  1953. }
  1954. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  1955. {
  1956. u32 last_status = *info->status_idx_ptr;
  1957. int kcqe_cnt;
  1958. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  1959. service_kcqes(dev, kcqe_cnt);
  1960. /* Tell compiler that sblk fields can change. */
  1961. barrier();
  1962. if (last_status == *info->status_idx_ptr)
  1963. break;
  1964. last_status = *info->status_idx_ptr;
  1965. }
  1966. return last_status;
  1967. }
  1968. static void cnic_service_bnx2x_bh(unsigned long data)
  1969. {
  1970. struct cnic_dev *dev = (struct cnic_dev *) data;
  1971. struct cnic_local *cp = dev->cnic_priv;
  1972. u32 status_idx;
  1973. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1974. return;
  1975. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  1976. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  1977. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  1978. status_idx, IGU_INT_ENABLE, 1);
  1979. }
  1980. static int cnic_service_bnx2x(void *data, void *status_blk)
  1981. {
  1982. struct cnic_dev *dev = data;
  1983. struct cnic_local *cp = dev->cnic_priv;
  1984. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  1985. cnic_doirq(dev);
  1986. cnic_chk_pkt_rings(cp);
  1987. return 0;
  1988. }
  1989. static void cnic_ulp_stop(struct cnic_dev *dev)
  1990. {
  1991. struct cnic_local *cp = dev->cnic_priv;
  1992. int if_type;
  1993. if (cp->cnic_uinfo)
  1994. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  1995. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1996. struct cnic_ulp_ops *ulp_ops;
  1997. mutex_lock(&cnic_lock);
  1998. ulp_ops = cp->ulp_ops[if_type];
  1999. if (!ulp_ops) {
  2000. mutex_unlock(&cnic_lock);
  2001. continue;
  2002. }
  2003. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2004. mutex_unlock(&cnic_lock);
  2005. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2006. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2007. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2008. }
  2009. }
  2010. static void cnic_ulp_start(struct cnic_dev *dev)
  2011. {
  2012. struct cnic_local *cp = dev->cnic_priv;
  2013. int if_type;
  2014. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2015. struct cnic_ulp_ops *ulp_ops;
  2016. mutex_lock(&cnic_lock);
  2017. ulp_ops = cp->ulp_ops[if_type];
  2018. if (!ulp_ops || !ulp_ops->cnic_start) {
  2019. mutex_unlock(&cnic_lock);
  2020. continue;
  2021. }
  2022. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2023. mutex_unlock(&cnic_lock);
  2024. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2025. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2026. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2027. }
  2028. }
  2029. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2030. {
  2031. struct cnic_dev *dev = data;
  2032. switch (info->cmd) {
  2033. case CNIC_CTL_STOP_CMD:
  2034. cnic_hold(dev);
  2035. cnic_ulp_stop(dev);
  2036. cnic_stop_hw(dev);
  2037. cnic_put(dev);
  2038. break;
  2039. case CNIC_CTL_START_CMD:
  2040. cnic_hold(dev);
  2041. if (!cnic_start_hw(dev))
  2042. cnic_ulp_start(dev);
  2043. cnic_put(dev);
  2044. break;
  2045. case CNIC_CTL_COMPLETION_CMD: {
  2046. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2047. u32 l5_cid;
  2048. struct cnic_local *cp = dev->cnic_priv;
  2049. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2050. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2051. ctx->wait_cond = 1;
  2052. wake_up(&ctx->waitq);
  2053. }
  2054. break;
  2055. }
  2056. default:
  2057. return -EINVAL;
  2058. }
  2059. return 0;
  2060. }
  2061. static void cnic_ulp_init(struct cnic_dev *dev)
  2062. {
  2063. int i;
  2064. struct cnic_local *cp = dev->cnic_priv;
  2065. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2066. struct cnic_ulp_ops *ulp_ops;
  2067. mutex_lock(&cnic_lock);
  2068. ulp_ops = cnic_ulp_tbl[i];
  2069. if (!ulp_ops || !ulp_ops->cnic_init) {
  2070. mutex_unlock(&cnic_lock);
  2071. continue;
  2072. }
  2073. ulp_get(ulp_ops);
  2074. mutex_unlock(&cnic_lock);
  2075. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2076. ulp_ops->cnic_init(dev);
  2077. ulp_put(ulp_ops);
  2078. }
  2079. }
  2080. static void cnic_ulp_exit(struct cnic_dev *dev)
  2081. {
  2082. int i;
  2083. struct cnic_local *cp = dev->cnic_priv;
  2084. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2085. struct cnic_ulp_ops *ulp_ops;
  2086. mutex_lock(&cnic_lock);
  2087. ulp_ops = cnic_ulp_tbl[i];
  2088. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2089. mutex_unlock(&cnic_lock);
  2090. continue;
  2091. }
  2092. ulp_get(ulp_ops);
  2093. mutex_unlock(&cnic_lock);
  2094. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2095. ulp_ops->cnic_exit(dev);
  2096. ulp_put(ulp_ops);
  2097. }
  2098. }
  2099. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2100. {
  2101. struct cnic_dev *dev = csk->dev;
  2102. struct l4_kwq_offload_pg *l4kwqe;
  2103. struct kwqe *wqes[1];
  2104. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2105. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2106. wqes[0] = (struct kwqe *) l4kwqe;
  2107. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2108. l4kwqe->flags =
  2109. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2110. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2111. l4kwqe->da0 = csk->ha[0];
  2112. l4kwqe->da1 = csk->ha[1];
  2113. l4kwqe->da2 = csk->ha[2];
  2114. l4kwqe->da3 = csk->ha[3];
  2115. l4kwqe->da4 = csk->ha[4];
  2116. l4kwqe->da5 = csk->ha[5];
  2117. l4kwqe->sa0 = dev->mac_addr[0];
  2118. l4kwqe->sa1 = dev->mac_addr[1];
  2119. l4kwqe->sa2 = dev->mac_addr[2];
  2120. l4kwqe->sa3 = dev->mac_addr[3];
  2121. l4kwqe->sa4 = dev->mac_addr[4];
  2122. l4kwqe->sa5 = dev->mac_addr[5];
  2123. l4kwqe->etype = ETH_P_IP;
  2124. l4kwqe->ipid_start = DEF_IPID_START;
  2125. l4kwqe->host_opaque = csk->l5_cid;
  2126. if (csk->vlan_id) {
  2127. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2128. l4kwqe->vlan_tag = csk->vlan_id;
  2129. l4kwqe->l2hdr_nbytes += 4;
  2130. }
  2131. return dev->submit_kwqes(dev, wqes, 1);
  2132. }
  2133. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2134. {
  2135. struct cnic_dev *dev = csk->dev;
  2136. struct l4_kwq_update_pg *l4kwqe;
  2137. struct kwqe *wqes[1];
  2138. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2139. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2140. wqes[0] = (struct kwqe *) l4kwqe;
  2141. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2142. l4kwqe->flags =
  2143. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2144. l4kwqe->pg_cid = csk->pg_cid;
  2145. l4kwqe->da0 = csk->ha[0];
  2146. l4kwqe->da1 = csk->ha[1];
  2147. l4kwqe->da2 = csk->ha[2];
  2148. l4kwqe->da3 = csk->ha[3];
  2149. l4kwqe->da4 = csk->ha[4];
  2150. l4kwqe->da5 = csk->ha[5];
  2151. l4kwqe->pg_host_opaque = csk->l5_cid;
  2152. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2153. return dev->submit_kwqes(dev, wqes, 1);
  2154. }
  2155. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2156. {
  2157. struct cnic_dev *dev = csk->dev;
  2158. struct l4_kwq_upload *l4kwqe;
  2159. struct kwqe *wqes[1];
  2160. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2161. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2162. wqes[0] = (struct kwqe *) l4kwqe;
  2163. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2164. l4kwqe->flags =
  2165. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2166. l4kwqe->cid = csk->pg_cid;
  2167. return dev->submit_kwqes(dev, wqes, 1);
  2168. }
  2169. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2170. {
  2171. struct cnic_dev *dev = csk->dev;
  2172. struct l4_kwq_connect_req1 *l4kwqe1;
  2173. struct l4_kwq_connect_req2 *l4kwqe2;
  2174. struct l4_kwq_connect_req3 *l4kwqe3;
  2175. struct kwqe *wqes[3];
  2176. u8 tcp_flags = 0;
  2177. int num_wqes = 2;
  2178. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2179. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2180. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2181. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2182. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2183. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2184. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2185. l4kwqe3->flags =
  2186. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2187. l4kwqe3->ka_timeout = csk->ka_timeout;
  2188. l4kwqe3->ka_interval = csk->ka_interval;
  2189. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2190. l4kwqe3->tos = csk->tos;
  2191. l4kwqe3->ttl = csk->ttl;
  2192. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2193. l4kwqe3->pmtu = csk->mtu;
  2194. l4kwqe3->rcv_buf = csk->rcv_buf;
  2195. l4kwqe3->snd_buf = csk->snd_buf;
  2196. l4kwqe3->seed = csk->seed;
  2197. wqes[0] = (struct kwqe *) l4kwqe1;
  2198. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2199. wqes[1] = (struct kwqe *) l4kwqe2;
  2200. wqes[2] = (struct kwqe *) l4kwqe3;
  2201. num_wqes = 3;
  2202. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2203. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2204. l4kwqe2->flags =
  2205. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2206. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2207. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2208. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2209. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2210. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2211. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2212. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2213. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2214. sizeof(struct tcphdr);
  2215. } else {
  2216. wqes[1] = (struct kwqe *) l4kwqe3;
  2217. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2218. sizeof(struct tcphdr);
  2219. }
  2220. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2221. l4kwqe1->flags =
  2222. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2223. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2224. l4kwqe1->cid = csk->cid;
  2225. l4kwqe1->pg_cid = csk->pg_cid;
  2226. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2227. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2228. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2229. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2230. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2231. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2232. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2233. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2234. if (csk->tcp_flags & SK_TCP_NAGLE)
  2235. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2236. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2237. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2238. if (csk->tcp_flags & SK_TCP_SACK)
  2239. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2240. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2241. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2242. l4kwqe1->tcp_flags = tcp_flags;
  2243. return dev->submit_kwqes(dev, wqes, num_wqes);
  2244. }
  2245. static int cnic_cm_close_req(struct cnic_sock *csk)
  2246. {
  2247. struct cnic_dev *dev = csk->dev;
  2248. struct l4_kwq_close_req *l4kwqe;
  2249. struct kwqe *wqes[1];
  2250. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2251. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2252. wqes[0] = (struct kwqe *) l4kwqe;
  2253. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2254. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2255. l4kwqe->cid = csk->cid;
  2256. return dev->submit_kwqes(dev, wqes, 1);
  2257. }
  2258. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2259. {
  2260. struct cnic_dev *dev = csk->dev;
  2261. struct l4_kwq_reset_req *l4kwqe;
  2262. struct kwqe *wqes[1];
  2263. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2264. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2265. wqes[0] = (struct kwqe *) l4kwqe;
  2266. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2267. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2268. l4kwqe->cid = csk->cid;
  2269. return dev->submit_kwqes(dev, wqes, 1);
  2270. }
  2271. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2272. u32 l5_cid, struct cnic_sock **csk, void *context)
  2273. {
  2274. struct cnic_local *cp = dev->cnic_priv;
  2275. struct cnic_sock *csk1;
  2276. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2277. return -EINVAL;
  2278. csk1 = &cp->csk_tbl[l5_cid];
  2279. if (atomic_read(&csk1->ref_count))
  2280. return -EAGAIN;
  2281. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2282. return -EBUSY;
  2283. csk1->dev = dev;
  2284. csk1->cid = cid;
  2285. csk1->l5_cid = l5_cid;
  2286. csk1->ulp_type = ulp_type;
  2287. csk1->context = context;
  2288. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2289. csk1->ka_interval = DEF_KA_INTERVAL;
  2290. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2291. csk1->tos = DEF_TOS;
  2292. csk1->ttl = DEF_TTL;
  2293. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2294. csk1->rcv_buf = DEF_RCV_BUF;
  2295. csk1->snd_buf = DEF_SND_BUF;
  2296. csk1->seed = DEF_SEED;
  2297. *csk = csk1;
  2298. return 0;
  2299. }
  2300. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2301. {
  2302. if (csk->src_port) {
  2303. struct cnic_dev *dev = csk->dev;
  2304. struct cnic_local *cp = dev->cnic_priv;
  2305. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2306. csk->src_port = 0;
  2307. }
  2308. }
  2309. static void cnic_close_conn(struct cnic_sock *csk)
  2310. {
  2311. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2312. cnic_cm_upload_pg(csk);
  2313. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2314. }
  2315. cnic_cm_cleanup(csk);
  2316. }
  2317. static int cnic_cm_destroy(struct cnic_sock *csk)
  2318. {
  2319. if (!cnic_in_use(csk))
  2320. return -EINVAL;
  2321. csk_hold(csk);
  2322. clear_bit(SK_F_INUSE, &csk->flags);
  2323. smp_mb__after_clear_bit();
  2324. while (atomic_read(&csk->ref_count) != 1)
  2325. msleep(1);
  2326. cnic_cm_cleanup(csk);
  2327. csk->flags = 0;
  2328. csk_put(csk);
  2329. return 0;
  2330. }
  2331. static inline u16 cnic_get_vlan(struct net_device *dev,
  2332. struct net_device **vlan_dev)
  2333. {
  2334. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2335. *vlan_dev = vlan_dev_real_dev(dev);
  2336. return vlan_dev_vlan_id(dev);
  2337. }
  2338. *vlan_dev = dev;
  2339. return 0;
  2340. }
  2341. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2342. struct dst_entry **dst)
  2343. {
  2344. #if defined(CONFIG_INET)
  2345. struct flowi fl;
  2346. int err;
  2347. struct rtable *rt;
  2348. memset(&fl, 0, sizeof(fl));
  2349. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2350. err = ip_route_output_key(&init_net, &rt, &fl);
  2351. if (!err)
  2352. *dst = &rt->dst;
  2353. return err;
  2354. #else
  2355. return -ENETUNREACH;
  2356. #endif
  2357. }
  2358. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2359. struct dst_entry **dst)
  2360. {
  2361. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2362. struct flowi fl;
  2363. memset(&fl, 0, sizeof(fl));
  2364. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2365. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2366. fl.oif = dst_addr->sin6_scope_id;
  2367. *dst = ip6_route_output(&init_net, NULL, &fl);
  2368. if (*dst)
  2369. return 0;
  2370. #endif
  2371. return -ENETUNREACH;
  2372. }
  2373. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2374. int ulp_type)
  2375. {
  2376. struct cnic_dev *dev = NULL;
  2377. struct dst_entry *dst;
  2378. struct net_device *netdev = NULL;
  2379. int err = -ENETUNREACH;
  2380. if (dst_addr->sin_family == AF_INET)
  2381. err = cnic_get_v4_route(dst_addr, &dst);
  2382. else if (dst_addr->sin_family == AF_INET6) {
  2383. struct sockaddr_in6 *dst_addr6 =
  2384. (struct sockaddr_in6 *) dst_addr;
  2385. err = cnic_get_v6_route(dst_addr6, &dst);
  2386. } else
  2387. return NULL;
  2388. if (err)
  2389. return NULL;
  2390. if (!dst->dev)
  2391. goto done;
  2392. cnic_get_vlan(dst->dev, &netdev);
  2393. dev = cnic_from_netdev(netdev);
  2394. done:
  2395. dst_release(dst);
  2396. if (dev)
  2397. cnic_put(dev);
  2398. return dev;
  2399. }
  2400. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2401. {
  2402. struct cnic_dev *dev = csk->dev;
  2403. struct cnic_local *cp = dev->cnic_priv;
  2404. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2405. }
  2406. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2407. {
  2408. struct cnic_dev *dev = csk->dev;
  2409. struct cnic_local *cp = dev->cnic_priv;
  2410. int is_v6, rc = 0;
  2411. struct dst_entry *dst = NULL;
  2412. struct net_device *realdev;
  2413. u32 local_port;
  2414. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2415. saddr->remote.v6.sin6_family == AF_INET6)
  2416. is_v6 = 1;
  2417. else if (saddr->local.v4.sin_family == AF_INET &&
  2418. saddr->remote.v4.sin_family == AF_INET)
  2419. is_v6 = 0;
  2420. else
  2421. return -EINVAL;
  2422. clear_bit(SK_F_IPV6, &csk->flags);
  2423. if (is_v6) {
  2424. set_bit(SK_F_IPV6, &csk->flags);
  2425. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2426. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2427. sizeof(struct in6_addr));
  2428. csk->dst_port = saddr->remote.v6.sin6_port;
  2429. local_port = saddr->local.v6.sin6_port;
  2430. } else {
  2431. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2432. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2433. csk->dst_port = saddr->remote.v4.sin_port;
  2434. local_port = saddr->local.v4.sin_port;
  2435. }
  2436. csk->vlan_id = 0;
  2437. csk->mtu = dev->netdev->mtu;
  2438. if (dst && dst->dev) {
  2439. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2440. if (realdev == dev->netdev) {
  2441. csk->vlan_id = vlan;
  2442. csk->mtu = dst_mtu(dst);
  2443. }
  2444. }
  2445. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2446. local_port < CNIC_LOCAL_PORT_MAX) {
  2447. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2448. local_port = 0;
  2449. } else
  2450. local_port = 0;
  2451. if (!local_port) {
  2452. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2453. if (local_port == -1) {
  2454. rc = -ENOMEM;
  2455. goto err_out;
  2456. }
  2457. }
  2458. csk->src_port = local_port;
  2459. err_out:
  2460. dst_release(dst);
  2461. return rc;
  2462. }
  2463. static void cnic_init_csk_state(struct cnic_sock *csk)
  2464. {
  2465. csk->state = 0;
  2466. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2467. clear_bit(SK_F_CLOSING, &csk->flags);
  2468. }
  2469. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2470. {
  2471. int err = 0;
  2472. if (!cnic_in_use(csk))
  2473. return -EINVAL;
  2474. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2475. return -EINVAL;
  2476. cnic_init_csk_state(csk);
  2477. err = cnic_get_route(csk, saddr);
  2478. if (err)
  2479. goto err_out;
  2480. err = cnic_resolve_addr(csk, saddr);
  2481. if (!err)
  2482. return 0;
  2483. err_out:
  2484. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2485. return err;
  2486. }
  2487. static int cnic_cm_abort(struct cnic_sock *csk)
  2488. {
  2489. struct cnic_local *cp = csk->dev->cnic_priv;
  2490. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2491. if (!cnic_in_use(csk))
  2492. return -EINVAL;
  2493. if (cnic_abort_prep(csk))
  2494. return cnic_cm_abort_req(csk);
  2495. /* Getting here means that we haven't started connect, or
  2496. * connect was not successful.
  2497. */
  2498. cp->close_conn(csk, opcode);
  2499. if (csk->state != opcode)
  2500. return -EALREADY;
  2501. return 0;
  2502. }
  2503. static int cnic_cm_close(struct cnic_sock *csk)
  2504. {
  2505. if (!cnic_in_use(csk))
  2506. return -EINVAL;
  2507. if (cnic_close_prep(csk)) {
  2508. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2509. return cnic_cm_close_req(csk);
  2510. } else {
  2511. return -EALREADY;
  2512. }
  2513. return 0;
  2514. }
  2515. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2516. u8 opcode)
  2517. {
  2518. struct cnic_ulp_ops *ulp_ops;
  2519. int ulp_type = csk->ulp_type;
  2520. rcu_read_lock();
  2521. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2522. if (ulp_ops) {
  2523. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2524. ulp_ops->cm_connect_complete(csk);
  2525. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2526. ulp_ops->cm_close_complete(csk);
  2527. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2528. ulp_ops->cm_remote_abort(csk);
  2529. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2530. ulp_ops->cm_abort_complete(csk);
  2531. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2532. ulp_ops->cm_remote_close(csk);
  2533. }
  2534. rcu_read_unlock();
  2535. }
  2536. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2537. {
  2538. if (cnic_offld_prep(csk)) {
  2539. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2540. cnic_cm_update_pg(csk);
  2541. else
  2542. cnic_cm_offload_pg(csk);
  2543. }
  2544. return 0;
  2545. }
  2546. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2547. {
  2548. struct cnic_local *cp = dev->cnic_priv;
  2549. u32 l5_cid = kcqe->pg_host_opaque;
  2550. u8 opcode = kcqe->op_code;
  2551. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2552. csk_hold(csk);
  2553. if (!cnic_in_use(csk))
  2554. goto done;
  2555. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2556. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2557. goto done;
  2558. }
  2559. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2560. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2561. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2562. cnic_cm_upcall(cp, csk,
  2563. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2564. goto done;
  2565. }
  2566. csk->pg_cid = kcqe->pg_cid;
  2567. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2568. cnic_cm_conn_req(csk);
  2569. done:
  2570. csk_put(csk);
  2571. }
  2572. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2573. {
  2574. struct cnic_local *cp = dev->cnic_priv;
  2575. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2576. u8 opcode = l4kcqe->op_code;
  2577. u32 l5_cid;
  2578. struct cnic_sock *csk;
  2579. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2580. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2581. cnic_cm_process_offld_pg(dev, l4kcqe);
  2582. return;
  2583. }
  2584. l5_cid = l4kcqe->conn_id;
  2585. if (opcode & 0x80)
  2586. l5_cid = l4kcqe->cid;
  2587. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2588. return;
  2589. csk = &cp->csk_tbl[l5_cid];
  2590. csk_hold(csk);
  2591. if (!cnic_in_use(csk)) {
  2592. csk_put(csk);
  2593. return;
  2594. }
  2595. switch (opcode) {
  2596. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2597. if (l4kcqe->status != 0) {
  2598. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2599. cnic_cm_upcall(cp, csk,
  2600. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2601. }
  2602. break;
  2603. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2604. if (l4kcqe->status == 0)
  2605. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2606. smp_mb__before_clear_bit();
  2607. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2608. cnic_cm_upcall(cp, csk, opcode);
  2609. break;
  2610. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2611. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2612. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2613. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2614. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2615. cp->close_conn(csk, opcode);
  2616. break;
  2617. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2618. cnic_cm_upcall(cp, csk, opcode);
  2619. break;
  2620. }
  2621. csk_put(csk);
  2622. }
  2623. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2624. {
  2625. struct cnic_dev *dev = data;
  2626. int i;
  2627. for (i = 0; i < num; i++)
  2628. cnic_cm_process_kcqe(dev, kcqe[i]);
  2629. }
  2630. static struct cnic_ulp_ops cm_ulp_ops = {
  2631. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2632. };
  2633. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2634. {
  2635. struct cnic_local *cp = dev->cnic_priv;
  2636. kfree(cp->csk_tbl);
  2637. cp->csk_tbl = NULL;
  2638. cnic_free_id_tbl(&cp->csk_port_tbl);
  2639. }
  2640. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2641. {
  2642. struct cnic_local *cp = dev->cnic_priv;
  2643. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2644. GFP_KERNEL);
  2645. if (!cp->csk_tbl)
  2646. return -ENOMEM;
  2647. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2648. CNIC_LOCAL_PORT_MIN)) {
  2649. cnic_cm_free_mem(dev);
  2650. return -ENOMEM;
  2651. }
  2652. return 0;
  2653. }
  2654. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2655. {
  2656. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  2657. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  2658. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2659. csk->state = opcode;
  2660. }
  2661. /* 1. If event opcode matches the expected event in csk->state
  2662. * 2. If the expected event is CLOSE_COMP, we accept any event
  2663. * 3. If the expected event is 0, meaning the connection was never
  2664. * never established, we accept the opcode from cm_abort.
  2665. */
  2666. if (opcode == csk->state || csk->state == 0 ||
  2667. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  2668. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2669. if (csk->state == 0)
  2670. csk->state = opcode;
  2671. return 1;
  2672. }
  2673. }
  2674. return 0;
  2675. }
  2676. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2677. {
  2678. struct cnic_dev *dev = csk->dev;
  2679. struct cnic_local *cp = dev->cnic_priv;
  2680. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  2681. cnic_cm_upcall(cp, csk, opcode);
  2682. return;
  2683. }
  2684. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2685. cnic_close_conn(csk);
  2686. csk->state = opcode;
  2687. cnic_cm_upcall(cp, csk, opcode);
  2688. }
  2689. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2690. {
  2691. }
  2692. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2693. {
  2694. u32 seed;
  2695. get_random_bytes(&seed, 4);
  2696. cnic_ctx_wr(dev, 45, 0, seed);
  2697. return 0;
  2698. }
  2699. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2700. {
  2701. struct cnic_dev *dev = csk->dev;
  2702. struct cnic_local *cp = dev->cnic_priv;
  2703. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2704. union l5cm_specific_data l5_data;
  2705. u32 cmd = 0;
  2706. int close_complete = 0;
  2707. switch (opcode) {
  2708. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2709. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2710. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2711. if (cnic_ready_to_close(csk, opcode)) {
  2712. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2713. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2714. else
  2715. close_complete = 1;
  2716. }
  2717. break;
  2718. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2719. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2720. break;
  2721. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2722. close_complete = 1;
  2723. break;
  2724. }
  2725. if (cmd) {
  2726. memset(&l5_data, 0, sizeof(l5_data));
  2727. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2728. &l5_data);
  2729. } else if (close_complete) {
  2730. ctx->timestamp = jiffies;
  2731. cnic_close_conn(csk);
  2732. cnic_cm_upcall(cp, csk, csk->state);
  2733. }
  2734. }
  2735. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2736. {
  2737. }
  2738. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2739. {
  2740. struct cnic_local *cp = dev->cnic_priv;
  2741. u32 pfid = cp->pfid;
  2742. u32 port = CNIC_PORT(cp);
  2743. cnic_init_bnx2x_mac(dev);
  2744. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2745. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2746. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  2747. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2748. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  2749. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2750. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  2751. DEF_MAX_DA_COUNT);
  2752. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2753. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  2754. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2755. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  2756. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2757. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  2758. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2759. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  2760. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  2761. DEF_MAX_CWND);
  2762. return 0;
  2763. }
  2764. static int cnic_cm_open(struct cnic_dev *dev)
  2765. {
  2766. struct cnic_local *cp = dev->cnic_priv;
  2767. int err;
  2768. err = cnic_cm_alloc_mem(dev);
  2769. if (err)
  2770. return err;
  2771. err = cp->start_cm(dev);
  2772. if (err)
  2773. goto err_out;
  2774. dev->cm_create = cnic_cm_create;
  2775. dev->cm_destroy = cnic_cm_destroy;
  2776. dev->cm_connect = cnic_cm_connect;
  2777. dev->cm_abort = cnic_cm_abort;
  2778. dev->cm_close = cnic_cm_close;
  2779. dev->cm_select_dev = cnic_cm_select_dev;
  2780. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2781. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2782. return 0;
  2783. err_out:
  2784. cnic_cm_free_mem(dev);
  2785. return err;
  2786. }
  2787. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2788. {
  2789. struct cnic_local *cp = dev->cnic_priv;
  2790. int i;
  2791. cp->stop_cm(dev);
  2792. if (!cp->csk_tbl)
  2793. return 0;
  2794. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2795. struct cnic_sock *csk = &cp->csk_tbl[i];
  2796. clear_bit(SK_F_INUSE, &csk->flags);
  2797. cnic_cm_cleanup(csk);
  2798. }
  2799. cnic_cm_free_mem(dev);
  2800. return 0;
  2801. }
  2802. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2803. {
  2804. u32 cid_addr;
  2805. int i;
  2806. cid_addr = GET_CID_ADDR(cid);
  2807. for (i = 0; i < CTX_SIZE; i += 4)
  2808. cnic_ctx_wr(dev, cid_addr, i, 0);
  2809. }
  2810. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2811. {
  2812. struct cnic_local *cp = dev->cnic_priv;
  2813. int ret = 0, i;
  2814. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2815. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2816. return 0;
  2817. for (i = 0; i < cp->ctx_blks; i++) {
  2818. int j;
  2819. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2820. u32 val;
  2821. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2822. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2823. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2824. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2825. (u64) cp->ctx_arr[i].mapping >> 32);
  2826. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2827. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2828. for (j = 0; j < 10; j++) {
  2829. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2830. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2831. break;
  2832. udelay(5);
  2833. }
  2834. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2835. ret = -EBUSY;
  2836. break;
  2837. }
  2838. }
  2839. return ret;
  2840. }
  2841. static void cnic_free_irq(struct cnic_dev *dev)
  2842. {
  2843. struct cnic_local *cp = dev->cnic_priv;
  2844. struct cnic_eth_dev *ethdev = cp->ethdev;
  2845. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2846. cp->disable_int_sync(dev);
  2847. tasklet_kill(&cp->cnic_irq_task);
  2848. free_irq(ethdev->irq_arr[0].vector, dev);
  2849. }
  2850. }
  2851. static int cnic_request_irq(struct cnic_dev *dev)
  2852. {
  2853. struct cnic_local *cp = dev->cnic_priv;
  2854. struct cnic_eth_dev *ethdev = cp->ethdev;
  2855. int err;
  2856. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  2857. if (err)
  2858. tasklet_disable(&cp->cnic_irq_task);
  2859. return err;
  2860. }
  2861. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2862. {
  2863. struct cnic_local *cp = dev->cnic_priv;
  2864. struct cnic_eth_dev *ethdev = cp->ethdev;
  2865. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2866. int err, i = 0;
  2867. int sblk_num = cp->status_blk_num;
  2868. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2869. BNX2_HC_SB_CONFIG_1;
  2870. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2871. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2872. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2873. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2874. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  2875. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2876. (unsigned long) dev);
  2877. err = cnic_request_irq(dev);
  2878. if (err)
  2879. return err;
  2880. while (cp->status_blk.bnx2->status_completion_producer_index &&
  2881. i < 10) {
  2882. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2883. 1 << (11 + sblk_num));
  2884. udelay(10);
  2885. i++;
  2886. barrier();
  2887. }
  2888. if (cp->status_blk.bnx2->status_completion_producer_index) {
  2889. cnic_free_irq(dev);
  2890. goto failed;
  2891. }
  2892. } else {
  2893. struct status_block *sblk = cp->status_blk.gen;
  2894. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2895. int i = 0;
  2896. while (sblk->status_completion_producer_index && i < 10) {
  2897. CNIC_WR(dev, BNX2_HC_COMMAND,
  2898. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2899. udelay(10);
  2900. i++;
  2901. barrier();
  2902. }
  2903. if (sblk->status_completion_producer_index)
  2904. goto failed;
  2905. }
  2906. return 0;
  2907. failed:
  2908. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  2909. return -EBUSY;
  2910. }
  2911. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2912. {
  2913. struct cnic_local *cp = dev->cnic_priv;
  2914. struct cnic_eth_dev *ethdev = cp->ethdev;
  2915. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2916. return;
  2917. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2918. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2919. }
  2920. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  2921. {
  2922. struct cnic_local *cp = dev->cnic_priv;
  2923. struct cnic_eth_dev *ethdev = cp->ethdev;
  2924. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2925. return;
  2926. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2927. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2928. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  2929. synchronize_irq(ethdev->irq_arr[0].vector);
  2930. }
  2931. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  2932. {
  2933. struct cnic_local *cp = dev->cnic_priv;
  2934. struct cnic_eth_dev *ethdev = cp->ethdev;
  2935. u32 cid_addr, tx_cid, sb_id;
  2936. u32 val, offset0, offset1, offset2, offset3;
  2937. int i;
  2938. struct tx_bd *txbd;
  2939. dma_addr_t buf_map;
  2940. struct status_block *s_blk = cp->status_blk.gen;
  2941. sb_id = cp->status_blk_num;
  2942. tx_cid = 20;
  2943. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  2944. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2945. struct status_block_msix *sblk = cp->status_blk.bnx2;
  2946. tx_cid = TX_TSS_CID + sb_id - 1;
  2947. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  2948. (TX_TSS_CID << 7));
  2949. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  2950. }
  2951. cp->tx_cons = *cp->tx_cons_ptr;
  2952. cid_addr = GET_CID_ADDR(tx_cid);
  2953. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  2954. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  2955. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  2956. cnic_ctx_wr(dev, cid_addr2, i, 0);
  2957. offset0 = BNX2_L2CTX_TYPE_XI;
  2958. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  2959. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  2960. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  2961. } else {
  2962. cnic_init_context(dev, tx_cid);
  2963. cnic_init_context(dev, tx_cid + 1);
  2964. offset0 = BNX2_L2CTX_TYPE;
  2965. offset1 = BNX2_L2CTX_CMD_TYPE;
  2966. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  2967. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  2968. }
  2969. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  2970. cnic_ctx_wr(dev, cid_addr, offset0, val);
  2971. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  2972. cnic_ctx_wr(dev, cid_addr, offset1, val);
  2973. txbd = (struct tx_bd *) cp->l2_ring;
  2974. buf_map = cp->l2_buf_map;
  2975. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  2976. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  2977. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2978. }
  2979. val = (u64) cp->l2_ring_map >> 32;
  2980. cnic_ctx_wr(dev, cid_addr, offset2, val);
  2981. txbd->tx_bd_haddr_hi = val;
  2982. val = (u64) cp->l2_ring_map & 0xffffffff;
  2983. cnic_ctx_wr(dev, cid_addr, offset3, val);
  2984. txbd->tx_bd_haddr_lo = val;
  2985. }
  2986. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  2987. {
  2988. struct cnic_local *cp = dev->cnic_priv;
  2989. struct cnic_eth_dev *ethdev = cp->ethdev;
  2990. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  2991. int i;
  2992. struct rx_bd *rxbd;
  2993. struct status_block *s_blk = cp->status_blk.gen;
  2994. sb_id = cp->status_blk_num;
  2995. cnic_init_context(dev, 2);
  2996. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  2997. coal_reg = BNX2_HC_COMMAND;
  2998. coal_val = CNIC_RD(dev, coal_reg);
  2999. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3000. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3001. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3002. coal_reg = BNX2_HC_COALESCE_NOW;
  3003. coal_val = 1 << (11 + sb_id);
  3004. }
  3005. i = 0;
  3006. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3007. CNIC_WR(dev, coal_reg, coal_val);
  3008. udelay(10);
  3009. i++;
  3010. barrier();
  3011. }
  3012. cp->rx_cons = *cp->rx_cons_ptr;
  3013. cid_addr = GET_CID_ADDR(2);
  3014. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3015. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3016. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3017. if (sb_id == 0)
  3018. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3019. else
  3020. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3021. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3022. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  3023. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3024. dma_addr_t buf_map;
  3025. int n = (i % cp->l2_rx_ring_size) + 1;
  3026. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3027. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3028. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3029. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3030. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3031. }
  3032. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3033. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3034. rxbd->rx_bd_haddr_hi = val;
  3035. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3036. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3037. rxbd->rx_bd_haddr_lo = val;
  3038. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3039. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3040. }
  3041. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3042. {
  3043. struct kwqe *wqes[1], l2kwqe;
  3044. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3045. wqes[0] = &l2kwqe;
  3046. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3047. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3048. KWQE_OPCODE_SHIFT) | 2;
  3049. dev->submit_kwqes(dev, wqes, 1);
  3050. }
  3051. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3052. {
  3053. struct cnic_local *cp = dev->cnic_priv;
  3054. u32 val;
  3055. val = cp->func << 2;
  3056. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3057. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3058. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3059. dev->mac_addr[0] = (u8) (val >> 8);
  3060. dev->mac_addr[1] = (u8) val;
  3061. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3062. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3063. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3064. dev->mac_addr[2] = (u8) (val >> 24);
  3065. dev->mac_addr[3] = (u8) (val >> 16);
  3066. dev->mac_addr[4] = (u8) (val >> 8);
  3067. dev->mac_addr[5] = (u8) val;
  3068. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3069. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3070. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3071. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3072. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3073. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3074. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3075. }
  3076. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3077. {
  3078. struct cnic_local *cp = dev->cnic_priv;
  3079. struct cnic_eth_dev *ethdev = cp->ethdev;
  3080. struct status_block *sblk = cp->status_blk.gen;
  3081. u32 val, kcq_cid_addr, kwq_cid_addr;
  3082. int err;
  3083. cnic_set_bnx2_mac(dev);
  3084. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3085. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3086. if (BCM_PAGE_BITS > 12)
  3087. val |= (12 - 8) << 4;
  3088. else
  3089. val |= (BCM_PAGE_BITS - 8) << 4;
  3090. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3091. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3092. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3093. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3094. err = cnic_setup_5709_context(dev, 1);
  3095. if (err)
  3096. return err;
  3097. cnic_init_context(dev, KWQ_CID);
  3098. cnic_init_context(dev, KCQ_CID);
  3099. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3100. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3101. cp->max_kwq_idx = MAX_KWQ_IDX;
  3102. cp->kwq_prod_idx = 0;
  3103. cp->kwq_con_idx = 0;
  3104. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3105. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3106. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3107. else
  3108. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3109. /* Initialize the kernel work queue context. */
  3110. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3111. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3112. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3113. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3114. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3115. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3116. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3117. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3118. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3119. val = (u32) cp->kwq_info.pgtbl_map;
  3120. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3121. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3122. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3123. cp->kcq1.sw_prod_idx = 0;
  3124. cp->kcq1.hw_prod_idx_ptr =
  3125. (u16 *) &sblk->status_completion_producer_index;
  3126. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3127. /* Initialize the kernel complete queue context. */
  3128. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3129. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3130. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3131. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3132. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3133. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3134. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3135. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3136. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3137. val = (u32) cp->kcq1.dma.pgtbl_map;
  3138. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3139. cp->int_num = 0;
  3140. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3141. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3142. u32 sb_id = cp->status_blk_num;
  3143. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3144. cp->kcq1.hw_prod_idx_ptr =
  3145. (u16 *) &msblk->status_completion_producer_index;
  3146. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3147. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3148. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3149. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3150. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3151. }
  3152. /* Enable Commnad Scheduler notification when we write to the
  3153. * host producer index of the kernel contexts. */
  3154. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3155. /* Enable Command Scheduler notification when we write to either
  3156. * the Send Queue or Receive Queue producer indexes of the kernel
  3157. * bypass contexts. */
  3158. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3159. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3160. /* Notify COM when the driver post an application buffer. */
  3161. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3162. /* Set the CP and COM doorbells. These two processors polls the
  3163. * doorbell for a non zero value before running. This must be done
  3164. * after setting up the kernel queue contexts. */
  3165. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3166. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3167. cnic_init_bnx2_tx_ring(dev);
  3168. cnic_init_bnx2_rx_ring(dev);
  3169. err = cnic_init_bnx2_irq(dev);
  3170. if (err) {
  3171. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3172. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3173. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3174. return err;
  3175. }
  3176. return 0;
  3177. }
  3178. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3179. {
  3180. struct cnic_local *cp = dev->cnic_priv;
  3181. struct cnic_eth_dev *ethdev = cp->ethdev;
  3182. u32 start_offset = ethdev->ctx_tbl_offset;
  3183. int i;
  3184. for (i = 0; i < cp->ctx_blks; i++) {
  3185. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3186. dma_addr_t map = ctx->mapping;
  3187. if (cp->ctx_align) {
  3188. unsigned long mask = cp->ctx_align - 1;
  3189. map = (map + mask) & ~mask;
  3190. }
  3191. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3192. }
  3193. }
  3194. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3195. {
  3196. struct cnic_local *cp = dev->cnic_priv;
  3197. struct cnic_eth_dev *ethdev = cp->ethdev;
  3198. int err = 0;
  3199. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3200. (unsigned long) dev);
  3201. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3202. err = cnic_request_irq(dev);
  3203. return err;
  3204. }
  3205. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3206. u16 sb_id, u8 sb_index,
  3207. u8 disable)
  3208. {
  3209. u32 addr = BAR_CSTRORM_INTMEM +
  3210. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3211. offsetof(struct hc_status_block_data_e1x, index_data) +
  3212. sizeof(struct hc_index_data)*sb_index +
  3213. offsetof(struct hc_index_data, flags);
  3214. u16 flags = CNIC_RD16(dev, addr);
  3215. /* clear and set */
  3216. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3217. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3218. HC_INDEX_DATA_HC_ENABLED);
  3219. CNIC_WR16(dev, addr, flags);
  3220. }
  3221. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3222. {
  3223. struct cnic_local *cp = dev->cnic_priv;
  3224. u8 sb_id = cp->status_blk_num;
  3225. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3226. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3227. offsetof(struct hc_status_block_data_e1x, index_data) +
  3228. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3229. offsetof(struct hc_index_data, timeout), 64 / 12);
  3230. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3231. }
  3232. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3233. {
  3234. }
  3235. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3236. struct client_init_ramrod_data *data)
  3237. {
  3238. struct cnic_local *cp = dev->cnic_priv;
  3239. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
  3240. dma_addr_t buf_map, ring_map = cp->l2_ring_map;
  3241. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3242. int port = CNIC_PORT(cp);
  3243. int i;
  3244. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3245. u32 val;
  3246. memset(txbd, 0, BCM_PAGE_SIZE);
  3247. buf_map = cp->l2_buf_map;
  3248. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3249. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3250. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3251. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3252. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3253. reg_bd->addr_hi = start_bd->addr_hi;
  3254. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3255. start_bd->nbytes = cpu_to_le16(0x10);
  3256. start_bd->nbd = cpu_to_le16(3);
  3257. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3258. start_bd->general_data = (UNICAST_ADDRESS <<
  3259. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3260. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3261. }
  3262. val = (u64) ring_map >> 32;
  3263. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3264. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3265. val = (u64) ring_map & 0xffffffff;
  3266. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3267. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3268. /* Other ramrod params */
  3269. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3270. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3271. /* reset xstorm per client statistics */
  3272. if (cli < MAX_STAT_COUNTER_ID) {
  3273. val = BAR_XSTRORM_INTMEM +
  3274. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3275. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3276. CNIC_WR(dev, val + i * 4, 0);
  3277. }
  3278. cp->tx_cons_ptr =
  3279. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3280. }
  3281. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3282. struct client_init_ramrod_data *data)
  3283. {
  3284. struct cnic_local *cp = dev->cnic_priv;
  3285. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
  3286. BCM_PAGE_SIZE);
  3287. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3288. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  3289. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3290. int i;
  3291. int port = CNIC_PORT(cp);
  3292. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3293. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3294. u32 val;
  3295. dma_addr_t ring_map = cp->l2_ring_map;
  3296. /* General data */
  3297. data->general.client_id = cli;
  3298. data->general.statistics_en_flg = 1;
  3299. data->general.statistics_counter_id = cli;
  3300. data->general.activate_flg = 1;
  3301. data->general.sp_client_id = cli;
  3302. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3303. dma_addr_t buf_map;
  3304. int n = (i % cp->l2_rx_ring_size) + 1;
  3305. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3306. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3307. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3308. }
  3309. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3310. rxbd->addr_hi = cpu_to_le32(val);
  3311. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3312. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3313. rxbd->addr_lo = cpu_to_le32(val);
  3314. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3315. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3316. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3317. rxcqe->addr_hi = cpu_to_le32(val);
  3318. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3319. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3320. rxcqe->addr_lo = cpu_to_le32(val);
  3321. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3322. /* Other ramrod params */
  3323. data->rx.client_qzone_id = cl_qzone_id;
  3324. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3325. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3326. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3327. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3328. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3329. data->rx.outer_vlan_removal_enable_flg = 1;
  3330. /* reset tstorm and ustorm per client statistics */
  3331. if (cli < MAX_STAT_COUNTER_ID) {
  3332. val = BAR_TSTRORM_INTMEM +
  3333. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3334. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3335. CNIC_WR(dev, val + i * 4, 0);
  3336. val = BAR_USTRORM_INTMEM +
  3337. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3338. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3339. CNIC_WR(dev, val + i * 4, 0);
  3340. }
  3341. cp->rx_cons_ptr =
  3342. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3343. }
  3344. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3345. {
  3346. struct cnic_local *cp = dev->cnic_priv;
  3347. u32 base, addr, val;
  3348. int port = CNIC_PORT(cp);
  3349. dev->max_iscsi_conn = 0;
  3350. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3351. if (base == 0)
  3352. return;
  3353. addr = BNX2X_SHMEM_ADDR(base,
  3354. dev_info.port_hw_config[port].iscsi_mac_upper);
  3355. val = CNIC_RD(dev, addr);
  3356. dev->mac_addr[0] = (u8) (val >> 8);
  3357. dev->mac_addr[1] = (u8) val;
  3358. addr = BNX2X_SHMEM_ADDR(base,
  3359. dev_info.port_hw_config[port].iscsi_mac_lower);
  3360. val = CNIC_RD(dev, addr);
  3361. dev->mac_addr[2] = (u8) (val >> 24);
  3362. dev->mac_addr[3] = (u8) (val >> 16);
  3363. dev->mac_addr[4] = (u8) (val >> 8);
  3364. dev->mac_addr[5] = (u8) val;
  3365. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3366. val = CNIC_RD(dev, addr);
  3367. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3368. u16 val16;
  3369. addr = BNX2X_SHMEM_ADDR(base,
  3370. drv_lic_key[port].max_iscsi_init_conn);
  3371. val16 = CNIC_RD16(dev, addr);
  3372. if (val16)
  3373. val16 ^= 0x1e1e;
  3374. dev->max_iscsi_conn = val16;
  3375. }
  3376. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3377. int func = CNIC_FUNC(cp);
  3378. u32 mf_cfg_addr;
  3379. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3380. addr = mf_cfg_addr +
  3381. offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
  3382. val = CNIC_RD(dev, addr);
  3383. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3384. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3385. addr = mf_cfg_addr +
  3386. offsetof(struct mf_cfg,
  3387. func_mf_config[func].config);
  3388. val = CNIC_RD(dev, addr);
  3389. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3390. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3391. dev->max_iscsi_conn = 0;
  3392. }
  3393. }
  3394. }
  3395. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3396. {
  3397. struct cnic_local *cp = dev->cnic_priv;
  3398. struct cnic_eth_dev *ethdev = cp->ethdev;
  3399. int func = CNIC_FUNC(cp), ret, i;
  3400. u32 pfid;
  3401. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3402. cp->pfid = func;
  3403. pfid = cp->pfid;
  3404. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3405. cp->iscsi_start_cid);
  3406. if (ret)
  3407. return -ENOMEM;
  3408. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3409. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3410. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3411. cp->kcq1.sw_prod_idx = 0;
  3412. cp->kcq1.hw_prod_idx_ptr =
  3413. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3414. cp->kcq1.status_idx_ptr =
  3415. &sb->sb.running_index[SM_RX_ID];
  3416. cnic_get_bnx2x_iscsi_info(dev);
  3417. /* Only 1 EQ */
  3418. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3419. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3420. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3421. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3422. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3423. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3424. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3425. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3426. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3427. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3428. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3429. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3430. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3431. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  3432. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3433. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3434. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  3435. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3436. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  3437. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3438. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  3439. HC_INDEX_ISCSI_EQ_CONS);
  3440. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3441. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3442. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  3443. cp->conn_buf_info.pgtbl[2 * i]);
  3444. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3445. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  3446. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3447. }
  3448. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3449. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  3450. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3451. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3452. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  3453. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3454. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3455. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  3456. cnic_setup_bnx2x_context(dev);
  3457. ret = cnic_init_bnx2x_irq(dev);
  3458. if (ret)
  3459. return ret;
  3460. return 0;
  3461. }
  3462. static void cnic_init_rings(struct cnic_dev *dev)
  3463. {
  3464. struct cnic_local *cp = dev->cnic_priv;
  3465. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3466. return;
  3467. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3468. cnic_init_bnx2_tx_ring(dev);
  3469. cnic_init_bnx2_rx_ring(dev);
  3470. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3471. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3472. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3473. u32 cl_qzone_id, type;
  3474. struct client_init_ramrod_data *data;
  3475. union l5cm_specific_data l5_data;
  3476. struct ustorm_eth_rx_producers rx_prods = {0};
  3477. u32 off, i;
  3478. rx_prods.bd_prod = 0;
  3479. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3480. barrier();
  3481. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3482. off = BAR_USTRORM_INTMEM +
  3483. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli);
  3484. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3485. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3486. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3487. data = cp->l2_buf;
  3488. memset(data, 0, sizeof(*data));
  3489. cnic_init_bnx2x_tx_ring(dev, data);
  3490. cnic_init_bnx2x_rx_ring(dev, data);
  3491. l5_data.phy_address.lo = cp->l2_buf_map & 0xffffffff;
  3492. l5_data.phy_address.hi = (u64) cp->l2_buf_map >> 32;
  3493. type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3494. & SPE_HDR_CONN_TYPE;
  3495. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3496. SPE_HDR_FUNCTION_ID);
  3497. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3498. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3499. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3500. i = 0;
  3501. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3502. ++i < 10)
  3503. msleep(1);
  3504. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3505. netdev_err(dev->netdev,
  3506. "iSCSI CLIENT_SETUP did not complete\n");
  3507. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3508. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3509. }
  3510. }
  3511. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3512. {
  3513. struct cnic_local *cp = dev->cnic_priv;
  3514. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3515. return;
  3516. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3517. cnic_shutdown_bnx2_rx_ring(dev);
  3518. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3519. struct cnic_local *cp = dev->cnic_priv;
  3520. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3521. union l5cm_specific_data l5_data;
  3522. int i;
  3523. u32 type;
  3524. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3525. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3526. l5_data.phy_address.lo = cli;
  3527. l5_data.phy_address.hi = 0;
  3528. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3529. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3530. i = 0;
  3531. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3532. ++i < 10)
  3533. msleep(1);
  3534. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3535. netdev_err(dev->netdev,
  3536. "iSCSI CLIENT_HALT did not complete\n");
  3537. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3538. memset(&l5_data, 0, sizeof(l5_data));
  3539. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3540. & SPE_HDR_CONN_TYPE;
  3541. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3542. SPE_HDR_FUNCTION_ID);
  3543. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  3544. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3545. msleep(10);
  3546. }
  3547. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3548. }
  3549. static int cnic_register_netdev(struct cnic_dev *dev)
  3550. {
  3551. struct cnic_local *cp = dev->cnic_priv;
  3552. struct cnic_eth_dev *ethdev = cp->ethdev;
  3553. int err;
  3554. if (!ethdev)
  3555. return -ENODEV;
  3556. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3557. return 0;
  3558. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3559. if (err)
  3560. netdev_err(dev->netdev, "register_cnic failed\n");
  3561. return err;
  3562. }
  3563. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3564. {
  3565. struct cnic_local *cp = dev->cnic_priv;
  3566. struct cnic_eth_dev *ethdev = cp->ethdev;
  3567. if (!ethdev)
  3568. return;
  3569. ethdev->drv_unregister_cnic(dev->netdev);
  3570. }
  3571. static int cnic_start_hw(struct cnic_dev *dev)
  3572. {
  3573. struct cnic_local *cp = dev->cnic_priv;
  3574. struct cnic_eth_dev *ethdev = cp->ethdev;
  3575. int err;
  3576. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3577. return -EALREADY;
  3578. dev->regview = ethdev->io_base;
  3579. cp->chip_id = ethdev->chip_id;
  3580. pci_dev_get(dev->pcidev);
  3581. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3582. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3583. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3584. err = cp->alloc_resc(dev);
  3585. if (err) {
  3586. netdev_err(dev->netdev, "allocate resource failure\n");
  3587. goto err1;
  3588. }
  3589. err = cp->start_hw(dev);
  3590. if (err)
  3591. goto err1;
  3592. err = cnic_cm_open(dev);
  3593. if (err)
  3594. goto err1;
  3595. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3596. cp->enable_int(dev);
  3597. return 0;
  3598. err1:
  3599. cp->free_resc(dev);
  3600. pci_dev_put(dev->pcidev);
  3601. return err;
  3602. }
  3603. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3604. {
  3605. cnic_disable_bnx2_int_sync(dev);
  3606. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3607. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3608. cnic_init_context(dev, KWQ_CID);
  3609. cnic_init_context(dev, KCQ_CID);
  3610. cnic_setup_5709_context(dev, 0);
  3611. cnic_free_irq(dev);
  3612. cnic_free_resc(dev);
  3613. }
  3614. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3615. {
  3616. struct cnic_local *cp = dev->cnic_priv;
  3617. cnic_free_irq(dev);
  3618. *cp->kcq1.hw_prod_idx_ptr = 0;
  3619. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3620. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  3621. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  3622. cnic_free_resc(dev);
  3623. }
  3624. static void cnic_stop_hw(struct cnic_dev *dev)
  3625. {
  3626. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3627. struct cnic_local *cp = dev->cnic_priv;
  3628. int i = 0;
  3629. /* Need to wait for the ring shutdown event to complete
  3630. * before clearing the CNIC_UP flag.
  3631. */
  3632. while (cp->uio_dev != -1 && i < 15) {
  3633. msleep(100);
  3634. i++;
  3635. }
  3636. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3637. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3638. synchronize_rcu();
  3639. cnic_cm_shutdown(dev);
  3640. cp->stop_hw(dev);
  3641. pci_dev_put(dev->pcidev);
  3642. }
  3643. }
  3644. static void cnic_free_dev(struct cnic_dev *dev)
  3645. {
  3646. int i = 0;
  3647. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3648. msleep(100);
  3649. i++;
  3650. }
  3651. if (atomic_read(&dev->ref_count) != 0)
  3652. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3653. netdev_info(dev->netdev, "Removed CNIC device\n");
  3654. dev_put(dev->netdev);
  3655. kfree(dev);
  3656. }
  3657. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3658. struct pci_dev *pdev)
  3659. {
  3660. struct cnic_dev *cdev;
  3661. struct cnic_local *cp;
  3662. int alloc_size;
  3663. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3664. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3665. if (cdev == NULL) {
  3666. netdev_err(dev, "allocate dev struct failure\n");
  3667. return NULL;
  3668. }
  3669. cdev->netdev = dev;
  3670. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3671. cdev->register_device = cnic_register_device;
  3672. cdev->unregister_device = cnic_unregister_device;
  3673. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3674. cp = cdev->cnic_priv;
  3675. cp->dev = cdev;
  3676. cp->uio_dev = -1;
  3677. cp->l2_single_buf_size = 0x400;
  3678. cp->l2_rx_ring_size = 3;
  3679. spin_lock_init(&cp->cnic_ulp_lock);
  3680. netdev_info(dev, "Added CNIC device\n");
  3681. return cdev;
  3682. }
  3683. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3684. {
  3685. struct pci_dev *pdev;
  3686. struct cnic_dev *cdev;
  3687. struct cnic_local *cp;
  3688. struct cnic_eth_dev *ethdev = NULL;
  3689. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3690. probe = symbol_get(bnx2_cnic_probe);
  3691. if (probe) {
  3692. ethdev = (*probe)(dev);
  3693. symbol_put(bnx2_cnic_probe);
  3694. }
  3695. if (!ethdev)
  3696. return NULL;
  3697. pdev = ethdev->pdev;
  3698. if (!pdev)
  3699. return NULL;
  3700. dev_hold(dev);
  3701. pci_dev_get(pdev);
  3702. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3703. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3704. u8 rev;
  3705. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3706. if (rev < 0x10) {
  3707. pci_dev_put(pdev);
  3708. goto cnic_err;
  3709. }
  3710. }
  3711. pci_dev_put(pdev);
  3712. cdev = cnic_alloc_dev(dev, pdev);
  3713. if (cdev == NULL)
  3714. goto cnic_err;
  3715. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3716. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3717. cp = cdev->cnic_priv;
  3718. cp->ethdev = ethdev;
  3719. cdev->pcidev = pdev;
  3720. cp->cnic_ops = &cnic_bnx2_ops;
  3721. cp->start_hw = cnic_start_bnx2_hw;
  3722. cp->stop_hw = cnic_stop_bnx2_hw;
  3723. cp->setup_pgtbl = cnic_setup_page_tbl;
  3724. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3725. cp->free_resc = cnic_free_resc;
  3726. cp->start_cm = cnic_cm_init_bnx2_hw;
  3727. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3728. cp->enable_int = cnic_enable_bnx2_int;
  3729. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3730. cp->close_conn = cnic_close_bnx2_conn;
  3731. cp->next_idx = cnic_bnx2_next_idx;
  3732. cp->hw_idx = cnic_bnx2_hw_idx;
  3733. return cdev;
  3734. cnic_err:
  3735. dev_put(dev);
  3736. return NULL;
  3737. }
  3738. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3739. {
  3740. struct pci_dev *pdev;
  3741. struct cnic_dev *cdev;
  3742. struct cnic_local *cp;
  3743. struct cnic_eth_dev *ethdev = NULL;
  3744. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3745. probe = symbol_get(bnx2x_cnic_probe);
  3746. if (probe) {
  3747. ethdev = (*probe)(dev);
  3748. symbol_put(bnx2x_cnic_probe);
  3749. }
  3750. if (!ethdev)
  3751. return NULL;
  3752. pdev = ethdev->pdev;
  3753. if (!pdev)
  3754. return NULL;
  3755. dev_hold(dev);
  3756. cdev = cnic_alloc_dev(dev, pdev);
  3757. if (cdev == NULL) {
  3758. dev_put(dev);
  3759. return NULL;
  3760. }
  3761. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3762. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3763. cp = cdev->cnic_priv;
  3764. cp->ethdev = ethdev;
  3765. cdev->pcidev = pdev;
  3766. cp->cnic_ops = &cnic_bnx2x_ops;
  3767. cp->start_hw = cnic_start_bnx2x_hw;
  3768. cp->stop_hw = cnic_stop_bnx2x_hw;
  3769. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3770. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3771. cp->free_resc = cnic_free_resc;
  3772. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3773. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3774. cp->enable_int = cnic_enable_bnx2x_int;
  3775. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3776. cp->ack_int = cnic_ack_bnx2x_msix;
  3777. cp->close_conn = cnic_close_bnx2x_conn;
  3778. cp->next_idx = cnic_bnx2x_next_idx;
  3779. cp->hw_idx = cnic_bnx2x_hw_idx;
  3780. return cdev;
  3781. }
  3782. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3783. {
  3784. struct ethtool_drvinfo drvinfo;
  3785. struct cnic_dev *cdev = NULL;
  3786. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3787. memset(&drvinfo, 0, sizeof(drvinfo));
  3788. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3789. if (!strcmp(drvinfo.driver, "bnx2"))
  3790. cdev = init_bnx2_cnic(dev);
  3791. if (!strcmp(drvinfo.driver, "bnx2x"))
  3792. cdev = init_bnx2x_cnic(dev);
  3793. if (cdev) {
  3794. write_lock(&cnic_dev_lock);
  3795. list_add(&cdev->list, &cnic_dev_list);
  3796. write_unlock(&cnic_dev_lock);
  3797. }
  3798. }
  3799. return cdev;
  3800. }
  3801. /**
  3802. * netdev event handler
  3803. */
  3804. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3805. void *ptr)
  3806. {
  3807. struct net_device *netdev = ptr;
  3808. struct cnic_dev *dev;
  3809. int if_type;
  3810. int new_dev = 0;
  3811. dev = cnic_from_netdev(netdev);
  3812. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3813. /* Check for the hot-plug device */
  3814. dev = is_cnic_dev(netdev);
  3815. if (dev) {
  3816. new_dev = 1;
  3817. cnic_hold(dev);
  3818. }
  3819. }
  3820. if (dev) {
  3821. struct cnic_local *cp = dev->cnic_priv;
  3822. if (new_dev)
  3823. cnic_ulp_init(dev);
  3824. else if (event == NETDEV_UNREGISTER)
  3825. cnic_ulp_exit(dev);
  3826. if (event == NETDEV_UP) {
  3827. if (cnic_register_netdev(dev) != 0) {
  3828. cnic_put(dev);
  3829. goto done;
  3830. }
  3831. if (!cnic_start_hw(dev))
  3832. cnic_ulp_start(dev);
  3833. }
  3834. rcu_read_lock();
  3835. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3836. struct cnic_ulp_ops *ulp_ops;
  3837. void *ctx;
  3838. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3839. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3840. continue;
  3841. ctx = cp->ulp_handle[if_type];
  3842. ulp_ops->indicate_netevent(ctx, event);
  3843. }
  3844. rcu_read_unlock();
  3845. if (event == NETDEV_GOING_DOWN) {
  3846. cnic_ulp_stop(dev);
  3847. cnic_stop_hw(dev);
  3848. cnic_unregister_netdev(dev);
  3849. } else if (event == NETDEV_UNREGISTER) {
  3850. write_lock(&cnic_dev_lock);
  3851. list_del_init(&dev->list);
  3852. write_unlock(&cnic_dev_lock);
  3853. cnic_put(dev);
  3854. cnic_free_dev(dev);
  3855. goto done;
  3856. }
  3857. cnic_put(dev);
  3858. }
  3859. done:
  3860. return NOTIFY_DONE;
  3861. }
  3862. static struct notifier_block cnic_netdev_notifier = {
  3863. .notifier_call = cnic_netdev_event
  3864. };
  3865. static void cnic_release(void)
  3866. {
  3867. struct cnic_dev *dev;
  3868. while (!list_empty(&cnic_dev_list)) {
  3869. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3870. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3871. cnic_ulp_stop(dev);
  3872. cnic_stop_hw(dev);
  3873. }
  3874. cnic_ulp_exit(dev);
  3875. cnic_unregister_netdev(dev);
  3876. list_del_init(&dev->list);
  3877. cnic_free_dev(dev);
  3878. }
  3879. }
  3880. static int __init cnic_init(void)
  3881. {
  3882. int rc = 0;
  3883. pr_info("%s", version);
  3884. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3885. if (rc) {
  3886. cnic_release();
  3887. return rc;
  3888. }
  3889. return 0;
  3890. }
  3891. static void __exit cnic_exit(void)
  3892. {
  3893. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3894. cnic_release();
  3895. }
  3896. module_init(cnic_init);
  3897. module_exit(cnic_exit);