core.c 12 KB

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  1. /*
  2. * core.c - ChipIdea USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: ChipIdea USB IP core family device controller
  14. *
  15. * This driver is composed of several blocks:
  16. * - HW: hardware interface
  17. * - DBG: debug facilities (optional)
  18. * - UTIL: utilities
  19. * - ISR: interrupts handling
  20. * - ENDPT: endpoint operations (Gadget API)
  21. * - GADGET: gadget operations (Gadget API)
  22. * - BUS: bus glue code, bus abstraction layer
  23. *
  24. * Compile Options
  25. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  26. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  27. * if defined mass storage compliance succeeds but with warnings
  28. * => case 4: Hi > Dn
  29. * => case 5: Hi > Di
  30. * => case 8: Hi <> Do
  31. * if undefined usbtest 13 fails
  32. * - TRACE: enable function tracing (depends on DEBUG)
  33. *
  34. * Main Features
  35. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  36. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  37. * - Normal & LPM support
  38. *
  39. * USBTEST Report
  40. * - OK: 0-12, 13 (STALL_IN defined) & 14
  41. * - Not Supported: 15 & 16 (ISO)
  42. *
  43. * TODO List
  44. * - OTG
  45. * - Isochronous & Interrupt Traffic
  46. * - Handle requests which spawns into several TDs
  47. * - GET_STATUS(device) - always reports 0
  48. * - Gadget API (majority of optional features)
  49. * - Suspend & Remote Wakeup
  50. */
  51. #include <linux/delay.h>
  52. #include <linux/device.h>
  53. #include <linux/dmapool.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/init.h>
  56. #include <linux/platform_device.h>
  57. #include <linux/module.h>
  58. #include <linux/idr.h>
  59. #include <linux/interrupt.h>
  60. #include <linux/io.h>
  61. #include <linux/irq.h>
  62. #include <linux/kernel.h>
  63. #include <linux/slab.h>
  64. #include <linux/pm_runtime.h>
  65. #include <linux/usb/ch9.h>
  66. #include <linux/usb/gadget.h>
  67. #include <linux/usb/otg.h>
  68. #include <linux/usb/chipidea.h>
  69. #include "ci.h"
  70. #include "udc.h"
  71. #include "bits.h"
  72. #include "host.h"
  73. #include "debug.h"
  74. /* Controller register map */
  75. static uintptr_t ci_regs_nolpm[] = {
  76. [CAP_CAPLENGTH] = 0x000UL,
  77. [CAP_HCCPARAMS] = 0x008UL,
  78. [CAP_DCCPARAMS] = 0x024UL,
  79. [CAP_TESTMODE] = 0x038UL,
  80. [OP_USBCMD] = 0x000UL,
  81. [OP_USBSTS] = 0x004UL,
  82. [OP_USBINTR] = 0x008UL,
  83. [OP_DEVICEADDR] = 0x014UL,
  84. [OP_ENDPTLISTADDR] = 0x018UL,
  85. [OP_PORTSC] = 0x044UL,
  86. [OP_DEVLC] = 0x084UL,
  87. [OP_OTGSC] = 0x064UL,
  88. [OP_USBMODE] = 0x068UL,
  89. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  90. [OP_ENDPTPRIME] = 0x070UL,
  91. [OP_ENDPTFLUSH] = 0x074UL,
  92. [OP_ENDPTSTAT] = 0x078UL,
  93. [OP_ENDPTCOMPLETE] = 0x07CUL,
  94. [OP_ENDPTCTRL] = 0x080UL,
  95. };
  96. static uintptr_t ci_regs_lpm[] = {
  97. [CAP_CAPLENGTH] = 0x000UL,
  98. [CAP_HCCPARAMS] = 0x008UL,
  99. [CAP_DCCPARAMS] = 0x024UL,
  100. [CAP_TESTMODE] = 0x0FCUL,
  101. [OP_USBCMD] = 0x000UL,
  102. [OP_USBSTS] = 0x004UL,
  103. [OP_USBINTR] = 0x008UL,
  104. [OP_DEVICEADDR] = 0x014UL,
  105. [OP_ENDPTLISTADDR] = 0x018UL,
  106. [OP_PORTSC] = 0x044UL,
  107. [OP_DEVLC] = 0x084UL,
  108. [OP_OTGSC] = 0x0C4UL,
  109. [OP_USBMODE] = 0x0C8UL,
  110. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  111. [OP_ENDPTPRIME] = 0x0DCUL,
  112. [OP_ENDPTFLUSH] = 0x0E0UL,
  113. [OP_ENDPTSTAT] = 0x0E4UL,
  114. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  115. [OP_ENDPTCTRL] = 0x0ECUL,
  116. };
  117. static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
  118. {
  119. int i;
  120. kfree(ci->hw_bank.regmap);
  121. ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  122. GFP_KERNEL);
  123. if (!ci->hw_bank.regmap)
  124. return -ENOMEM;
  125. for (i = 0; i < OP_ENDPTCTRL; i++)
  126. ci->hw_bank.regmap[i] =
  127. (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
  128. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  129. for (; i <= OP_LAST; i++)
  130. ci->hw_bank.regmap[i] = ci->hw_bank.op +
  131. 4 * (i - OP_ENDPTCTRL) +
  132. (is_lpm
  133. ? ci_regs_lpm[OP_ENDPTCTRL]
  134. : ci_regs_nolpm[OP_ENDPTCTRL]);
  135. return 0;
  136. }
  137. /**
  138. * hw_port_test_set: writes port test mode (execute without interruption)
  139. * @mode: new value
  140. *
  141. * This function returns an error code
  142. */
  143. int hw_port_test_set(struct ci13xxx *ci, u8 mode)
  144. {
  145. const u8 TEST_MODE_MAX = 7;
  146. if (mode > TEST_MODE_MAX)
  147. return -EINVAL;
  148. hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  149. return 0;
  150. }
  151. /**
  152. * hw_port_test_get: reads port test mode value
  153. *
  154. * This function returns port test mode value
  155. */
  156. u8 hw_port_test_get(struct ci13xxx *ci)
  157. {
  158. return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  159. }
  160. static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
  161. {
  162. u32 reg;
  163. /* bank is a module variable */
  164. ci->hw_bank.abs = base;
  165. ci->hw_bank.cap = ci->hw_bank.abs;
  166. ci->hw_bank.cap += ci->platdata->capoffset;
  167. ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);
  168. hw_alloc_regmap(ci, false);
  169. reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  170. ffs_nr(HCCPARAMS_LEN);
  171. ci->hw_bank.lpm = reg;
  172. hw_alloc_regmap(ci, !!reg);
  173. ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
  174. ci->hw_bank.size += OP_LAST;
  175. ci->hw_bank.size /= sizeof(u32);
  176. reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  177. ffs_nr(DCCPARAMS_DEN);
  178. ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  179. if (ci->hw_ep_max > ENDPT_MAX)
  180. return -ENODEV;
  181. dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
  182. ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
  183. /* setup lock mode ? */
  184. /* ENDPTSETUPSTAT is '0' by default */
  185. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  186. return 0;
  187. }
  188. /**
  189. * hw_device_reset: resets chip (execute without interruption)
  190. * @ci: the controller
  191. *
  192. * This function returns an error code
  193. */
  194. int hw_device_reset(struct ci13xxx *ci, u32 mode)
  195. {
  196. /* should flush & stop before reset */
  197. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  198. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  199. hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  200. while (hw_read(ci, OP_USBCMD, USBCMD_RST))
  201. udelay(10); /* not RTOS friendly */
  202. if (ci->platdata->notify_event)
  203. ci->platdata->notify_event(ci,
  204. CI13XXX_CONTROLLER_RESET_EVENT);
  205. if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING)
  206. hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
  207. /* USBMODE should be configured step by step */
  208. hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  209. hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
  210. /* HW >= 2.3 */
  211. hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  212. if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
  213. pr_err("cannot enter in %s mode", ci_role(ci)->name);
  214. pr_err("lpm = %i", ci->hw_bank.lpm);
  215. return -ENODEV;
  216. }
  217. return 0;
  218. }
  219. /**
  220. * ci_otg_role - pick role based on ID pin state
  221. * @ci: the controller
  222. */
  223. static enum ci_role ci_otg_role(struct ci13xxx *ci)
  224. {
  225. u32 sts = hw_read(ci, OP_OTGSC, ~0);
  226. enum ci_role role = sts & OTGSC_ID
  227. ? CI_ROLE_GADGET
  228. : CI_ROLE_HOST;
  229. return role;
  230. }
  231. /**
  232. * ci_role_work - perform role changing based on ID pin
  233. * @work: work struct
  234. */
  235. static void ci_role_work(struct work_struct *work)
  236. {
  237. struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
  238. enum ci_role role = ci_otg_role(ci);
  239. hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
  240. if (role != ci->role) {
  241. dev_dbg(ci->dev, "switching from %s to %s\n",
  242. ci_role(ci)->name, ci->roles[role]->name);
  243. ci_role_stop(ci);
  244. ci_role_start(ci, role);
  245. }
  246. }
  247. static ssize_t show_role(struct device *dev, struct device_attribute *attr,
  248. char *buf)
  249. {
  250. struct ci13xxx *ci = dev_get_drvdata(dev);
  251. return sprintf(buf, "%s\n", ci_role(ci)->name);
  252. }
  253. static ssize_t store_role(struct device *dev, struct device_attribute *attr,
  254. const char *buf, size_t count)
  255. {
  256. struct ci13xxx *ci = dev_get_drvdata(dev);
  257. enum ci_role role;
  258. int ret;
  259. for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
  260. if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
  261. break;
  262. if (role == CI_ROLE_END || role == ci->role)
  263. return -EINVAL;
  264. ci_role_stop(ci);
  265. ret = ci_role_start(ci, role);
  266. if (ret)
  267. return ret;
  268. return count;
  269. }
  270. static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role);
  271. static irqreturn_t ci_irq(int irq, void *data)
  272. {
  273. struct ci13xxx *ci = data;
  274. irqreturn_t ret = IRQ_NONE;
  275. if (ci->is_otg) {
  276. u32 sts = hw_read(ci, OP_OTGSC, ~0);
  277. if (sts & OTGSC_IDIS) {
  278. queue_work(ci->wq, &ci->work);
  279. ret = IRQ_HANDLED;
  280. }
  281. }
  282. return ci->role == CI_ROLE_END ? ret : ci_role(ci)->irq(ci);
  283. }
  284. static DEFINE_IDA(ci_ida);
  285. struct platform_device *ci13xxx_add_device(struct device *dev,
  286. struct resource *res, int nres,
  287. struct ci13xxx_platform_data *platdata)
  288. {
  289. struct platform_device *pdev;
  290. int id, ret;
  291. id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
  292. if (id < 0)
  293. return ERR_PTR(id);
  294. pdev = platform_device_alloc("ci_hdrc", id);
  295. if (!pdev) {
  296. ret = -ENOMEM;
  297. goto put_id;
  298. }
  299. pdev->dev.parent = dev;
  300. pdev->dev.dma_mask = dev->dma_mask;
  301. pdev->dev.dma_parms = dev->dma_parms;
  302. dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
  303. ret = platform_device_add_resources(pdev, res, nres);
  304. if (ret)
  305. goto err;
  306. ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
  307. if (ret)
  308. goto err;
  309. ret = platform_device_add(pdev);
  310. if (ret)
  311. goto err;
  312. return pdev;
  313. err:
  314. platform_device_put(pdev);
  315. put_id:
  316. ida_simple_remove(&ci_ida, id);
  317. return ERR_PTR(ret);
  318. }
  319. EXPORT_SYMBOL_GPL(ci13xxx_add_device);
  320. void ci13xxx_remove_device(struct platform_device *pdev)
  321. {
  322. platform_device_unregister(pdev);
  323. ida_simple_remove(&ci_ida, pdev->id);
  324. }
  325. EXPORT_SYMBOL_GPL(ci13xxx_remove_device);
  326. static int __devinit ci_hdrc_probe(struct platform_device *pdev)
  327. {
  328. struct device *dev = &pdev->dev;
  329. struct ci13xxx *ci;
  330. struct resource *res;
  331. void __iomem *base;
  332. int ret;
  333. if (!dev->platform_data) {
  334. dev_err(dev, "platform data missing\n");
  335. return -ENODEV;
  336. }
  337. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  338. if (!res) {
  339. dev_err(dev, "missing resource\n");
  340. return -ENODEV;
  341. }
  342. base = devm_request_and_ioremap(dev, res);
  343. if (!res) {
  344. dev_err(dev, "can't request and ioremap resource\n");
  345. return -ENOMEM;
  346. }
  347. ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
  348. if (!ci) {
  349. dev_err(dev, "can't allocate device\n");
  350. return -ENOMEM;
  351. }
  352. ci->dev = dev;
  353. ci->platdata = dev->platform_data;
  354. if (ci->platdata->phy)
  355. ci->transceiver = ci->platdata->phy;
  356. else
  357. ci->global_phy = true;
  358. ret = hw_device_init(ci, base);
  359. if (ret < 0) {
  360. dev_err(dev, "can't initialize hardware\n");
  361. return -ENODEV;
  362. }
  363. ci->hw_bank.phys = res->start;
  364. ci->irq = platform_get_irq(pdev, 0);
  365. if (ci->irq < 0) {
  366. dev_err(dev, "missing IRQ\n");
  367. return -ENODEV;
  368. }
  369. INIT_WORK(&ci->work, ci_role_work);
  370. ci->wq = create_singlethread_workqueue("ci_otg");
  371. if (!ci->wq) {
  372. dev_err(dev, "can't create workqueue\n");
  373. return -ENODEV;
  374. }
  375. /* initialize role(s) before the interrupt is requested */
  376. ret = ci_hdrc_host_init(ci);
  377. if (ret)
  378. dev_info(dev, "doesn't support host\n");
  379. ret = ci_hdrc_gadget_init(ci);
  380. if (ret)
  381. dev_info(dev, "doesn't support gadget\n");
  382. if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
  383. dev_err(dev, "no supported roles\n");
  384. ret = -ENODEV;
  385. goto rm_wq;
  386. }
  387. if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
  388. ci->is_otg = true;
  389. ci->role = ci_otg_role(ci);
  390. } else {
  391. ci->role = ci->roles[CI_ROLE_HOST]
  392. ? CI_ROLE_HOST
  393. : CI_ROLE_GADGET;
  394. }
  395. ret = ci_role_start(ci, ci->role);
  396. if (ret) {
  397. dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
  398. ret = -ENODEV;
  399. goto rm_wq;
  400. }
  401. platform_set_drvdata(pdev, ci);
  402. ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
  403. ci);
  404. if (ret)
  405. goto stop;
  406. ret = device_create_file(dev, &dev_attr_role);
  407. if (ret)
  408. goto rm_attr;
  409. if (ci->is_otg)
  410. hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
  411. return ret;
  412. rm_attr:
  413. device_remove_file(dev, &dev_attr_role);
  414. stop:
  415. ci_role_stop(ci);
  416. rm_wq:
  417. flush_workqueue(ci->wq);
  418. destroy_workqueue(ci->wq);
  419. return ret;
  420. }
  421. static int __devexit ci_hdrc_remove(struct platform_device *pdev)
  422. {
  423. struct ci13xxx *ci = platform_get_drvdata(pdev);
  424. flush_workqueue(ci->wq);
  425. destroy_workqueue(ci->wq);
  426. device_remove_file(ci->dev, &dev_attr_role);
  427. free_irq(ci->irq, ci);
  428. ci_role_stop(ci);
  429. return 0;
  430. }
  431. static struct platform_driver ci_hdrc_driver = {
  432. .probe = ci_hdrc_probe,
  433. .remove = __devexit_p(ci_hdrc_remove),
  434. .driver = {
  435. .name = "ci_hdrc",
  436. },
  437. };
  438. module_platform_driver(ci_hdrc_driver);
  439. MODULE_ALIAS("platform:ci_hdrc");
  440. MODULE_ALIAS("platform:ci13xxx");
  441. MODULE_LICENSE("GPL v2");
  442. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  443. MODULE_DESCRIPTION("ChipIdea HDRC Driver");