ci.h 7.5 KB

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  1. /*
  2. * ci.h - common structures, functions, and macros of the ChipIdea driver
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  13. #define __DRIVERS_USB_CHIPIDEA_CI_H
  14. #include <linux/list.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/usb.h>
  17. #include <linux/usb/gadget.h>
  18. /******************************************************************************
  19. * DEFINE
  20. *****************************************************************************/
  21. #define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
  22. #define ENDPT_MAX 32
  23. /******************************************************************************
  24. * STRUCTURES
  25. *****************************************************************************/
  26. /**
  27. * struct ci13xxx_ep - endpoint representation
  28. * @ep: endpoint structure for gadget drivers
  29. * @dir: endpoint direction (TX/RX)
  30. * @num: endpoint number
  31. * @type: endpoint type
  32. * @name: string description of the endpoint
  33. * @qh: queue head for this endpoint
  34. * @wedge: is the endpoint wedged
  35. * @ci: pointer to the controller
  36. * @lock: pointer to controller's spinlock
  37. * @td_pool: pointer to controller's TD pool
  38. */
  39. struct ci13xxx_ep {
  40. struct usb_ep ep;
  41. u8 dir;
  42. u8 num;
  43. u8 type;
  44. char name[16];
  45. struct {
  46. struct list_head queue;
  47. struct ci13xxx_qh *ptr;
  48. dma_addr_t dma;
  49. } qh;
  50. int wedge;
  51. /* global resources */
  52. struct ci13xxx *ci;
  53. spinlock_t *lock;
  54. struct dma_pool *td_pool;
  55. };
  56. enum ci_role {
  57. CI_ROLE_HOST = 0,
  58. CI_ROLE_GADGET,
  59. CI_ROLE_END,
  60. };
  61. /**
  62. * struct ci_role_driver - host/gadget role driver
  63. * start: start this role
  64. * stop: stop this role
  65. * irq: irq handler for this role
  66. * name: role name string (host/gadget)
  67. */
  68. struct ci_role_driver {
  69. int (*start)(struct ci13xxx *);
  70. void (*stop)(struct ci13xxx *);
  71. irqreturn_t (*irq)(struct ci13xxx *);
  72. const char *name;
  73. };
  74. /**
  75. * struct hw_bank - hardware register mapping representation
  76. * @lpm: set if the device is LPM capable
  77. * @phys: physical address of the controller's registers
  78. * @abs: absolute address of the beginning of register window
  79. * @cap: capability registers
  80. * @op: operational registers
  81. * @size: size of the register window
  82. * @regmap: register lookup table
  83. */
  84. struct hw_bank {
  85. unsigned lpm;
  86. resource_size_t phys;
  87. void __iomem *abs;
  88. void __iomem *cap;
  89. void __iomem *op;
  90. size_t size;
  91. void __iomem **regmap;
  92. };
  93. /**
  94. * struct ci13xxx - chipidea device representation
  95. * @dev: pointer to parent device
  96. * @lock: access synchronization
  97. * @hw_bank: hardware register mapping
  98. * @irq: IRQ number
  99. * @roles: array of supported roles for this controller
  100. * @role: current role
  101. * @is_otg: if the device is otg-capable
  102. * @work: work for role changing
  103. * @wq: workqueue thread
  104. * @qh_pool: allocation pool for queue heads
  105. * @td_pool: allocation pool for transfer descriptors
  106. * @gadget: device side representation for peripheral controller
  107. * @driver: gadget driver
  108. * @hw_ep_max: total number of endpoints supported by hardware
  109. * @ci13xxx_ep: array of endpoints
  110. * @ep0_dir: ep0 direction
  111. * @ep0out: pointer to ep0 OUT endpoint
  112. * @ep0in: pointer to ep0 IN endpoint
  113. * @status: ep0 status request
  114. * @setaddr: if we should set the address on status completion
  115. * @address: usb address received from the host
  116. * @remote_wakeup: host-enabled remote wakeup
  117. * @suspended: suspended by host
  118. * @test_mode: the selected test mode
  119. * @platdata: platform specific information supplied by parent device
  120. * @vbus_active: is VBUS active
  121. * @transceiver: pointer to USB PHY, if any
  122. * @hcd: pointer to usb_hcd for ehci host driver
  123. */
  124. struct ci13xxx {
  125. struct device *dev;
  126. spinlock_t lock;
  127. struct hw_bank hw_bank;
  128. int irq;
  129. struct ci_role_driver *roles[CI_ROLE_END];
  130. enum ci_role role;
  131. bool is_otg;
  132. struct work_struct work;
  133. struct workqueue_struct *wq;
  134. struct dma_pool *qh_pool;
  135. struct dma_pool *td_pool;
  136. struct usb_gadget gadget;
  137. struct usb_gadget_driver *driver;
  138. unsigned hw_ep_max;
  139. struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX];
  140. u32 ep0_dir;
  141. struct ci13xxx_ep *ep0out, *ep0in;
  142. struct usb_request *status;
  143. bool setaddr;
  144. u8 address;
  145. u8 remote_wakeup;
  146. u8 suspended;
  147. u8 test_mode;
  148. struct ci13xxx_platform_data *platdata;
  149. int vbus_active;
  150. /* FIXME: some day, we'll not use global phy */
  151. bool global_phy;
  152. struct usb_phy *transceiver;
  153. struct usb_hcd *hcd;
  154. };
  155. static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
  156. {
  157. BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
  158. return ci->roles[ci->role];
  159. }
  160. static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
  161. {
  162. int ret;
  163. if (role >= CI_ROLE_END)
  164. return -EINVAL;
  165. if (!ci->roles[role])
  166. return -ENXIO;
  167. ret = ci->roles[role]->start(ci);
  168. if (!ret)
  169. ci->role = role;
  170. return ret;
  171. }
  172. static inline void ci_role_stop(struct ci13xxx *ci)
  173. {
  174. enum ci_role role = ci->role;
  175. if (role == CI_ROLE_END)
  176. return;
  177. ci->role = CI_ROLE_END;
  178. ci->roles[role]->stop(ci);
  179. }
  180. /******************************************************************************
  181. * REGISTERS
  182. *****************************************************************************/
  183. /* register size */
  184. #define REG_BITS (32)
  185. /* register indices */
  186. enum ci13xxx_regs {
  187. CAP_CAPLENGTH,
  188. CAP_HCCPARAMS,
  189. CAP_DCCPARAMS,
  190. CAP_TESTMODE,
  191. CAP_LAST = CAP_TESTMODE,
  192. OP_USBCMD,
  193. OP_USBSTS,
  194. OP_USBINTR,
  195. OP_DEVICEADDR,
  196. OP_ENDPTLISTADDR,
  197. OP_PORTSC,
  198. OP_DEVLC,
  199. OP_OTGSC,
  200. OP_USBMODE,
  201. OP_ENDPTSETUPSTAT,
  202. OP_ENDPTPRIME,
  203. OP_ENDPTFLUSH,
  204. OP_ENDPTSTAT,
  205. OP_ENDPTCOMPLETE,
  206. OP_ENDPTCTRL,
  207. /* endptctrl1..15 follow */
  208. OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
  209. };
  210. /**
  211. * ffs_nr: find first (least significant) bit set
  212. * @x: the word to search
  213. *
  214. * This function returns bit number (instead of position)
  215. */
  216. static inline int ffs_nr(u32 x)
  217. {
  218. int n = ffs(x);
  219. return n ? n-1 : 32;
  220. }
  221. /**
  222. * hw_read: reads from a hw register
  223. * @reg: register index
  224. * @mask: bitfield mask
  225. *
  226. * This function returns register contents
  227. */
  228. static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
  229. {
  230. return ioread32(ci->hw_bank.regmap[reg]) & mask;
  231. }
  232. /**
  233. * hw_write: writes to a hw register
  234. * @reg: register index
  235. * @mask: bitfield mask
  236. * @data: new value
  237. */
  238. static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
  239. u32 mask, u32 data)
  240. {
  241. if (~mask)
  242. data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
  243. | (data & mask);
  244. iowrite32(data, ci->hw_bank.regmap[reg]);
  245. }
  246. /**
  247. * hw_test_and_clear: tests & clears a hw register
  248. * @reg: register index
  249. * @mask: bitfield mask
  250. *
  251. * This function returns register contents
  252. */
  253. static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
  254. u32 mask)
  255. {
  256. u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
  257. iowrite32(val, ci->hw_bank.regmap[reg]);
  258. return val;
  259. }
  260. /**
  261. * hw_test_and_write: tests & writes a hw register
  262. * @reg: register index
  263. * @mask: bitfield mask
  264. * @data: new value
  265. *
  266. * This function returns register contents
  267. */
  268. static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
  269. u32 mask, u32 data)
  270. {
  271. u32 val = hw_read(ci, reg, ~0);
  272. hw_write(ci, reg, mask, data);
  273. return (val & mask) >> ffs_nr(mask);
  274. }
  275. int hw_device_reset(struct ci13xxx *ci, u32 mode);
  276. int hw_port_test_set(struct ci13xxx *ci, u8 mode);
  277. u8 hw_port_test_get(struct ci13xxx *ci);
  278. #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */