mpc8568mds.dts 8.4 KB

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  1. /*
  2. * MPC8568E MDS Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /*
  12. /memreserve/ 00000000 1000000;
  13. */
  14. / {
  15. model = "MPC8568EMDS";
  16. compatible = "MPC85xxMDS";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. linux,phandle = <100>;
  20. cpus {
  21. #cpus = <1>;
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. linux,phandle = <200>;
  25. PowerPC,8568@0 {
  26. device_type = "cpu";
  27. reg = <0>;
  28. d-cache-line-size = <20>; // 32 bytes
  29. i-cache-line-size = <20>; // 32 bytes
  30. d-cache-size = <8000>; // L1, 32K
  31. i-cache-size = <8000>; // L1, 32K
  32. timebase-frequency = <0>;
  33. bus-frequency = <0>;
  34. clock-frequency = <0>;
  35. 32-bit;
  36. linux,phandle = <201>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. linux,phandle = <300>;
  42. reg = <00000000 10000000>;
  43. };
  44. bcsr@f8000000 {
  45. device_type = "board-control";
  46. reg = <f8000000 8000>;
  47. };
  48. soc8568@e0000000 {
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. #interrupt-cells = <2>;
  52. device_type = "soc";
  53. ranges = <0 e0000000 00100000>;
  54. reg = <e0000000 00100000>;
  55. bus-frequency = <0>;
  56. i2c@3000 {
  57. device_type = "i2c";
  58. compatible = "fsl-i2c";
  59. reg = <3000 100>;
  60. interrupts = <1b 2>;
  61. interrupt-parent = <40000>;
  62. dfsrr;
  63. };
  64. i2c@3100 {
  65. device_type = "i2c";
  66. compatible = "fsl-i2c";
  67. reg = <3100 100>;
  68. interrupts = <1b 2>;
  69. interrupt-parent = <40000>;
  70. dfsrr;
  71. };
  72. mdio@24520 {
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. device_type = "mdio";
  76. compatible = "gianfar";
  77. reg = <24520 20>;
  78. linux,phandle = <24520>;
  79. ethernet-phy@0 {
  80. linux,phandle = <2452000>;
  81. interrupt-parent = <40000>;
  82. interrupts = <31 1>;
  83. reg = <0>;
  84. device_type = "ethernet-phy";
  85. };
  86. ethernet-phy@1 {
  87. linux,phandle = <2452001>;
  88. interrupt-parent = <40000>;
  89. interrupts = <32 1>;
  90. reg = <1>;
  91. device_type = "ethernet-phy";
  92. };
  93. ethernet-phy@2 {
  94. linux,phandle = <2452002>;
  95. interrupt-parent = <40000>;
  96. interrupts = <31 1>;
  97. reg = <2>;
  98. device_type = "ethernet-phy";
  99. };
  100. ethernet-phy@3 {
  101. linux,phandle = <2452003>;
  102. interrupt-parent = <40000>;
  103. interrupts = <32 1>;
  104. reg = <3>;
  105. device_type = "ethernet-phy";
  106. };
  107. };
  108. ethernet@24000 {
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. device_type = "network";
  112. model = "eTSEC";
  113. compatible = "gianfar";
  114. reg = <24000 1000>;
  115. mac-address = [ 00 00 00 00 00 00 ];
  116. interrupts = <d 2 e 2 12 2>;
  117. interrupt-parent = <40000>;
  118. phy-handle = <2452002>;
  119. };
  120. ethernet@25000 {
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. device_type = "network";
  124. model = "eTSEC";
  125. compatible = "gianfar";
  126. reg = <25000 1000>;
  127. mac-address = [ 00 00 00 00 00 00];
  128. interrupts = <13 2 14 2 18 2>;
  129. interrupt-parent = <40000>;
  130. phy-handle = <2452003>;
  131. };
  132. serial@4500 {
  133. device_type = "serial";
  134. compatible = "ns16550";
  135. reg = <4500 100>;
  136. clock-frequency = <0>;
  137. interrupts = <1a 2>;
  138. interrupt-parent = <40000>;
  139. };
  140. serial@4600 {
  141. device_type = "serial";
  142. compatible = "ns16550";
  143. reg = <4600 100>;
  144. clock-frequency = <0>;
  145. interrupts = <1a 2>;
  146. interrupt-parent = <40000>;
  147. };
  148. crypto@30000 {
  149. device_type = "crypto";
  150. model = "SEC2";
  151. compatible = "talitos";
  152. reg = <30000 f000>;
  153. interrupts = <1d 2>;
  154. interrupt-parent = <40000>;
  155. num-channels = <4>;
  156. channel-fifo-len = <18>;
  157. exec-units-mask = <000000fe>;
  158. descriptor-types-mask = <012b0ebf>;
  159. };
  160. pic@40000 {
  161. linux,phandle = <40000>;
  162. clock-frequency = <0>;
  163. interrupt-controller;
  164. #address-cells = <0>;
  165. #interrupt-cells = <2>;
  166. reg = <40000 40000>;
  167. built-in;
  168. compatible = "chrp,open-pic";
  169. device_type = "open-pic";
  170. big-endian;
  171. };
  172. par_io@e0100 {
  173. reg = <e0100 100>;
  174. device_type = "par_io";
  175. num-ports = <7>;
  176. ucc_pin@01 {
  177. linux,phandle = <e010001>;
  178. pio-map = <
  179. /* port pin dir open_drain assignment has_irq */
  180. 4 0a 1 0 2 0 /* TxD0 */
  181. 4 09 1 0 2 0 /* TxD1 */
  182. 4 08 1 0 2 0 /* TxD2 */
  183. 4 07 1 0 2 0 /* TxD3 */
  184. 4 17 1 0 2 0 /* TxD4 */
  185. 4 16 1 0 2 0 /* TxD5 */
  186. 4 15 1 0 2 0 /* TxD6 */
  187. 4 14 1 0 2 0 /* TxD7 */
  188. 4 0f 2 0 2 0 /* RxD0 */
  189. 4 0e 2 0 2 0 /* RxD1 */
  190. 4 0d 2 0 2 0 /* RxD2 */
  191. 4 0c 2 0 2 0 /* RxD3 */
  192. 4 1d 2 0 2 0 /* RxD4 */
  193. 4 1c 2 0 2 0 /* RxD5 */
  194. 4 1b 2 0 2 0 /* RxD6 */
  195. 4 1a 2 0 2 0 /* RxD7 */
  196. 4 0b 1 0 2 0 /* TX_EN */
  197. 4 18 1 0 2 0 /* TX_ER */
  198. 4 0f 2 0 2 0 /* RX_DV */
  199. 4 1e 2 0 2 0 /* RX_ER */
  200. 4 11 2 0 2 0 /* RX_CLK */
  201. 4 13 1 0 2 0 /* GTX_CLK */
  202. 1 1f 2 0 3 0>; /* GTX125 */
  203. };
  204. ucc_pin@02 {
  205. linux,phandle = <e010002>;
  206. pio-map = <
  207. /* port pin dir open_drain assignment has_irq */
  208. 5 0a 1 0 2 0 /* TxD0 */
  209. 5 09 1 0 2 0 /* TxD1 */
  210. 5 08 1 0 2 0 /* TxD2 */
  211. 5 07 1 0 2 0 /* TxD3 */
  212. 5 17 1 0 2 0 /* TxD4 */
  213. 5 16 1 0 2 0 /* TxD5 */
  214. 5 15 1 0 2 0 /* TxD6 */
  215. 5 14 1 0 2 0 /* TxD7 */
  216. 5 0f 2 0 2 0 /* RxD0 */
  217. 5 0e 2 0 2 0 /* RxD1 */
  218. 5 0d 2 0 2 0 /* RxD2 */
  219. 5 0c 2 0 2 0 /* RxD3 */
  220. 5 1d 2 0 2 0 /* RxD4 */
  221. 5 1c 2 0 2 0 /* RxD5 */
  222. 5 1b 2 0 2 0 /* RxD6 */
  223. 5 1a 2 0 2 0 /* RxD7 */
  224. 5 0b 1 0 2 0 /* TX_EN */
  225. 5 18 1 0 2 0 /* TX_ER */
  226. 5 10 2 0 2 0 /* RX_DV */
  227. 5 1e 2 0 2 0 /* RX_ER */
  228. 5 11 2 0 2 0 /* RX_CLK */
  229. 5 13 1 0 2 0 /* GTX_CLK */
  230. 1 1f 2 0 3 0 /* GTX125 */
  231. 4 06 3 0 2 0 /* MDIO */
  232. 4 05 1 0 2 0>; /* MDC */
  233. };
  234. };
  235. };
  236. qe@e0080000 {
  237. #address-cells = <1>;
  238. #size-cells = <1>;
  239. device_type = "qe";
  240. model = "QE";
  241. ranges = <0 e0080000 00040000>;
  242. reg = <e0080000 480>;
  243. brg-frequency = <0>;
  244. bus-frequency = <179A7B00>;
  245. muram@10000 {
  246. device_type = "muram";
  247. ranges = <0 00010000 0000c000>;
  248. data-only@0{
  249. reg = <0 c000>;
  250. };
  251. };
  252. spi@4c0 {
  253. device_type = "spi";
  254. compatible = "fsl_spi";
  255. reg = <4c0 40>;
  256. interrupts = <2>;
  257. interrupt-parent = <80>;
  258. mode = "cpu";
  259. };
  260. spi@500 {
  261. device_type = "spi";
  262. compatible = "fsl_spi";
  263. reg = <500 40>;
  264. interrupts = <1>;
  265. interrupt-parent = <80>;
  266. mode = "cpu";
  267. };
  268. ucc@2000 {
  269. device_type = "network";
  270. compatible = "ucc_geth";
  271. model = "UCC";
  272. device-id = <1>;
  273. reg = <2000 200>;
  274. interrupts = <20>;
  275. interrupt-parent = <80>;
  276. mac-address = [ 00 04 9f 00 23 23 ];
  277. rx-clock = <0>;
  278. tx-clock = <19>;
  279. phy-handle = <212000>;
  280. pio-handle = <e010001>;
  281. };
  282. ucc@3000 {
  283. device_type = "network";
  284. compatible = "ucc_geth";
  285. model = "UCC";
  286. device-id = <2>;
  287. reg = <3000 200>;
  288. interrupts = <21>;
  289. interrupt-parent = <80>;
  290. mac-address = [ 00 11 22 33 44 55 ];
  291. rx-clock = <0>;
  292. tx-clock = <14>;
  293. phy-handle = <212001>;
  294. pio-handle = <e010002>;
  295. };
  296. mdio@2120 {
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. reg = <2120 18>;
  300. device_type = "mdio";
  301. compatible = "ucc_geth_phy";
  302. /* These are the same PHYs as on
  303. * gianfar's MDIO bus */
  304. ethernet-phy@00 {
  305. linux,phandle = <212000>;
  306. interrupt-parent = <40000>;
  307. interrupts = <31 1>;
  308. reg = <0>;
  309. device_type = "ethernet-phy";
  310. interface = <6>; //ENET_1000_GMII
  311. };
  312. ethernet-phy@01 {
  313. linux,phandle = <212001>;
  314. interrupt-parent = <40000>;
  315. interrupts = <32 1>;
  316. reg = <1>;
  317. device_type = "ethernet-phy";
  318. interface = <6>;
  319. };
  320. ethernet-phy@02 {
  321. linux,phandle = <212002>;
  322. interrupt-parent = <40000>;
  323. interrupts = <31 1>;
  324. reg = <2>;
  325. device_type = "ethernet-phy";
  326. interface = <6>; //ENET_1000_GMII
  327. };
  328. ethernet-phy@03 {
  329. linux,phandle = <212003>;
  330. interrupt-parent = <40000>;
  331. interrupts = <32 1>;
  332. reg = <3>;
  333. device_type = "ethernet-phy";
  334. interface = <6>; //ENET_1000_GMII
  335. };
  336. };
  337. qeic@80 {
  338. linux,phandle = <80>;
  339. interrupt-controller;
  340. device_type = "qeic";
  341. #address-cells = <0>;
  342. #interrupt-cells = <1>;
  343. reg = <80 80>;
  344. built-in;
  345. big-endian;
  346. interrupts = <1e 2 1e 2>; //high:30 low:30
  347. interrupt-parent = <40000>;
  348. };
  349. };
  350. };