ste_dma40.c 96 KB

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  1. /*
  2. * Copyright (C) Ericsson AB 2007-2008
  3. * Copyright (C) ST-Ericsson SA 2008-2010
  4. * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
  5. * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
  6. * License terms: GNU General Public License (GPL) version 2
  7. */
  8. #include <linux/dma-mapping.h>
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/export.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/err.h>
  19. #include <linux/of.h>
  20. #include <linux/of_dma.h>
  21. #include <linux/amba/bus.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/platform_data/dma-ste-dma40.h>
  24. #include "dmaengine.h"
  25. #include "ste_dma40_ll.h"
  26. #define D40_NAME "dma40"
  27. #define D40_PHY_CHAN -1
  28. /* For masking out/in 2 bit channel positions */
  29. #define D40_CHAN_POS(chan) (2 * (chan / 2))
  30. #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
  31. /* Maximum iterations taken before giving up suspending a channel */
  32. #define D40_SUSPEND_MAX_IT 500
  33. /* Milliseconds */
  34. #define DMA40_AUTOSUSPEND_DELAY 100
  35. /* Hardware requirement on LCLA alignment */
  36. #define LCLA_ALIGNMENT 0x40000
  37. /* Max number of links per event group */
  38. #define D40_LCLA_LINK_PER_EVENT_GRP 128
  39. #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
  40. /* Max number of logical channels per physical channel */
  41. #define D40_MAX_LOG_CHAN_PER_PHY 32
  42. /* Attempts before giving up to trying to get pages that are aligned */
  43. #define MAX_LCLA_ALLOC_ATTEMPTS 256
  44. /* Bit markings for allocation map */
  45. #define D40_ALLOC_FREE BIT(31)
  46. #define D40_ALLOC_PHY BIT(30)
  47. #define D40_ALLOC_LOG_FREE 0
  48. #define D40_MEMCPY_MAX_CHANS 8
  49. /* Reserved event lines for memcpy only. */
  50. #define DB8500_DMA_MEMCPY_EV_0 51
  51. #define DB8500_DMA_MEMCPY_EV_1 56
  52. #define DB8500_DMA_MEMCPY_EV_2 57
  53. #define DB8500_DMA_MEMCPY_EV_3 58
  54. #define DB8500_DMA_MEMCPY_EV_4 59
  55. #define DB8500_DMA_MEMCPY_EV_5 60
  56. static int dma40_memcpy_channels[] = {
  57. DB8500_DMA_MEMCPY_EV_0,
  58. DB8500_DMA_MEMCPY_EV_1,
  59. DB8500_DMA_MEMCPY_EV_2,
  60. DB8500_DMA_MEMCPY_EV_3,
  61. DB8500_DMA_MEMCPY_EV_4,
  62. DB8500_DMA_MEMCPY_EV_5,
  63. };
  64. /* Default configuration for physcial memcpy */
  65. static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
  66. .mode = STEDMA40_MODE_PHYSICAL,
  67. .dir = DMA_MEM_TO_MEM,
  68. .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  69. .src_info.psize = STEDMA40_PSIZE_PHY_1,
  70. .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  71. .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  72. .dst_info.psize = STEDMA40_PSIZE_PHY_1,
  73. .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  74. };
  75. /* Default configuration for logical memcpy */
  76. static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  77. .mode = STEDMA40_MODE_LOGICAL,
  78. .dir = DMA_MEM_TO_MEM,
  79. .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  80. .src_info.psize = STEDMA40_PSIZE_LOG_1,
  81. .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  82. .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  83. .dst_info.psize = STEDMA40_PSIZE_LOG_1,
  84. .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  85. };
  86. /**
  87. * enum 40_command - The different commands and/or statuses.
  88. *
  89. * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
  90. * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
  91. * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
  92. * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
  93. */
  94. enum d40_command {
  95. D40_DMA_STOP = 0,
  96. D40_DMA_RUN = 1,
  97. D40_DMA_SUSPEND_REQ = 2,
  98. D40_DMA_SUSPENDED = 3
  99. };
  100. /*
  101. * enum d40_events - The different Event Enables for the event lines.
  102. *
  103. * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
  104. * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
  105. * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
  106. * @D40_ROUND_EVENTLINE: Status check for event line.
  107. */
  108. enum d40_events {
  109. D40_DEACTIVATE_EVENTLINE = 0,
  110. D40_ACTIVATE_EVENTLINE = 1,
  111. D40_SUSPEND_REQ_EVENTLINE = 2,
  112. D40_ROUND_EVENTLINE = 3
  113. };
  114. /*
  115. * These are the registers that has to be saved and later restored
  116. * when the DMA hw is powered off.
  117. * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
  118. */
  119. static u32 d40_backup_regs[] = {
  120. D40_DREG_LCPA,
  121. D40_DREG_LCLA,
  122. D40_DREG_PRMSE,
  123. D40_DREG_PRMSO,
  124. D40_DREG_PRMOE,
  125. D40_DREG_PRMOO,
  126. };
  127. #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
  128. /*
  129. * since 9540 and 8540 has the same HW revision
  130. * use v4a for 9540 or ealier
  131. * use v4b for 8540 or later
  132. * HW revision:
  133. * DB8500ed has revision 0
  134. * DB8500v1 has revision 2
  135. * DB8500v2 has revision 3
  136. * AP9540v1 has revision 4
  137. * DB8540v1 has revision 4
  138. * TODO: Check if all these registers have to be saved/restored on dma40 v4a
  139. */
  140. static u32 d40_backup_regs_v4a[] = {
  141. D40_DREG_PSEG1,
  142. D40_DREG_PSEG2,
  143. D40_DREG_PSEG3,
  144. D40_DREG_PSEG4,
  145. D40_DREG_PCEG1,
  146. D40_DREG_PCEG2,
  147. D40_DREG_PCEG3,
  148. D40_DREG_PCEG4,
  149. D40_DREG_RSEG1,
  150. D40_DREG_RSEG2,
  151. D40_DREG_RSEG3,
  152. D40_DREG_RSEG4,
  153. D40_DREG_RCEG1,
  154. D40_DREG_RCEG2,
  155. D40_DREG_RCEG3,
  156. D40_DREG_RCEG4,
  157. };
  158. #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
  159. static u32 d40_backup_regs_v4b[] = {
  160. D40_DREG_CPSEG1,
  161. D40_DREG_CPSEG2,
  162. D40_DREG_CPSEG3,
  163. D40_DREG_CPSEG4,
  164. D40_DREG_CPSEG5,
  165. D40_DREG_CPCEG1,
  166. D40_DREG_CPCEG2,
  167. D40_DREG_CPCEG3,
  168. D40_DREG_CPCEG4,
  169. D40_DREG_CPCEG5,
  170. D40_DREG_CRSEG1,
  171. D40_DREG_CRSEG2,
  172. D40_DREG_CRSEG3,
  173. D40_DREG_CRSEG4,
  174. D40_DREG_CRSEG5,
  175. D40_DREG_CRCEG1,
  176. D40_DREG_CRCEG2,
  177. D40_DREG_CRCEG3,
  178. D40_DREG_CRCEG4,
  179. D40_DREG_CRCEG5,
  180. };
  181. #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
  182. static u32 d40_backup_regs_chan[] = {
  183. D40_CHAN_REG_SSCFG,
  184. D40_CHAN_REG_SSELT,
  185. D40_CHAN_REG_SSPTR,
  186. D40_CHAN_REG_SSLNK,
  187. D40_CHAN_REG_SDCFG,
  188. D40_CHAN_REG_SDELT,
  189. D40_CHAN_REG_SDPTR,
  190. D40_CHAN_REG_SDLNK,
  191. };
  192. #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
  193. BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
  194. /**
  195. * struct d40_interrupt_lookup - lookup table for interrupt handler
  196. *
  197. * @src: Interrupt mask register.
  198. * @clr: Interrupt clear register.
  199. * @is_error: true if this is an error interrupt.
  200. * @offset: start delta in the lookup_log_chans in d40_base. If equals to
  201. * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
  202. */
  203. struct d40_interrupt_lookup {
  204. u32 src;
  205. u32 clr;
  206. bool is_error;
  207. int offset;
  208. };
  209. static struct d40_interrupt_lookup il_v4a[] = {
  210. {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
  211. {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
  212. {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
  213. {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
  214. {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
  215. {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
  216. {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
  217. {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
  218. {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
  219. {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
  220. };
  221. static struct d40_interrupt_lookup il_v4b[] = {
  222. {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
  223. {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
  224. {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
  225. {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
  226. {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
  227. {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
  228. {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
  229. {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
  230. {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
  231. {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
  232. {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
  233. {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
  234. };
  235. /**
  236. * struct d40_reg_val - simple lookup struct
  237. *
  238. * @reg: The register.
  239. * @val: The value that belongs to the register in reg.
  240. */
  241. struct d40_reg_val {
  242. unsigned int reg;
  243. unsigned int val;
  244. };
  245. static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
  246. /* Clock every part of the DMA block from start */
  247. { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
  248. /* Interrupts on all logical channels */
  249. { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
  250. { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
  251. { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
  252. { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
  253. { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
  254. { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
  255. { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
  256. { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
  257. { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
  258. { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
  259. { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
  260. { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
  261. };
  262. static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
  263. /* Clock every part of the DMA block from start */
  264. { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
  265. /* Interrupts on all logical channels */
  266. { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
  267. { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
  268. { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
  269. { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
  270. { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
  271. { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
  272. { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
  273. { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
  274. { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
  275. { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
  276. { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
  277. { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
  278. { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
  279. { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
  280. { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
  281. };
  282. /**
  283. * struct d40_lli_pool - Structure for keeping LLIs in memory
  284. *
  285. * @base: Pointer to memory area when the pre_alloc_lli's are not large
  286. * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
  287. * pre_alloc_lli is used.
  288. * @dma_addr: DMA address, if mapped
  289. * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
  290. * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
  291. * one buffer to one buffer.
  292. */
  293. struct d40_lli_pool {
  294. void *base;
  295. int size;
  296. dma_addr_t dma_addr;
  297. /* Space for dst and src, plus an extra for padding */
  298. u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
  299. };
  300. /**
  301. * struct d40_desc - A descriptor is one DMA job.
  302. *
  303. * @lli_phy: LLI settings for physical channel. Both src and dst=
  304. * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
  305. * lli_len equals one.
  306. * @lli_log: Same as above but for logical channels.
  307. * @lli_pool: The pool with two entries pre-allocated.
  308. * @lli_len: Number of llis of current descriptor.
  309. * @lli_current: Number of transferred llis.
  310. * @lcla_alloc: Number of LCLA entries allocated.
  311. * @txd: DMA engine struct. Used for among other things for communication
  312. * during a transfer.
  313. * @node: List entry.
  314. * @is_in_client_list: true if the client owns this descriptor.
  315. * @cyclic: true if this is a cyclic job
  316. *
  317. * This descriptor is used for both logical and physical transfers.
  318. */
  319. struct d40_desc {
  320. /* LLI physical */
  321. struct d40_phy_lli_bidir lli_phy;
  322. /* LLI logical */
  323. struct d40_log_lli_bidir lli_log;
  324. struct d40_lli_pool lli_pool;
  325. int lli_len;
  326. int lli_current;
  327. int lcla_alloc;
  328. struct dma_async_tx_descriptor txd;
  329. struct list_head node;
  330. bool is_in_client_list;
  331. bool cyclic;
  332. };
  333. /**
  334. * struct d40_lcla_pool - LCLA pool settings and data.
  335. *
  336. * @base: The virtual address of LCLA. 18 bit aligned.
  337. * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
  338. * This pointer is only there for clean-up on error.
  339. * @pages: The number of pages needed for all physical channels.
  340. * Only used later for clean-up on error
  341. * @lock: Lock to protect the content in this struct.
  342. * @alloc_map: big map over which LCLA entry is own by which job.
  343. */
  344. struct d40_lcla_pool {
  345. void *base;
  346. dma_addr_t dma_addr;
  347. void *base_unaligned;
  348. int pages;
  349. spinlock_t lock;
  350. struct d40_desc **alloc_map;
  351. };
  352. /**
  353. * struct d40_phy_res - struct for handling eventlines mapped to physical
  354. * channels.
  355. *
  356. * @lock: A lock protection this entity.
  357. * @reserved: True if used by secure world or otherwise.
  358. * @num: The physical channel number of this entity.
  359. * @allocated_src: Bit mapped to show which src event line's are mapped to
  360. * this physical channel. Can also be free or physically allocated.
  361. * @allocated_dst: Same as for src but is dst.
  362. * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
  363. * event line number.
  364. * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
  365. */
  366. struct d40_phy_res {
  367. spinlock_t lock;
  368. bool reserved;
  369. int num;
  370. u32 allocated_src;
  371. u32 allocated_dst;
  372. bool use_soft_lli;
  373. };
  374. struct d40_base;
  375. /**
  376. * struct d40_chan - Struct that describes a channel.
  377. *
  378. * @lock: A spinlock to protect this struct.
  379. * @log_num: The logical number, if any of this channel.
  380. * @pending_tx: The number of pending transfers. Used between interrupt handler
  381. * and tasklet.
  382. * @busy: Set to true when transfer is ongoing on this channel.
  383. * @phy_chan: Pointer to physical channel which this instance runs on. If this
  384. * point is NULL, then the channel is not allocated.
  385. * @chan: DMA engine handle.
  386. * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
  387. * transfer and call client callback.
  388. * @client: Cliented owned descriptor list.
  389. * @pending_queue: Submitted jobs, to be issued by issue_pending()
  390. * @active: Active descriptor.
  391. * @done: Completed jobs
  392. * @queue: Queued jobs.
  393. * @prepare_queue: Prepared jobs.
  394. * @dma_cfg: The client configuration of this dma channel.
  395. * @configured: whether the dma_cfg configuration is valid
  396. * @base: Pointer to the device instance struct.
  397. * @src_def_cfg: Default cfg register setting for src.
  398. * @dst_def_cfg: Default cfg register setting for dst.
  399. * @log_def: Default logical channel settings.
  400. * @lcpa: Pointer to dst and src lcpa settings.
  401. * @runtime_addr: runtime configured address.
  402. * @runtime_direction: runtime configured direction.
  403. *
  404. * This struct can either "be" a logical or a physical channel.
  405. */
  406. struct d40_chan {
  407. spinlock_t lock;
  408. int log_num;
  409. int pending_tx;
  410. bool busy;
  411. struct d40_phy_res *phy_chan;
  412. struct dma_chan chan;
  413. struct tasklet_struct tasklet;
  414. struct list_head client;
  415. struct list_head pending_queue;
  416. struct list_head active;
  417. struct list_head done;
  418. struct list_head queue;
  419. struct list_head prepare_queue;
  420. struct stedma40_chan_cfg dma_cfg;
  421. bool configured;
  422. struct d40_base *base;
  423. /* Default register configurations */
  424. u32 src_def_cfg;
  425. u32 dst_def_cfg;
  426. struct d40_def_lcsp log_def;
  427. struct d40_log_lli_full *lcpa;
  428. /* Runtime reconfiguration */
  429. dma_addr_t runtime_addr;
  430. enum dma_transfer_direction runtime_direction;
  431. };
  432. /**
  433. * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
  434. * controller
  435. *
  436. * @backup: the pointer to the registers address array for backup
  437. * @backup_size: the size of the registers address array for backup
  438. * @realtime_en: the realtime enable register
  439. * @realtime_clear: the realtime clear register
  440. * @high_prio_en: the high priority enable register
  441. * @high_prio_clear: the high priority clear register
  442. * @interrupt_en: the interrupt enable register
  443. * @interrupt_clear: the interrupt clear register
  444. * @il: the pointer to struct d40_interrupt_lookup
  445. * @il_size: the size of d40_interrupt_lookup array
  446. * @init_reg: the pointer to the struct d40_reg_val
  447. * @init_reg_size: the size of d40_reg_val array
  448. */
  449. struct d40_gen_dmac {
  450. u32 *backup;
  451. u32 backup_size;
  452. u32 realtime_en;
  453. u32 realtime_clear;
  454. u32 high_prio_en;
  455. u32 high_prio_clear;
  456. u32 interrupt_en;
  457. u32 interrupt_clear;
  458. struct d40_interrupt_lookup *il;
  459. u32 il_size;
  460. struct d40_reg_val *init_reg;
  461. u32 init_reg_size;
  462. };
  463. /**
  464. * struct d40_base - The big global struct, one for each probe'd instance.
  465. *
  466. * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
  467. * @execmd_lock: Lock for execute command usage since several channels share
  468. * the same physical register.
  469. * @dev: The device structure.
  470. * @virtbase: The virtual base address of the DMA's register.
  471. * @rev: silicon revision detected.
  472. * @clk: Pointer to the DMA clock structure.
  473. * @phy_start: Physical memory start of the DMA registers.
  474. * @phy_size: Size of the DMA register map.
  475. * @irq: The IRQ number.
  476. * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
  477. * transfers).
  478. * @num_phy_chans: The number of physical channels. Read from HW. This
  479. * is the number of available channels for this driver, not counting "Secure
  480. * mode" allocated physical channels.
  481. * @num_log_chans: The number of logical channels. Calculated from
  482. * num_phy_chans.
  483. * @dma_both: dma_device channels that can do both memcpy and slave transfers.
  484. * @dma_slave: dma_device channels that can do only do slave transfers.
  485. * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
  486. * @phy_chans: Room for all possible physical channels in system.
  487. * @log_chans: Room for all possible logical channels in system.
  488. * @lookup_log_chans: Used to map interrupt number to logical channel. Points
  489. * to log_chans entries.
  490. * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
  491. * to phy_chans entries.
  492. * @plat_data: Pointer to provided platform_data which is the driver
  493. * configuration.
  494. * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
  495. * @phy_res: Vector containing all physical channels.
  496. * @lcla_pool: lcla pool settings and data.
  497. * @lcpa_base: The virtual mapped address of LCPA.
  498. * @phy_lcpa: The physical address of the LCPA.
  499. * @lcpa_size: The size of the LCPA area.
  500. * @desc_slab: cache for descriptors.
  501. * @reg_val_backup: Here the values of some hardware registers are stored
  502. * before the DMA is powered off. They are restored when the power is back on.
  503. * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
  504. * later
  505. * @reg_val_backup_chan: Backup data for standard channel parameter registers.
  506. * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
  507. * @initialized: true if the dma has been initialized
  508. * @gen_dmac: the struct for generic registers values to represent u8500/8540
  509. * DMA controller
  510. */
  511. struct d40_base {
  512. spinlock_t interrupt_lock;
  513. spinlock_t execmd_lock;
  514. struct device *dev;
  515. void __iomem *virtbase;
  516. u8 rev:4;
  517. struct clk *clk;
  518. phys_addr_t phy_start;
  519. resource_size_t phy_size;
  520. int irq;
  521. int num_memcpy_chans;
  522. int num_phy_chans;
  523. int num_log_chans;
  524. struct device_dma_parameters dma_parms;
  525. struct dma_device dma_both;
  526. struct dma_device dma_slave;
  527. struct dma_device dma_memcpy;
  528. struct d40_chan *phy_chans;
  529. struct d40_chan *log_chans;
  530. struct d40_chan **lookup_log_chans;
  531. struct d40_chan **lookup_phy_chans;
  532. struct stedma40_platform_data *plat_data;
  533. struct regulator *lcpa_regulator;
  534. /* Physical half channels */
  535. struct d40_phy_res *phy_res;
  536. struct d40_lcla_pool lcla_pool;
  537. void *lcpa_base;
  538. dma_addr_t phy_lcpa;
  539. resource_size_t lcpa_size;
  540. struct kmem_cache *desc_slab;
  541. u32 reg_val_backup[BACKUP_REGS_SZ];
  542. u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
  543. u32 *reg_val_backup_chan;
  544. u16 gcc_pwr_off_mask;
  545. bool initialized;
  546. struct d40_gen_dmac gen_dmac;
  547. };
  548. static struct device *chan2dev(struct d40_chan *d40c)
  549. {
  550. return &d40c->chan.dev->device;
  551. }
  552. static bool chan_is_physical(struct d40_chan *chan)
  553. {
  554. return chan->log_num == D40_PHY_CHAN;
  555. }
  556. static bool chan_is_logical(struct d40_chan *chan)
  557. {
  558. return !chan_is_physical(chan);
  559. }
  560. static void __iomem *chan_base(struct d40_chan *chan)
  561. {
  562. return chan->base->virtbase + D40_DREG_PCBASE +
  563. chan->phy_chan->num * D40_DREG_PCDELTA;
  564. }
  565. #define d40_err(dev, format, arg...) \
  566. dev_err(dev, "[%s] " format, __func__, ## arg)
  567. #define chan_err(d40c, format, arg...) \
  568. d40_err(chan2dev(d40c), format, ## arg)
  569. static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
  570. int lli_len)
  571. {
  572. bool is_log = chan_is_logical(d40c);
  573. u32 align;
  574. void *base;
  575. if (is_log)
  576. align = sizeof(struct d40_log_lli);
  577. else
  578. align = sizeof(struct d40_phy_lli);
  579. if (lli_len == 1) {
  580. base = d40d->lli_pool.pre_alloc_lli;
  581. d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
  582. d40d->lli_pool.base = NULL;
  583. } else {
  584. d40d->lli_pool.size = lli_len * 2 * align;
  585. base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
  586. d40d->lli_pool.base = base;
  587. if (d40d->lli_pool.base == NULL)
  588. return -ENOMEM;
  589. }
  590. if (is_log) {
  591. d40d->lli_log.src = PTR_ALIGN(base, align);
  592. d40d->lli_log.dst = d40d->lli_log.src + lli_len;
  593. d40d->lli_pool.dma_addr = 0;
  594. } else {
  595. d40d->lli_phy.src = PTR_ALIGN(base, align);
  596. d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
  597. d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
  598. d40d->lli_phy.src,
  599. d40d->lli_pool.size,
  600. DMA_TO_DEVICE);
  601. if (dma_mapping_error(d40c->base->dev,
  602. d40d->lli_pool.dma_addr)) {
  603. kfree(d40d->lli_pool.base);
  604. d40d->lli_pool.base = NULL;
  605. d40d->lli_pool.dma_addr = 0;
  606. return -ENOMEM;
  607. }
  608. }
  609. return 0;
  610. }
  611. static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
  612. {
  613. if (d40d->lli_pool.dma_addr)
  614. dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
  615. d40d->lli_pool.size, DMA_TO_DEVICE);
  616. kfree(d40d->lli_pool.base);
  617. d40d->lli_pool.base = NULL;
  618. d40d->lli_pool.size = 0;
  619. d40d->lli_log.src = NULL;
  620. d40d->lli_log.dst = NULL;
  621. d40d->lli_phy.src = NULL;
  622. d40d->lli_phy.dst = NULL;
  623. }
  624. static int d40_lcla_alloc_one(struct d40_chan *d40c,
  625. struct d40_desc *d40d)
  626. {
  627. unsigned long flags;
  628. int i;
  629. int ret = -EINVAL;
  630. spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
  631. /*
  632. * Allocate both src and dst at the same time, therefore the half
  633. * start on 1 since 0 can't be used since zero is used as end marker.
  634. */
  635. for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
  636. int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
  637. if (!d40c->base->lcla_pool.alloc_map[idx]) {
  638. d40c->base->lcla_pool.alloc_map[idx] = d40d;
  639. d40d->lcla_alloc++;
  640. ret = i;
  641. break;
  642. }
  643. }
  644. spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
  645. return ret;
  646. }
  647. static int d40_lcla_free_all(struct d40_chan *d40c,
  648. struct d40_desc *d40d)
  649. {
  650. unsigned long flags;
  651. int i;
  652. int ret = -EINVAL;
  653. if (chan_is_physical(d40c))
  654. return 0;
  655. spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
  656. for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
  657. int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
  658. if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
  659. d40c->base->lcla_pool.alloc_map[idx] = NULL;
  660. d40d->lcla_alloc--;
  661. if (d40d->lcla_alloc == 0) {
  662. ret = 0;
  663. break;
  664. }
  665. }
  666. }
  667. spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
  668. return ret;
  669. }
  670. static void d40_desc_remove(struct d40_desc *d40d)
  671. {
  672. list_del(&d40d->node);
  673. }
  674. static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
  675. {
  676. struct d40_desc *desc = NULL;
  677. if (!list_empty(&d40c->client)) {
  678. struct d40_desc *d;
  679. struct d40_desc *_d;
  680. list_for_each_entry_safe(d, _d, &d40c->client, node) {
  681. if (async_tx_test_ack(&d->txd)) {
  682. d40_desc_remove(d);
  683. desc = d;
  684. memset(desc, 0, sizeof(*desc));
  685. break;
  686. }
  687. }
  688. }
  689. if (!desc)
  690. desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
  691. if (desc)
  692. INIT_LIST_HEAD(&desc->node);
  693. return desc;
  694. }
  695. static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
  696. {
  697. d40_pool_lli_free(d40c, d40d);
  698. d40_lcla_free_all(d40c, d40d);
  699. kmem_cache_free(d40c->base->desc_slab, d40d);
  700. }
  701. static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
  702. {
  703. list_add_tail(&desc->node, &d40c->active);
  704. }
  705. static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
  706. {
  707. struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
  708. struct d40_phy_lli *lli_src = desc->lli_phy.src;
  709. void __iomem *base = chan_base(chan);
  710. writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
  711. writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
  712. writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
  713. writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
  714. writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
  715. writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
  716. writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
  717. writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
  718. }
  719. static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
  720. {
  721. list_add_tail(&desc->node, &d40c->done);
  722. }
  723. static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
  724. {
  725. struct d40_lcla_pool *pool = &chan->base->lcla_pool;
  726. struct d40_log_lli_bidir *lli = &desc->lli_log;
  727. int lli_current = desc->lli_current;
  728. int lli_len = desc->lli_len;
  729. bool cyclic = desc->cyclic;
  730. int curr_lcla = -EINVAL;
  731. int first_lcla = 0;
  732. bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
  733. bool linkback;
  734. /*
  735. * We may have partially running cyclic transfers, in case we did't get
  736. * enough LCLA entries.
  737. */
  738. linkback = cyclic && lli_current == 0;
  739. /*
  740. * For linkback, we need one LCLA even with only one link, because we
  741. * can't link back to the one in LCPA space
  742. */
  743. if (linkback || (lli_len - lli_current > 1)) {
  744. /*
  745. * If the channel is expected to use only soft_lli don't
  746. * allocate a lcla. This is to avoid a HW issue that exists
  747. * in some controller during a peripheral to memory transfer
  748. * that uses linked lists.
  749. */
  750. if (!(chan->phy_chan->use_soft_lli &&
  751. chan->dma_cfg.dir == DMA_DEV_TO_MEM))
  752. curr_lcla = d40_lcla_alloc_one(chan, desc);
  753. first_lcla = curr_lcla;
  754. }
  755. /*
  756. * For linkback, we normally load the LCPA in the loop since we need to
  757. * link it to the second LCLA and not the first. However, if we
  758. * couldn't even get a first LCLA, then we have to run in LCPA and
  759. * reload manually.
  760. */
  761. if (!linkback || curr_lcla == -EINVAL) {
  762. unsigned int flags = 0;
  763. if (curr_lcla == -EINVAL)
  764. flags |= LLI_TERM_INT;
  765. d40_log_lli_lcpa_write(chan->lcpa,
  766. &lli->dst[lli_current],
  767. &lli->src[lli_current],
  768. curr_lcla,
  769. flags);
  770. lli_current++;
  771. }
  772. if (curr_lcla < 0)
  773. goto out;
  774. for (; lli_current < lli_len; lli_current++) {
  775. unsigned int lcla_offset = chan->phy_chan->num * 1024 +
  776. 8 * curr_lcla * 2;
  777. struct d40_log_lli *lcla = pool->base + lcla_offset;
  778. unsigned int flags = 0;
  779. int next_lcla;
  780. if (lli_current + 1 < lli_len)
  781. next_lcla = d40_lcla_alloc_one(chan, desc);
  782. else
  783. next_lcla = linkback ? first_lcla : -EINVAL;
  784. if (cyclic || next_lcla == -EINVAL)
  785. flags |= LLI_TERM_INT;
  786. if (linkback && curr_lcla == first_lcla) {
  787. /* First link goes in both LCPA and LCLA */
  788. d40_log_lli_lcpa_write(chan->lcpa,
  789. &lli->dst[lli_current],
  790. &lli->src[lli_current],
  791. next_lcla, flags);
  792. }
  793. /*
  794. * One unused LCLA in the cyclic case if the very first
  795. * next_lcla fails...
  796. */
  797. d40_log_lli_lcla_write(lcla,
  798. &lli->dst[lli_current],
  799. &lli->src[lli_current],
  800. next_lcla, flags);
  801. /*
  802. * Cache maintenance is not needed if lcla is
  803. * mapped in esram
  804. */
  805. if (!use_esram_lcla) {
  806. dma_sync_single_range_for_device(chan->base->dev,
  807. pool->dma_addr, lcla_offset,
  808. 2 * sizeof(struct d40_log_lli),
  809. DMA_TO_DEVICE);
  810. }
  811. curr_lcla = next_lcla;
  812. if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
  813. lli_current++;
  814. break;
  815. }
  816. }
  817. out:
  818. desc->lli_current = lli_current;
  819. }
  820. static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
  821. {
  822. if (chan_is_physical(d40c)) {
  823. d40_phy_lli_load(d40c, d40d);
  824. d40d->lli_current = d40d->lli_len;
  825. } else
  826. d40_log_lli_to_lcxa(d40c, d40d);
  827. }
  828. static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
  829. {
  830. struct d40_desc *d;
  831. if (list_empty(&d40c->active))
  832. return NULL;
  833. d = list_first_entry(&d40c->active,
  834. struct d40_desc,
  835. node);
  836. return d;
  837. }
  838. /* remove desc from current queue and add it to the pending_queue */
  839. static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
  840. {
  841. d40_desc_remove(desc);
  842. desc->is_in_client_list = false;
  843. list_add_tail(&desc->node, &d40c->pending_queue);
  844. }
  845. static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
  846. {
  847. struct d40_desc *d;
  848. if (list_empty(&d40c->pending_queue))
  849. return NULL;
  850. d = list_first_entry(&d40c->pending_queue,
  851. struct d40_desc,
  852. node);
  853. return d;
  854. }
  855. static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
  856. {
  857. struct d40_desc *d;
  858. if (list_empty(&d40c->queue))
  859. return NULL;
  860. d = list_first_entry(&d40c->queue,
  861. struct d40_desc,
  862. node);
  863. return d;
  864. }
  865. static struct d40_desc *d40_first_done(struct d40_chan *d40c)
  866. {
  867. if (list_empty(&d40c->done))
  868. return NULL;
  869. return list_first_entry(&d40c->done, struct d40_desc, node);
  870. }
  871. static int d40_psize_2_burst_size(bool is_log, int psize)
  872. {
  873. if (is_log) {
  874. if (psize == STEDMA40_PSIZE_LOG_1)
  875. return 1;
  876. } else {
  877. if (psize == STEDMA40_PSIZE_PHY_1)
  878. return 1;
  879. }
  880. return 2 << psize;
  881. }
  882. /*
  883. * The dma only supports transmitting packages up to
  884. * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
  885. *
  886. * Calculate the total number of dma elements required to send the entire sg list.
  887. */
  888. static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
  889. {
  890. int dmalen;
  891. u32 max_w = max(data_width1, data_width2);
  892. u32 min_w = min(data_width1, data_width2);
  893. u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
  894. if (seg_max > STEDMA40_MAX_SEG_SIZE)
  895. seg_max -= max_w;
  896. if (!IS_ALIGNED(size, max_w))
  897. return -EINVAL;
  898. if (size <= seg_max)
  899. dmalen = 1;
  900. else {
  901. dmalen = size / seg_max;
  902. if (dmalen * seg_max < size)
  903. dmalen++;
  904. }
  905. return dmalen;
  906. }
  907. static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
  908. u32 data_width1, u32 data_width2)
  909. {
  910. struct scatterlist *sg;
  911. int i;
  912. int len = 0;
  913. int ret;
  914. for_each_sg(sgl, sg, sg_len, i) {
  915. ret = d40_size_2_dmalen(sg_dma_len(sg),
  916. data_width1, data_width2);
  917. if (ret < 0)
  918. return ret;
  919. len += ret;
  920. }
  921. return len;
  922. }
  923. #ifdef CONFIG_PM
  924. static void dma40_backup(void __iomem *baseaddr, u32 *backup,
  925. u32 *regaddr, int num, bool save)
  926. {
  927. int i;
  928. for (i = 0; i < num; i++) {
  929. void __iomem *addr = baseaddr + regaddr[i];
  930. if (save)
  931. backup[i] = readl_relaxed(addr);
  932. else
  933. writel_relaxed(backup[i], addr);
  934. }
  935. }
  936. static void d40_save_restore_registers(struct d40_base *base, bool save)
  937. {
  938. int i;
  939. /* Save/Restore channel specific registers */
  940. for (i = 0; i < base->num_phy_chans; i++) {
  941. void __iomem *addr;
  942. int idx;
  943. if (base->phy_res[i].reserved)
  944. continue;
  945. addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
  946. idx = i * ARRAY_SIZE(d40_backup_regs_chan);
  947. dma40_backup(addr, &base->reg_val_backup_chan[idx],
  948. d40_backup_regs_chan,
  949. ARRAY_SIZE(d40_backup_regs_chan),
  950. save);
  951. }
  952. /* Save/Restore global registers */
  953. dma40_backup(base->virtbase, base->reg_val_backup,
  954. d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
  955. save);
  956. /* Save/Restore registers only existing on dma40 v3 and later */
  957. if (base->gen_dmac.backup)
  958. dma40_backup(base->virtbase, base->reg_val_backup_v4,
  959. base->gen_dmac.backup,
  960. base->gen_dmac.backup_size,
  961. save);
  962. }
  963. #else
  964. static void d40_save_restore_registers(struct d40_base *base, bool save)
  965. {
  966. }
  967. #endif
  968. static int __d40_execute_command_phy(struct d40_chan *d40c,
  969. enum d40_command command)
  970. {
  971. u32 status;
  972. int i;
  973. void __iomem *active_reg;
  974. int ret = 0;
  975. unsigned long flags;
  976. u32 wmask;
  977. if (command == D40_DMA_STOP) {
  978. ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
  979. if (ret)
  980. return ret;
  981. }
  982. spin_lock_irqsave(&d40c->base->execmd_lock, flags);
  983. if (d40c->phy_chan->num % 2 == 0)
  984. active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
  985. else
  986. active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
  987. if (command == D40_DMA_SUSPEND_REQ) {
  988. status = (readl(active_reg) &
  989. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  990. D40_CHAN_POS(d40c->phy_chan->num);
  991. if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
  992. goto done;
  993. }
  994. wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
  995. writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
  996. active_reg);
  997. if (command == D40_DMA_SUSPEND_REQ) {
  998. for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
  999. status = (readl(active_reg) &
  1000. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  1001. D40_CHAN_POS(d40c->phy_chan->num);
  1002. cpu_relax();
  1003. /*
  1004. * Reduce the number of bus accesses while
  1005. * waiting for the DMA to suspend.
  1006. */
  1007. udelay(3);
  1008. if (status == D40_DMA_STOP ||
  1009. status == D40_DMA_SUSPENDED)
  1010. break;
  1011. }
  1012. if (i == D40_SUSPEND_MAX_IT) {
  1013. chan_err(d40c,
  1014. "unable to suspend the chl %d (log: %d) status %x\n",
  1015. d40c->phy_chan->num, d40c->log_num,
  1016. status);
  1017. dump_stack();
  1018. ret = -EBUSY;
  1019. }
  1020. }
  1021. done:
  1022. spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
  1023. return ret;
  1024. }
  1025. static void d40_term_all(struct d40_chan *d40c)
  1026. {
  1027. struct d40_desc *d40d;
  1028. struct d40_desc *_d;
  1029. /* Release completed descriptors */
  1030. while ((d40d = d40_first_done(d40c))) {
  1031. d40_desc_remove(d40d);
  1032. d40_desc_free(d40c, d40d);
  1033. }
  1034. /* Release active descriptors */
  1035. while ((d40d = d40_first_active_get(d40c))) {
  1036. d40_desc_remove(d40d);
  1037. d40_desc_free(d40c, d40d);
  1038. }
  1039. /* Release queued descriptors waiting for transfer */
  1040. while ((d40d = d40_first_queued(d40c))) {
  1041. d40_desc_remove(d40d);
  1042. d40_desc_free(d40c, d40d);
  1043. }
  1044. /* Release pending descriptors */
  1045. while ((d40d = d40_first_pending(d40c))) {
  1046. d40_desc_remove(d40d);
  1047. d40_desc_free(d40c, d40d);
  1048. }
  1049. /* Release client owned descriptors */
  1050. if (!list_empty(&d40c->client))
  1051. list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
  1052. d40_desc_remove(d40d);
  1053. d40_desc_free(d40c, d40d);
  1054. }
  1055. /* Release descriptors in prepare queue */
  1056. if (!list_empty(&d40c->prepare_queue))
  1057. list_for_each_entry_safe(d40d, _d,
  1058. &d40c->prepare_queue, node) {
  1059. d40_desc_remove(d40d);
  1060. d40_desc_free(d40c, d40d);
  1061. }
  1062. d40c->pending_tx = 0;
  1063. }
  1064. static void __d40_config_set_event(struct d40_chan *d40c,
  1065. enum d40_events event_type, u32 event,
  1066. int reg)
  1067. {
  1068. void __iomem *addr = chan_base(d40c) + reg;
  1069. int tries;
  1070. u32 status;
  1071. switch (event_type) {
  1072. case D40_DEACTIVATE_EVENTLINE:
  1073. writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
  1074. | ~D40_EVENTLINE_MASK(event), addr);
  1075. break;
  1076. case D40_SUSPEND_REQ_EVENTLINE:
  1077. status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
  1078. D40_EVENTLINE_POS(event);
  1079. if (status == D40_DEACTIVATE_EVENTLINE ||
  1080. status == D40_SUSPEND_REQ_EVENTLINE)
  1081. break;
  1082. writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
  1083. | ~D40_EVENTLINE_MASK(event), addr);
  1084. for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
  1085. status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
  1086. D40_EVENTLINE_POS(event);
  1087. cpu_relax();
  1088. /*
  1089. * Reduce the number of bus accesses while
  1090. * waiting for the DMA to suspend.
  1091. */
  1092. udelay(3);
  1093. if (status == D40_DEACTIVATE_EVENTLINE)
  1094. break;
  1095. }
  1096. if (tries == D40_SUSPEND_MAX_IT) {
  1097. chan_err(d40c,
  1098. "unable to stop the event_line chl %d (log: %d)"
  1099. "status %x\n", d40c->phy_chan->num,
  1100. d40c->log_num, status);
  1101. }
  1102. break;
  1103. case D40_ACTIVATE_EVENTLINE:
  1104. /*
  1105. * The hardware sometimes doesn't register the enable when src and dst
  1106. * event lines are active on the same logical channel. Retry to ensure
  1107. * it does. Usually only one retry is sufficient.
  1108. */
  1109. tries = 100;
  1110. while (--tries) {
  1111. writel((D40_ACTIVATE_EVENTLINE <<
  1112. D40_EVENTLINE_POS(event)) |
  1113. ~D40_EVENTLINE_MASK(event), addr);
  1114. if (readl(addr) & D40_EVENTLINE_MASK(event))
  1115. break;
  1116. }
  1117. if (tries != 99)
  1118. dev_dbg(chan2dev(d40c),
  1119. "[%s] workaround enable S%cLNK (%d tries)\n",
  1120. __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
  1121. 100 - tries);
  1122. WARN_ON(!tries);
  1123. break;
  1124. case D40_ROUND_EVENTLINE:
  1125. BUG();
  1126. break;
  1127. }
  1128. }
  1129. static void d40_config_set_event(struct d40_chan *d40c,
  1130. enum d40_events event_type)
  1131. {
  1132. u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
  1133. /* Enable event line connected to device (or memcpy) */
  1134. if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
  1135. (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
  1136. __d40_config_set_event(d40c, event_type, event,
  1137. D40_CHAN_REG_SSLNK);
  1138. if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
  1139. __d40_config_set_event(d40c, event_type, event,
  1140. D40_CHAN_REG_SDLNK);
  1141. }
  1142. static u32 d40_chan_has_events(struct d40_chan *d40c)
  1143. {
  1144. void __iomem *chanbase = chan_base(d40c);
  1145. u32 val;
  1146. val = readl(chanbase + D40_CHAN_REG_SSLNK);
  1147. val |= readl(chanbase + D40_CHAN_REG_SDLNK);
  1148. return val;
  1149. }
  1150. static int
  1151. __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
  1152. {
  1153. unsigned long flags;
  1154. int ret = 0;
  1155. u32 active_status;
  1156. void __iomem *active_reg;
  1157. if (d40c->phy_chan->num % 2 == 0)
  1158. active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
  1159. else
  1160. active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
  1161. spin_lock_irqsave(&d40c->phy_chan->lock, flags);
  1162. switch (command) {
  1163. case D40_DMA_STOP:
  1164. case D40_DMA_SUSPEND_REQ:
  1165. active_status = (readl(active_reg) &
  1166. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  1167. D40_CHAN_POS(d40c->phy_chan->num);
  1168. if (active_status == D40_DMA_RUN)
  1169. d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
  1170. else
  1171. d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
  1172. if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
  1173. ret = __d40_execute_command_phy(d40c, command);
  1174. break;
  1175. case D40_DMA_RUN:
  1176. d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
  1177. ret = __d40_execute_command_phy(d40c, command);
  1178. break;
  1179. case D40_DMA_SUSPENDED:
  1180. BUG();
  1181. break;
  1182. }
  1183. spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
  1184. return ret;
  1185. }
  1186. static int d40_channel_execute_command(struct d40_chan *d40c,
  1187. enum d40_command command)
  1188. {
  1189. if (chan_is_logical(d40c))
  1190. return __d40_execute_command_log(d40c, command);
  1191. else
  1192. return __d40_execute_command_phy(d40c, command);
  1193. }
  1194. static u32 d40_get_prmo(struct d40_chan *d40c)
  1195. {
  1196. static const unsigned int phy_map[] = {
  1197. [STEDMA40_PCHAN_BASIC_MODE]
  1198. = D40_DREG_PRMO_PCHAN_BASIC,
  1199. [STEDMA40_PCHAN_MODULO_MODE]
  1200. = D40_DREG_PRMO_PCHAN_MODULO,
  1201. [STEDMA40_PCHAN_DOUBLE_DST_MODE]
  1202. = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
  1203. };
  1204. static const unsigned int log_map[] = {
  1205. [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
  1206. = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
  1207. [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
  1208. = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
  1209. [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
  1210. = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
  1211. };
  1212. if (chan_is_physical(d40c))
  1213. return phy_map[d40c->dma_cfg.mode_opt];
  1214. else
  1215. return log_map[d40c->dma_cfg.mode_opt];
  1216. }
  1217. static void d40_config_write(struct d40_chan *d40c)
  1218. {
  1219. u32 addr_base;
  1220. u32 var;
  1221. /* Odd addresses are even addresses + 4 */
  1222. addr_base = (d40c->phy_chan->num % 2) * 4;
  1223. /* Setup channel mode to logical or physical */
  1224. var = ((u32)(chan_is_logical(d40c)) + 1) <<
  1225. D40_CHAN_POS(d40c->phy_chan->num);
  1226. writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
  1227. /* Setup operational mode option register */
  1228. var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
  1229. writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
  1230. if (chan_is_logical(d40c)) {
  1231. int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
  1232. & D40_SREG_ELEM_LOG_LIDX_MASK;
  1233. void __iomem *chanbase = chan_base(d40c);
  1234. /* Set default config for CFG reg */
  1235. writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
  1236. writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
  1237. /* Set LIDX for lcla */
  1238. writel(lidx, chanbase + D40_CHAN_REG_SSELT);
  1239. writel(lidx, chanbase + D40_CHAN_REG_SDELT);
  1240. /* Clear LNK which will be used by d40_chan_has_events() */
  1241. writel(0, chanbase + D40_CHAN_REG_SSLNK);
  1242. writel(0, chanbase + D40_CHAN_REG_SDLNK);
  1243. }
  1244. }
  1245. static u32 d40_residue(struct d40_chan *d40c)
  1246. {
  1247. u32 num_elt;
  1248. if (chan_is_logical(d40c))
  1249. num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
  1250. >> D40_MEM_LCSP2_ECNT_POS;
  1251. else {
  1252. u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
  1253. num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
  1254. >> D40_SREG_ELEM_PHY_ECNT_POS;
  1255. }
  1256. return num_elt * d40c->dma_cfg.dst_info.data_width;
  1257. }
  1258. static bool d40_tx_is_linked(struct d40_chan *d40c)
  1259. {
  1260. bool is_link;
  1261. if (chan_is_logical(d40c))
  1262. is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
  1263. else
  1264. is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
  1265. & D40_SREG_LNK_PHYS_LNK_MASK;
  1266. return is_link;
  1267. }
  1268. static int d40_pause(struct d40_chan *d40c)
  1269. {
  1270. int res = 0;
  1271. unsigned long flags;
  1272. if (!d40c->busy)
  1273. return 0;
  1274. pm_runtime_get_sync(d40c->base->dev);
  1275. spin_lock_irqsave(&d40c->lock, flags);
  1276. res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
  1277. pm_runtime_mark_last_busy(d40c->base->dev);
  1278. pm_runtime_put_autosuspend(d40c->base->dev);
  1279. spin_unlock_irqrestore(&d40c->lock, flags);
  1280. return res;
  1281. }
  1282. static int d40_resume(struct d40_chan *d40c)
  1283. {
  1284. int res = 0;
  1285. unsigned long flags;
  1286. if (!d40c->busy)
  1287. return 0;
  1288. spin_lock_irqsave(&d40c->lock, flags);
  1289. pm_runtime_get_sync(d40c->base->dev);
  1290. /* If bytes left to transfer or linked tx resume job */
  1291. if (d40_residue(d40c) || d40_tx_is_linked(d40c))
  1292. res = d40_channel_execute_command(d40c, D40_DMA_RUN);
  1293. pm_runtime_mark_last_busy(d40c->base->dev);
  1294. pm_runtime_put_autosuspend(d40c->base->dev);
  1295. spin_unlock_irqrestore(&d40c->lock, flags);
  1296. return res;
  1297. }
  1298. static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
  1299. {
  1300. struct d40_chan *d40c = container_of(tx->chan,
  1301. struct d40_chan,
  1302. chan);
  1303. struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
  1304. unsigned long flags;
  1305. dma_cookie_t cookie;
  1306. spin_lock_irqsave(&d40c->lock, flags);
  1307. cookie = dma_cookie_assign(tx);
  1308. d40_desc_queue(d40c, d40d);
  1309. spin_unlock_irqrestore(&d40c->lock, flags);
  1310. return cookie;
  1311. }
  1312. static int d40_start(struct d40_chan *d40c)
  1313. {
  1314. return d40_channel_execute_command(d40c, D40_DMA_RUN);
  1315. }
  1316. static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
  1317. {
  1318. struct d40_desc *d40d;
  1319. int err;
  1320. /* Start queued jobs, if any */
  1321. d40d = d40_first_queued(d40c);
  1322. if (d40d != NULL) {
  1323. if (!d40c->busy) {
  1324. d40c->busy = true;
  1325. pm_runtime_get_sync(d40c->base->dev);
  1326. }
  1327. /* Remove from queue */
  1328. d40_desc_remove(d40d);
  1329. /* Add to active queue */
  1330. d40_desc_submit(d40c, d40d);
  1331. /* Initiate DMA job */
  1332. d40_desc_load(d40c, d40d);
  1333. /* Start dma job */
  1334. err = d40_start(d40c);
  1335. if (err)
  1336. return NULL;
  1337. }
  1338. return d40d;
  1339. }
  1340. /* called from interrupt context */
  1341. static void dma_tc_handle(struct d40_chan *d40c)
  1342. {
  1343. struct d40_desc *d40d;
  1344. /* Get first active entry from list */
  1345. d40d = d40_first_active_get(d40c);
  1346. if (d40d == NULL)
  1347. return;
  1348. if (d40d->cyclic) {
  1349. /*
  1350. * If this was a paritially loaded list, we need to reloaded
  1351. * it, and only when the list is completed. We need to check
  1352. * for done because the interrupt will hit for every link, and
  1353. * not just the last one.
  1354. */
  1355. if (d40d->lli_current < d40d->lli_len
  1356. && !d40_tx_is_linked(d40c)
  1357. && !d40_residue(d40c)) {
  1358. d40_lcla_free_all(d40c, d40d);
  1359. d40_desc_load(d40c, d40d);
  1360. (void) d40_start(d40c);
  1361. if (d40d->lli_current == d40d->lli_len)
  1362. d40d->lli_current = 0;
  1363. }
  1364. } else {
  1365. d40_lcla_free_all(d40c, d40d);
  1366. if (d40d->lli_current < d40d->lli_len) {
  1367. d40_desc_load(d40c, d40d);
  1368. /* Start dma job */
  1369. (void) d40_start(d40c);
  1370. return;
  1371. }
  1372. if (d40_queue_start(d40c) == NULL) {
  1373. d40c->busy = false;
  1374. pm_runtime_mark_last_busy(d40c->base->dev);
  1375. pm_runtime_put_autosuspend(d40c->base->dev);
  1376. }
  1377. d40_desc_remove(d40d);
  1378. d40_desc_done(d40c, d40d);
  1379. }
  1380. d40c->pending_tx++;
  1381. tasklet_schedule(&d40c->tasklet);
  1382. }
  1383. static void dma_tasklet(unsigned long data)
  1384. {
  1385. struct d40_chan *d40c = (struct d40_chan *) data;
  1386. struct d40_desc *d40d;
  1387. unsigned long flags;
  1388. dma_async_tx_callback callback;
  1389. void *callback_param;
  1390. spin_lock_irqsave(&d40c->lock, flags);
  1391. /* Get first entry from the done list */
  1392. d40d = d40_first_done(d40c);
  1393. if (d40d == NULL) {
  1394. /* Check if we have reached here for cyclic job */
  1395. d40d = d40_first_active_get(d40c);
  1396. if (d40d == NULL || !d40d->cyclic)
  1397. goto err;
  1398. }
  1399. if (!d40d->cyclic)
  1400. dma_cookie_complete(&d40d->txd);
  1401. /*
  1402. * If terminating a channel pending_tx is set to zero.
  1403. * This prevents any finished active jobs to return to the client.
  1404. */
  1405. if (d40c->pending_tx == 0) {
  1406. spin_unlock_irqrestore(&d40c->lock, flags);
  1407. return;
  1408. }
  1409. /* Callback to client */
  1410. callback = d40d->txd.callback;
  1411. callback_param = d40d->txd.callback_param;
  1412. if (!d40d->cyclic) {
  1413. if (async_tx_test_ack(&d40d->txd)) {
  1414. d40_desc_remove(d40d);
  1415. d40_desc_free(d40c, d40d);
  1416. } else if (!d40d->is_in_client_list) {
  1417. d40_desc_remove(d40d);
  1418. d40_lcla_free_all(d40c, d40d);
  1419. list_add_tail(&d40d->node, &d40c->client);
  1420. d40d->is_in_client_list = true;
  1421. }
  1422. }
  1423. d40c->pending_tx--;
  1424. if (d40c->pending_tx)
  1425. tasklet_schedule(&d40c->tasklet);
  1426. spin_unlock_irqrestore(&d40c->lock, flags);
  1427. if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
  1428. callback(callback_param);
  1429. return;
  1430. err:
  1431. /* Rescue manouver if receiving double interrupts */
  1432. if (d40c->pending_tx > 0)
  1433. d40c->pending_tx--;
  1434. spin_unlock_irqrestore(&d40c->lock, flags);
  1435. }
  1436. static irqreturn_t d40_handle_interrupt(int irq, void *data)
  1437. {
  1438. int i;
  1439. u32 idx;
  1440. u32 row;
  1441. long chan = -1;
  1442. struct d40_chan *d40c;
  1443. unsigned long flags;
  1444. struct d40_base *base = data;
  1445. u32 regs[base->gen_dmac.il_size];
  1446. struct d40_interrupt_lookup *il = base->gen_dmac.il;
  1447. u32 il_size = base->gen_dmac.il_size;
  1448. spin_lock_irqsave(&base->interrupt_lock, flags);
  1449. /* Read interrupt status of both logical and physical channels */
  1450. for (i = 0; i < il_size; i++)
  1451. regs[i] = readl(base->virtbase + il[i].src);
  1452. for (;;) {
  1453. chan = find_next_bit((unsigned long *)regs,
  1454. BITS_PER_LONG * il_size, chan + 1);
  1455. /* No more set bits found? */
  1456. if (chan == BITS_PER_LONG * il_size)
  1457. break;
  1458. row = chan / BITS_PER_LONG;
  1459. idx = chan & (BITS_PER_LONG - 1);
  1460. if (il[row].offset == D40_PHY_CHAN)
  1461. d40c = base->lookup_phy_chans[idx];
  1462. else
  1463. d40c = base->lookup_log_chans[il[row].offset + idx];
  1464. if (!d40c) {
  1465. /*
  1466. * No error because this can happen if something else
  1467. * in the system is using the channel.
  1468. */
  1469. continue;
  1470. }
  1471. /* ACK interrupt */
  1472. writel(BIT(idx), base->virtbase + il[row].clr);
  1473. spin_lock(&d40c->lock);
  1474. if (!il[row].is_error)
  1475. dma_tc_handle(d40c);
  1476. else
  1477. d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
  1478. chan, il[row].offset, idx);
  1479. spin_unlock(&d40c->lock);
  1480. }
  1481. spin_unlock_irqrestore(&base->interrupt_lock, flags);
  1482. return IRQ_HANDLED;
  1483. }
  1484. static int d40_validate_conf(struct d40_chan *d40c,
  1485. struct stedma40_chan_cfg *conf)
  1486. {
  1487. int res = 0;
  1488. bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
  1489. if (!conf->dir) {
  1490. chan_err(d40c, "Invalid direction.\n");
  1491. res = -EINVAL;
  1492. }
  1493. if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
  1494. (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
  1495. (conf->dev_type < 0)) {
  1496. chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
  1497. res = -EINVAL;
  1498. }
  1499. if (conf->dir == DMA_DEV_TO_DEV) {
  1500. /*
  1501. * DMAC HW supports it. Will be added to this driver,
  1502. * in case any dma client requires it.
  1503. */
  1504. chan_err(d40c, "periph to periph not supported\n");
  1505. res = -EINVAL;
  1506. }
  1507. if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
  1508. conf->src_info.data_width !=
  1509. d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
  1510. conf->dst_info.data_width) {
  1511. /*
  1512. * The DMAC hardware only supports
  1513. * src (burst x width) == dst (burst x width)
  1514. */
  1515. chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
  1516. res = -EINVAL;
  1517. }
  1518. return res;
  1519. }
  1520. static bool d40_alloc_mask_set(struct d40_phy_res *phy,
  1521. bool is_src, int log_event_line, bool is_log,
  1522. bool *first_user)
  1523. {
  1524. unsigned long flags;
  1525. spin_lock_irqsave(&phy->lock, flags);
  1526. *first_user = ((phy->allocated_src | phy->allocated_dst)
  1527. == D40_ALLOC_FREE);
  1528. if (!is_log) {
  1529. /* Physical interrupts are masked per physical full channel */
  1530. if (phy->allocated_src == D40_ALLOC_FREE &&
  1531. phy->allocated_dst == D40_ALLOC_FREE) {
  1532. phy->allocated_dst = D40_ALLOC_PHY;
  1533. phy->allocated_src = D40_ALLOC_PHY;
  1534. goto found;
  1535. } else
  1536. goto not_found;
  1537. }
  1538. /* Logical channel */
  1539. if (is_src) {
  1540. if (phy->allocated_src == D40_ALLOC_PHY)
  1541. goto not_found;
  1542. if (phy->allocated_src == D40_ALLOC_FREE)
  1543. phy->allocated_src = D40_ALLOC_LOG_FREE;
  1544. if (!(phy->allocated_src & BIT(log_event_line))) {
  1545. phy->allocated_src |= BIT(log_event_line);
  1546. goto found;
  1547. } else
  1548. goto not_found;
  1549. } else {
  1550. if (phy->allocated_dst == D40_ALLOC_PHY)
  1551. goto not_found;
  1552. if (phy->allocated_dst == D40_ALLOC_FREE)
  1553. phy->allocated_dst = D40_ALLOC_LOG_FREE;
  1554. if (!(phy->allocated_dst & BIT(log_event_line))) {
  1555. phy->allocated_dst |= BIT(log_event_line);
  1556. goto found;
  1557. } else
  1558. goto not_found;
  1559. }
  1560. not_found:
  1561. spin_unlock_irqrestore(&phy->lock, flags);
  1562. return false;
  1563. found:
  1564. spin_unlock_irqrestore(&phy->lock, flags);
  1565. return true;
  1566. }
  1567. static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
  1568. int log_event_line)
  1569. {
  1570. unsigned long flags;
  1571. bool is_free = false;
  1572. spin_lock_irqsave(&phy->lock, flags);
  1573. if (!log_event_line) {
  1574. phy->allocated_dst = D40_ALLOC_FREE;
  1575. phy->allocated_src = D40_ALLOC_FREE;
  1576. is_free = true;
  1577. goto out;
  1578. }
  1579. /* Logical channel */
  1580. if (is_src) {
  1581. phy->allocated_src &= ~BIT(log_event_line);
  1582. if (phy->allocated_src == D40_ALLOC_LOG_FREE)
  1583. phy->allocated_src = D40_ALLOC_FREE;
  1584. } else {
  1585. phy->allocated_dst &= ~BIT(log_event_line);
  1586. if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
  1587. phy->allocated_dst = D40_ALLOC_FREE;
  1588. }
  1589. is_free = ((phy->allocated_src | phy->allocated_dst) ==
  1590. D40_ALLOC_FREE);
  1591. out:
  1592. spin_unlock_irqrestore(&phy->lock, flags);
  1593. return is_free;
  1594. }
  1595. static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
  1596. {
  1597. int dev_type = d40c->dma_cfg.dev_type;
  1598. int event_group;
  1599. int event_line;
  1600. struct d40_phy_res *phys;
  1601. int i;
  1602. int j;
  1603. int log_num;
  1604. int num_phy_chans;
  1605. bool is_src;
  1606. bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
  1607. phys = d40c->base->phy_res;
  1608. num_phy_chans = d40c->base->num_phy_chans;
  1609. if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
  1610. log_num = 2 * dev_type;
  1611. is_src = true;
  1612. } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
  1613. d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
  1614. /* dst event lines are used for logical memcpy */
  1615. log_num = 2 * dev_type + 1;
  1616. is_src = false;
  1617. } else
  1618. return -EINVAL;
  1619. event_group = D40_TYPE_TO_GROUP(dev_type);
  1620. event_line = D40_TYPE_TO_EVENT(dev_type);
  1621. if (!is_log) {
  1622. if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
  1623. /* Find physical half channel */
  1624. if (d40c->dma_cfg.use_fixed_channel) {
  1625. i = d40c->dma_cfg.phy_channel;
  1626. if (d40_alloc_mask_set(&phys[i], is_src,
  1627. 0, is_log,
  1628. first_phy_user))
  1629. goto found_phy;
  1630. } else {
  1631. for (i = 0; i < num_phy_chans; i++) {
  1632. if (d40_alloc_mask_set(&phys[i], is_src,
  1633. 0, is_log,
  1634. first_phy_user))
  1635. goto found_phy;
  1636. }
  1637. }
  1638. } else
  1639. for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
  1640. int phy_num = j + event_group * 2;
  1641. for (i = phy_num; i < phy_num + 2; i++) {
  1642. if (d40_alloc_mask_set(&phys[i],
  1643. is_src,
  1644. 0,
  1645. is_log,
  1646. first_phy_user))
  1647. goto found_phy;
  1648. }
  1649. }
  1650. return -EINVAL;
  1651. found_phy:
  1652. d40c->phy_chan = &phys[i];
  1653. d40c->log_num = D40_PHY_CHAN;
  1654. goto out;
  1655. }
  1656. if (dev_type == -1)
  1657. return -EINVAL;
  1658. /* Find logical channel */
  1659. for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
  1660. int phy_num = j + event_group * 2;
  1661. if (d40c->dma_cfg.use_fixed_channel) {
  1662. i = d40c->dma_cfg.phy_channel;
  1663. if ((i != phy_num) && (i != phy_num + 1)) {
  1664. dev_err(chan2dev(d40c),
  1665. "invalid fixed phy channel %d\n", i);
  1666. return -EINVAL;
  1667. }
  1668. if (d40_alloc_mask_set(&phys[i], is_src, event_line,
  1669. is_log, first_phy_user))
  1670. goto found_log;
  1671. dev_err(chan2dev(d40c),
  1672. "could not allocate fixed phy channel %d\n", i);
  1673. return -EINVAL;
  1674. }
  1675. /*
  1676. * Spread logical channels across all available physical rather
  1677. * than pack every logical channel at the first available phy
  1678. * channels.
  1679. */
  1680. if (is_src) {
  1681. for (i = phy_num; i < phy_num + 2; i++) {
  1682. if (d40_alloc_mask_set(&phys[i], is_src,
  1683. event_line, is_log,
  1684. first_phy_user))
  1685. goto found_log;
  1686. }
  1687. } else {
  1688. for (i = phy_num + 1; i >= phy_num; i--) {
  1689. if (d40_alloc_mask_set(&phys[i], is_src,
  1690. event_line, is_log,
  1691. first_phy_user))
  1692. goto found_log;
  1693. }
  1694. }
  1695. }
  1696. return -EINVAL;
  1697. found_log:
  1698. d40c->phy_chan = &phys[i];
  1699. d40c->log_num = log_num;
  1700. out:
  1701. if (is_log)
  1702. d40c->base->lookup_log_chans[d40c->log_num] = d40c;
  1703. else
  1704. d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
  1705. return 0;
  1706. }
  1707. static int d40_config_memcpy(struct d40_chan *d40c)
  1708. {
  1709. dma_cap_mask_t cap = d40c->chan.device->cap_mask;
  1710. if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
  1711. d40c->dma_cfg = dma40_memcpy_conf_log;
  1712. d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
  1713. d40_log_cfg(&d40c->dma_cfg,
  1714. &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
  1715. } else if (dma_has_cap(DMA_MEMCPY, cap) &&
  1716. dma_has_cap(DMA_SLAVE, cap)) {
  1717. d40c->dma_cfg = dma40_memcpy_conf_phy;
  1718. /* Generate interrrupt at end of transfer or relink. */
  1719. d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
  1720. /* Generate interrupt on error. */
  1721. d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
  1722. d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
  1723. } else {
  1724. chan_err(d40c, "No memcpy\n");
  1725. return -EINVAL;
  1726. }
  1727. return 0;
  1728. }
  1729. static int d40_free_dma(struct d40_chan *d40c)
  1730. {
  1731. int res = 0;
  1732. u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
  1733. struct d40_phy_res *phy = d40c->phy_chan;
  1734. bool is_src;
  1735. /* Terminate all queued and active transfers */
  1736. d40_term_all(d40c);
  1737. if (phy == NULL) {
  1738. chan_err(d40c, "phy == null\n");
  1739. return -EINVAL;
  1740. }
  1741. if (phy->allocated_src == D40_ALLOC_FREE &&
  1742. phy->allocated_dst == D40_ALLOC_FREE) {
  1743. chan_err(d40c, "channel already free\n");
  1744. return -EINVAL;
  1745. }
  1746. if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
  1747. d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
  1748. is_src = false;
  1749. else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
  1750. is_src = true;
  1751. else {
  1752. chan_err(d40c, "Unknown direction\n");
  1753. return -EINVAL;
  1754. }
  1755. pm_runtime_get_sync(d40c->base->dev);
  1756. res = d40_channel_execute_command(d40c, D40_DMA_STOP);
  1757. if (res) {
  1758. chan_err(d40c, "stop failed\n");
  1759. goto out;
  1760. }
  1761. d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
  1762. if (chan_is_logical(d40c))
  1763. d40c->base->lookup_log_chans[d40c->log_num] = NULL;
  1764. else
  1765. d40c->base->lookup_phy_chans[phy->num] = NULL;
  1766. if (d40c->busy) {
  1767. pm_runtime_mark_last_busy(d40c->base->dev);
  1768. pm_runtime_put_autosuspend(d40c->base->dev);
  1769. }
  1770. d40c->busy = false;
  1771. d40c->phy_chan = NULL;
  1772. d40c->configured = false;
  1773. out:
  1774. pm_runtime_mark_last_busy(d40c->base->dev);
  1775. pm_runtime_put_autosuspend(d40c->base->dev);
  1776. return res;
  1777. }
  1778. static bool d40_is_paused(struct d40_chan *d40c)
  1779. {
  1780. void __iomem *chanbase = chan_base(d40c);
  1781. bool is_paused = false;
  1782. unsigned long flags;
  1783. void __iomem *active_reg;
  1784. u32 status;
  1785. u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
  1786. spin_lock_irqsave(&d40c->lock, flags);
  1787. if (chan_is_physical(d40c)) {
  1788. if (d40c->phy_chan->num % 2 == 0)
  1789. active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
  1790. else
  1791. active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
  1792. status = (readl(active_reg) &
  1793. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  1794. D40_CHAN_POS(d40c->phy_chan->num);
  1795. if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
  1796. is_paused = true;
  1797. goto _exit;
  1798. }
  1799. if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
  1800. d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
  1801. status = readl(chanbase + D40_CHAN_REG_SDLNK);
  1802. } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
  1803. status = readl(chanbase + D40_CHAN_REG_SSLNK);
  1804. } else {
  1805. chan_err(d40c, "Unknown direction\n");
  1806. goto _exit;
  1807. }
  1808. status = (status & D40_EVENTLINE_MASK(event)) >>
  1809. D40_EVENTLINE_POS(event);
  1810. if (status != D40_DMA_RUN)
  1811. is_paused = true;
  1812. _exit:
  1813. spin_unlock_irqrestore(&d40c->lock, flags);
  1814. return is_paused;
  1815. }
  1816. static u32 stedma40_residue(struct dma_chan *chan)
  1817. {
  1818. struct d40_chan *d40c =
  1819. container_of(chan, struct d40_chan, chan);
  1820. u32 bytes_left;
  1821. unsigned long flags;
  1822. spin_lock_irqsave(&d40c->lock, flags);
  1823. bytes_left = d40_residue(d40c);
  1824. spin_unlock_irqrestore(&d40c->lock, flags);
  1825. return bytes_left;
  1826. }
  1827. static int
  1828. d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
  1829. struct scatterlist *sg_src, struct scatterlist *sg_dst,
  1830. unsigned int sg_len, dma_addr_t src_dev_addr,
  1831. dma_addr_t dst_dev_addr)
  1832. {
  1833. struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
  1834. struct stedma40_half_channel_info *src_info = &cfg->src_info;
  1835. struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
  1836. int ret;
  1837. ret = d40_log_sg_to_lli(sg_src, sg_len,
  1838. src_dev_addr,
  1839. desc->lli_log.src,
  1840. chan->log_def.lcsp1,
  1841. src_info->data_width,
  1842. dst_info->data_width);
  1843. ret = d40_log_sg_to_lli(sg_dst, sg_len,
  1844. dst_dev_addr,
  1845. desc->lli_log.dst,
  1846. chan->log_def.lcsp3,
  1847. dst_info->data_width,
  1848. src_info->data_width);
  1849. return ret < 0 ? ret : 0;
  1850. }
  1851. static int
  1852. d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
  1853. struct scatterlist *sg_src, struct scatterlist *sg_dst,
  1854. unsigned int sg_len, dma_addr_t src_dev_addr,
  1855. dma_addr_t dst_dev_addr)
  1856. {
  1857. struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
  1858. struct stedma40_half_channel_info *src_info = &cfg->src_info;
  1859. struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
  1860. unsigned long flags = 0;
  1861. int ret;
  1862. if (desc->cyclic)
  1863. flags |= LLI_CYCLIC | LLI_TERM_INT;
  1864. ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
  1865. desc->lli_phy.src,
  1866. virt_to_phys(desc->lli_phy.src),
  1867. chan->src_def_cfg,
  1868. src_info, dst_info, flags);
  1869. ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
  1870. desc->lli_phy.dst,
  1871. virt_to_phys(desc->lli_phy.dst),
  1872. chan->dst_def_cfg,
  1873. dst_info, src_info, flags);
  1874. dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
  1875. desc->lli_pool.size, DMA_TO_DEVICE);
  1876. return ret < 0 ? ret : 0;
  1877. }
  1878. static struct d40_desc *
  1879. d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
  1880. unsigned int sg_len, unsigned long dma_flags)
  1881. {
  1882. struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
  1883. struct d40_desc *desc;
  1884. int ret;
  1885. desc = d40_desc_get(chan);
  1886. if (!desc)
  1887. return NULL;
  1888. desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
  1889. cfg->dst_info.data_width);
  1890. if (desc->lli_len < 0) {
  1891. chan_err(chan, "Unaligned size\n");
  1892. goto err;
  1893. }
  1894. ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
  1895. if (ret < 0) {
  1896. chan_err(chan, "Could not allocate lli\n");
  1897. goto err;
  1898. }
  1899. desc->lli_current = 0;
  1900. desc->txd.flags = dma_flags;
  1901. desc->txd.tx_submit = d40_tx_submit;
  1902. dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
  1903. return desc;
  1904. err:
  1905. d40_desc_free(chan, desc);
  1906. return NULL;
  1907. }
  1908. static struct dma_async_tx_descriptor *
  1909. d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
  1910. struct scatterlist *sg_dst, unsigned int sg_len,
  1911. enum dma_transfer_direction direction, unsigned long dma_flags)
  1912. {
  1913. struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
  1914. dma_addr_t src_dev_addr = 0;
  1915. dma_addr_t dst_dev_addr = 0;
  1916. struct d40_desc *desc;
  1917. unsigned long flags;
  1918. int ret;
  1919. if (!chan->phy_chan) {
  1920. chan_err(chan, "Cannot prepare unallocated channel\n");
  1921. return NULL;
  1922. }
  1923. spin_lock_irqsave(&chan->lock, flags);
  1924. desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
  1925. if (desc == NULL)
  1926. goto err;
  1927. if (sg_next(&sg_src[sg_len - 1]) == sg_src)
  1928. desc->cyclic = true;
  1929. if (direction == DMA_DEV_TO_MEM)
  1930. src_dev_addr = chan->runtime_addr;
  1931. else if (direction == DMA_MEM_TO_DEV)
  1932. dst_dev_addr = chan->runtime_addr;
  1933. if (chan_is_logical(chan))
  1934. ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
  1935. sg_len, src_dev_addr, dst_dev_addr);
  1936. else
  1937. ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
  1938. sg_len, src_dev_addr, dst_dev_addr);
  1939. if (ret) {
  1940. chan_err(chan, "Failed to prepare %s sg job: %d\n",
  1941. chan_is_logical(chan) ? "log" : "phy", ret);
  1942. goto err;
  1943. }
  1944. /*
  1945. * add descriptor to the prepare queue in order to be able
  1946. * to free them later in terminate_all
  1947. */
  1948. list_add_tail(&desc->node, &chan->prepare_queue);
  1949. spin_unlock_irqrestore(&chan->lock, flags);
  1950. return &desc->txd;
  1951. err:
  1952. if (desc)
  1953. d40_desc_free(chan, desc);
  1954. spin_unlock_irqrestore(&chan->lock, flags);
  1955. return NULL;
  1956. }
  1957. bool stedma40_filter(struct dma_chan *chan, void *data)
  1958. {
  1959. struct stedma40_chan_cfg *info = data;
  1960. struct d40_chan *d40c =
  1961. container_of(chan, struct d40_chan, chan);
  1962. int err;
  1963. if (data) {
  1964. err = d40_validate_conf(d40c, info);
  1965. if (!err)
  1966. d40c->dma_cfg = *info;
  1967. } else
  1968. err = d40_config_memcpy(d40c);
  1969. if (!err)
  1970. d40c->configured = true;
  1971. return err == 0;
  1972. }
  1973. EXPORT_SYMBOL(stedma40_filter);
  1974. static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
  1975. {
  1976. bool realtime = d40c->dma_cfg.realtime;
  1977. bool highprio = d40c->dma_cfg.high_priority;
  1978. u32 rtreg;
  1979. u32 event = D40_TYPE_TO_EVENT(dev_type);
  1980. u32 group = D40_TYPE_TO_GROUP(dev_type);
  1981. u32 bit = BIT(event);
  1982. u32 prioreg;
  1983. struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
  1984. rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
  1985. /*
  1986. * Due to a hardware bug, in some cases a logical channel triggered by
  1987. * a high priority destination event line can generate extra packet
  1988. * transactions.
  1989. *
  1990. * The workaround is to not set the high priority level for the
  1991. * destination event lines that trigger logical channels.
  1992. */
  1993. if (!src && chan_is_logical(d40c))
  1994. highprio = false;
  1995. prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
  1996. /* Destination event lines are stored in the upper halfword */
  1997. if (!src)
  1998. bit <<= 16;
  1999. writel(bit, d40c->base->virtbase + prioreg + group * 4);
  2000. writel(bit, d40c->base->virtbase + rtreg + group * 4);
  2001. }
  2002. static void d40_set_prio_realtime(struct d40_chan *d40c)
  2003. {
  2004. if (d40c->base->rev < 3)
  2005. return;
  2006. if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
  2007. (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
  2008. __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
  2009. if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
  2010. (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
  2011. __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
  2012. }
  2013. #define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
  2014. #define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
  2015. #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
  2016. #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
  2017. static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
  2018. struct of_dma *ofdma)
  2019. {
  2020. struct stedma40_chan_cfg cfg;
  2021. dma_cap_mask_t cap;
  2022. u32 flags;
  2023. memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
  2024. dma_cap_zero(cap);
  2025. dma_cap_set(DMA_SLAVE, cap);
  2026. cfg.dev_type = dma_spec->args[0];
  2027. flags = dma_spec->args[2];
  2028. switch (D40_DT_FLAGS_MODE(flags)) {
  2029. case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
  2030. case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
  2031. }
  2032. switch (D40_DT_FLAGS_DIR(flags)) {
  2033. case 0:
  2034. cfg.dir = DMA_MEM_TO_DEV;
  2035. cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
  2036. break;
  2037. case 1:
  2038. cfg.dir = DMA_DEV_TO_MEM;
  2039. cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
  2040. break;
  2041. }
  2042. if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
  2043. cfg.phy_channel = dma_spec->args[1];
  2044. cfg.use_fixed_channel = true;
  2045. }
  2046. return dma_request_channel(cap, stedma40_filter, &cfg);
  2047. }
  2048. /* DMA ENGINE functions */
  2049. static int d40_alloc_chan_resources(struct dma_chan *chan)
  2050. {
  2051. int err;
  2052. unsigned long flags;
  2053. struct d40_chan *d40c =
  2054. container_of(chan, struct d40_chan, chan);
  2055. bool is_free_phy;
  2056. spin_lock_irqsave(&d40c->lock, flags);
  2057. dma_cookie_init(chan);
  2058. /* If no dma configuration is set use default configuration (memcpy) */
  2059. if (!d40c->configured) {
  2060. err = d40_config_memcpy(d40c);
  2061. if (err) {
  2062. chan_err(d40c, "Failed to configure memcpy channel\n");
  2063. goto fail;
  2064. }
  2065. }
  2066. err = d40_allocate_channel(d40c, &is_free_phy);
  2067. if (err) {
  2068. chan_err(d40c, "Failed to allocate channel\n");
  2069. d40c->configured = false;
  2070. goto fail;
  2071. }
  2072. pm_runtime_get_sync(d40c->base->dev);
  2073. d40_set_prio_realtime(d40c);
  2074. if (chan_is_logical(d40c)) {
  2075. if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
  2076. d40c->lcpa = d40c->base->lcpa_base +
  2077. d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
  2078. else
  2079. d40c->lcpa = d40c->base->lcpa_base +
  2080. d40c->dma_cfg.dev_type *
  2081. D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
  2082. /* Unmask the Global Interrupt Mask. */
  2083. d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
  2084. d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
  2085. }
  2086. dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
  2087. chan_is_logical(d40c) ? "logical" : "physical",
  2088. d40c->phy_chan->num,
  2089. d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
  2090. /*
  2091. * Only write channel configuration to the DMA if the physical
  2092. * resource is free. In case of multiple logical channels
  2093. * on the same physical resource, only the first write is necessary.
  2094. */
  2095. if (is_free_phy)
  2096. d40_config_write(d40c);
  2097. fail:
  2098. pm_runtime_mark_last_busy(d40c->base->dev);
  2099. pm_runtime_put_autosuspend(d40c->base->dev);
  2100. spin_unlock_irqrestore(&d40c->lock, flags);
  2101. return err;
  2102. }
  2103. static void d40_free_chan_resources(struct dma_chan *chan)
  2104. {
  2105. struct d40_chan *d40c =
  2106. container_of(chan, struct d40_chan, chan);
  2107. int err;
  2108. unsigned long flags;
  2109. if (d40c->phy_chan == NULL) {
  2110. chan_err(d40c, "Cannot free unallocated channel\n");
  2111. return;
  2112. }
  2113. spin_lock_irqsave(&d40c->lock, flags);
  2114. err = d40_free_dma(d40c);
  2115. if (err)
  2116. chan_err(d40c, "Failed to free channel\n");
  2117. spin_unlock_irqrestore(&d40c->lock, flags);
  2118. }
  2119. static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
  2120. dma_addr_t dst,
  2121. dma_addr_t src,
  2122. size_t size,
  2123. unsigned long dma_flags)
  2124. {
  2125. struct scatterlist dst_sg;
  2126. struct scatterlist src_sg;
  2127. sg_init_table(&dst_sg, 1);
  2128. sg_init_table(&src_sg, 1);
  2129. sg_dma_address(&dst_sg) = dst;
  2130. sg_dma_address(&src_sg) = src;
  2131. sg_dma_len(&dst_sg) = size;
  2132. sg_dma_len(&src_sg) = size;
  2133. return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
  2134. }
  2135. static struct dma_async_tx_descriptor *
  2136. d40_prep_memcpy_sg(struct dma_chan *chan,
  2137. struct scatterlist *dst_sg, unsigned int dst_nents,
  2138. struct scatterlist *src_sg, unsigned int src_nents,
  2139. unsigned long dma_flags)
  2140. {
  2141. if (dst_nents != src_nents)
  2142. return NULL;
  2143. return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
  2144. }
  2145. static struct dma_async_tx_descriptor *
  2146. d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  2147. unsigned int sg_len, enum dma_transfer_direction direction,
  2148. unsigned long dma_flags, void *context)
  2149. {
  2150. if (!is_slave_direction(direction))
  2151. return NULL;
  2152. return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
  2153. }
  2154. static struct dma_async_tx_descriptor *
  2155. dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
  2156. size_t buf_len, size_t period_len,
  2157. enum dma_transfer_direction direction, unsigned long flags,
  2158. void *context)
  2159. {
  2160. unsigned int periods = buf_len / period_len;
  2161. struct dma_async_tx_descriptor *txd;
  2162. struct scatterlist *sg;
  2163. int i;
  2164. sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
  2165. for (i = 0; i < periods; i++) {
  2166. sg_dma_address(&sg[i]) = dma_addr;
  2167. sg_dma_len(&sg[i]) = period_len;
  2168. dma_addr += period_len;
  2169. }
  2170. sg[periods].offset = 0;
  2171. sg_dma_len(&sg[periods]) = 0;
  2172. sg[periods].page_link =
  2173. ((unsigned long)sg | 0x01) & ~0x02;
  2174. txd = d40_prep_sg(chan, sg, sg, periods, direction,
  2175. DMA_PREP_INTERRUPT);
  2176. kfree(sg);
  2177. return txd;
  2178. }
  2179. static enum dma_status d40_tx_status(struct dma_chan *chan,
  2180. dma_cookie_t cookie,
  2181. struct dma_tx_state *txstate)
  2182. {
  2183. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2184. enum dma_status ret;
  2185. if (d40c->phy_chan == NULL) {
  2186. chan_err(d40c, "Cannot read status of unallocated channel\n");
  2187. return -EINVAL;
  2188. }
  2189. ret = dma_cookie_status(chan, cookie, txstate);
  2190. if (ret != DMA_SUCCESS)
  2191. dma_set_residue(txstate, stedma40_residue(chan));
  2192. if (d40_is_paused(d40c))
  2193. ret = DMA_PAUSED;
  2194. return ret;
  2195. }
  2196. static void d40_issue_pending(struct dma_chan *chan)
  2197. {
  2198. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2199. unsigned long flags;
  2200. if (d40c->phy_chan == NULL) {
  2201. chan_err(d40c, "Channel is not allocated!\n");
  2202. return;
  2203. }
  2204. spin_lock_irqsave(&d40c->lock, flags);
  2205. list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
  2206. /* Busy means that queued jobs are already being processed */
  2207. if (!d40c->busy)
  2208. (void) d40_queue_start(d40c);
  2209. spin_unlock_irqrestore(&d40c->lock, flags);
  2210. }
  2211. static void d40_terminate_all(struct dma_chan *chan)
  2212. {
  2213. unsigned long flags;
  2214. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2215. int ret;
  2216. spin_lock_irqsave(&d40c->lock, flags);
  2217. pm_runtime_get_sync(d40c->base->dev);
  2218. ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
  2219. if (ret)
  2220. chan_err(d40c, "Failed to stop channel\n");
  2221. d40_term_all(d40c);
  2222. pm_runtime_mark_last_busy(d40c->base->dev);
  2223. pm_runtime_put_autosuspend(d40c->base->dev);
  2224. if (d40c->busy) {
  2225. pm_runtime_mark_last_busy(d40c->base->dev);
  2226. pm_runtime_put_autosuspend(d40c->base->dev);
  2227. }
  2228. d40c->busy = false;
  2229. spin_unlock_irqrestore(&d40c->lock, flags);
  2230. }
  2231. static int
  2232. dma40_config_to_halfchannel(struct d40_chan *d40c,
  2233. struct stedma40_half_channel_info *info,
  2234. u32 maxburst)
  2235. {
  2236. int psize;
  2237. if (chan_is_logical(d40c)) {
  2238. if (maxburst >= 16)
  2239. psize = STEDMA40_PSIZE_LOG_16;
  2240. else if (maxburst >= 8)
  2241. psize = STEDMA40_PSIZE_LOG_8;
  2242. else if (maxburst >= 4)
  2243. psize = STEDMA40_PSIZE_LOG_4;
  2244. else
  2245. psize = STEDMA40_PSIZE_LOG_1;
  2246. } else {
  2247. if (maxburst >= 16)
  2248. psize = STEDMA40_PSIZE_PHY_16;
  2249. else if (maxburst >= 8)
  2250. psize = STEDMA40_PSIZE_PHY_8;
  2251. else if (maxburst >= 4)
  2252. psize = STEDMA40_PSIZE_PHY_4;
  2253. else
  2254. psize = STEDMA40_PSIZE_PHY_1;
  2255. }
  2256. info->psize = psize;
  2257. info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
  2258. return 0;
  2259. }
  2260. /* Runtime reconfiguration extension */
  2261. static int d40_set_runtime_config(struct dma_chan *chan,
  2262. struct dma_slave_config *config)
  2263. {
  2264. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2265. struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
  2266. enum dma_slave_buswidth src_addr_width, dst_addr_width;
  2267. dma_addr_t config_addr;
  2268. u32 src_maxburst, dst_maxburst;
  2269. int ret;
  2270. src_addr_width = config->src_addr_width;
  2271. src_maxburst = config->src_maxburst;
  2272. dst_addr_width = config->dst_addr_width;
  2273. dst_maxburst = config->dst_maxburst;
  2274. if (config->direction == DMA_DEV_TO_MEM) {
  2275. config_addr = config->src_addr;
  2276. if (cfg->dir != DMA_DEV_TO_MEM)
  2277. dev_dbg(d40c->base->dev,
  2278. "channel was not configured for peripheral "
  2279. "to memory transfer (%d) overriding\n",
  2280. cfg->dir);
  2281. cfg->dir = DMA_DEV_TO_MEM;
  2282. /* Configure the memory side */
  2283. if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  2284. dst_addr_width = src_addr_width;
  2285. if (dst_maxburst == 0)
  2286. dst_maxburst = src_maxburst;
  2287. } else if (config->direction == DMA_MEM_TO_DEV) {
  2288. config_addr = config->dst_addr;
  2289. if (cfg->dir != DMA_MEM_TO_DEV)
  2290. dev_dbg(d40c->base->dev,
  2291. "channel was not configured for memory "
  2292. "to peripheral transfer (%d) overriding\n",
  2293. cfg->dir);
  2294. cfg->dir = DMA_MEM_TO_DEV;
  2295. /* Configure the memory side */
  2296. if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  2297. src_addr_width = dst_addr_width;
  2298. if (src_maxburst == 0)
  2299. src_maxburst = dst_maxburst;
  2300. } else {
  2301. dev_err(d40c->base->dev,
  2302. "unrecognized channel direction %d\n",
  2303. config->direction);
  2304. return -EINVAL;
  2305. }
  2306. if (config_addr <= 0) {
  2307. dev_err(d40c->base->dev, "no address supplied\n");
  2308. return -EINVAL;
  2309. }
  2310. if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
  2311. dev_err(d40c->base->dev,
  2312. "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
  2313. src_maxburst,
  2314. src_addr_width,
  2315. dst_maxburst,
  2316. dst_addr_width);
  2317. return -EINVAL;
  2318. }
  2319. if (src_maxburst > 16) {
  2320. src_maxburst = 16;
  2321. dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
  2322. } else if (dst_maxburst > 16) {
  2323. dst_maxburst = 16;
  2324. src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
  2325. }
  2326. /* Only valid widths are; 1, 2, 4 and 8. */
  2327. if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
  2328. src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
  2329. dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
  2330. dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
  2331. ((src_addr_width > 1) && (src_addr_width & 1)) ||
  2332. ((dst_addr_width > 1) && (dst_addr_width & 1)))
  2333. return -EINVAL;
  2334. cfg->src_info.data_width = src_addr_width;
  2335. cfg->dst_info.data_width = dst_addr_width;
  2336. ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
  2337. src_maxburst);
  2338. if (ret)
  2339. return ret;
  2340. ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
  2341. dst_maxburst);
  2342. if (ret)
  2343. return ret;
  2344. /* Fill in register values */
  2345. if (chan_is_logical(d40c))
  2346. d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
  2347. else
  2348. d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
  2349. /* These settings will take precedence later */
  2350. d40c->runtime_addr = config_addr;
  2351. d40c->runtime_direction = config->direction;
  2352. dev_dbg(d40c->base->dev,
  2353. "configured channel %s for %s, data width %d/%d, "
  2354. "maxburst %d/%d elements, LE, no flow control\n",
  2355. dma_chan_name(chan),
  2356. (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
  2357. src_addr_width, dst_addr_width,
  2358. src_maxburst, dst_maxburst);
  2359. return 0;
  2360. }
  2361. static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
  2362. unsigned long arg)
  2363. {
  2364. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2365. if (d40c->phy_chan == NULL) {
  2366. chan_err(d40c, "Channel is not allocated!\n");
  2367. return -EINVAL;
  2368. }
  2369. switch (cmd) {
  2370. case DMA_TERMINATE_ALL:
  2371. d40_terminate_all(chan);
  2372. return 0;
  2373. case DMA_PAUSE:
  2374. return d40_pause(d40c);
  2375. case DMA_RESUME:
  2376. return d40_resume(d40c);
  2377. case DMA_SLAVE_CONFIG:
  2378. return d40_set_runtime_config(chan,
  2379. (struct dma_slave_config *) arg);
  2380. default:
  2381. break;
  2382. }
  2383. /* Other commands are unimplemented */
  2384. return -ENXIO;
  2385. }
  2386. /* Initialization functions */
  2387. static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
  2388. struct d40_chan *chans, int offset,
  2389. int num_chans)
  2390. {
  2391. int i = 0;
  2392. struct d40_chan *d40c;
  2393. INIT_LIST_HEAD(&dma->channels);
  2394. for (i = offset; i < offset + num_chans; i++) {
  2395. d40c = &chans[i];
  2396. d40c->base = base;
  2397. d40c->chan.device = dma;
  2398. spin_lock_init(&d40c->lock);
  2399. d40c->log_num = D40_PHY_CHAN;
  2400. INIT_LIST_HEAD(&d40c->done);
  2401. INIT_LIST_HEAD(&d40c->active);
  2402. INIT_LIST_HEAD(&d40c->queue);
  2403. INIT_LIST_HEAD(&d40c->pending_queue);
  2404. INIT_LIST_HEAD(&d40c->client);
  2405. INIT_LIST_HEAD(&d40c->prepare_queue);
  2406. tasklet_init(&d40c->tasklet, dma_tasklet,
  2407. (unsigned long) d40c);
  2408. list_add_tail(&d40c->chan.device_node,
  2409. &dma->channels);
  2410. }
  2411. }
  2412. static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
  2413. {
  2414. if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
  2415. dev->device_prep_slave_sg = d40_prep_slave_sg;
  2416. if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
  2417. dev->device_prep_dma_memcpy = d40_prep_memcpy;
  2418. /*
  2419. * This controller can only access address at even
  2420. * 32bit boundaries, i.e. 2^2
  2421. */
  2422. dev->copy_align = 2;
  2423. }
  2424. if (dma_has_cap(DMA_SG, dev->cap_mask))
  2425. dev->device_prep_dma_sg = d40_prep_memcpy_sg;
  2426. if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
  2427. dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
  2428. dev->device_alloc_chan_resources = d40_alloc_chan_resources;
  2429. dev->device_free_chan_resources = d40_free_chan_resources;
  2430. dev->device_issue_pending = d40_issue_pending;
  2431. dev->device_tx_status = d40_tx_status;
  2432. dev->device_control = d40_control;
  2433. dev->dev = base->dev;
  2434. }
  2435. static int __init d40_dmaengine_init(struct d40_base *base,
  2436. int num_reserved_chans)
  2437. {
  2438. int err ;
  2439. d40_chan_init(base, &base->dma_slave, base->log_chans,
  2440. 0, base->num_log_chans);
  2441. dma_cap_zero(base->dma_slave.cap_mask);
  2442. dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
  2443. dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
  2444. d40_ops_init(base, &base->dma_slave);
  2445. err = dma_async_device_register(&base->dma_slave);
  2446. if (err) {
  2447. d40_err(base->dev, "Failed to register slave channels\n");
  2448. goto failure1;
  2449. }
  2450. d40_chan_init(base, &base->dma_memcpy, base->log_chans,
  2451. base->num_log_chans, base->num_memcpy_chans);
  2452. dma_cap_zero(base->dma_memcpy.cap_mask);
  2453. dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
  2454. dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
  2455. d40_ops_init(base, &base->dma_memcpy);
  2456. err = dma_async_device_register(&base->dma_memcpy);
  2457. if (err) {
  2458. d40_err(base->dev,
  2459. "Failed to regsiter memcpy only channels\n");
  2460. goto failure2;
  2461. }
  2462. d40_chan_init(base, &base->dma_both, base->phy_chans,
  2463. 0, num_reserved_chans);
  2464. dma_cap_zero(base->dma_both.cap_mask);
  2465. dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
  2466. dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
  2467. dma_cap_set(DMA_SG, base->dma_both.cap_mask);
  2468. dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
  2469. d40_ops_init(base, &base->dma_both);
  2470. err = dma_async_device_register(&base->dma_both);
  2471. if (err) {
  2472. d40_err(base->dev,
  2473. "Failed to register logical and physical capable channels\n");
  2474. goto failure3;
  2475. }
  2476. return 0;
  2477. failure3:
  2478. dma_async_device_unregister(&base->dma_memcpy);
  2479. failure2:
  2480. dma_async_device_unregister(&base->dma_slave);
  2481. failure1:
  2482. return err;
  2483. }
  2484. /* Suspend resume functionality */
  2485. #ifdef CONFIG_PM
  2486. static int dma40_pm_suspend(struct device *dev)
  2487. {
  2488. struct platform_device *pdev = to_platform_device(dev);
  2489. struct d40_base *base = platform_get_drvdata(pdev);
  2490. int ret = 0;
  2491. if (base->lcpa_regulator)
  2492. ret = regulator_disable(base->lcpa_regulator);
  2493. return ret;
  2494. }
  2495. static int dma40_runtime_suspend(struct device *dev)
  2496. {
  2497. struct platform_device *pdev = to_platform_device(dev);
  2498. struct d40_base *base = platform_get_drvdata(pdev);
  2499. d40_save_restore_registers(base, true);
  2500. /* Don't disable/enable clocks for v1 due to HW bugs */
  2501. if (base->rev != 1)
  2502. writel_relaxed(base->gcc_pwr_off_mask,
  2503. base->virtbase + D40_DREG_GCC);
  2504. return 0;
  2505. }
  2506. static int dma40_runtime_resume(struct device *dev)
  2507. {
  2508. struct platform_device *pdev = to_platform_device(dev);
  2509. struct d40_base *base = platform_get_drvdata(pdev);
  2510. if (base->initialized)
  2511. d40_save_restore_registers(base, false);
  2512. writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
  2513. base->virtbase + D40_DREG_GCC);
  2514. return 0;
  2515. }
  2516. static int dma40_resume(struct device *dev)
  2517. {
  2518. struct platform_device *pdev = to_platform_device(dev);
  2519. struct d40_base *base = platform_get_drvdata(pdev);
  2520. int ret = 0;
  2521. if (base->lcpa_regulator)
  2522. ret = regulator_enable(base->lcpa_regulator);
  2523. return ret;
  2524. }
  2525. static const struct dev_pm_ops dma40_pm_ops = {
  2526. .suspend = dma40_pm_suspend,
  2527. .runtime_suspend = dma40_runtime_suspend,
  2528. .runtime_resume = dma40_runtime_resume,
  2529. .resume = dma40_resume,
  2530. };
  2531. #define DMA40_PM_OPS (&dma40_pm_ops)
  2532. #else
  2533. #define DMA40_PM_OPS NULL
  2534. #endif
  2535. /* Initialization functions. */
  2536. static int __init d40_phy_res_init(struct d40_base *base)
  2537. {
  2538. int i;
  2539. int num_phy_chans_avail = 0;
  2540. u32 val[2];
  2541. int odd_even_bit = -2;
  2542. int gcc = D40_DREG_GCC_ENA;
  2543. val[0] = readl(base->virtbase + D40_DREG_PRSME);
  2544. val[1] = readl(base->virtbase + D40_DREG_PRSMO);
  2545. for (i = 0; i < base->num_phy_chans; i++) {
  2546. base->phy_res[i].num = i;
  2547. odd_even_bit += 2 * ((i % 2) == 0);
  2548. if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
  2549. /* Mark security only channels as occupied */
  2550. base->phy_res[i].allocated_src = D40_ALLOC_PHY;
  2551. base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
  2552. base->phy_res[i].reserved = true;
  2553. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
  2554. D40_DREG_GCC_SRC);
  2555. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
  2556. D40_DREG_GCC_DST);
  2557. } else {
  2558. base->phy_res[i].allocated_src = D40_ALLOC_FREE;
  2559. base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
  2560. base->phy_res[i].reserved = false;
  2561. num_phy_chans_avail++;
  2562. }
  2563. spin_lock_init(&base->phy_res[i].lock);
  2564. }
  2565. /* Mark disabled channels as occupied */
  2566. for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
  2567. int chan = base->plat_data->disabled_channels[i];
  2568. base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
  2569. base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
  2570. base->phy_res[chan].reserved = true;
  2571. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
  2572. D40_DREG_GCC_SRC);
  2573. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
  2574. D40_DREG_GCC_DST);
  2575. num_phy_chans_avail--;
  2576. }
  2577. /* Mark soft_lli channels */
  2578. for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
  2579. int chan = base->plat_data->soft_lli_chans[i];
  2580. base->phy_res[chan].use_soft_lli = true;
  2581. }
  2582. dev_info(base->dev, "%d of %d physical DMA channels available\n",
  2583. num_phy_chans_avail, base->num_phy_chans);
  2584. /* Verify settings extended vs standard */
  2585. val[0] = readl(base->virtbase + D40_DREG_PRTYP);
  2586. for (i = 0; i < base->num_phy_chans; i++) {
  2587. if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
  2588. (val[0] & 0x3) != 1)
  2589. dev_info(base->dev,
  2590. "[%s] INFO: channel %d is misconfigured (%d)\n",
  2591. __func__, i, val[0] & 0x3);
  2592. val[0] = val[0] >> 2;
  2593. }
  2594. /*
  2595. * To keep things simple, Enable all clocks initially.
  2596. * The clocks will get managed later post channel allocation.
  2597. * The clocks for the event lines on which reserved channels exists
  2598. * are not managed here.
  2599. */
  2600. writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
  2601. base->gcc_pwr_off_mask = gcc;
  2602. return num_phy_chans_avail;
  2603. }
  2604. static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
  2605. {
  2606. struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
  2607. struct clk *clk = NULL;
  2608. void __iomem *virtbase = NULL;
  2609. struct resource *res = NULL;
  2610. struct d40_base *base = NULL;
  2611. int num_log_chans = 0;
  2612. int num_phy_chans;
  2613. int num_memcpy_chans;
  2614. int clk_ret = -EINVAL;
  2615. int i;
  2616. u32 pid;
  2617. u32 cid;
  2618. u8 rev;
  2619. clk = clk_get(&pdev->dev, NULL);
  2620. if (IS_ERR(clk)) {
  2621. d40_err(&pdev->dev, "No matching clock found\n");
  2622. goto failure;
  2623. }
  2624. clk_ret = clk_prepare_enable(clk);
  2625. if (clk_ret) {
  2626. d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
  2627. goto failure;
  2628. }
  2629. /* Get IO for DMAC base address */
  2630. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
  2631. if (!res)
  2632. goto failure;
  2633. if (request_mem_region(res->start, resource_size(res),
  2634. D40_NAME " I/O base") == NULL)
  2635. goto failure;
  2636. virtbase = ioremap(res->start, resource_size(res));
  2637. if (!virtbase)
  2638. goto failure;
  2639. /* This is just a regular AMBA PrimeCell ID actually */
  2640. for (pid = 0, i = 0; i < 4; i++)
  2641. pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
  2642. & 255) << (i * 8);
  2643. for (cid = 0, i = 0; i < 4; i++)
  2644. cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
  2645. & 255) << (i * 8);
  2646. if (cid != AMBA_CID) {
  2647. d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
  2648. goto failure;
  2649. }
  2650. if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
  2651. d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
  2652. AMBA_MANF_BITS(pid),
  2653. AMBA_VENDOR_ST);
  2654. goto failure;
  2655. }
  2656. /*
  2657. * HW revision:
  2658. * DB8500ed has revision 0
  2659. * ? has revision 1
  2660. * DB8500v1 has revision 2
  2661. * DB8500v2 has revision 3
  2662. * AP9540v1 has revision 4
  2663. * DB8540v1 has revision 4
  2664. */
  2665. rev = AMBA_REV_BITS(pid);
  2666. if (rev < 2) {
  2667. d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
  2668. goto failure;
  2669. }
  2670. /* The number of physical channels on this HW */
  2671. if (plat_data->num_of_phy_chans)
  2672. num_phy_chans = plat_data->num_of_phy_chans;
  2673. else
  2674. num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
  2675. /* The number of channels used for memcpy */
  2676. if (plat_data->num_of_memcpy_chans)
  2677. num_memcpy_chans = plat_data->num_of_memcpy_chans;
  2678. else
  2679. num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
  2680. num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
  2681. dev_info(&pdev->dev,
  2682. "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n",
  2683. rev, res->start, num_phy_chans, num_log_chans);
  2684. base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
  2685. (num_phy_chans + num_log_chans + num_memcpy_chans) *
  2686. sizeof(struct d40_chan), GFP_KERNEL);
  2687. if (base == NULL) {
  2688. d40_err(&pdev->dev, "Out of memory\n");
  2689. goto failure;
  2690. }
  2691. base->rev = rev;
  2692. base->clk = clk;
  2693. base->num_memcpy_chans = num_memcpy_chans;
  2694. base->num_phy_chans = num_phy_chans;
  2695. base->num_log_chans = num_log_chans;
  2696. base->phy_start = res->start;
  2697. base->phy_size = resource_size(res);
  2698. base->virtbase = virtbase;
  2699. base->plat_data = plat_data;
  2700. base->dev = &pdev->dev;
  2701. base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
  2702. base->log_chans = &base->phy_chans[num_phy_chans];
  2703. if (base->plat_data->num_of_phy_chans == 14) {
  2704. base->gen_dmac.backup = d40_backup_regs_v4b;
  2705. base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
  2706. base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
  2707. base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
  2708. base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
  2709. base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
  2710. base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
  2711. base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
  2712. base->gen_dmac.il = il_v4b;
  2713. base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
  2714. base->gen_dmac.init_reg = dma_init_reg_v4b;
  2715. base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
  2716. } else {
  2717. if (base->rev >= 3) {
  2718. base->gen_dmac.backup = d40_backup_regs_v4a;
  2719. base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
  2720. }
  2721. base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
  2722. base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
  2723. base->gen_dmac.realtime_en = D40_DREG_RSEG1;
  2724. base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
  2725. base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
  2726. base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
  2727. base->gen_dmac.il = il_v4a;
  2728. base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
  2729. base->gen_dmac.init_reg = dma_init_reg_v4a;
  2730. base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
  2731. }
  2732. base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
  2733. GFP_KERNEL);
  2734. if (!base->phy_res)
  2735. goto failure;
  2736. base->lookup_phy_chans = kzalloc(num_phy_chans *
  2737. sizeof(struct d40_chan *),
  2738. GFP_KERNEL);
  2739. if (!base->lookup_phy_chans)
  2740. goto failure;
  2741. base->lookup_log_chans = kzalloc(num_log_chans *
  2742. sizeof(struct d40_chan *),
  2743. GFP_KERNEL);
  2744. if (!base->lookup_log_chans)
  2745. goto failure;
  2746. base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
  2747. sizeof(d40_backup_regs_chan),
  2748. GFP_KERNEL);
  2749. if (!base->reg_val_backup_chan)
  2750. goto failure;
  2751. base->lcla_pool.alloc_map =
  2752. kzalloc(num_phy_chans * sizeof(struct d40_desc *)
  2753. * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
  2754. if (!base->lcla_pool.alloc_map)
  2755. goto failure;
  2756. base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
  2757. 0, SLAB_HWCACHE_ALIGN,
  2758. NULL);
  2759. if (base->desc_slab == NULL)
  2760. goto failure;
  2761. return base;
  2762. failure:
  2763. if (!clk_ret)
  2764. clk_disable_unprepare(clk);
  2765. if (!IS_ERR(clk))
  2766. clk_put(clk);
  2767. if (virtbase)
  2768. iounmap(virtbase);
  2769. if (res)
  2770. release_mem_region(res->start,
  2771. resource_size(res));
  2772. if (virtbase)
  2773. iounmap(virtbase);
  2774. if (base) {
  2775. kfree(base->lcla_pool.alloc_map);
  2776. kfree(base->reg_val_backup_chan);
  2777. kfree(base->lookup_log_chans);
  2778. kfree(base->lookup_phy_chans);
  2779. kfree(base->phy_res);
  2780. kfree(base);
  2781. }
  2782. return NULL;
  2783. }
  2784. static void __init d40_hw_init(struct d40_base *base)
  2785. {
  2786. int i;
  2787. u32 prmseo[2] = {0, 0};
  2788. u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
  2789. u32 pcmis = 0;
  2790. u32 pcicr = 0;
  2791. struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
  2792. u32 reg_size = base->gen_dmac.init_reg_size;
  2793. for (i = 0; i < reg_size; i++)
  2794. writel(dma_init_reg[i].val,
  2795. base->virtbase + dma_init_reg[i].reg);
  2796. /* Configure all our dma channels to default settings */
  2797. for (i = 0; i < base->num_phy_chans; i++) {
  2798. activeo[i % 2] = activeo[i % 2] << 2;
  2799. if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
  2800. == D40_ALLOC_PHY) {
  2801. activeo[i % 2] |= 3;
  2802. continue;
  2803. }
  2804. /* Enable interrupt # */
  2805. pcmis = (pcmis << 1) | 1;
  2806. /* Clear interrupt # */
  2807. pcicr = (pcicr << 1) | 1;
  2808. /* Set channel to physical mode */
  2809. prmseo[i % 2] = prmseo[i % 2] << 2;
  2810. prmseo[i % 2] |= 1;
  2811. }
  2812. writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
  2813. writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
  2814. writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
  2815. writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
  2816. /* Write which interrupt to enable */
  2817. writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
  2818. /* Write which interrupt to clear */
  2819. writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
  2820. /* These are __initdata and cannot be accessed after init */
  2821. base->gen_dmac.init_reg = NULL;
  2822. base->gen_dmac.init_reg_size = 0;
  2823. }
  2824. static int __init d40_lcla_allocate(struct d40_base *base)
  2825. {
  2826. struct d40_lcla_pool *pool = &base->lcla_pool;
  2827. unsigned long *page_list;
  2828. int i, j;
  2829. int ret = 0;
  2830. /*
  2831. * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
  2832. * To full fill this hardware requirement without wasting 256 kb
  2833. * we allocate pages until we get an aligned one.
  2834. */
  2835. page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
  2836. GFP_KERNEL);
  2837. if (!page_list) {
  2838. ret = -ENOMEM;
  2839. goto failure;
  2840. }
  2841. /* Calculating how many pages that are required */
  2842. base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
  2843. for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
  2844. page_list[i] = __get_free_pages(GFP_KERNEL,
  2845. base->lcla_pool.pages);
  2846. if (!page_list[i]) {
  2847. d40_err(base->dev, "Failed to allocate %d pages.\n",
  2848. base->lcla_pool.pages);
  2849. for (j = 0; j < i; j++)
  2850. free_pages(page_list[j], base->lcla_pool.pages);
  2851. goto failure;
  2852. }
  2853. if ((virt_to_phys((void *)page_list[i]) &
  2854. (LCLA_ALIGNMENT - 1)) == 0)
  2855. break;
  2856. }
  2857. for (j = 0; j < i; j++)
  2858. free_pages(page_list[j], base->lcla_pool.pages);
  2859. if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
  2860. base->lcla_pool.base = (void *)page_list[i];
  2861. } else {
  2862. /*
  2863. * After many attempts and no succees with finding the correct
  2864. * alignment, try with allocating a big buffer.
  2865. */
  2866. dev_warn(base->dev,
  2867. "[%s] Failed to get %d pages @ 18 bit align.\n",
  2868. __func__, base->lcla_pool.pages);
  2869. base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
  2870. base->num_phy_chans +
  2871. LCLA_ALIGNMENT,
  2872. GFP_KERNEL);
  2873. if (!base->lcla_pool.base_unaligned) {
  2874. ret = -ENOMEM;
  2875. goto failure;
  2876. }
  2877. base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
  2878. LCLA_ALIGNMENT);
  2879. }
  2880. pool->dma_addr = dma_map_single(base->dev, pool->base,
  2881. SZ_1K * base->num_phy_chans,
  2882. DMA_TO_DEVICE);
  2883. if (dma_mapping_error(base->dev, pool->dma_addr)) {
  2884. pool->dma_addr = 0;
  2885. ret = -ENOMEM;
  2886. goto failure;
  2887. }
  2888. writel(virt_to_phys(base->lcla_pool.base),
  2889. base->virtbase + D40_DREG_LCLA);
  2890. failure:
  2891. kfree(page_list);
  2892. return ret;
  2893. }
  2894. static int __init d40_of_probe(struct platform_device *pdev,
  2895. struct device_node *np)
  2896. {
  2897. struct stedma40_platform_data *pdata;
  2898. int num_phy = 0, num_memcpy = 0, num_disabled = 0;
  2899. const const __be32 *list;
  2900. pdata = devm_kzalloc(&pdev->dev,
  2901. sizeof(struct stedma40_platform_data),
  2902. GFP_KERNEL);
  2903. if (!pdata)
  2904. return -ENOMEM;
  2905. /* If absent this value will be obtained from h/w. */
  2906. of_property_read_u32(np, "dma-channels", &num_phy);
  2907. if (num_phy > 0)
  2908. pdata->num_of_phy_chans = num_phy;
  2909. list = of_get_property(np, "memcpy-channels", &num_memcpy);
  2910. num_memcpy /= sizeof(*list);
  2911. if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
  2912. d40_err(&pdev->dev,
  2913. "Invalid number of memcpy channels specified (%d)\n",
  2914. num_memcpy);
  2915. return -EINVAL;
  2916. }
  2917. pdata->num_of_memcpy_chans = num_memcpy;
  2918. of_property_read_u32_array(np, "memcpy-channels",
  2919. dma40_memcpy_channels,
  2920. num_memcpy);
  2921. list = of_get_property(np, "disabled-channels", &num_disabled);
  2922. num_disabled /= sizeof(*list);
  2923. if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
  2924. d40_err(&pdev->dev,
  2925. "Invalid number of disabled channels specified (%d)\n",
  2926. num_disabled);
  2927. return -EINVAL;
  2928. }
  2929. of_property_read_u32_array(np, "disabled-channels",
  2930. pdata->disabled_channels,
  2931. num_disabled);
  2932. pdata->disabled_channels[num_disabled] = -1;
  2933. pdev->dev.platform_data = pdata;
  2934. return 0;
  2935. }
  2936. static int __init d40_probe(struct platform_device *pdev)
  2937. {
  2938. struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
  2939. struct device_node *np = pdev->dev.of_node;
  2940. int ret = -ENOENT;
  2941. struct d40_base *base = NULL;
  2942. struct resource *res = NULL;
  2943. int num_reserved_chans;
  2944. u32 val;
  2945. if (!plat_data) {
  2946. if (np) {
  2947. if(d40_of_probe(pdev, np)) {
  2948. ret = -ENOMEM;
  2949. goto failure;
  2950. }
  2951. } else {
  2952. d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
  2953. goto failure;
  2954. }
  2955. }
  2956. base = d40_hw_detect_init(pdev);
  2957. if (!base)
  2958. goto failure;
  2959. num_reserved_chans = d40_phy_res_init(base);
  2960. platform_set_drvdata(pdev, base);
  2961. spin_lock_init(&base->interrupt_lock);
  2962. spin_lock_init(&base->execmd_lock);
  2963. /* Get IO for logical channel parameter address */
  2964. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
  2965. if (!res) {
  2966. ret = -ENOENT;
  2967. d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
  2968. goto failure;
  2969. }
  2970. base->lcpa_size = resource_size(res);
  2971. base->phy_lcpa = res->start;
  2972. if (request_mem_region(res->start, resource_size(res),
  2973. D40_NAME " I/O lcpa") == NULL) {
  2974. ret = -EBUSY;
  2975. d40_err(&pdev->dev,
  2976. "Failed to request LCPA region 0x%x-0x%x\n",
  2977. res->start, res->end);
  2978. goto failure;
  2979. }
  2980. /* We make use of ESRAM memory for this. */
  2981. val = readl(base->virtbase + D40_DREG_LCPA);
  2982. if (res->start != val && val != 0) {
  2983. dev_warn(&pdev->dev,
  2984. "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
  2985. __func__, val, res->start);
  2986. } else
  2987. writel(res->start, base->virtbase + D40_DREG_LCPA);
  2988. base->lcpa_base = ioremap(res->start, resource_size(res));
  2989. if (!base->lcpa_base) {
  2990. ret = -ENOMEM;
  2991. d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
  2992. goto failure;
  2993. }
  2994. /* If lcla has to be located in ESRAM we don't need to allocate */
  2995. if (base->plat_data->use_esram_lcla) {
  2996. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  2997. "lcla_esram");
  2998. if (!res) {
  2999. ret = -ENOENT;
  3000. d40_err(&pdev->dev,
  3001. "No \"lcla_esram\" memory resource\n");
  3002. goto failure;
  3003. }
  3004. base->lcla_pool.base = ioremap(res->start,
  3005. resource_size(res));
  3006. if (!base->lcla_pool.base) {
  3007. ret = -ENOMEM;
  3008. d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
  3009. goto failure;
  3010. }
  3011. writel(res->start, base->virtbase + D40_DREG_LCLA);
  3012. } else {
  3013. ret = d40_lcla_allocate(base);
  3014. if (ret) {
  3015. d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
  3016. goto failure;
  3017. }
  3018. }
  3019. spin_lock_init(&base->lcla_pool.lock);
  3020. base->irq = platform_get_irq(pdev, 0);
  3021. ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
  3022. if (ret) {
  3023. d40_err(&pdev->dev, "No IRQ defined\n");
  3024. goto failure;
  3025. }
  3026. pm_runtime_irq_safe(base->dev);
  3027. pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
  3028. pm_runtime_use_autosuspend(base->dev);
  3029. pm_runtime_enable(base->dev);
  3030. pm_runtime_resume(base->dev);
  3031. if (base->plat_data->use_esram_lcla) {
  3032. base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
  3033. if (IS_ERR(base->lcpa_regulator)) {
  3034. d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
  3035. ret = PTR_ERR(base->lcpa_regulator);
  3036. base->lcpa_regulator = NULL;
  3037. goto failure;
  3038. }
  3039. ret = regulator_enable(base->lcpa_regulator);
  3040. if (ret) {
  3041. d40_err(&pdev->dev,
  3042. "Failed to enable lcpa_regulator\n");
  3043. regulator_put(base->lcpa_regulator);
  3044. base->lcpa_regulator = NULL;
  3045. goto failure;
  3046. }
  3047. }
  3048. base->initialized = true;
  3049. ret = d40_dmaengine_init(base, num_reserved_chans);
  3050. if (ret)
  3051. goto failure;
  3052. base->dev->dma_parms = &base->dma_parms;
  3053. ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
  3054. if (ret) {
  3055. d40_err(&pdev->dev, "Failed to set dma max seg size\n");
  3056. goto failure;
  3057. }
  3058. d40_hw_init(base);
  3059. if (np) {
  3060. ret = of_dma_controller_register(np, d40_xlate, NULL);
  3061. if (ret)
  3062. dev_err(&pdev->dev,
  3063. "could not register of_dma_controller\n");
  3064. }
  3065. dev_info(base->dev, "initialized\n");
  3066. return 0;
  3067. failure:
  3068. if (base) {
  3069. if (base->desc_slab)
  3070. kmem_cache_destroy(base->desc_slab);
  3071. if (base->virtbase)
  3072. iounmap(base->virtbase);
  3073. if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
  3074. iounmap(base->lcla_pool.base);
  3075. base->lcla_pool.base = NULL;
  3076. }
  3077. if (base->lcla_pool.dma_addr)
  3078. dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
  3079. SZ_1K * base->num_phy_chans,
  3080. DMA_TO_DEVICE);
  3081. if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
  3082. free_pages((unsigned long)base->lcla_pool.base,
  3083. base->lcla_pool.pages);
  3084. kfree(base->lcla_pool.base_unaligned);
  3085. if (base->phy_lcpa)
  3086. release_mem_region(base->phy_lcpa,
  3087. base->lcpa_size);
  3088. if (base->phy_start)
  3089. release_mem_region(base->phy_start,
  3090. base->phy_size);
  3091. if (base->clk) {
  3092. clk_disable_unprepare(base->clk);
  3093. clk_put(base->clk);
  3094. }
  3095. if (base->lcpa_regulator) {
  3096. regulator_disable(base->lcpa_regulator);
  3097. regulator_put(base->lcpa_regulator);
  3098. }
  3099. kfree(base->lcla_pool.alloc_map);
  3100. kfree(base->lookup_log_chans);
  3101. kfree(base->lookup_phy_chans);
  3102. kfree(base->phy_res);
  3103. kfree(base);
  3104. }
  3105. d40_err(&pdev->dev, "probe failed\n");
  3106. return ret;
  3107. }
  3108. static const struct of_device_id d40_match[] = {
  3109. { .compatible = "stericsson,dma40", },
  3110. {}
  3111. };
  3112. static struct platform_driver d40_driver = {
  3113. .driver = {
  3114. .owner = THIS_MODULE,
  3115. .name = D40_NAME,
  3116. .pm = DMA40_PM_OPS,
  3117. .of_match_table = d40_match,
  3118. },
  3119. };
  3120. static int __init stedma40_init(void)
  3121. {
  3122. return platform_driver_probe(&d40_driver, d40_probe);
  3123. }
  3124. subsys_initcall(stedma40_init);