dmaengine.c 29 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/acpi.h>
  63. #include <linux/acpi_dma.h>
  64. #include <linux/of_dma.h>
  65. static DEFINE_MUTEX(dma_list_mutex);
  66. static DEFINE_IDR(dma_idr);
  67. static LIST_HEAD(dma_device_list);
  68. static long dmaengine_ref_count;
  69. /* --- sysfs implementation --- */
  70. /**
  71. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  72. * @dev - device node
  73. *
  74. * Must be called under dma_list_mutex
  75. */
  76. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  77. {
  78. struct dma_chan_dev *chan_dev;
  79. chan_dev = container_of(dev, typeof(*chan_dev), device);
  80. return chan_dev->chan;
  81. }
  82. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  83. {
  84. struct dma_chan *chan;
  85. unsigned long count = 0;
  86. int i;
  87. int err;
  88. mutex_lock(&dma_list_mutex);
  89. chan = dev_to_dma_chan(dev);
  90. if (chan) {
  91. for_each_possible_cpu(i)
  92. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  93. err = sprintf(buf, "%lu\n", count);
  94. } else
  95. err = -ENODEV;
  96. mutex_unlock(&dma_list_mutex);
  97. return err;
  98. }
  99. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  100. char *buf)
  101. {
  102. struct dma_chan *chan;
  103. unsigned long count = 0;
  104. int i;
  105. int err;
  106. mutex_lock(&dma_list_mutex);
  107. chan = dev_to_dma_chan(dev);
  108. if (chan) {
  109. for_each_possible_cpu(i)
  110. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  111. err = sprintf(buf, "%lu\n", count);
  112. } else
  113. err = -ENODEV;
  114. mutex_unlock(&dma_list_mutex);
  115. return err;
  116. }
  117. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  118. {
  119. struct dma_chan *chan;
  120. int err;
  121. mutex_lock(&dma_list_mutex);
  122. chan = dev_to_dma_chan(dev);
  123. if (chan)
  124. err = sprintf(buf, "%d\n", chan->client_count);
  125. else
  126. err = -ENODEV;
  127. mutex_unlock(&dma_list_mutex);
  128. return err;
  129. }
  130. static struct device_attribute dma_attrs[] = {
  131. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  132. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  133. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  134. __ATTR_NULL
  135. };
  136. static void chan_dev_release(struct device *dev)
  137. {
  138. struct dma_chan_dev *chan_dev;
  139. chan_dev = container_of(dev, typeof(*chan_dev), device);
  140. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  141. mutex_lock(&dma_list_mutex);
  142. idr_remove(&dma_idr, chan_dev->dev_id);
  143. mutex_unlock(&dma_list_mutex);
  144. kfree(chan_dev->idr_ref);
  145. }
  146. kfree(chan_dev);
  147. }
  148. static struct class dma_devclass = {
  149. .name = "dma",
  150. .dev_attrs = dma_attrs,
  151. .dev_release = chan_dev_release,
  152. };
  153. /* --- client and device registration --- */
  154. #define dma_device_satisfies_mask(device, mask) \
  155. __dma_device_satisfies_mask((device), &(mask))
  156. static int
  157. __dma_device_satisfies_mask(struct dma_device *device,
  158. const dma_cap_mask_t *want)
  159. {
  160. dma_cap_mask_t has;
  161. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  162. DMA_TX_TYPE_END);
  163. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  164. }
  165. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  166. {
  167. return chan->device->dev->driver->owner;
  168. }
  169. /**
  170. * balance_ref_count - catch up the channel reference count
  171. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  172. *
  173. * balance_ref_count must be called under dma_list_mutex
  174. */
  175. static void balance_ref_count(struct dma_chan *chan)
  176. {
  177. struct module *owner = dma_chan_to_owner(chan);
  178. while (chan->client_count < dmaengine_ref_count) {
  179. __module_get(owner);
  180. chan->client_count++;
  181. }
  182. }
  183. /**
  184. * dma_chan_get - try to grab a dma channel's parent driver module
  185. * @chan - channel to grab
  186. *
  187. * Must be called under dma_list_mutex
  188. */
  189. static int dma_chan_get(struct dma_chan *chan)
  190. {
  191. int err = -ENODEV;
  192. struct module *owner = dma_chan_to_owner(chan);
  193. if (chan->client_count) {
  194. __module_get(owner);
  195. err = 0;
  196. } else if (try_module_get(owner))
  197. err = 0;
  198. if (err == 0)
  199. chan->client_count++;
  200. /* allocate upon first client reference */
  201. if (chan->client_count == 1 && err == 0) {
  202. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  203. if (desc_cnt < 0) {
  204. err = desc_cnt;
  205. chan->client_count = 0;
  206. module_put(owner);
  207. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  208. balance_ref_count(chan);
  209. }
  210. return err;
  211. }
  212. /**
  213. * dma_chan_put - drop a reference to a dma channel's parent driver module
  214. * @chan - channel to release
  215. *
  216. * Must be called under dma_list_mutex
  217. */
  218. static void dma_chan_put(struct dma_chan *chan)
  219. {
  220. if (!chan->client_count)
  221. return; /* this channel failed alloc_chan_resources */
  222. chan->client_count--;
  223. module_put(dma_chan_to_owner(chan));
  224. if (chan->client_count == 0)
  225. chan->device->device_free_chan_resources(chan);
  226. }
  227. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  228. {
  229. enum dma_status status;
  230. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  231. dma_async_issue_pending(chan);
  232. do {
  233. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  234. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  235. pr_err("%s: timeout!\n", __func__);
  236. return DMA_ERROR;
  237. }
  238. if (status != DMA_IN_PROGRESS)
  239. break;
  240. cpu_relax();
  241. } while (1);
  242. return status;
  243. }
  244. EXPORT_SYMBOL(dma_sync_wait);
  245. /**
  246. * dma_cap_mask_all - enable iteration over all operation types
  247. */
  248. static dma_cap_mask_t dma_cap_mask_all;
  249. /**
  250. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  251. * @chan - associated channel for this entry
  252. */
  253. struct dma_chan_tbl_ent {
  254. struct dma_chan *chan;
  255. };
  256. /**
  257. * channel_table - percpu lookup table for memory-to-memory offload providers
  258. */
  259. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  260. static int __init dma_channel_table_init(void)
  261. {
  262. enum dma_transaction_type cap;
  263. int err = 0;
  264. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  265. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  266. * but are not associated with an operation so they do not need
  267. * an entry in the channel_table
  268. */
  269. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  270. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  271. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  272. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  273. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  274. if (!channel_table[cap]) {
  275. err = -ENOMEM;
  276. break;
  277. }
  278. }
  279. if (err) {
  280. pr_err("initialization failure\n");
  281. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  282. if (channel_table[cap])
  283. free_percpu(channel_table[cap]);
  284. }
  285. return err;
  286. }
  287. arch_initcall(dma_channel_table_init);
  288. /**
  289. * dma_find_channel - find a channel to carry out the operation
  290. * @tx_type: transaction type
  291. */
  292. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  293. {
  294. return this_cpu_read(channel_table[tx_type]->chan);
  295. }
  296. EXPORT_SYMBOL(dma_find_channel);
  297. /*
  298. * net_dma_find_channel - find a channel for net_dma
  299. * net_dma has alignment requirements
  300. */
  301. struct dma_chan *net_dma_find_channel(void)
  302. {
  303. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  304. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  305. return NULL;
  306. return chan;
  307. }
  308. EXPORT_SYMBOL(net_dma_find_channel);
  309. /**
  310. * dma_issue_pending_all - flush all pending operations across all channels
  311. */
  312. void dma_issue_pending_all(void)
  313. {
  314. struct dma_device *device;
  315. struct dma_chan *chan;
  316. rcu_read_lock();
  317. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  318. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  319. continue;
  320. list_for_each_entry(chan, &device->channels, device_node)
  321. if (chan->client_count)
  322. device->device_issue_pending(chan);
  323. }
  324. rcu_read_unlock();
  325. }
  326. EXPORT_SYMBOL(dma_issue_pending_all);
  327. /**
  328. * nth_chan - returns the nth channel of the given capability
  329. * @cap: capability to match
  330. * @n: nth channel desired
  331. *
  332. * Defaults to returning the channel with the desired capability and the
  333. * lowest reference count when 'n' cannot be satisfied. Must be called
  334. * under dma_list_mutex.
  335. */
  336. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  337. {
  338. struct dma_device *device;
  339. struct dma_chan *chan;
  340. struct dma_chan *ret = NULL;
  341. struct dma_chan *min = NULL;
  342. list_for_each_entry(device, &dma_device_list, global_node) {
  343. if (!dma_has_cap(cap, device->cap_mask) ||
  344. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  345. continue;
  346. list_for_each_entry(chan, &device->channels, device_node) {
  347. if (!chan->client_count)
  348. continue;
  349. if (!min)
  350. min = chan;
  351. else if (chan->table_count < min->table_count)
  352. min = chan;
  353. if (n-- == 0) {
  354. ret = chan;
  355. break; /* done */
  356. }
  357. }
  358. if (ret)
  359. break; /* done */
  360. }
  361. if (!ret)
  362. ret = min;
  363. if (ret)
  364. ret->table_count++;
  365. return ret;
  366. }
  367. /**
  368. * dma_channel_rebalance - redistribute the available channels
  369. *
  370. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  371. * operation type) in the SMP case, and operation isolation (avoid
  372. * multi-tasking channels) in the non-SMP case. Must be called under
  373. * dma_list_mutex.
  374. */
  375. static void dma_channel_rebalance(void)
  376. {
  377. struct dma_chan *chan;
  378. struct dma_device *device;
  379. int cpu;
  380. int cap;
  381. int n;
  382. /* undo the last distribution */
  383. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  384. for_each_possible_cpu(cpu)
  385. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  386. list_for_each_entry(device, &dma_device_list, global_node) {
  387. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  388. continue;
  389. list_for_each_entry(chan, &device->channels, device_node)
  390. chan->table_count = 0;
  391. }
  392. /* don't populate the channel_table if no clients are available */
  393. if (!dmaengine_ref_count)
  394. return;
  395. /* redistribute available channels */
  396. n = 0;
  397. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  398. for_each_online_cpu(cpu) {
  399. if (num_possible_cpus() > 1)
  400. chan = nth_chan(cap, n++);
  401. else
  402. chan = nth_chan(cap, -1);
  403. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  404. }
  405. }
  406. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  407. struct dma_device *dev,
  408. dma_filter_fn fn, void *fn_param)
  409. {
  410. struct dma_chan *chan;
  411. if (!__dma_device_satisfies_mask(dev, mask)) {
  412. pr_debug("%s: wrong capabilities\n", __func__);
  413. return NULL;
  414. }
  415. /* devices with multiple channels need special handling as we need to
  416. * ensure that all channels are either private or public.
  417. */
  418. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  419. list_for_each_entry(chan, &dev->channels, device_node) {
  420. /* some channels are already publicly allocated */
  421. if (chan->client_count)
  422. return NULL;
  423. }
  424. list_for_each_entry(chan, &dev->channels, device_node) {
  425. if (chan->client_count) {
  426. pr_debug("%s: %s busy\n",
  427. __func__, dma_chan_name(chan));
  428. continue;
  429. }
  430. if (fn && !fn(chan, fn_param)) {
  431. pr_debug("%s: %s filter said false\n",
  432. __func__, dma_chan_name(chan));
  433. continue;
  434. }
  435. return chan;
  436. }
  437. return NULL;
  438. }
  439. /**
  440. * dma_request_channel - try to allocate an exclusive channel
  441. * @mask: capabilities that the channel must satisfy
  442. * @fn: optional callback to disposition available channels
  443. * @fn_param: opaque parameter to pass to dma_filter_fn
  444. */
  445. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  446. dma_filter_fn fn, void *fn_param)
  447. {
  448. struct dma_device *device, *_d;
  449. struct dma_chan *chan = NULL;
  450. int err;
  451. /* Find a channel */
  452. mutex_lock(&dma_list_mutex);
  453. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  454. chan = private_candidate(mask, device, fn, fn_param);
  455. if (chan) {
  456. /* Found a suitable channel, try to grab, prep, and
  457. * return it. We first set DMA_PRIVATE to disable
  458. * balance_ref_count as this channel will not be
  459. * published in the general-purpose allocator
  460. */
  461. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  462. device->privatecnt++;
  463. err = dma_chan_get(chan);
  464. if (err == -ENODEV) {
  465. pr_debug("%s: %s module removed\n",
  466. __func__, dma_chan_name(chan));
  467. list_del_rcu(&device->global_node);
  468. } else if (err)
  469. pr_debug("%s: failed to get %s: (%d)\n",
  470. __func__, dma_chan_name(chan), err);
  471. else
  472. break;
  473. if (--device->privatecnt == 0)
  474. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  475. chan = NULL;
  476. }
  477. }
  478. mutex_unlock(&dma_list_mutex);
  479. pr_debug("%s: %s (%s)\n",
  480. __func__,
  481. chan ? "success" : "fail",
  482. chan ? dma_chan_name(chan) : NULL);
  483. return chan;
  484. }
  485. EXPORT_SYMBOL_GPL(__dma_request_channel);
  486. /**
  487. * dma_request_slave_channel - try to allocate an exclusive slave channel
  488. * @dev: pointer to client device structure
  489. * @name: slave channel name
  490. */
  491. struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
  492. {
  493. /* If device-tree is present get slave info from here */
  494. if (dev->of_node)
  495. return of_dma_request_slave_channel(dev->of_node, name);
  496. /* If device was enumerated by ACPI get slave info from here */
  497. if (ACPI_HANDLE(dev))
  498. return acpi_dma_request_slave_chan_by_name(dev, name);
  499. return NULL;
  500. }
  501. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  502. void dma_release_channel(struct dma_chan *chan)
  503. {
  504. mutex_lock(&dma_list_mutex);
  505. WARN_ONCE(chan->client_count != 1,
  506. "chan reference count %d != 1\n", chan->client_count);
  507. dma_chan_put(chan);
  508. /* drop PRIVATE cap enabled by __dma_request_channel() */
  509. if (--chan->device->privatecnt == 0)
  510. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  511. mutex_unlock(&dma_list_mutex);
  512. }
  513. EXPORT_SYMBOL_GPL(dma_release_channel);
  514. /**
  515. * dmaengine_get - register interest in dma_channels
  516. */
  517. void dmaengine_get(void)
  518. {
  519. struct dma_device *device, *_d;
  520. struct dma_chan *chan;
  521. int err;
  522. mutex_lock(&dma_list_mutex);
  523. dmaengine_ref_count++;
  524. /* try to grab channels */
  525. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  526. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  527. continue;
  528. list_for_each_entry(chan, &device->channels, device_node) {
  529. err = dma_chan_get(chan);
  530. if (err == -ENODEV) {
  531. /* module removed before we could use it */
  532. list_del_rcu(&device->global_node);
  533. break;
  534. } else if (err)
  535. pr_debug("%s: failed to get %s: (%d)\n",
  536. __func__, dma_chan_name(chan), err);
  537. }
  538. }
  539. /* if this is the first reference and there were channels
  540. * waiting we need to rebalance to get those channels
  541. * incorporated into the channel table
  542. */
  543. if (dmaengine_ref_count == 1)
  544. dma_channel_rebalance();
  545. mutex_unlock(&dma_list_mutex);
  546. }
  547. EXPORT_SYMBOL(dmaengine_get);
  548. /**
  549. * dmaengine_put - let dma drivers be removed when ref_count == 0
  550. */
  551. void dmaengine_put(void)
  552. {
  553. struct dma_device *device;
  554. struct dma_chan *chan;
  555. mutex_lock(&dma_list_mutex);
  556. dmaengine_ref_count--;
  557. BUG_ON(dmaengine_ref_count < 0);
  558. /* drop channel references */
  559. list_for_each_entry(device, &dma_device_list, global_node) {
  560. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  561. continue;
  562. list_for_each_entry(chan, &device->channels, device_node)
  563. dma_chan_put(chan);
  564. }
  565. mutex_unlock(&dma_list_mutex);
  566. }
  567. EXPORT_SYMBOL(dmaengine_put);
  568. static bool device_has_all_tx_types(struct dma_device *device)
  569. {
  570. /* A device that satisfies this test has channels that will never cause
  571. * an async_tx channel switch event as all possible operation types can
  572. * be handled.
  573. */
  574. #ifdef CONFIG_ASYNC_TX_DMA
  575. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  576. return false;
  577. #endif
  578. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  579. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  580. return false;
  581. #endif
  582. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  583. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  584. return false;
  585. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  586. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  587. return false;
  588. #endif
  589. #endif
  590. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  591. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  592. return false;
  593. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  594. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  595. return false;
  596. #endif
  597. #endif
  598. return true;
  599. }
  600. static int get_dma_id(struct dma_device *device)
  601. {
  602. int rc;
  603. mutex_lock(&dma_list_mutex);
  604. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  605. if (rc >= 0)
  606. device->dev_id = rc;
  607. mutex_unlock(&dma_list_mutex);
  608. return rc < 0 ? rc : 0;
  609. }
  610. /**
  611. * dma_async_device_register - registers DMA devices found
  612. * @device: &dma_device
  613. */
  614. int dma_async_device_register(struct dma_device *device)
  615. {
  616. int chancnt = 0, rc;
  617. struct dma_chan* chan;
  618. atomic_t *idr_ref;
  619. if (!device)
  620. return -ENODEV;
  621. /* validate device routines */
  622. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  623. !device->device_prep_dma_memcpy);
  624. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  625. !device->device_prep_dma_xor);
  626. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  627. !device->device_prep_dma_xor_val);
  628. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  629. !device->device_prep_dma_pq);
  630. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  631. !device->device_prep_dma_pq_val);
  632. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  633. !device->device_prep_dma_interrupt);
  634. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  635. !device->device_prep_dma_sg);
  636. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  637. !device->device_prep_dma_cyclic);
  638. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  639. !device->device_control);
  640. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  641. !device->device_prep_interleaved_dma);
  642. BUG_ON(!device->device_alloc_chan_resources);
  643. BUG_ON(!device->device_free_chan_resources);
  644. BUG_ON(!device->device_tx_status);
  645. BUG_ON(!device->device_issue_pending);
  646. BUG_ON(!device->dev);
  647. /* note: this only matters in the
  648. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  649. */
  650. if (device_has_all_tx_types(device))
  651. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  652. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  653. if (!idr_ref)
  654. return -ENOMEM;
  655. rc = get_dma_id(device);
  656. if (rc != 0) {
  657. kfree(idr_ref);
  658. return rc;
  659. }
  660. atomic_set(idr_ref, 0);
  661. /* represent channels in sysfs. Probably want devs too */
  662. list_for_each_entry(chan, &device->channels, device_node) {
  663. rc = -ENOMEM;
  664. chan->local = alloc_percpu(typeof(*chan->local));
  665. if (chan->local == NULL)
  666. goto err_out;
  667. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  668. if (chan->dev == NULL) {
  669. free_percpu(chan->local);
  670. chan->local = NULL;
  671. goto err_out;
  672. }
  673. chan->chan_id = chancnt++;
  674. chan->dev->device.class = &dma_devclass;
  675. chan->dev->device.parent = device->dev;
  676. chan->dev->chan = chan;
  677. chan->dev->idr_ref = idr_ref;
  678. chan->dev->dev_id = device->dev_id;
  679. atomic_inc(idr_ref);
  680. dev_set_name(&chan->dev->device, "dma%dchan%d",
  681. device->dev_id, chan->chan_id);
  682. rc = device_register(&chan->dev->device);
  683. if (rc) {
  684. free_percpu(chan->local);
  685. chan->local = NULL;
  686. kfree(chan->dev);
  687. atomic_dec(idr_ref);
  688. goto err_out;
  689. }
  690. chan->client_count = 0;
  691. }
  692. device->chancnt = chancnt;
  693. mutex_lock(&dma_list_mutex);
  694. /* take references on public channels */
  695. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  696. list_for_each_entry(chan, &device->channels, device_node) {
  697. /* if clients are already waiting for channels we need
  698. * to take references on their behalf
  699. */
  700. if (dma_chan_get(chan) == -ENODEV) {
  701. /* note we can only get here for the first
  702. * channel as the remaining channels are
  703. * guaranteed to get a reference
  704. */
  705. rc = -ENODEV;
  706. mutex_unlock(&dma_list_mutex);
  707. goto err_out;
  708. }
  709. }
  710. list_add_tail_rcu(&device->global_node, &dma_device_list);
  711. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  712. device->privatecnt++; /* Always private */
  713. dma_channel_rebalance();
  714. mutex_unlock(&dma_list_mutex);
  715. return 0;
  716. err_out:
  717. /* if we never registered a channel just release the idr */
  718. if (atomic_read(idr_ref) == 0) {
  719. mutex_lock(&dma_list_mutex);
  720. idr_remove(&dma_idr, device->dev_id);
  721. mutex_unlock(&dma_list_mutex);
  722. kfree(idr_ref);
  723. return rc;
  724. }
  725. list_for_each_entry(chan, &device->channels, device_node) {
  726. if (chan->local == NULL)
  727. continue;
  728. mutex_lock(&dma_list_mutex);
  729. chan->dev->chan = NULL;
  730. mutex_unlock(&dma_list_mutex);
  731. device_unregister(&chan->dev->device);
  732. free_percpu(chan->local);
  733. }
  734. return rc;
  735. }
  736. EXPORT_SYMBOL(dma_async_device_register);
  737. /**
  738. * dma_async_device_unregister - unregister a DMA device
  739. * @device: &dma_device
  740. *
  741. * This routine is called by dma driver exit routines, dmaengine holds module
  742. * references to prevent it being called while channels are in use.
  743. */
  744. void dma_async_device_unregister(struct dma_device *device)
  745. {
  746. struct dma_chan *chan;
  747. mutex_lock(&dma_list_mutex);
  748. list_del_rcu(&device->global_node);
  749. dma_channel_rebalance();
  750. mutex_unlock(&dma_list_mutex);
  751. list_for_each_entry(chan, &device->channels, device_node) {
  752. WARN_ONCE(chan->client_count,
  753. "%s called while %d clients hold a reference\n",
  754. __func__, chan->client_count);
  755. mutex_lock(&dma_list_mutex);
  756. chan->dev->chan = NULL;
  757. mutex_unlock(&dma_list_mutex);
  758. device_unregister(&chan->dev->device);
  759. free_percpu(chan->local);
  760. }
  761. }
  762. EXPORT_SYMBOL(dma_async_device_unregister);
  763. /**
  764. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  765. * @chan: DMA channel to offload copy to
  766. * @dest: destination address (virtual)
  767. * @src: source address (virtual)
  768. * @len: length
  769. *
  770. * Both @dest and @src must be mappable to a bus address according to the
  771. * DMA mapping API rules for streaming mappings.
  772. * Both @dest and @src must stay memory resident (kernel memory or locked
  773. * user space pages).
  774. */
  775. dma_cookie_t
  776. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  777. void *src, size_t len)
  778. {
  779. struct dma_device *dev = chan->device;
  780. struct dma_async_tx_descriptor *tx;
  781. dma_addr_t dma_dest, dma_src;
  782. dma_cookie_t cookie;
  783. unsigned long flags;
  784. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  785. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  786. flags = DMA_CTRL_ACK |
  787. DMA_COMPL_SRC_UNMAP_SINGLE |
  788. DMA_COMPL_DEST_UNMAP_SINGLE;
  789. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  790. if (!tx) {
  791. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  792. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  793. return -ENOMEM;
  794. }
  795. tx->callback = NULL;
  796. cookie = tx->tx_submit(tx);
  797. preempt_disable();
  798. __this_cpu_add(chan->local->bytes_transferred, len);
  799. __this_cpu_inc(chan->local->memcpy_count);
  800. preempt_enable();
  801. return cookie;
  802. }
  803. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  804. /**
  805. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  806. * @chan: DMA channel to offload copy to
  807. * @page: destination page
  808. * @offset: offset in page to copy to
  809. * @kdata: source address (virtual)
  810. * @len: length
  811. *
  812. * Both @page/@offset and @kdata must be mappable to a bus address according
  813. * to the DMA mapping API rules for streaming mappings.
  814. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  815. * locked user space pages)
  816. */
  817. dma_cookie_t
  818. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  819. unsigned int offset, void *kdata, size_t len)
  820. {
  821. struct dma_device *dev = chan->device;
  822. struct dma_async_tx_descriptor *tx;
  823. dma_addr_t dma_dest, dma_src;
  824. dma_cookie_t cookie;
  825. unsigned long flags;
  826. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  827. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  828. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  829. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  830. if (!tx) {
  831. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  832. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  833. return -ENOMEM;
  834. }
  835. tx->callback = NULL;
  836. cookie = tx->tx_submit(tx);
  837. preempt_disable();
  838. __this_cpu_add(chan->local->bytes_transferred, len);
  839. __this_cpu_inc(chan->local->memcpy_count);
  840. preempt_enable();
  841. return cookie;
  842. }
  843. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  844. /**
  845. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  846. * @chan: DMA channel to offload copy to
  847. * @dest_pg: destination page
  848. * @dest_off: offset in page to copy to
  849. * @src_pg: source page
  850. * @src_off: offset in page to copy from
  851. * @len: length
  852. *
  853. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  854. * address according to the DMA mapping API rules for streaming mappings.
  855. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  856. * (kernel memory or locked user space pages).
  857. */
  858. dma_cookie_t
  859. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  860. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  861. size_t len)
  862. {
  863. struct dma_device *dev = chan->device;
  864. struct dma_async_tx_descriptor *tx;
  865. dma_addr_t dma_dest, dma_src;
  866. dma_cookie_t cookie;
  867. unsigned long flags;
  868. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  869. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  870. DMA_FROM_DEVICE);
  871. flags = DMA_CTRL_ACK;
  872. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  873. if (!tx) {
  874. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  875. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  876. return -ENOMEM;
  877. }
  878. tx->callback = NULL;
  879. cookie = tx->tx_submit(tx);
  880. preempt_disable();
  881. __this_cpu_add(chan->local->bytes_transferred, len);
  882. __this_cpu_inc(chan->local->memcpy_count);
  883. preempt_enable();
  884. return cookie;
  885. }
  886. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  887. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  888. struct dma_chan *chan)
  889. {
  890. tx->chan = chan;
  891. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  892. spin_lock_init(&tx->lock);
  893. #endif
  894. }
  895. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  896. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  897. * @tx: in-flight transaction to wait on
  898. */
  899. enum dma_status
  900. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  901. {
  902. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  903. if (!tx)
  904. return DMA_SUCCESS;
  905. while (tx->cookie == -EBUSY) {
  906. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  907. pr_err("%s timeout waiting for descriptor submission\n",
  908. __func__);
  909. return DMA_ERROR;
  910. }
  911. cpu_relax();
  912. }
  913. return dma_sync_wait(tx->chan, tx->cookie);
  914. }
  915. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  916. /* dma_run_dependencies - helper routine for dma drivers to process
  917. * (start) dependent operations on their target channel
  918. * @tx: transaction with dependencies
  919. */
  920. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  921. {
  922. struct dma_async_tx_descriptor *dep = txd_next(tx);
  923. struct dma_async_tx_descriptor *dep_next;
  924. struct dma_chan *chan;
  925. if (!dep)
  926. return;
  927. /* we'll submit tx->next now, so clear the link */
  928. txd_clear_next(tx);
  929. chan = dep->chan;
  930. /* keep submitting up until a channel switch is detected
  931. * in that case we will be called again as a result of
  932. * processing the interrupt from async_tx_channel_switch
  933. */
  934. for (; dep; dep = dep_next) {
  935. txd_lock(dep);
  936. txd_clear_parent(dep);
  937. dep_next = txd_next(dep);
  938. if (dep_next && dep_next->chan == chan)
  939. txd_clear_next(dep); /* ->next will be submitted */
  940. else
  941. dep_next = NULL; /* submit current dep and terminate */
  942. txd_unlock(dep);
  943. dep->tx_submit(dep);
  944. }
  945. chan->device->device_issue_pending(chan);
  946. }
  947. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  948. static int __init dma_bus_init(void)
  949. {
  950. return class_register(&dma_devclass);
  951. }
  952. arch_initcall(dma_bus_init);