coh901318.c 80 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825
  1. /*
  2. * driver/dma/coh901318.c
  3. *
  4. * Copyright (C) 2007-2009 ST-Ericsson
  5. * License terms: GNU General Public License (GPL) version 2
  6. * DMA driver for COH 901 318
  7. * Author: Per Friden <per.friden@stericsson.com>
  8. */
  9. #include <linux/init.h>
  10. #include <linux/module.h>
  11. #include <linux/kernel.h> /* printk() */
  12. #include <linux/fs.h> /* everything... */
  13. #include <linux/scatterlist.h>
  14. #include <linux/slab.h> /* kmalloc() */
  15. #include <linux/dmaengine.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/device.h>
  18. #include <linux/irqreturn.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/uaccess.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/platform_data/dma-coh901318.h>
  24. #include <linux/of_dma.h>
  25. #include "coh901318.h"
  26. #include "dmaengine.h"
  27. #define COH901318_MOD32_MASK (0x1F)
  28. #define COH901318_WORD_MASK (0xFFFFFFFF)
  29. /* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
  30. #define COH901318_INT_STATUS1 (0x0000)
  31. #define COH901318_INT_STATUS2 (0x0004)
  32. /* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
  33. #define COH901318_TC_INT_STATUS1 (0x0008)
  34. #define COH901318_TC_INT_STATUS2 (0x000C)
  35. /* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
  36. #define COH901318_TC_INT_CLEAR1 (0x0010)
  37. #define COH901318_TC_INT_CLEAR2 (0x0014)
  38. /* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
  39. #define COH901318_RAW_TC_INT_STATUS1 (0x0018)
  40. #define COH901318_RAW_TC_INT_STATUS2 (0x001C)
  41. /* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
  42. #define COH901318_BE_INT_STATUS1 (0x0020)
  43. #define COH901318_BE_INT_STATUS2 (0x0024)
  44. /* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
  45. #define COH901318_BE_INT_CLEAR1 (0x0028)
  46. #define COH901318_BE_INT_CLEAR2 (0x002C)
  47. /* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
  48. #define COH901318_RAW_BE_INT_STATUS1 (0x0030)
  49. #define COH901318_RAW_BE_INT_STATUS2 (0x0034)
  50. /*
  51. * CX_CFG - Channel Configuration Registers 32bit (R/W)
  52. */
  53. #define COH901318_CX_CFG (0x0100)
  54. #define COH901318_CX_CFG_SPACING (0x04)
  55. /* Channel enable activates tha dma job */
  56. #define COH901318_CX_CFG_CH_ENABLE (0x00000001)
  57. #define COH901318_CX_CFG_CH_DISABLE (0x00000000)
  58. /* Request Mode */
  59. #define COH901318_CX_CFG_RM_MASK (0x00000006)
  60. #define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
  61. #define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
  62. #define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
  63. #define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
  64. #define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
  65. /* Linked channel request field. RM must == 11 */
  66. #define COH901318_CX_CFG_LCRF_SHIFT 3
  67. #define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
  68. #define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
  69. /* Terminal Counter Interrupt Request Mask */
  70. #define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
  71. #define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
  72. /* Bus Error interrupt Mask */
  73. #define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
  74. #define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
  75. /*
  76. * CX_STAT - Channel Status Registers 32bit (R/-)
  77. */
  78. #define COH901318_CX_STAT (0x0200)
  79. #define COH901318_CX_STAT_SPACING (0x04)
  80. #define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
  81. #define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
  82. #define COH901318_CX_STAT_ACTIVE (0x00000002)
  83. #define COH901318_CX_STAT_ENABLED (0x00000001)
  84. /*
  85. * CX_CTRL - Channel Control Registers 32bit (R/W)
  86. */
  87. #define COH901318_CX_CTRL (0x0400)
  88. #define COH901318_CX_CTRL_SPACING (0x10)
  89. /* Transfer Count Enable */
  90. #define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
  91. #define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
  92. /* Transfer Count Value 0 - 4095 */
  93. #define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
  94. /* Burst count */
  95. #define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
  96. #define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
  97. #define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
  98. #define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
  99. #define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
  100. #define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
  101. #define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
  102. #define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
  103. #define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
  104. /* Source bus size */
  105. #define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
  106. #define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
  107. #define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
  108. #define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
  109. /* Source address increment */
  110. #define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
  111. #define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
  112. /* Destination Bus Size */
  113. #define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
  114. #define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
  115. #define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
  116. #define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
  117. /* Destination address increment */
  118. #define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
  119. #define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
  120. /* Master Mode (Master2 is only connected to MSL) */
  121. #define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
  122. #define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
  123. #define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
  124. #define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
  125. #define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
  126. /* Terminal Count flag to PER enable */
  127. #define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
  128. #define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
  129. /* Terminal Count flags to CPU enable */
  130. #define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
  131. #define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
  132. /* Hand shake to peripheral */
  133. #define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
  134. #define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
  135. #define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
  136. #define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
  137. /* DMA mode */
  138. #define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
  139. #define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
  140. #define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
  141. #define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
  142. /* Primary Request Data Destination */
  143. #define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
  144. #define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
  145. #define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
  146. /*
  147. * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
  148. */
  149. #define COH901318_CX_SRC_ADDR (0x0404)
  150. #define COH901318_CX_SRC_ADDR_SPACING (0x10)
  151. /*
  152. * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
  153. */
  154. #define COH901318_CX_DST_ADDR (0x0408)
  155. #define COH901318_CX_DST_ADDR_SPACING (0x10)
  156. /*
  157. * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
  158. */
  159. #define COH901318_CX_LNK_ADDR (0x040C)
  160. #define COH901318_CX_LNK_ADDR_SPACING (0x10)
  161. #define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
  162. /**
  163. * struct coh901318_params - parameters for DMAC configuration
  164. * @config: DMA config register
  165. * @ctrl_lli_last: DMA control register for the last lli in the list
  166. * @ctrl_lli: DMA control register for an lli
  167. * @ctrl_lli_chained: DMA control register for a chained lli
  168. */
  169. struct coh901318_params {
  170. u32 config;
  171. u32 ctrl_lli_last;
  172. u32 ctrl_lli;
  173. u32 ctrl_lli_chained;
  174. };
  175. /**
  176. * struct coh_dma_channel - dma channel base
  177. * @name: ascii name of dma channel
  178. * @number: channel id number
  179. * @desc_nbr_max: number of preallocated descriptors
  180. * @priority_high: prio of channel, 0 low otherwise high.
  181. * @param: configuration parameters
  182. */
  183. struct coh_dma_channel {
  184. const char name[32];
  185. const int number;
  186. const int desc_nbr_max;
  187. const int priority_high;
  188. const struct coh901318_params param;
  189. };
  190. /**
  191. * struct powersave - DMA power save structure
  192. * @lock: lock protecting data in this struct
  193. * @started_channels: bit mask indicating active dma channels
  194. */
  195. struct powersave {
  196. spinlock_t lock;
  197. u64 started_channels;
  198. };
  199. /* points out all dma slave channels.
  200. * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
  201. * Select all channels from A to B, end of list is marked with -1,-1
  202. */
  203. static int dma_slave_channels[] = {
  204. U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
  205. U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
  206. /* points out all dma memcpy channels. */
  207. static int dma_memcpy_channels[] = {
  208. U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
  209. #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
  210. COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
  211. COH901318_CX_CFG_LCR_DISABLE | \
  212. COH901318_CX_CFG_TC_IRQ_ENABLE | \
  213. COH901318_CX_CFG_BE_IRQ_ENABLE)
  214. #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
  215. COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
  216. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
  217. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
  218. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
  219. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
  220. COH901318_CX_CTRL_MASTER_MODE_M1RW | \
  221. COH901318_CX_CTRL_TCP_DISABLE | \
  222. COH901318_CX_CTRL_TC_IRQ_DISABLE | \
  223. COH901318_CX_CTRL_HSP_DISABLE | \
  224. COH901318_CX_CTRL_HSS_DISABLE | \
  225. COH901318_CX_CTRL_DDMA_LEGACY | \
  226. COH901318_CX_CTRL_PRDD_SOURCE)
  227. #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
  228. COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
  229. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
  230. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
  231. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
  232. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
  233. COH901318_CX_CTRL_MASTER_MODE_M1RW | \
  234. COH901318_CX_CTRL_TCP_DISABLE | \
  235. COH901318_CX_CTRL_TC_IRQ_DISABLE | \
  236. COH901318_CX_CTRL_HSP_DISABLE | \
  237. COH901318_CX_CTRL_HSS_DISABLE | \
  238. COH901318_CX_CTRL_DDMA_LEGACY | \
  239. COH901318_CX_CTRL_PRDD_SOURCE)
  240. #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
  241. COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
  242. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
  243. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
  244. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
  245. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
  246. COH901318_CX_CTRL_MASTER_MODE_M1RW | \
  247. COH901318_CX_CTRL_TCP_DISABLE | \
  248. COH901318_CX_CTRL_TC_IRQ_ENABLE | \
  249. COH901318_CX_CTRL_HSP_DISABLE | \
  250. COH901318_CX_CTRL_HSS_DISABLE | \
  251. COH901318_CX_CTRL_DDMA_LEGACY | \
  252. COH901318_CX_CTRL_PRDD_SOURCE)
  253. const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
  254. {
  255. .number = U300_DMA_MSL_TX_0,
  256. .name = "MSL TX 0",
  257. .priority_high = 0,
  258. },
  259. {
  260. .number = U300_DMA_MSL_TX_1,
  261. .name = "MSL TX 1",
  262. .priority_high = 0,
  263. .param.config = COH901318_CX_CFG_CH_DISABLE |
  264. COH901318_CX_CFG_LCR_DISABLE |
  265. COH901318_CX_CFG_TC_IRQ_ENABLE |
  266. COH901318_CX_CFG_BE_IRQ_ENABLE,
  267. .param.ctrl_lli_chained = 0 |
  268. COH901318_CX_CTRL_TC_ENABLE |
  269. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  270. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  271. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  272. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  273. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  274. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  275. COH901318_CX_CTRL_TCP_DISABLE |
  276. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  277. COH901318_CX_CTRL_HSP_ENABLE |
  278. COH901318_CX_CTRL_HSS_DISABLE |
  279. COH901318_CX_CTRL_DDMA_LEGACY |
  280. COH901318_CX_CTRL_PRDD_SOURCE,
  281. .param.ctrl_lli = 0 |
  282. COH901318_CX_CTRL_TC_ENABLE |
  283. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  284. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  285. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  286. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  287. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  288. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  289. COH901318_CX_CTRL_TCP_ENABLE |
  290. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  291. COH901318_CX_CTRL_HSP_ENABLE |
  292. COH901318_CX_CTRL_HSS_DISABLE |
  293. COH901318_CX_CTRL_DDMA_LEGACY |
  294. COH901318_CX_CTRL_PRDD_SOURCE,
  295. .param.ctrl_lli_last = 0 |
  296. COH901318_CX_CTRL_TC_ENABLE |
  297. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  298. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  299. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  300. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  301. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  302. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  303. COH901318_CX_CTRL_TCP_ENABLE |
  304. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  305. COH901318_CX_CTRL_HSP_ENABLE |
  306. COH901318_CX_CTRL_HSS_DISABLE |
  307. COH901318_CX_CTRL_DDMA_LEGACY |
  308. COH901318_CX_CTRL_PRDD_SOURCE,
  309. },
  310. {
  311. .number = U300_DMA_MSL_TX_2,
  312. .name = "MSL TX 2",
  313. .priority_high = 0,
  314. .param.config = COH901318_CX_CFG_CH_DISABLE |
  315. COH901318_CX_CFG_LCR_DISABLE |
  316. COH901318_CX_CFG_TC_IRQ_ENABLE |
  317. COH901318_CX_CFG_BE_IRQ_ENABLE,
  318. .param.ctrl_lli_chained = 0 |
  319. COH901318_CX_CTRL_TC_ENABLE |
  320. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  321. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  322. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  323. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  324. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  325. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  326. COH901318_CX_CTRL_TCP_DISABLE |
  327. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  328. COH901318_CX_CTRL_HSP_ENABLE |
  329. COH901318_CX_CTRL_HSS_DISABLE |
  330. COH901318_CX_CTRL_DDMA_LEGACY |
  331. COH901318_CX_CTRL_PRDD_SOURCE,
  332. .param.ctrl_lli = 0 |
  333. COH901318_CX_CTRL_TC_ENABLE |
  334. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  335. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  336. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  337. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  338. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  339. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  340. COH901318_CX_CTRL_TCP_ENABLE |
  341. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  342. COH901318_CX_CTRL_HSP_ENABLE |
  343. COH901318_CX_CTRL_HSS_DISABLE |
  344. COH901318_CX_CTRL_DDMA_LEGACY |
  345. COH901318_CX_CTRL_PRDD_SOURCE,
  346. .param.ctrl_lli_last = 0 |
  347. COH901318_CX_CTRL_TC_ENABLE |
  348. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  349. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  350. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  351. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  352. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  353. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  354. COH901318_CX_CTRL_TCP_ENABLE |
  355. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  356. COH901318_CX_CTRL_HSP_ENABLE |
  357. COH901318_CX_CTRL_HSS_DISABLE |
  358. COH901318_CX_CTRL_DDMA_LEGACY |
  359. COH901318_CX_CTRL_PRDD_SOURCE,
  360. .desc_nbr_max = 10,
  361. },
  362. {
  363. .number = U300_DMA_MSL_TX_3,
  364. .name = "MSL TX 3",
  365. .priority_high = 0,
  366. .param.config = COH901318_CX_CFG_CH_DISABLE |
  367. COH901318_CX_CFG_LCR_DISABLE |
  368. COH901318_CX_CFG_TC_IRQ_ENABLE |
  369. COH901318_CX_CFG_BE_IRQ_ENABLE,
  370. .param.ctrl_lli_chained = 0 |
  371. COH901318_CX_CTRL_TC_ENABLE |
  372. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  373. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  374. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  375. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  376. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  377. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  378. COH901318_CX_CTRL_TCP_DISABLE |
  379. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  380. COH901318_CX_CTRL_HSP_ENABLE |
  381. COH901318_CX_CTRL_HSS_DISABLE |
  382. COH901318_CX_CTRL_DDMA_LEGACY |
  383. COH901318_CX_CTRL_PRDD_SOURCE,
  384. .param.ctrl_lli = 0 |
  385. COH901318_CX_CTRL_TC_ENABLE |
  386. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  387. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  388. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  389. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  390. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  391. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  392. COH901318_CX_CTRL_TCP_ENABLE |
  393. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  394. COH901318_CX_CTRL_HSP_ENABLE |
  395. COH901318_CX_CTRL_HSS_DISABLE |
  396. COH901318_CX_CTRL_DDMA_LEGACY |
  397. COH901318_CX_CTRL_PRDD_SOURCE,
  398. .param.ctrl_lli_last = 0 |
  399. COH901318_CX_CTRL_TC_ENABLE |
  400. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  401. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  402. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  403. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  404. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  405. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  406. COH901318_CX_CTRL_TCP_ENABLE |
  407. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  408. COH901318_CX_CTRL_HSP_ENABLE |
  409. COH901318_CX_CTRL_HSS_DISABLE |
  410. COH901318_CX_CTRL_DDMA_LEGACY |
  411. COH901318_CX_CTRL_PRDD_SOURCE,
  412. },
  413. {
  414. .number = U300_DMA_MSL_TX_4,
  415. .name = "MSL TX 4",
  416. .priority_high = 0,
  417. .param.config = COH901318_CX_CFG_CH_DISABLE |
  418. COH901318_CX_CFG_LCR_DISABLE |
  419. COH901318_CX_CFG_TC_IRQ_ENABLE |
  420. COH901318_CX_CFG_BE_IRQ_ENABLE,
  421. .param.ctrl_lli_chained = 0 |
  422. COH901318_CX_CTRL_TC_ENABLE |
  423. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  424. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  425. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  426. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  427. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  428. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  429. COH901318_CX_CTRL_TCP_DISABLE |
  430. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  431. COH901318_CX_CTRL_HSP_ENABLE |
  432. COH901318_CX_CTRL_HSS_DISABLE |
  433. COH901318_CX_CTRL_DDMA_LEGACY |
  434. COH901318_CX_CTRL_PRDD_SOURCE,
  435. .param.ctrl_lli = 0 |
  436. COH901318_CX_CTRL_TC_ENABLE |
  437. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  438. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  439. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  440. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  441. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  442. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  443. COH901318_CX_CTRL_TCP_ENABLE |
  444. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  445. COH901318_CX_CTRL_HSP_ENABLE |
  446. COH901318_CX_CTRL_HSS_DISABLE |
  447. COH901318_CX_CTRL_DDMA_LEGACY |
  448. COH901318_CX_CTRL_PRDD_SOURCE,
  449. .param.ctrl_lli_last = 0 |
  450. COH901318_CX_CTRL_TC_ENABLE |
  451. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  452. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  453. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  454. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  455. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  456. COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
  457. COH901318_CX_CTRL_TCP_ENABLE |
  458. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  459. COH901318_CX_CTRL_HSP_ENABLE |
  460. COH901318_CX_CTRL_HSS_DISABLE |
  461. COH901318_CX_CTRL_DDMA_LEGACY |
  462. COH901318_CX_CTRL_PRDD_SOURCE,
  463. },
  464. {
  465. .number = U300_DMA_MSL_TX_5,
  466. .name = "MSL TX 5",
  467. .priority_high = 0,
  468. },
  469. {
  470. .number = U300_DMA_MSL_TX_6,
  471. .name = "MSL TX 6",
  472. .priority_high = 0,
  473. },
  474. {
  475. .number = U300_DMA_MSL_RX_0,
  476. .name = "MSL RX 0",
  477. .priority_high = 0,
  478. },
  479. {
  480. .number = U300_DMA_MSL_RX_1,
  481. .name = "MSL RX 1",
  482. .priority_high = 0,
  483. .param.config = COH901318_CX_CFG_CH_DISABLE |
  484. COH901318_CX_CFG_LCR_DISABLE |
  485. COH901318_CX_CFG_TC_IRQ_ENABLE |
  486. COH901318_CX_CFG_BE_IRQ_ENABLE,
  487. .param.ctrl_lli_chained = 0 |
  488. COH901318_CX_CTRL_TC_ENABLE |
  489. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  490. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  491. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  492. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  493. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  494. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  495. COH901318_CX_CTRL_TCP_DISABLE |
  496. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  497. COH901318_CX_CTRL_HSP_ENABLE |
  498. COH901318_CX_CTRL_HSS_DISABLE |
  499. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  500. COH901318_CX_CTRL_PRDD_DEST,
  501. .param.ctrl_lli = 0,
  502. .param.ctrl_lli_last = 0 |
  503. COH901318_CX_CTRL_TC_ENABLE |
  504. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  505. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  506. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  507. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  508. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  509. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  510. COH901318_CX_CTRL_TCP_DISABLE |
  511. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  512. COH901318_CX_CTRL_HSP_ENABLE |
  513. COH901318_CX_CTRL_HSS_DISABLE |
  514. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  515. COH901318_CX_CTRL_PRDD_DEST,
  516. },
  517. {
  518. .number = U300_DMA_MSL_RX_2,
  519. .name = "MSL RX 2",
  520. .priority_high = 0,
  521. .param.config = COH901318_CX_CFG_CH_DISABLE |
  522. COH901318_CX_CFG_LCR_DISABLE |
  523. COH901318_CX_CFG_TC_IRQ_ENABLE |
  524. COH901318_CX_CFG_BE_IRQ_ENABLE,
  525. .param.ctrl_lli_chained = 0 |
  526. COH901318_CX_CTRL_TC_ENABLE |
  527. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  528. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  529. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  530. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  531. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  532. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  533. COH901318_CX_CTRL_TCP_DISABLE |
  534. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  535. COH901318_CX_CTRL_HSP_ENABLE |
  536. COH901318_CX_CTRL_HSS_DISABLE |
  537. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  538. COH901318_CX_CTRL_PRDD_DEST,
  539. .param.ctrl_lli = 0 |
  540. COH901318_CX_CTRL_TC_ENABLE |
  541. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  542. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  543. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  544. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  545. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  546. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  547. COH901318_CX_CTRL_TCP_DISABLE |
  548. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  549. COH901318_CX_CTRL_HSP_ENABLE |
  550. COH901318_CX_CTRL_HSS_DISABLE |
  551. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  552. COH901318_CX_CTRL_PRDD_DEST,
  553. .param.ctrl_lli_last = 0 |
  554. COH901318_CX_CTRL_TC_ENABLE |
  555. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  556. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  557. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  558. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  559. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  560. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  561. COH901318_CX_CTRL_TCP_DISABLE |
  562. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  563. COH901318_CX_CTRL_HSP_ENABLE |
  564. COH901318_CX_CTRL_HSS_DISABLE |
  565. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  566. COH901318_CX_CTRL_PRDD_DEST,
  567. },
  568. {
  569. .number = U300_DMA_MSL_RX_3,
  570. .name = "MSL RX 3",
  571. .priority_high = 0,
  572. .param.config = COH901318_CX_CFG_CH_DISABLE |
  573. COH901318_CX_CFG_LCR_DISABLE |
  574. COH901318_CX_CFG_TC_IRQ_ENABLE |
  575. COH901318_CX_CFG_BE_IRQ_ENABLE,
  576. .param.ctrl_lli_chained = 0 |
  577. COH901318_CX_CTRL_TC_ENABLE |
  578. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  579. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  580. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  581. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  582. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  583. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  584. COH901318_CX_CTRL_TCP_DISABLE |
  585. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  586. COH901318_CX_CTRL_HSP_ENABLE |
  587. COH901318_CX_CTRL_HSS_DISABLE |
  588. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  589. COH901318_CX_CTRL_PRDD_DEST,
  590. .param.ctrl_lli = 0 |
  591. COH901318_CX_CTRL_TC_ENABLE |
  592. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  593. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  594. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  595. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  596. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  597. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  598. COH901318_CX_CTRL_TCP_DISABLE |
  599. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  600. COH901318_CX_CTRL_HSP_ENABLE |
  601. COH901318_CX_CTRL_HSS_DISABLE |
  602. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  603. COH901318_CX_CTRL_PRDD_DEST,
  604. .param.ctrl_lli_last = 0 |
  605. COH901318_CX_CTRL_TC_ENABLE |
  606. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  607. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  608. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  609. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  610. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  611. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  612. COH901318_CX_CTRL_TCP_DISABLE |
  613. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  614. COH901318_CX_CTRL_HSP_ENABLE |
  615. COH901318_CX_CTRL_HSS_DISABLE |
  616. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  617. COH901318_CX_CTRL_PRDD_DEST,
  618. },
  619. {
  620. .number = U300_DMA_MSL_RX_4,
  621. .name = "MSL RX 4",
  622. .priority_high = 0,
  623. .param.config = COH901318_CX_CFG_CH_DISABLE |
  624. COH901318_CX_CFG_LCR_DISABLE |
  625. COH901318_CX_CFG_TC_IRQ_ENABLE |
  626. COH901318_CX_CFG_BE_IRQ_ENABLE,
  627. .param.ctrl_lli_chained = 0 |
  628. COH901318_CX_CTRL_TC_ENABLE |
  629. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  630. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  631. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  632. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  633. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  634. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  635. COH901318_CX_CTRL_TCP_DISABLE |
  636. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  637. COH901318_CX_CTRL_HSP_ENABLE |
  638. COH901318_CX_CTRL_HSS_DISABLE |
  639. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  640. COH901318_CX_CTRL_PRDD_DEST,
  641. .param.ctrl_lli = 0 |
  642. COH901318_CX_CTRL_TC_ENABLE |
  643. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  644. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  645. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  646. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  647. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  648. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  649. COH901318_CX_CTRL_TCP_DISABLE |
  650. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  651. COH901318_CX_CTRL_HSP_ENABLE |
  652. COH901318_CX_CTRL_HSS_DISABLE |
  653. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  654. COH901318_CX_CTRL_PRDD_DEST,
  655. .param.ctrl_lli_last = 0 |
  656. COH901318_CX_CTRL_TC_ENABLE |
  657. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  658. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  659. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  660. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  661. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  662. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  663. COH901318_CX_CTRL_TCP_DISABLE |
  664. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  665. COH901318_CX_CTRL_HSP_ENABLE |
  666. COH901318_CX_CTRL_HSS_DISABLE |
  667. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  668. COH901318_CX_CTRL_PRDD_DEST,
  669. },
  670. {
  671. .number = U300_DMA_MSL_RX_5,
  672. .name = "MSL RX 5",
  673. .priority_high = 0,
  674. .param.config = COH901318_CX_CFG_CH_DISABLE |
  675. COH901318_CX_CFG_LCR_DISABLE |
  676. COH901318_CX_CFG_TC_IRQ_ENABLE |
  677. COH901318_CX_CFG_BE_IRQ_ENABLE,
  678. .param.ctrl_lli_chained = 0 |
  679. COH901318_CX_CTRL_TC_ENABLE |
  680. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  681. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  682. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  683. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  684. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  685. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  686. COH901318_CX_CTRL_TCP_DISABLE |
  687. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  688. COH901318_CX_CTRL_HSP_ENABLE |
  689. COH901318_CX_CTRL_HSS_DISABLE |
  690. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  691. COH901318_CX_CTRL_PRDD_DEST,
  692. .param.ctrl_lli = 0 |
  693. COH901318_CX_CTRL_TC_ENABLE |
  694. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  695. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  696. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  697. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  698. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  699. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  700. COH901318_CX_CTRL_TCP_DISABLE |
  701. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  702. COH901318_CX_CTRL_HSP_ENABLE |
  703. COH901318_CX_CTRL_HSS_DISABLE |
  704. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  705. COH901318_CX_CTRL_PRDD_DEST,
  706. .param.ctrl_lli_last = 0 |
  707. COH901318_CX_CTRL_TC_ENABLE |
  708. COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
  709. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  710. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  711. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  712. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  713. COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
  714. COH901318_CX_CTRL_TCP_DISABLE |
  715. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  716. COH901318_CX_CTRL_HSP_ENABLE |
  717. COH901318_CX_CTRL_HSS_DISABLE |
  718. COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
  719. COH901318_CX_CTRL_PRDD_DEST,
  720. },
  721. {
  722. .number = U300_DMA_MSL_RX_6,
  723. .name = "MSL RX 6",
  724. .priority_high = 0,
  725. },
  726. /*
  727. * Don't set up device address, burst count or size of src
  728. * or dst bus for this peripheral - handled by PrimeCell
  729. * DMA extension.
  730. */
  731. {
  732. .number = U300_DMA_MMCSD_RX_TX,
  733. .name = "MMCSD RX TX",
  734. .priority_high = 0,
  735. .param.config = COH901318_CX_CFG_CH_DISABLE |
  736. COH901318_CX_CFG_LCR_DISABLE |
  737. COH901318_CX_CFG_TC_IRQ_ENABLE |
  738. COH901318_CX_CFG_BE_IRQ_ENABLE,
  739. .param.ctrl_lli_chained = 0 |
  740. COH901318_CX_CTRL_TC_ENABLE |
  741. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  742. COH901318_CX_CTRL_TCP_ENABLE |
  743. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  744. COH901318_CX_CTRL_HSP_ENABLE |
  745. COH901318_CX_CTRL_HSS_DISABLE |
  746. COH901318_CX_CTRL_DDMA_LEGACY,
  747. .param.ctrl_lli = 0 |
  748. COH901318_CX_CTRL_TC_ENABLE |
  749. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  750. COH901318_CX_CTRL_TCP_ENABLE |
  751. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  752. COH901318_CX_CTRL_HSP_ENABLE |
  753. COH901318_CX_CTRL_HSS_DISABLE |
  754. COH901318_CX_CTRL_DDMA_LEGACY,
  755. .param.ctrl_lli_last = 0 |
  756. COH901318_CX_CTRL_TC_ENABLE |
  757. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  758. COH901318_CX_CTRL_TCP_DISABLE |
  759. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  760. COH901318_CX_CTRL_HSP_ENABLE |
  761. COH901318_CX_CTRL_HSS_DISABLE |
  762. COH901318_CX_CTRL_DDMA_LEGACY,
  763. },
  764. {
  765. .number = U300_DMA_MSPRO_TX,
  766. .name = "MSPRO TX",
  767. .priority_high = 0,
  768. },
  769. {
  770. .number = U300_DMA_MSPRO_RX,
  771. .name = "MSPRO RX",
  772. .priority_high = 0,
  773. },
  774. /*
  775. * Don't set up device address, burst count or size of src
  776. * or dst bus for this peripheral - handled by PrimeCell
  777. * DMA extension.
  778. */
  779. {
  780. .number = U300_DMA_UART0_TX,
  781. .name = "UART0 TX",
  782. .priority_high = 0,
  783. .param.config = COH901318_CX_CFG_CH_DISABLE |
  784. COH901318_CX_CFG_LCR_DISABLE |
  785. COH901318_CX_CFG_TC_IRQ_ENABLE |
  786. COH901318_CX_CFG_BE_IRQ_ENABLE,
  787. .param.ctrl_lli_chained = 0 |
  788. COH901318_CX_CTRL_TC_ENABLE |
  789. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  790. COH901318_CX_CTRL_TCP_ENABLE |
  791. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  792. COH901318_CX_CTRL_HSP_ENABLE |
  793. COH901318_CX_CTRL_HSS_DISABLE |
  794. COH901318_CX_CTRL_DDMA_LEGACY,
  795. .param.ctrl_lli = 0 |
  796. COH901318_CX_CTRL_TC_ENABLE |
  797. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  798. COH901318_CX_CTRL_TCP_ENABLE |
  799. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  800. COH901318_CX_CTRL_HSP_ENABLE |
  801. COH901318_CX_CTRL_HSS_DISABLE |
  802. COH901318_CX_CTRL_DDMA_LEGACY,
  803. .param.ctrl_lli_last = 0 |
  804. COH901318_CX_CTRL_TC_ENABLE |
  805. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  806. COH901318_CX_CTRL_TCP_ENABLE |
  807. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  808. COH901318_CX_CTRL_HSP_ENABLE |
  809. COH901318_CX_CTRL_HSS_DISABLE |
  810. COH901318_CX_CTRL_DDMA_LEGACY,
  811. },
  812. {
  813. .number = U300_DMA_UART0_RX,
  814. .name = "UART0 RX",
  815. .priority_high = 0,
  816. .param.config = COH901318_CX_CFG_CH_DISABLE |
  817. COH901318_CX_CFG_LCR_DISABLE |
  818. COH901318_CX_CFG_TC_IRQ_ENABLE |
  819. COH901318_CX_CFG_BE_IRQ_ENABLE,
  820. .param.ctrl_lli_chained = 0 |
  821. COH901318_CX_CTRL_TC_ENABLE |
  822. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  823. COH901318_CX_CTRL_TCP_ENABLE |
  824. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  825. COH901318_CX_CTRL_HSP_ENABLE |
  826. COH901318_CX_CTRL_HSS_DISABLE |
  827. COH901318_CX_CTRL_DDMA_LEGACY,
  828. .param.ctrl_lli = 0 |
  829. COH901318_CX_CTRL_TC_ENABLE |
  830. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  831. COH901318_CX_CTRL_TCP_ENABLE |
  832. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  833. COH901318_CX_CTRL_HSP_ENABLE |
  834. COH901318_CX_CTRL_HSS_DISABLE |
  835. COH901318_CX_CTRL_DDMA_LEGACY,
  836. .param.ctrl_lli_last = 0 |
  837. COH901318_CX_CTRL_TC_ENABLE |
  838. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  839. COH901318_CX_CTRL_TCP_ENABLE |
  840. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  841. COH901318_CX_CTRL_HSP_ENABLE |
  842. COH901318_CX_CTRL_HSS_DISABLE |
  843. COH901318_CX_CTRL_DDMA_LEGACY,
  844. },
  845. {
  846. .number = U300_DMA_APEX_TX,
  847. .name = "APEX TX",
  848. .priority_high = 0,
  849. },
  850. {
  851. .number = U300_DMA_APEX_RX,
  852. .name = "APEX RX",
  853. .priority_high = 0,
  854. },
  855. {
  856. .number = U300_DMA_PCM_I2S0_TX,
  857. .name = "PCM I2S0 TX",
  858. .priority_high = 1,
  859. .param.config = COH901318_CX_CFG_CH_DISABLE |
  860. COH901318_CX_CFG_LCR_DISABLE |
  861. COH901318_CX_CFG_TC_IRQ_ENABLE |
  862. COH901318_CX_CFG_BE_IRQ_ENABLE,
  863. .param.ctrl_lli_chained = 0 |
  864. COH901318_CX_CTRL_TC_ENABLE |
  865. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  866. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  867. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  868. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  869. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  870. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  871. COH901318_CX_CTRL_TCP_DISABLE |
  872. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  873. COH901318_CX_CTRL_HSP_ENABLE |
  874. COH901318_CX_CTRL_HSS_DISABLE |
  875. COH901318_CX_CTRL_DDMA_LEGACY |
  876. COH901318_CX_CTRL_PRDD_SOURCE,
  877. .param.ctrl_lli = 0 |
  878. COH901318_CX_CTRL_TC_ENABLE |
  879. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  880. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  881. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  882. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  883. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  884. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  885. COH901318_CX_CTRL_TCP_ENABLE |
  886. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  887. COH901318_CX_CTRL_HSP_ENABLE |
  888. COH901318_CX_CTRL_HSS_DISABLE |
  889. COH901318_CX_CTRL_DDMA_LEGACY |
  890. COH901318_CX_CTRL_PRDD_SOURCE,
  891. .param.ctrl_lli_last = 0 |
  892. COH901318_CX_CTRL_TC_ENABLE |
  893. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  894. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  895. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  896. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  897. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  898. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  899. COH901318_CX_CTRL_TCP_ENABLE |
  900. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  901. COH901318_CX_CTRL_HSP_ENABLE |
  902. COH901318_CX_CTRL_HSS_DISABLE |
  903. COH901318_CX_CTRL_DDMA_LEGACY |
  904. COH901318_CX_CTRL_PRDD_SOURCE,
  905. },
  906. {
  907. .number = U300_DMA_PCM_I2S0_RX,
  908. .name = "PCM I2S0 RX",
  909. .priority_high = 1,
  910. .param.config = COH901318_CX_CFG_CH_DISABLE |
  911. COH901318_CX_CFG_LCR_DISABLE |
  912. COH901318_CX_CFG_TC_IRQ_ENABLE |
  913. COH901318_CX_CFG_BE_IRQ_ENABLE,
  914. .param.ctrl_lli_chained = 0 |
  915. COH901318_CX_CTRL_TC_ENABLE |
  916. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  917. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  918. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  919. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  920. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  921. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  922. COH901318_CX_CTRL_TCP_DISABLE |
  923. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  924. COH901318_CX_CTRL_HSP_ENABLE |
  925. COH901318_CX_CTRL_HSS_DISABLE |
  926. COH901318_CX_CTRL_DDMA_LEGACY |
  927. COH901318_CX_CTRL_PRDD_DEST,
  928. .param.ctrl_lli = 0 |
  929. COH901318_CX_CTRL_TC_ENABLE |
  930. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  931. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  932. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  933. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  934. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  935. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  936. COH901318_CX_CTRL_TCP_ENABLE |
  937. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  938. COH901318_CX_CTRL_HSP_ENABLE |
  939. COH901318_CX_CTRL_HSS_DISABLE |
  940. COH901318_CX_CTRL_DDMA_LEGACY |
  941. COH901318_CX_CTRL_PRDD_DEST,
  942. .param.ctrl_lli_last = 0 |
  943. COH901318_CX_CTRL_TC_ENABLE |
  944. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  945. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  946. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  947. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  948. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  949. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  950. COH901318_CX_CTRL_TCP_ENABLE |
  951. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  952. COH901318_CX_CTRL_HSP_ENABLE |
  953. COH901318_CX_CTRL_HSS_DISABLE |
  954. COH901318_CX_CTRL_DDMA_LEGACY |
  955. COH901318_CX_CTRL_PRDD_DEST,
  956. },
  957. {
  958. .number = U300_DMA_PCM_I2S1_TX,
  959. .name = "PCM I2S1 TX",
  960. .priority_high = 1,
  961. .param.config = COH901318_CX_CFG_CH_DISABLE |
  962. COH901318_CX_CFG_LCR_DISABLE |
  963. COH901318_CX_CFG_TC_IRQ_ENABLE |
  964. COH901318_CX_CFG_BE_IRQ_ENABLE,
  965. .param.ctrl_lli_chained = 0 |
  966. COH901318_CX_CTRL_TC_ENABLE |
  967. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  968. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  969. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  970. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  971. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  972. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  973. COH901318_CX_CTRL_TCP_DISABLE |
  974. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  975. COH901318_CX_CTRL_HSP_ENABLE |
  976. COH901318_CX_CTRL_HSS_DISABLE |
  977. COH901318_CX_CTRL_DDMA_LEGACY |
  978. COH901318_CX_CTRL_PRDD_SOURCE,
  979. .param.ctrl_lli = 0 |
  980. COH901318_CX_CTRL_TC_ENABLE |
  981. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  982. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  983. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  984. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  985. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  986. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  987. COH901318_CX_CTRL_TCP_ENABLE |
  988. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  989. COH901318_CX_CTRL_HSP_ENABLE |
  990. COH901318_CX_CTRL_HSS_DISABLE |
  991. COH901318_CX_CTRL_DDMA_LEGACY |
  992. COH901318_CX_CTRL_PRDD_SOURCE,
  993. .param.ctrl_lli_last = 0 |
  994. COH901318_CX_CTRL_TC_ENABLE |
  995. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  996. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  997. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
  998. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  999. COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
  1000. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1001. COH901318_CX_CTRL_TCP_ENABLE |
  1002. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  1003. COH901318_CX_CTRL_HSP_ENABLE |
  1004. COH901318_CX_CTRL_HSS_DISABLE |
  1005. COH901318_CX_CTRL_DDMA_LEGACY |
  1006. COH901318_CX_CTRL_PRDD_SOURCE,
  1007. },
  1008. {
  1009. .number = U300_DMA_PCM_I2S1_RX,
  1010. .name = "PCM I2S1 RX",
  1011. .priority_high = 1,
  1012. .param.config = COH901318_CX_CFG_CH_DISABLE |
  1013. COH901318_CX_CFG_LCR_DISABLE |
  1014. COH901318_CX_CFG_TC_IRQ_ENABLE |
  1015. COH901318_CX_CFG_BE_IRQ_ENABLE,
  1016. .param.ctrl_lli_chained = 0 |
  1017. COH901318_CX_CTRL_TC_ENABLE |
  1018. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  1019. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  1020. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  1021. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  1022. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  1023. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1024. COH901318_CX_CTRL_TCP_DISABLE |
  1025. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  1026. COH901318_CX_CTRL_HSP_ENABLE |
  1027. COH901318_CX_CTRL_HSS_DISABLE |
  1028. COH901318_CX_CTRL_DDMA_LEGACY |
  1029. COH901318_CX_CTRL_PRDD_DEST,
  1030. .param.ctrl_lli = 0 |
  1031. COH901318_CX_CTRL_TC_ENABLE |
  1032. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  1033. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  1034. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  1035. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  1036. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  1037. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1038. COH901318_CX_CTRL_TCP_ENABLE |
  1039. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  1040. COH901318_CX_CTRL_HSP_ENABLE |
  1041. COH901318_CX_CTRL_HSS_DISABLE |
  1042. COH901318_CX_CTRL_DDMA_LEGACY |
  1043. COH901318_CX_CTRL_PRDD_DEST,
  1044. .param.ctrl_lli_last = 0 |
  1045. COH901318_CX_CTRL_TC_ENABLE |
  1046. COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
  1047. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  1048. COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
  1049. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
  1050. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
  1051. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1052. COH901318_CX_CTRL_TCP_ENABLE |
  1053. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  1054. COH901318_CX_CTRL_HSP_ENABLE |
  1055. COH901318_CX_CTRL_HSS_DISABLE |
  1056. COH901318_CX_CTRL_DDMA_LEGACY |
  1057. COH901318_CX_CTRL_PRDD_DEST,
  1058. },
  1059. {
  1060. .number = U300_DMA_XGAM_CDI,
  1061. .name = "XGAM CDI",
  1062. .priority_high = 0,
  1063. },
  1064. {
  1065. .number = U300_DMA_XGAM_PDI,
  1066. .name = "XGAM PDI",
  1067. .priority_high = 0,
  1068. },
  1069. /*
  1070. * Don't set up device address, burst count or size of src
  1071. * or dst bus for this peripheral - handled by PrimeCell
  1072. * DMA extension.
  1073. */
  1074. {
  1075. .number = U300_DMA_SPI_TX,
  1076. .name = "SPI TX",
  1077. .priority_high = 0,
  1078. .param.config = COH901318_CX_CFG_CH_DISABLE |
  1079. COH901318_CX_CFG_LCR_DISABLE |
  1080. COH901318_CX_CFG_TC_IRQ_ENABLE |
  1081. COH901318_CX_CFG_BE_IRQ_ENABLE,
  1082. .param.ctrl_lli_chained = 0 |
  1083. COH901318_CX_CTRL_TC_ENABLE |
  1084. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1085. COH901318_CX_CTRL_TCP_DISABLE |
  1086. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  1087. COH901318_CX_CTRL_HSP_ENABLE |
  1088. COH901318_CX_CTRL_HSS_DISABLE |
  1089. COH901318_CX_CTRL_DDMA_LEGACY,
  1090. .param.ctrl_lli = 0 |
  1091. COH901318_CX_CTRL_TC_ENABLE |
  1092. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1093. COH901318_CX_CTRL_TCP_DISABLE |
  1094. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  1095. COH901318_CX_CTRL_HSP_ENABLE |
  1096. COH901318_CX_CTRL_HSS_DISABLE |
  1097. COH901318_CX_CTRL_DDMA_LEGACY,
  1098. .param.ctrl_lli_last = 0 |
  1099. COH901318_CX_CTRL_TC_ENABLE |
  1100. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1101. COH901318_CX_CTRL_TCP_DISABLE |
  1102. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  1103. COH901318_CX_CTRL_HSP_ENABLE |
  1104. COH901318_CX_CTRL_HSS_DISABLE |
  1105. COH901318_CX_CTRL_DDMA_LEGACY,
  1106. },
  1107. {
  1108. .number = U300_DMA_SPI_RX,
  1109. .name = "SPI RX",
  1110. .priority_high = 0,
  1111. .param.config = COH901318_CX_CFG_CH_DISABLE |
  1112. COH901318_CX_CFG_LCR_DISABLE |
  1113. COH901318_CX_CFG_TC_IRQ_ENABLE |
  1114. COH901318_CX_CFG_BE_IRQ_ENABLE,
  1115. .param.ctrl_lli_chained = 0 |
  1116. COH901318_CX_CTRL_TC_ENABLE |
  1117. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1118. COH901318_CX_CTRL_TCP_DISABLE |
  1119. COH901318_CX_CTRL_TC_IRQ_DISABLE |
  1120. COH901318_CX_CTRL_HSP_ENABLE |
  1121. COH901318_CX_CTRL_HSS_DISABLE |
  1122. COH901318_CX_CTRL_DDMA_LEGACY,
  1123. .param.ctrl_lli = 0 |
  1124. COH901318_CX_CTRL_TC_ENABLE |
  1125. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1126. COH901318_CX_CTRL_TCP_DISABLE |
  1127. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  1128. COH901318_CX_CTRL_HSP_ENABLE |
  1129. COH901318_CX_CTRL_HSS_DISABLE |
  1130. COH901318_CX_CTRL_DDMA_LEGACY,
  1131. .param.ctrl_lli_last = 0 |
  1132. COH901318_CX_CTRL_TC_ENABLE |
  1133. COH901318_CX_CTRL_MASTER_MODE_M1RW |
  1134. COH901318_CX_CTRL_TCP_DISABLE |
  1135. COH901318_CX_CTRL_TC_IRQ_ENABLE |
  1136. COH901318_CX_CTRL_HSP_ENABLE |
  1137. COH901318_CX_CTRL_HSS_DISABLE |
  1138. COH901318_CX_CTRL_DDMA_LEGACY,
  1139. },
  1140. {
  1141. .number = U300_DMA_GENERAL_PURPOSE_0,
  1142. .name = "GENERAL 00",
  1143. .priority_high = 0,
  1144. .param.config = flags_memcpy_config,
  1145. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1146. .param.ctrl_lli = flags_memcpy_lli,
  1147. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1148. },
  1149. {
  1150. .number = U300_DMA_GENERAL_PURPOSE_1,
  1151. .name = "GENERAL 01",
  1152. .priority_high = 0,
  1153. .param.config = flags_memcpy_config,
  1154. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1155. .param.ctrl_lli = flags_memcpy_lli,
  1156. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1157. },
  1158. {
  1159. .number = U300_DMA_GENERAL_PURPOSE_2,
  1160. .name = "GENERAL 02",
  1161. .priority_high = 0,
  1162. .param.config = flags_memcpy_config,
  1163. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1164. .param.ctrl_lli = flags_memcpy_lli,
  1165. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1166. },
  1167. {
  1168. .number = U300_DMA_GENERAL_PURPOSE_3,
  1169. .name = "GENERAL 03",
  1170. .priority_high = 0,
  1171. .param.config = flags_memcpy_config,
  1172. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1173. .param.ctrl_lli = flags_memcpy_lli,
  1174. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1175. },
  1176. {
  1177. .number = U300_DMA_GENERAL_PURPOSE_4,
  1178. .name = "GENERAL 04",
  1179. .priority_high = 0,
  1180. .param.config = flags_memcpy_config,
  1181. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1182. .param.ctrl_lli = flags_memcpy_lli,
  1183. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1184. },
  1185. {
  1186. .number = U300_DMA_GENERAL_PURPOSE_5,
  1187. .name = "GENERAL 05",
  1188. .priority_high = 0,
  1189. .param.config = flags_memcpy_config,
  1190. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1191. .param.ctrl_lli = flags_memcpy_lli,
  1192. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1193. },
  1194. {
  1195. .number = U300_DMA_GENERAL_PURPOSE_6,
  1196. .name = "GENERAL 06",
  1197. .priority_high = 0,
  1198. .param.config = flags_memcpy_config,
  1199. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1200. .param.ctrl_lli = flags_memcpy_lli,
  1201. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1202. },
  1203. {
  1204. .number = U300_DMA_GENERAL_PURPOSE_7,
  1205. .name = "GENERAL 07",
  1206. .priority_high = 0,
  1207. .param.config = flags_memcpy_config,
  1208. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1209. .param.ctrl_lli = flags_memcpy_lli,
  1210. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1211. },
  1212. {
  1213. .number = U300_DMA_GENERAL_PURPOSE_8,
  1214. .name = "GENERAL 08",
  1215. .priority_high = 0,
  1216. .param.config = flags_memcpy_config,
  1217. .param.ctrl_lli_chained = flags_memcpy_lli_chained,
  1218. .param.ctrl_lli = flags_memcpy_lli,
  1219. .param.ctrl_lli_last = flags_memcpy_lli_last,
  1220. },
  1221. {
  1222. .number = U300_DMA_UART1_TX,
  1223. .name = "UART1 TX",
  1224. .priority_high = 0,
  1225. },
  1226. {
  1227. .number = U300_DMA_UART1_RX,
  1228. .name = "UART1 RX",
  1229. .priority_high = 0,
  1230. }
  1231. };
  1232. #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
  1233. #ifdef VERBOSE_DEBUG
  1234. #define COH_DBG(x) ({ if (1) x; 0; })
  1235. #else
  1236. #define COH_DBG(x) ({ if (0) x; 0; })
  1237. #endif
  1238. struct coh901318_desc {
  1239. struct dma_async_tx_descriptor desc;
  1240. struct list_head node;
  1241. struct scatterlist *sg;
  1242. unsigned int sg_len;
  1243. struct coh901318_lli *lli;
  1244. enum dma_transfer_direction dir;
  1245. unsigned long flags;
  1246. u32 head_config;
  1247. u32 head_ctrl;
  1248. };
  1249. struct coh901318_base {
  1250. struct device *dev;
  1251. void __iomem *virtbase;
  1252. struct coh901318_pool pool;
  1253. struct powersave pm;
  1254. struct dma_device dma_slave;
  1255. struct dma_device dma_memcpy;
  1256. struct coh901318_chan *chans;
  1257. };
  1258. struct coh901318_chan {
  1259. spinlock_t lock;
  1260. int allocated;
  1261. int id;
  1262. int stopped;
  1263. struct work_struct free_work;
  1264. struct dma_chan chan;
  1265. struct tasklet_struct tasklet;
  1266. struct list_head active;
  1267. struct list_head queue;
  1268. struct list_head free;
  1269. unsigned long nbr_active_done;
  1270. unsigned long busy;
  1271. u32 addr;
  1272. u32 ctrl;
  1273. struct coh901318_base *base;
  1274. };
  1275. static void coh901318_list_print(struct coh901318_chan *cohc,
  1276. struct coh901318_lli *lli)
  1277. {
  1278. struct coh901318_lli *l = lli;
  1279. int i = 0;
  1280. while (l) {
  1281. dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
  1282. ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
  1283. i, l, l->control, l->src_addr, l->dst_addr,
  1284. l->link_addr, l->virt_link_addr);
  1285. i++;
  1286. l = l->virt_link_addr;
  1287. }
  1288. }
  1289. #ifdef CONFIG_DEBUG_FS
  1290. #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
  1291. static struct coh901318_base *debugfs_dma_base;
  1292. static struct dentry *dma_dentry;
  1293. static int coh901318_debugfs_read(struct file *file, char __user *buf,
  1294. size_t count, loff_t *f_pos)
  1295. {
  1296. u64 started_channels = debugfs_dma_base->pm.started_channels;
  1297. int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
  1298. int i;
  1299. int ret = 0;
  1300. char *dev_buf;
  1301. char *tmp;
  1302. int dev_size;
  1303. dev_buf = kmalloc(4*1024, GFP_KERNEL);
  1304. if (dev_buf == NULL)
  1305. goto err_kmalloc;
  1306. tmp = dev_buf;
  1307. tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
  1308. for (i = 0; i < U300_DMA_CHANNELS; i++)
  1309. if (started_channels & (1 << i))
  1310. tmp += sprintf(tmp, "channel %d\n", i);
  1311. tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
  1312. dev_size = tmp - dev_buf;
  1313. /* No more to read if offset != 0 */
  1314. if (*f_pos > dev_size)
  1315. goto out;
  1316. if (count > dev_size - *f_pos)
  1317. count = dev_size - *f_pos;
  1318. if (copy_to_user(buf, dev_buf + *f_pos, count))
  1319. ret = -EINVAL;
  1320. ret = count;
  1321. *f_pos += count;
  1322. out:
  1323. kfree(dev_buf);
  1324. return ret;
  1325. err_kmalloc:
  1326. return 0;
  1327. }
  1328. static const struct file_operations coh901318_debugfs_status_operations = {
  1329. .owner = THIS_MODULE,
  1330. .open = simple_open,
  1331. .read = coh901318_debugfs_read,
  1332. .llseek = default_llseek,
  1333. };
  1334. static int __init init_coh901318_debugfs(void)
  1335. {
  1336. dma_dentry = debugfs_create_dir("dma", NULL);
  1337. (void) debugfs_create_file("status",
  1338. S_IFREG | S_IRUGO,
  1339. dma_dentry, NULL,
  1340. &coh901318_debugfs_status_operations);
  1341. return 0;
  1342. }
  1343. static void __exit exit_coh901318_debugfs(void)
  1344. {
  1345. debugfs_remove_recursive(dma_dentry);
  1346. }
  1347. module_init(init_coh901318_debugfs);
  1348. module_exit(exit_coh901318_debugfs);
  1349. #else
  1350. #define COH901318_DEBUGFS_ASSIGN(x, y)
  1351. #endif /* CONFIG_DEBUG_FS */
  1352. static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
  1353. {
  1354. return container_of(chan, struct coh901318_chan, chan);
  1355. }
  1356. static inline const struct coh901318_params *
  1357. cohc_chan_param(struct coh901318_chan *cohc)
  1358. {
  1359. return &chan_config[cohc->id].param;
  1360. }
  1361. static inline const struct coh_dma_channel *
  1362. cohc_chan_conf(struct coh901318_chan *cohc)
  1363. {
  1364. return &chan_config[cohc->id];
  1365. }
  1366. static void enable_powersave(struct coh901318_chan *cohc)
  1367. {
  1368. unsigned long flags;
  1369. struct powersave *pm = &cohc->base->pm;
  1370. spin_lock_irqsave(&pm->lock, flags);
  1371. pm->started_channels &= ~(1ULL << cohc->id);
  1372. spin_unlock_irqrestore(&pm->lock, flags);
  1373. }
  1374. static void disable_powersave(struct coh901318_chan *cohc)
  1375. {
  1376. unsigned long flags;
  1377. struct powersave *pm = &cohc->base->pm;
  1378. spin_lock_irqsave(&pm->lock, flags);
  1379. pm->started_channels |= (1ULL << cohc->id);
  1380. spin_unlock_irqrestore(&pm->lock, flags);
  1381. }
  1382. static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
  1383. {
  1384. int channel = cohc->id;
  1385. void __iomem *virtbase = cohc->base->virtbase;
  1386. writel(control,
  1387. virtbase + COH901318_CX_CTRL +
  1388. COH901318_CX_CTRL_SPACING * channel);
  1389. return 0;
  1390. }
  1391. static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
  1392. {
  1393. int channel = cohc->id;
  1394. void __iomem *virtbase = cohc->base->virtbase;
  1395. writel(conf,
  1396. virtbase + COH901318_CX_CFG +
  1397. COH901318_CX_CFG_SPACING*channel);
  1398. return 0;
  1399. }
  1400. static int coh901318_start(struct coh901318_chan *cohc)
  1401. {
  1402. u32 val;
  1403. int channel = cohc->id;
  1404. void __iomem *virtbase = cohc->base->virtbase;
  1405. disable_powersave(cohc);
  1406. val = readl(virtbase + COH901318_CX_CFG +
  1407. COH901318_CX_CFG_SPACING * channel);
  1408. /* Enable channel */
  1409. val |= COH901318_CX_CFG_CH_ENABLE;
  1410. writel(val, virtbase + COH901318_CX_CFG +
  1411. COH901318_CX_CFG_SPACING * channel);
  1412. return 0;
  1413. }
  1414. static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
  1415. struct coh901318_lli *lli)
  1416. {
  1417. int channel = cohc->id;
  1418. void __iomem *virtbase = cohc->base->virtbase;
  1419. BUG_ON(readl(virtbase + COH901318_CX_STAT +
  1420. COH901318_CX_STAT_SPACING*channel) &
  1421. COH901318_CX_STAT_ACTIVE);
  1422. writel(lli->src_addr,
  1423. virtbase + COH901318_CX_SRC_ADDR +
  1424. COH901318_CX_SRC_ADDR_SPACING * channel);
  1425. writel(lli->dst_addr, virtbase +
  1426. COH901318_CX_DST_ADDR +
  1427. COH901318_CX_DST_ADDR_SPACING * channel);
  1428. writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
  1429. COH901318_CX_LNK_ADDR_SPACING * channel);
  1430. writel(lli->control, virtbase + COH901318_CX_CTRL +
  1431. COH901318_CX_CTRL_SPACING * channel);
  1432. return 0;
  1433. }
  1434. static struct coh901318_desc *
  1435. coh901318_desc_get(struct coh901318_chan *cohc)
  1436. {
  1437. struct coh901318_desc *desc;
  1438. if (list_empty(&cohc->free)) {
  1439. /* alloc new desc because we're out of used ones
  1440. * TODO: alloc a pile of descs instead of just one,
  1441. * avoid many small allocations.
  1442. */
  1443. desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
  1444. if (desc == NULL)
  1445. goto out;
  1446. INIT_LIST_HEAD(&desc->node);
  1447. dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
  1448. } else {
  1449. /* Reuse an old desc. */
  1450. desc = list_first_entry(&cohc->free,
  1451. struct coh901318_desc,
  1452. node);
  1453. list_del(&desc->node);
  1454. /* Initialize it a bit so it's not insane */
  1455. desc->sg = NULL;
  1456. desc->sg_len = 0;
  1457. desc->desc.callback = NULL;
  1458. desc->desc.callback_param = NULL;
  1459. }
  1460. out:
  1461. return desc;
  1462. }
  1463. static void
  1464. coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
  1465. {
  1466. list_add_tail(&cohd->node, &cohc->free);
  1467. }
  1468. /* call with irq lock held */
  1469. static void
  1470. coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
  1471. {
  1472. list_add_tail(&desc->node, &cohc->active);
  1473. }
  1474. static struct coh901318_desc *
  1475. coh901318_first_active_get(struct coh901318_chan *cohc)
  1476. {
  1477. struct coh901318_desc *d;
  1478. if (list_empty(&cohc->active))
  1479. return NULL;
  1480. d = list_first_entry(&cohc->active,
  1481. struct coh901318_desc,
  1482. node);
  1483. return d;
  1484. }
  1485. static void
  1486. coh901318_desc_remove(struct coh901318_desc *cohd)
  1487. {
  1488. list_del(&cohd->node);
  1489. }
  1490. static void
  1491. coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
  1492. {
  1493. list_add_tail(&desc->node, &cohc->queue);
  1494. }
  1495. static struct coh901318_desc *
  1496. coh901318_first_queued(struct coh901318_chan *cohc)
  1497. {
  1498. struct coh901318_desc *d;
  1499. if (list_empty(&cohc->queue))
  1500. return NULL;
  1501. d = list_first_entry(&cohc->queue,
  1502. struct coh901318_desc,
  1503. node);
  1504. return d;
  1505. }
  1506. static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
  1507. {
  1508. struct coh901318_lli *lli = in_lli;
  1509. u32 bytes = 0;
  1510. while (lli) {
  1511. bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
  1512. lli = lli->virt_link_addr;
  1513. }
  1514. return bytes;
  1515. }
  1516. /*
  1517. * Get the number of bytes left to transfer on this channel,
  1518. * it is unwise to call this before stopping the channel for
  1519. * absolute measures, but for a rough guess you can still call
  1520. * it.
  1521. */
  1522. static u32 coh901318_get_bytes_left(struct dma_chan *chan)
  1523. {
  1524. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  1525. struct coh901318_desc *cohd;
  1526. struct list_head *pos;
  1527. unsigned long flags;
  1528. u32 left = 0;
  1529. int i = 0;
  1530. spin_lock_irqsave(&cohc->lock, flags);
  1531. /*
  1532. * If there are many queued jobs, we iterate and add the
  1533. * size of them all. We take a special look on the first
  1534. * job though, since it is probably active.
  1535. */
  1536. list_for_each(pos, &cohc->active) {
  1537. /*
  1538. * The first job in the list will be working on the
  1539. * hardware. The job can be stopped but still active,
  1540. * so that the transfer counter is somewhere inside
  1541. * the buffer.
  1542. */
  1543. cohd = list_entry(pos, struct coh901318_desc, node);
  1544. if (i == 0) {
  1545. struct coh901318_lli *lli;
  1546. dma_addr_t ladd;
  1547. /* Read current transfer count value */
  1548. left = readl(cohc->base->virtbase +
  1549. COH901318_CX_CTRL +
  1550. COH901318_CX_CTRL_SPACING * cohc->id) &
  1551. COH901318_CX_CTRL_TC_VALUE_MASK;
  1552. /* See if the transfer is linked... */
  1553. ladd = readl(cohc->base->virtbase +
  1554. COH901318_CX_LNK_ADDR +
  1555. COH901318_CX_LNK_ADDR_SPACING *
  1556. cohc->id) &
  1557. ~COH901318_CX_LNK_LINK_IMMEDIATE;
  1558. /* Single transaction */
  1559. if (!ladd)
  1560. continue;
  1561. /*
  1562. * Linked transaction, follow the lli, find the
  1563. * currently processing lli, and proceed to the next
  1564. */
  1565. lli = cohd->lli;
  1566. while (lli && lli->link_addr != ladd)
  1567. lli = lli->virt_link_addr;
  1568. if (lli)
  1569. lli = lli->virt_link_addr;
  1570. /*
  1571. * Follow remaining lli links around to count the total
  1572. * number of bytes left
  1573. */
  1574. left += coh901318_get_bytes_in_lli(lli);
  1575. } else {
  1576. left += coh901318_get_bytes_in_lli(cohd->lli);
  1577. }
  1578. i++;
  1579. }
  1580. /* Also count bytes in the queued jobs */
  1581. list_for_each(pos, &cohc->queue) {
  1582. cohd = list_entry(pos, struct coh901318_desc, node);
  1583. left += coh901318_get_bytes_in_lli(cohd->lli);
  1584. }
  1585. spin_unlock_irqrestore(&cohc->lock, flags);
  1586. return left;
  1587. }
  1588. /*
  1589. * Pauses a transfer without losing data. Enables power save.
  1590. * Use this function in conjunction with coh901318_resume.
  1591. */
  1592. static void coh901318_pause(struct dma_chan *chan)
  1593. {
  1594. u32 val;
  1595. unsigned long flags;
  1596. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  1597. int channel = cohc->id;
  1598. void __iomem *virtbase = cohc->base->virtbase;
  1599. spin_lock_irqsave(&cohc->lock, flags);
  1600. /* Disable channel in HW */
  1601. val = readl(virtbase + COH901318_CX_CFG +
  1602. COH901318_CX_CFG_SPACING * channel);
  1603. /* Stopping infinite transfer */
  1604. if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
  1605. (val & COH901318_CX_CFG_CH_ENABLE))
  1606. cohc->stopped = 1;
  1607. val &= ~COH901318_CX_CFG_CH_ENABLE;
  1608. /* Enable twice, HW bug work around */
  1609. writel(val, virtbase + COH901318_CX_CFG +
  1610. COH901318_CX_CFG_SPACING * channel);
  1611. writel(val, virtbase + COH901318_CX_CFG +
  1612. COH901318_CX_CFG_SPACING * channel);
  1613. /* Spin-wait for it to actually go inactive */
  1614. while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
  1615. channel) & COH901318_CX_STAT_ACTIVE)
  1616. cpu_relax();
  1617. /* Check if we stopped an active job */
  1618. if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
  1619. channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
  1620. cohc->stopped = 1;
  1621. enable_powersave(cohc);
  1622. spin_unlock_irqrestore(&cohc->lock, flags);
  1623. }
  1624. /* Resumes a transfer that has been stopped via 300_dma_stop(..).
  1625. Power save is handled.
  1626. */
  1627. static void coh901318_resume(struct dma_chan *chan)
  1628. {
  1629. u32 val;
  1630. unsigned long flags;
  1631. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  1632. int channel = cohc->id;
  1633. spin_lock_irqsave(&cohc->lock, flags);
  1634. disable_powersave(cohc);
  1635. if (cohc->stopped) {
  1636. /* Enable channel in HW */
  1637. val = readl(cohc->base->virtbase + COH901318_CX_CFG +
  1638. COH901318_CX_CFG_SPACING * channel);
  1639. val |= COH901318_CX_CFG_CH_ENABLE;
  1640. writel(val, cohc->base->virtbase + COH901318_CX_CFG +
  1641. COH901318_CX_CFG_SPACING*channel);
  1642. cohc->stopped = 0;
  1643. }
  1644. spin_unlock_irqrestore(&cohc->lock, flags);
  1645. }
  1646. bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
  1647. {
  1648. unsigned int ch_nr = (unsigned int) chan_id;
  1649. if (ch_nr == to_coh901318_chan(chan)->id)
  1650. return true;
  1651. return false;
  1652. }
  1653. EXPORT_SYMBOL(coh901318_filter_id);
  1654. struct coh901318_filter_args {
  1655. struct coh901318_base *base;
  1656. unsigned int ch_nr;
  1657. };
  1658. static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
  1659. {
  1660. struct coh901318_filter_args *args = data;
  1661. if (&args->base->dma_slave == chan->device &&
  1662. args->ch_nr == to_coh901318_chan(chan)->id)
  1663. return true;
  1664. return false;
  1665. }
  1666. static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
  1667. struct of_dma *ofdma)
  1668. {
  1669. struct coh901318_filter_args args = {
  1670. .base = ofdma->of_dma_data,
  1671. .ch_nr = dma_spec->args[0],
  1672. };
  1673. dma_cap_mask_t cap;
  1674. dma_cap_zero(cap);
  1675. dma_cap_set(DMA_SLAVE, cap);
  1676. return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
  1677. }
  1678. /*
  1679. * DMA channel allocation
  1680. */
  1681. static int coh901318_config(struct coh901318_chan *cohc,
  1682. struct coh901318_params *param)
  1683. {
  1684. unsigned long flags;
  1685. const struct coh901318_params *p;
  1686. int channel = cohc->id;
  1687. void __iomem *virtbase = cohc->base->virtbase;
  1688. spin_lock_irqsave(&cohc->lock, flags);
  1689. if (param)
  1690. p = param;
  1691. else
  1692. p = cohc_chan_param(cohc);
  1693. /* Clear any pending BE or TC interrupt */
  1694. if (channel < 32) {
  1695. writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
  1696. writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
  1697. } else {
  1698. writel(1 << (channel - 32), virtbase +
  1699. COH901318_BE_INT_CLEAR2);
  1700. writel(1 << (channel - 32), virtbase +
  1701. COH901318_TC_INT_CLEAR2);
  1702. }
  1703. coh901318_set_conf(cohc, p->config);
  1704. coh901318_set_ctrl(cohc, p->ctrl_lli_last);
  1705. spin_unlock_irqrestore(&cohc->lock, flags);
  1706. return 0;
  1707. }
  1708. /* must lock when calling this function
  1709. * start queued jobs, if any
  1710. * TODO: start all queued jobs in one go
  1711. *
  1712. * Returns descriptor if queued job is started otherwise NULL.
  1713. * If the queue is empty NULL is returned.
  1714. */
  1715. static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
  1716. {
  1717. struct coh901318_desc *cohd;
  1718. /*
  1719. * start queued jobs, if any
  1720. * TODO: transmit all queued jobs in one go
  1721. */
  1722. cohd = coh901318_first_queued(cohc);
  1723. if (cohd != NULL) {
  1724. /* Remove from queue */
  1725. coh901318_desc_remove(cohd);
  1726. /* initiate DMA job */
  1727. cohc->busy = 1;
  1728. coh901318_desc_submit(cohc, cohd);
  1729. /* Program the transaction head */
  1730. coh901318_set_conf(cohc, cohd->head_config);
  1731. coh901318_set_ctrl(cohc, cohd->head_ctrl);
  1732. coh901318_prep_linked_list(cohc, cohd->lli);
  1733. /* start dma job on this channel */
  1734. coh901318_start(cohc);
  1735. }
  1736. return cohd;
  1737. }
  1738. /*
  1739. * This tasklet is called from the interrupt handler to
  1740. * handle each descriptor (DMA job) that is sent to a channel.
  1741. */
  1742. static void dma_tasklet(unsigned long data)
  1743. {
  1744. struct coh901318_chan *cohc = (struct coh901318_chan *) data;
  1745. struct coh901318_desc *cohd_fin;
  1746. unsigned long flags;
  1747. dma_async_tx_callback callback;
  1748. void *callback_param;
  1749. dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
  1750. " nbr_active_done %ld\n", __func__,
  1751. cohc->id, cohc->nbr_active_done);
  1752. spin_lock_irqsave(&cohc->lock, flags);
  1753. /* get first active descriptor entry from list */
  1754. cohd_fin = coh901318_first_active_get(cohc);
  1755. if (cohd_fin == NULL)
  1756. goto err;
  1757. /* locate callback to client */
  1758. callback = cohd_fin->desc.callback;
  1759. callback_param = cohd_fin->desc.callback_param;
  1760. /* sign this job as completed on the channel */
  1761. dma_cookie_complete(&cohd_fin->desc);
  1762. /* release the lli allocation and remove the descriptor */
  1763. coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
  1764. /* return desc to free-list */
  1765. coh901318_desc_remove(cohd_fin);
  1766. coh901318_desc_free(cohc, cohd_fin);
  1767. spin_unlock_irqrestore(&cohc->lock, flags);
  1768. /* Call the callback when we're done */
  1769. if (callback)
  1770. callback(callback_param);
  1771. spin_lock_irqsave(&cohc->lock, flags);
  1772. /*
  1773. * If another interrupt fired while the tasklet was scheduling,
  1774. * we don't get called twice, so we have this number of active
  1775. * counter that keep track of the number of IRQs expected to
  1776. * be handled for this channel. If there happen to be more than
  1777. * one IRQ to be ack:ed, we simply schedule this tasklet again.
  1778. */
  1779. cohc->nbr_active_done--;
  1780. if (cohc->nbr_active_done) {
  1781. dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
  1782. "came in while we were scheduling this tasklet\n");
  1783. if (cohc_chan_conf(cohc)->priority_high)
  1784. tasklet_hi_schedule(&cohc->tasklet);
  1785. else
  1786. tasklet_schedule(&cohc->tasklet);
  1787. }
  1788. spin_unlock_irqrestore(&cohc->lock, flags);
  1789. return;
  1790. err:
  1791. spin_unlock_irqrestore(&cohc->lock, flags);
  1792. dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
  1793. }
  1794. /* called from interrupt context */
  1795. static void dma_tc_handle(struct coh901318_chan *cohc)
  1796. {
  1797. /*
  1798. * If the channel is not allocated, then we shouldn't have
  1799. * any TC interrupts on it.
  1800. */
  1801. if (!cohc->allocated) {
  1802. dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
  1803. "unallocated channel\n");
  1804. return;
  1805. }
  1806. spin_lock(&cohc->lock);
  1807. /*
  1808. * When we reach this point, at least one queue item
  1809. * should have been moved over from cohc->queue to
  1810. * cohc->active and run to completion, that is why we're
  1811. * getting a terminal count interrupt is it not?
  1812. * If you get this BUG() the most probable cause is that
  1813. * the individual nodes in the lli chain have IRQ enabled,
  1814. * so check your platform config for lli chain ctrl.
  1815. */
  1816. BUG_ON(list_empty(&cohc->active));
  1817. cohc->nbr_active_done++;
  1818. /*
  1819. * This attempt to take a job from cohc->queue, put it
  1820. * into cohc->active and start it.
  1821. */
  1822. if (coh901318_queue_start(cohc) == NULL)
  1823. cohc->busy = 0;
  1824. spin_unlock(&cohc->lock);
  1825. /*
  1826. * This tasklet will remove items from cohc->active
  1827. * and thus terminates them.
  1828. */
  1829. if (cohc_chan_conf(cohc)->priority_high)
  1830. tasklet_hi_schedule(&cohc->tasklet);
  1831. else
  1832. tasklet_schedule(&cohc->tasklet);
  1833. }
  1834. static irqreturn_t dma_irq_handler(int irq, void *dev_id)
  1835. {
  1836. u32 status1;
  1837. u32 status2;
  1838. int i;
  1839. int ch;
  1840. struct coh901318_base *base = dev_id;
  1841. struct coh901318_chan *cohc;
  1842. void __iomem *virtbase = base->virtbase;
  1843. status1 = readl(virtbase + COH901318_INT_STATUS1);
  1844. status2 = readl(virtbase + COH901318_INT_STATUS2);
  1845. if (unlikely(status1 == 0 && status2 == 0)) {
  1846. dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
  1847. return IRQ_HANDLED;
  1848. }
  1849. /* TODO: consider handle IRQ in tasklet here to
  1850. * minimize interrupt latency */
  1851. /* Check the first 32 DMA channels for IRQ */
  1852. while (status1) {
  1853. /* Find first bit set, return as a number. */
  1854. i = ffs(status1) - 1;
  1855. ch = i;
  1856. cohc = &base->chans[ch];
  1857. spin_lock(&cohc->lock);
  1858. /* Mask off this bit */
  1859. status1 &= ~(1 << i);
  1860. /* Check the individual channel bits */
  1861. if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
  1862. dev_crit(COHC_2_DEV(cohc),
  1863. "DMA bus error on channel %d!\n", ch);
  1864. BUG_ON(1);
  1865. /* Clear BE interrupt */
  1866. __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
  1867. } else {
  1868. /* Caused by TC, really? */
  1869. if (unlikely(!test_bit(i, virtbase +
  1870. COH901318_TC_INT_STATUS1))) {
  1871. dev_warn(COHC_2_DEV(cohc),
  1872. "ignoring interrupt not caused by terminal count on channel %d\n", ch);
  1873. /* Clear TC interrupt */
  1874. BUG_ON(1);
  1875. __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
  1876. } else {
  1877. /* Enable powersave if transfer has finished */
  1878. if (!(readl(virtbase + COH901318_CX_STAT +
  1879. COH901318_CX_STAT_SPACING*ch) &
  1880. COH901318_CX_STAT_ENABLED)) {
  1881. enable_powersave(cohc);
  1882. }
  1883. /* Must clear TC interrupt before calling
  1884. * dma_tc_handle
  1885. * in case tc_handle initiate a new dma job
  1886. */
  1887. __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
  1888. dma_tc_handle(cohc);
  1889. }
  1890. }
  1891. spin_unlock(&cohc->lock);
  1892. }
  1893. /* Check the remaining 32 DMA channels for IRQ */
  1894. while (status2) {
  1895. /* Find first bit set, return as a number. */
  1896. i = ffs(status2) - 1;
  1897. ch = i + 32;
  1898. cohc = &base->chans[ch];
  1899. spin_lock(&cohc->lock);
  1900. /* Mask off this bit */
  1901. status2 &= ~(1 << i);
  1902. /* Check the individual channel bits */
  1903. if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
  1904. dev_crit(COHC_2_DEV(cohc),
  1905. "DMA bus error on channel %d!\n", ch);
  1906. /* Clear BE interrupt */
  1907. BUG_ON(1);
  1908. __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
  1909. } else {
  1910. /* Caused by TC, really? */
  1911. if (unlikely(!test_bit(i, virtbase +
  1912. COH901318_TC_INT_STATUS2))) {
  1913. dev_warn(COHC_2_DEV(cohc),
  1914. "ignoring interrupt not caused by terminal count on channel %d\n", ch);
  1915. /* Clear TC interrupt */
  1916. __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
  1917. BUG_ON(1);
  1918. } else {
  1919. /* Enable powersave if transfer has finished */
  1920. if (!(readl(virtbase + COH901318_CX_STAT +
  1921. COH901318_CX_STAT_SPACING*ch) &
  1922. COH901318_CX_STAT_ENABLED)) {
  1923. enable_powersave(cohc);
  1924. }
  1925. /* Must clear TC interrupt before calling
  1926. * dma_tc_handle
  1927. * in case tc_handle initiate a new dma job
  1928. */
  1929. __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
  1930. dma_tc_handle(cohc);
  1931. }
  1932. }
  1933. spin_unlock(&cohc->lock);
  1934. }
  1935. return IRQ_HANDLED;
  1936. }
  1937. static int coh901318_alloc_chan_resources(struct dma_chan *chan)
  1938. {
  1939. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  1940. unsigned long flags;
  1941. dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
  1942. __func__, cohc->id);
  1943. if (chan->client_count > 1)
  1944. return -EBUSY;
  1945. spin_lock_irqsave(&cohc->lock, flags);
  1946. coh901318_config(cohc, NULL);
  1947. cohc->allocated = 1;
  1948. dma_cookie_init(chan);
  1949. spin_unlock_irqrestore(&cohc->lock, flags);
  1950. return 1;
  1951. }
  1952. static void
  1953. coh901318_free_chan_resources(struct dma_chan *chan)
  1954. {
  1955. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  1956. int channel = cohc->id;
  1957. unsigned long flags;
  1958. spin_lock_irqsave(&cohc->lock, flags);
  1959. /* Disable HW */
  1960. writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
  1961. COH901318_CX_CFG_SPACING*channel);
  1962. writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
  1963. COH901318_CX_CTRL_SPACING*channel);
  1964. cohc->allocated = 0;
  1965. spin_unlock_irqrestore(&cohc->lock, flags);
  1966. chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
  1967. }
  1968. static dma_cookie_t
  1969. coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
  1970. {
  1971. struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
  1972. desc);
  1973. struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
  1974. unsigned long flags;
  1975. dma_cookie_t cookie;
  1976. spin_lock_irqsave(&cohc->lock, flags);
  1977. cookie = dma_cookie_assign(tx);
  1978. coh901318_desc_queue(cohc, cohd);
  1979. spin_unlock_irqrestore(&cohc->lock, flags);
  1980. return cookie;
  1981. }
  1982. static struct dma_async_tx_descriptor *
  1983. coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  1984. size_t size, unsigned long flags)
  1985. {
  1986. struct coh901318_lli *lli;
  1987. struct coh901318_desc *cohd;
  1988. unsigned long flg;
  1989. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  1990. int lli_len;
  1991. u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
  1992. int ret;
  1993. spin_lock_irqsave(&cohc->lock, flg);
  1994. dev_vdbg(COHC_2_DEV(cohc),
  1995. "[%s] channel %d src 0x%x dest 0x%x size %d\n",
  1996. __func__, cohc->id, src, dest, size);
  1997. if (flags & DMA_PREP_INTERRUPT)
  1998. /* Trigger interrupt after last lli */
  1999. ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
  2000. lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
  2001. if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
  2002. lli_len++;
  2003. lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
  2004. if (lli == NULL)
  2005. goto err;
  2006. ret = coh901318_lli_fill_memcpy(
  2007. &cohc->base->pool, lli, src, size, dest,
  2008. cohc_chan_param(cohc)->ctrl_lli_chained,
  2009. ctrl_last);
  2010. if (ret)
  2011. goto err;
  2012. COH_DBG(coh901318_list_print(cohc, lli));
  2013. /* Pick a descriptor to handle this transfer */
  2014. cohd = coh901318_desc_get(cohc);
  2015. cohd->lli = lli;
  2016. cohd->flags = flags;
  2017. cohd->desc.tx_submit = coh901318_tx_submit;
  2018. spin_unlock_irqrestore(&cohc->lock, flg);
  2019. return &cohd->desc;
  2020. err:
  2021. spin_unlock_irqrestore(&cohc->lock, flg);
  2022. return NULL;
  2023. }
  2024. static struct dma_async_tx_descriptor *
  2025. coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  2026. unsigned int sg_len, enum dma_transfer_direction direction,
  2027. unsigned long flags, void *context)
  2028. {
  2029. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  2030. struct coh901318_lli *lli;
  2031. struct coh901318_desc *cohd;
  2032. const struct coh901318_params *params;
  2033. struct scatterlist *sg;
  2034. int len = 0;
  2035. int size;
  2036. int i;
  2037. u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
  2038. u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
  2039. u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
  2040. u32 config;
  2041. unsigned long flg;
  2042. int ret;
  2043. if (!sgl)
  2044. goto out;
  2045. if (sg_dma_len(sgl) == 0)
  2046. goto out;
  2047. spin_lock_irqsave(&cohc->lock, flg);
  2048. dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
  2049. __func__, sg_len, direction);
  2050. if (flags & DMA_PREP_INTERRUPT)
  2051. /* Trigger interrupt after last lli */
  2052. ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
  2053. params = cohc_chan_param(cohc);
  2054. config = params->config;
  2055. /*
  2056. * Add runtime-specific control on top, make
  2057. * sure the bits you set per peripheral channel are
  2058. * cleared in the default config from the platform.
  2059. */
  2060. ctrl_chained |= cohc->ctrl;
  2061. ctrl_last |= cohc->ctrl;
  2062. ctrl |= cohc->ctrl;
  2063. if (direction == DMA_MEM_TO_DEV) {
  2064. u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
  2065. COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
  2066. config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
  2067. ctrl_chained |= tx_flags;
  2068. ctrl_last |= tx_flags;
  2069. ctrl |= tx_flags;
  2070. } else if (direction == DMA_DEV_TO_MEM) {
  2071. u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
  2072. COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
  2073. config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
  2074. ctrl_chained |= rx_flags;
  2075. ctrl_last |= rx_flags;
  2076. ctrl |= rx_flags;
  2077. } else
  2078. goto err_direction;
  2079. /* The dma only supports transmitting packages up to
  2080. * MAX_DMA_PACKET_SIZE. Calculate to total number of
  2081. * dma elemts required to send the entire sg list
  2082. */
  2083. for_each_sg(sgl, sg, sg_len, i) {
  2084. unsigned int factor;
  2085. size = sg_dma_len(sg);
  2086. if (size <= MAX_DMA_PACKET_SIZE) {
  2087. len++;
  2088. continue;
  2089. }
  2090. factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
  2091. if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
  2092. factor++;
  2093. len += factor;
  2094. }
  2095. pr_debug("Allocate %d lli:s for this transfer\n", len);
  2096. lli = coh901318_lli_alloc(&cohc->base->pool, len);
  2097. if (lli == NULL)
  2098. goto err_dma_alloc;
  2099. /* initiate allocated lli list */
  2100. ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
  2101. cohc->addr,
  2102. ctrl_chained,
  2103. ctrl,
  2104. ctrl_last,
  2105. direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
  2106. if (ret)
  2107. goto err_lli_fill;
  2108. COH_DBG(coh901318_list_print(cohc, lli));
  2109. /* Pick a descriptor to handle this transfer */
  2110. cohd = coh901318_desc_get(cohc);
  2111. cohd->head_config = config;
  2112. /*
  2113. * Set the default head ctrl for the channel to the one from the
  2114. * lli, things may have changed due to odd buffer alignment
  2115. * etc.
  2116. */
  2117. cohd->head_ctrl = lli->control;
  2118. cohd->dir = direction;
  2119. cohd->flags = flags;
  2120. cohd->desc.tx_submit = coh901318_tx_submit;
  2121. cohd->lli = lli;
  2122. spin_unlock_irqrestore(&cohc->lock, flg);
  2123. return &cohd->desc;
  2124. err_lli_fill:
  2125. err_dma_alloc:
  2126. err_direction:
  2127. spin_unlock_irqrestore(&cohc->lock, flg);
  2128. out:
  2129. return NULL;
  2130. }
  2131. static enum dma_status
  2132. coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
  2133. struct dma_tx_state *txstate)
  2134. {
  2135. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  2136. enum dma_status ret;
  2137. ret = dma_cookie_status(chan, cookie, txstate);
  2138. if (ret == DMA_SUCCESS)
  2139. return ret;
  2140. dma_set_residue(txstate, coh901318_get_bytes_left(chan));
  2141. if (ret == DMA_IN_PROGRESS && cohc->stopped)
  2142. ret = DMA_PAUSED;
  2143. return ret;
  2144. }
  2145. static void
  2146. coh901318_issue_pending(struct dma_chan *chan)
  2147. {
  2148. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  2149. unsigned long flags;
  2150. spin_lock_irqsave(&cohc->lock, flags);
  2151. /*
  2152. * Busy means that pending jobs are already being processed,
  2153. * and then there is no point in starting the queue: the
  2154. * terminal count interrupt on the channel will take the next
  2155. * job on the queue and execute it anyway.
  2156. */
  2157. if (!cohc->busy)
  2158. coh901318_queue_start(cohc);
  2159. spin_unlock_irqrestore(&cohc->lock, flags);
  2160. }
  2161. /*
  2162. * Here we wrap in the runtime dma control interface
  2163. */
  2164. struct burst_table {
  2165. int burst_8bit;
  2166. int burst_16bit;
  2167. int burst_32bit;
  2168. u32 reg;
  2169. };
  2170. static const struct burst_table burst_sizes[] = {
  2171. {
  2172. .burst_8bit = 64,
  2173. .burst_16bit = 32,
  2174. .burst_32bit = 16,
  2175. .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
  2176. },
  2177. {
  2178. .burst_8bit = 48,
  2179. .burst_16bit = 24,
  2180. .burst_32bit = 12,
  2181. .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
  2182. },
  2183. {
  2184. .burst_8bit = 32,
  2185. .burst_16bit = 16,
  2186. .burst_32bit = 8,
  2187. .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
  2188. },
  2189. {
  2190. .burst_8bit = 16,
  2191. .burst_16bit = 8,
  2192. .burst_32bit = 4,
  2193. .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
  2194. },
  2195. {
  2196. .burst_8bit = 8,
  2197. .burst_16bit = 4,
  2198. .burst_32bit = 2,
  2199. .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
  2200. },
  2201. {
  2202. .burst_8bit = 4,
  2203. .burst_16bit = 2,
  2204. .burst_32bit = 1,
  2205. .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
  2206. },
  2207. {
  2208. .burst_8bit = 2,
  2209. .burst_16bit = 1,
  2210. .burst_32bit = 0,
  2211. .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
  2212. },
  2213. {
  2214. .burst_8bit = 1,
  2215. .burst_16bit = 0,
  2216. .burst_32bit = 0,
  2217. .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
  2218. },
  2219. };
  2220. static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
  2221. struct dma_slave_config *config)
  2222. {
  2223. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  2224. dma_addr_t addr;
  2225. enum dma_slave_buswidth addr_width;
  2226. u32 maxburst;
  2227. u32 ctrl = 0;
  2228. int i = 0;
  2229. /* We only support mem to per or per to mem transfers */
  2230. if (config->direction == DMA_DEV_TO_MEM) {
  2231. addr = config->src_addr;
  2232. addr_width = config->src_addr_width;
  2233. maxburst = config->src_maxburst;
  2234. } else if (config->direction == DMA_MEM_TO_DEV) {
  2235. addr = config->dst_addr;
  2236. addr_width = config->dst_addr_width;
  2237. maxburst = config->dst_maxburst;
  2238. } else {
  2239. dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
  2240. return;
  2241. }
  2242. dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
  2243. addr_width);
  2244. switch (addr_width) {
  2245. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  2246. ctrl |=
  2247. COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
  2248. COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
  2249. while (i < ARRAY_SIZE(burst_sizes)) {
  2250. if (burst_sizes[i].burst_8bit <= maxburst)
  2251. break;
  2252. i++;
  2253. }
  2254. break;
  2255. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  2256. ctrl |=
  2257. COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
  2258. COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
  2259. while (i < ARRAY_SIZE(burst_sizes)) {
  2260. if (burst_sizes[i].burst_16bit <= maxburst)
  2261. break;
  2262. i++;
  2263. }
  2264. break;
  2265. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  2266. /* Direction doesn't matter here, it's 32/32 bits */
  2267. ctrl |=
  2268. COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
  2269. COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
  2270. while (i < ARRAY_SIZE(burst_sizes)) {
  2271. if (burst_sizes[i].burst_32bit <= maxburst)
  2272. break;
  2273. i++;
  2274. }
  2275. break;
  2276. default:
  2277. dev_err(COHC_2_DEV(cohc),
  2278. "bad runtimeconfig: alien address width\n");
  2279. return;
  2280. }
  2281. ctrl |= burst_sizes[i].reg;
  2282. dev_dbg(COHC_2_DEV(cohc),
  2283. "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
  2284. burst_sizes[i].burst_8bit, addr_width, maxburst);
  2285. cohc->addr = addr;
  2286. cohc->ctrl = ctrl;
  2287. }
  2288. static int
  2289. coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
  2290. unsigned long arg)
  2291. {
  2292. unsigned long flags;
  2293. struct coh901318_chan *cohc = to_coh901318_chan(chan);
  2294. struct coh901318_desc *cohd;
  2295. void __iomem *virtbase = cohc->base->virtbase;
  2296. if (cmd == DMA_SLAVE_CONFIG) {
  2297. struct dma_slave_config *config =
  2298. (struct dma_slave_config *) arg;
  2299. coh901318_dma_set_runtimeconfig(chan, config);
  2300. return 0;
  2301. }
  2302. if (cmd == DMA_PAUSE) {
  2303. coh901318_pause(chan);
  2304. return 0;
  2305. }
  2306. if (cmd == DMA_RESUME) {
  2307. coh901318_resume(chan);
  2308. return 0;
  2309. }
  2310. if (cmd != DMA_TERMINATE_ALL)
  2311. return -ENXIO;
  2312. /* The remainder of this function terminates the transfer */
  2313. coh901318_pause(chan);
  2314. spin_lock_irqsave(&cohc->lock, flags);
  2315. /* Clear any pending BE or TC interrupt */
  2316. if (cohc->id < 32) {
  2317. writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
  2318. writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
  2319. } else {
  2320. writel(1 << (cohc->id - 32), virtbase +
  2321. COH901318_BE_INT_CLEAR2);
  2322. writel(1 << (cohc->id - 32), virtbase +
  2323. COH901318_TC_INT_CLEAR2);
  2324. }
  2325. enable_powersave(cohc);
  2326. while ((cohd = coh901318_first_active_get(cohc))) {
  2327. /* release the lli allocation*/
  2328. coh901318_lli_free(&cohc->base->pool, &cohd->lli);
  2329. /* return desc to free-list */
  2330. coh901318_desc_remove(cohd);
  2331. coh901318_desc_free(cohc, cohd);
  2332. }
  2333. while ((cohd = coh901318_first_queued(cohc))) {
  2334. /* release the lli allocation*/
  2335. coh901318_lli_free(&cohc->base->pool, &cohd->lli);
  2336. /* return desc to free-list */
  2337. coh901318_desc_remove(cohd);
  2338. coh901318_desc_free(cohc, cohd);
  2339. }
  2340. cohc->nbr_active_done = 0;
  2341. cohc->busy = 0;
  2342. spin_unlock_irqrestore(&cohc->lock, flags);
  2343. return 0;
  2344. }
  2345. void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
  2346. struct coh901318_base *base)
  2347. {
  2348. int chans_i;
  2349. int i = 0;
  2350. struct coh901318_chan *cohc;
  2351. INIT_LIST_HEAD(&dma->channels);
  2352. for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
  2353. for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
  2354. cohc = &base->chans[i];
  2355. cohc->base = base;
  2356. cohc->chan.device = dma;
  2357. cohc->id = i;
  2358. /* TODO: do we really need this lock if only one
  2359. * client is connected to each channel?
  2360. */
  2361. spin_lock_init(&cohc->lock);
  2362. cohc->nbr_active_done = 0;
  2363. cohc->busy = 0;
  2364. INIT_LIST_HEAD(&cohc->free);
  2365. INIT_LIST_HEAD(&cohc->active);
  2366. INIT_LIST_HEAD(&cohc->queue);
  2367. tasklet_init(&cohc->tasklet, dma_tasklet,
  2368. (unsigned long) cohc);
  2369. list_add_tail(&cohc->chan.device_node,
  2370. &dma->channels);
  2371. }
  2372. }
  2373. }
  2374. static int __init coh901318_probe(struct platform_device *pdev)
  2375. {
  2376. int err = 0;
  2377. struct coh901318_base *base;
  2378. int irq;
  2379. struct resource *io;
  2380. io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2381. if (!io)
  2382. return -ENODEV;
  2383. /* Map DMA controller registers to virtual memory */
  2384. if (devm_request_mem_region(&pdev->dev,
  2385. io->start,
  2386. resource_size(io),
  2387. pdev->dev.driver->name) == NULL)
  2388. return -ENOMEM;
  2389. base = devm_kzalloc(&pdev->dev,
  2390. ALIGN(sizeof(struct coh901318_base), 4) +
  2391. U300_DMA_CHANNELS *
  2392. sizeof(struct coh901318_chan),
  2393. GFP_KERNEL);
  2394. if (!base)
  2395. return -ENOMEM;
  2396. base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
  2397. base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
  2398. if (!base->virtbase)
  2399. return -ENOMEM;
  2400. base->dev = &pdev->dev;
  2401. spin_lock_init(&base->pm.lock);
  2402. base->pm.started_channels = 0;
  2403. COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
  2404. irq = platform_get_irq(pdev, 0);
  2405. if (irq < 0)
  2406. return irq;
  2407. err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
  2408. "coh901318", base);
  2409. if (err)
  2410. return err;
  2411. err = coh901318_pool_create(&base->pool, &pdev->dev,
  2412. sizeof(struct coh901318_lli),
  2413. 32);
  2414. if (err)
  2415. return err;
  2416. /* init channels for device transfers */
  2417. coh901318_base_init(&base->dma_slave, dma_slave_channels,
  2418. base);
  2419. dma_cap_zero(base->dma_slave.cap_mask);
  2420. dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
  2421. base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
  2422. base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
  2423. base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
  2424. base->dma_slave.device_tx_status = coh901318_tx_status;
  2425. base->dma_slave.device_issue_pending = coh901318_issue_pending;
  2426. base->dma_slave.device_control = coh901318_control;
  2427. base->dma_slave.dev = &pdev->dev;
  2428. err = dma_async_device_register(&base->dma_slave);
  2429. if (err)
  2430. goto err_register_slave;
  2431. /* init channels for memcpy */
  2432. coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
  2433. base);
  2434. dma_cap_zero(base->dma_memcpy.cap_mask);
  2435. dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
  2436. base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
  2437. base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
  2438. base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
  2439. base->dma_memcpy.device_tx_status = coh901318_tx_status;
  2440. base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
  2441. base->dma_memcpy.device_control = coh901318_control;
  2442. base->dma_memcpy.dev = &pdev->dev;
  2443. /*
  2444. * This controller can only access address at even 32bit boundaries,
  2445. * i.e. 2^2
  2446. */
  2447. base->dma_memcpy.copy_align = 2;
  2448. err = dma_async_device_register(&base->dma_memcpy);
  2449. if (err)
  2450. goto err_register_memcpy;
  2451. err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
  2452. base);
  2453. if (err)
  2454. goto err_register_of_dma;
  2455. platform_set_drvdata(pdev, base);
  2456. dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
  2457. (u32) base->virtbase);
  2458. return err;
  2459. err_register_of_dma:
  2460. dma_async_device_unregister(&base->dma_memcpy);
  2461. err_register_memcpy:
  2462. dma_async_device_unregister(&base->dma_slave);
  2463. err_register_slave:
  2464. coh901318_pool_destroy(&base->pool);
  2465. return err;
  2466. }
  2467. static int coh901318_remove(struct platform_device *pdev)
  2468. {
  2469. struct coh901318_base *base = platform_get_drvdata(pdev);
  2470. of_dma_controller_free(pdev->dev.of_node);
  2471. dma_async_device_unregister(&base->dma_memcpy);
  2472. dma_async_device_unregister(&base->dma_slave);
  2473. coh901318_pool_destroy(&base->pool);
  2474. return 0;
  2475. }
  2476. static const struct of_device_id coh901318_dt_match[] = {
  2477. { .compatible = "stericsson,coh901318" },
  2478. {},
  2479. };
  2480. static struct platform_driver coh901318_driver = {
  2481. .remove = coh901318_remove,
  2482. .driver = {
  2483. .name = "coh901318",
  2484. .of_match_table = coh901318_dt_match,
  2485. },
  2486. };
  2487. int __init coh901318_init(void)
  2488. {
  2489. return platform_driver_probe(&coh901318_driver, coh901318_probe);
  2490. }
  2491. subsys_initcall(coh901318_init);
  2492. void __exit coh901318_exit(void)
  2493. {
  2494. platform_driver_unregister(&coh901318_driver);
  2495. }
  2496. module_exit(coh901318_exit);
  2497. MODULE_LICENSE("GPL");
  2498. MODULE_AUTHOR("Per Friden");