cs4231.c 57 KB

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  1. /*
  2. * Driver for CS4231 sound chips found on Sparcs.
  3. * Copyright (C) 2002 David S. Miller <davem@redhat.com>
  4. *
  5. * Based entirely upon drivers/sbus/audio/cs4231.c which is:
  6. * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
  7. * and also sound/isa/cs423x/cs4231_lib.c which is:
  8. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/slab.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/irq.h>
  18. #include <linux/io.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/info.h>
  22. #include <sound/control.h>
  23. #include <sound/timer.h>
  24. #include <sound/initval.h>
  25. #include <sound/pcm_params.h>
  26. #ifdef CONFIG_SBUS
  27. #define SBUS_SUPPORT
  28. #include <asm/sbus.h>
  29. #endif
  30. #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  31. #define EBUS_SUPPORT
  32. #include <linux/pci.h>
  33. #include <asm/ebus.h>
  34. #endif
  35. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  36. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  37. /* Enable this card */
  38. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  39. module_param_array(index, int, NULL, 0444);
  40. MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  41. module_param_array(id, charp, NULL, 0444);
  42. MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  43. module_param_array(enable, bool, NULL, 0444);
  44. MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  45. MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  46. MODULE_DESCRIPTION("Sun CS4231");
  47. MODULE_LICENSE("GPL");
  48. MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  49. #ifdef SBUS_SUPPORT
  50. struct sbus_dma_info {
  51. spinlock_t lock; /* DMA access lock */
  52. int dir;
  53. void __iomem *regs;
  54. };
  55. #endif
  56. struct snd_cs4231;
  57. struct cs4231_dma_control {
  58. void (*prepare)(struct cs4231_dma_control *dma_cont,
  59. int dir);
  60. void (*enable)(struct cs4231_dma_control *dma_cont, int on);
  61. int (*request)(struct cs4231_dma_control *dma_cont,
  62. dma_addr_t bus_addr, size_t len);
  63. unsigned int (*address)(struct cs4231_dma_control *dma_cont);
  64. void (*preallocate)(struct snd_cs4231 *chip,
  65. struct snd_pcm *pcm);
  66. #ifdef EBUS_SUPPORT
  67. struct ebus_dma_info ebus_info;
  68. #endif
  69. #ifdef SBUS_SUPPORT
  70. struct sbus_dma_info sbus_info;
  71. #endif
  72. };
  73. struct snd_cs4231 {
  74. spinlock_t lock; /* registers access lock */
  75. void __iomem *port;
  76. struct cs4231_dma_control p_dma;
  77. struct cs4231_dma_control c_dma;
  78. u32 flags;
  79. #define CS4231_FLAG_EBUS 0x00000001
  80. #define CS4231_FLAG_PLAYBACK 0x00000002
  81. #define CS4231_FLAG_CAPTURE 0x00000004
  82. struct snd_card *card;
  83. struct snd_pcm *pcm;
  84. struct snd_pcm_substream *playback_substream;
  85. unsigned int p_periods_sent;
  86. struct snd_pcm_substream *capture_substream;
  87. unsigned int c_periods_sent;
  88. struct snd_timer *timer;
  89. unsigned short mode;
  90. #define CS4231_MODE_NONE 0x0000
  91. #define CS4231_MODE_PLAY 0x0001
  92. #define CS4231_MODE_RECORD 0x0002
  93. #define CS4231_MODE_TIMER 0x0004
  94. #define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
  95. CS4231_MODE_TIMER)
  96. unsigned char image[32]; /* registers image */
  97. int mce_bit;
  98. int calibrate_mute;
  99. struct mutex mce_mutex; /* mutex for mce register */
  100. struct mutex open_mutex; /* mutex for ALSA open/close */
  101. union {
  102. #ifdef SBUS_SUPPORT
  103. struct sbus_dev *sdev;
  104. #endif
  105. #ifdef EBUS_SUPPORT
  106. struct pci_dev *pdev;
  107. #endif
  108. } dev_u;
  109. unsigned int irq[2];
  110. unsigned int regs_size;
  111. struct snd_cs4231 *next;
  112. };
  113. static struct snd_cs4231 *cs4231_list;
  114. /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
  115. * now.... -DaveM
  116. */
  117. /* IO ports */
  118. #include <sound/cs4231-regs.h>
  119. /* XXX offsets are different than PC ISA chips... */
  120. #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
  121. /* SBUS DMA register defines. */
  122. #define APCCSR 0x10UL /* APC DMA CSR */
  123. #define APCCVA 0x20UL /* APC Capture DMA Address */
  124. #define APCCC 0x24UL /* APC Capture Count */
  125. #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
  126. #define APCCNC 0x2cUL /* APC Capture Next Count */
  127. #define APCPVA 0x30UL /* APC Play DMA Address */
  128. #define APCPC 0x34UL /* APC Play Count */
  129. #define APCPNVA 0x38UL /* APC Play DMA Next Address */
  130. #define APCPNC 0x3cUL /* APC Play Next Count */
  131. /* Defines for SBUS DMA-routines */
  132. #define APCVA 0x0UL /* APC DMA Address */
  133. #define APCC 0x4UL /* APC Count */
  134. #define APCNVA 0x8UL /* APC DMA Next Address */
  135. #define APCNC 0xcUL /* APC Next Count */
  136. #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
  137. #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
  138. /* APCCSR bits */
  139. #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
  140. #define APC_PLAY_INT 0x400000 /* Playback interrupt */
  141. #define APC_CAPT_INT 0x200000 /* Capture interrupt */
  142. #define APC_GENL_INT 0x100000 /* General interrupt */
  143. #define APC_XINT_ENA 0x80000 /* General ext int. enable */
  144. #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
  145. #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
  146. #define APC_XINT_GENL 0x10000 /* Error ext intr */
  147. #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
  148. #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
  149. #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
  150. #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
  151. #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
  152. #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
  153. #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
  154. #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
  155. #define APC_PPAUSE 0x80 /* Pause the play DMA */
  156. #define APC_CPAUSE 0x40 /* Pause the capture DMA */
  157. #define APC_CDC_RESET 0x20 /* CODEC RESET */
  158. #define APC_PDMA_READY 0x08 /* Play DMA Go */
  159. #define APC_CDMA_READY 0x04 /* Capture DMA Go */
  160. #define APC_CHIP_RESET 0x01 /* Reset the chip */
  161. /* EBUS DMA register offsets */
  162. #define EBDMA_CSR 0x00UL /* Control/Status */
  163. #define EBDMA_ADDR 0x04UL /* DMA Address */
  164. #define EBDMA_COUNT 0x08UL /* DMA Count */
  165. /*
  166. * Some variables
  167. */
  168. static unsigned char freq_bits[14] = {
  169. /* 5510 */ 0x00 | CS4231_XTAL2,
  170. /* 6620 */ 0x0E | CS4231_XTAL2,
  171. /* 8000 */ 0x00 | CS4231_XTAL1,
  172. /* 9600 */ 0x0E | CS4231_XTAL1,
  173. /* 11025 */ 0x02 | CS4231_XTAL2,
  174. /* 16000 */ 0x02 | CS4231_XTAL1,
  175. /* 18900 */ 0x04 | CS4231_XTAL2,
  176. /* 22050 */ 0x06 | CS4231_XTAL2,
  177. /* 27042 */ 0x04 | CS4231_XTAL1,
  178. /* 32000 */ 0x06 | CS4231_XTAL1,
  179. /* 33075 */ 0x0C | CS4231_XTAL2,
  180. /* 37800 */ 0x08 | CS4231_XTAL2,
  181. /* 44100 */ 0x0A | CS4231_XTAL2,
  182. /* 48000 */ 0x0C | CS4231_XTAL1
  183. };
  184. static unsigned int rates[14] = {
  185. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  186. 27042, 32000, 33075, 37800, 44100, 48000
  187. };
  188. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  189. .count = ARRAY_SIZE(rates),
  190. .list = rates,
  191. };
  192. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  193. {
  194. return snd_pcm_hw_constraint_list(runtime, 0,
  195. SNDRV_PCM_HW_PARAM_RATE,
  196. &hw_constraints_rates);
  197. }
  198. static unsigned char snd_cs4231_original_image[32] =
  199. {
  200. 0x00, /* 00/00 - lic */
  201. 0x00, /* 01/01 - ric */
  202. 0x9f, /* 02/02 - la1ic */
  203. 0x9f, /* 03/03 - ra1ic */
  204. 0x9f, /* 04/04 - la2ic */
  205. 0x9f, /* 05/05 - ra2ic */
  206. 0xbf, /* 06/06 - loc */
  207. 0xbf, /* 07/07 - roc */
  208. 0x20, /* 08/08 - pdfr */
  209. CS4231_AUTOCALIB, /* 09/09 - ic */
  210. 0x00, /* 0a/10 - pc */
  211. 0x00, /* 0b/11 - ti */
  212. CS4231_MODE2, /* 0c/12 - mi */
  213. 0x00, /* 0d/13 - lbc */
  214. 0x00, /* 0e/14 - pbru */
  215. 0x00, /* 0f/15 - pbrl */
  216. 0x80, /* 10/16 - afei */
  217. 0x01, /* 11/17 - afeii */
  218. 0x9f, /* 12/18 - llic */
  219. 0x9f, /* 13/19 - rlic */
  220. 0x00, /* 14/20 - tlb */
  221. 0x00, /* 15/21 - thb */
  222. 0x00, /* 16/22 - la3mic/reserved */
  223. 0x00, /* 17/23 - ra3mic/reserved */
  224. 0x00, /* 18/24 - afs */
  225. 0x00, /* 19/25 - lamoc/version */
  226. 0x00, /* 1a/26 - mioc */
  227. 0x00, /* 1b/27 - ramoc/reserved */
  228. 0x20, /* 1c/28 - cdfr */
  229. 0x00, /* 1d/29 - res4 */
  230. 0x00, /* 1e/30 - cbru */
  231. 0x00, /* 1f/31 - cbrl */
  232. };
  233. static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
  234. {
  235. #ifdef EBUS_SUPPORT
  236. if (cp->flags & CS4231_FLAG_EBUS)
  237. return readb(reg_addr);
  238. else
  239. #endif
  240. #ifdef SBUS_SUPPORT
  241. return sbus_readb(reg_addr);
  242. #endif
  243. }
  244. static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
  245. void __iomem *reg_addr)
  246. {
  247. #ifdef EBUS_SUPPORT
  248. if (cp->flags & CS4231_FLAG_EBUS)
  249. return writeb(val, reg_addr);
  250. else
  251. #endif
  252. #ifdef SBUS_SUPPORT
  253. return sbus_writeb(val, reg_addr);
  254. #endif
  255. }
  256. /*
  257. * Basic I/O functions
  258. */
  259. static void snd_cs4231_ready(struct snd_cs4231 *chip)
  260. {
  261. int timeout;
  262. for (timeout = 250; timeout > 0; timeout--) {
  263. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  264. if ((val & CS4231_INIT) == 0)
  265. break;
  266. udelay(100);
  267. }
  268. }
  269. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
  270. unsigned char value)
  271. {
  272. snd_cs4231_ready(chip);
  273. #ifdef CONFIG_SND_DEBUG
  274. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  275. snd_printdd("out: auto calibration time out - reg = 0x%x, "
  276. "value = 0x%x\n",
  277. reg, value);
  278. #endif
  279. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  280. wmb();
  281. __cs4231_writeb(chip, value, CS4231U(chip, REG));
  282. mb();
  283. }
  284. static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  285. unsigned char mask, unsigned char value)
  286. {
  287. unsigned char tmp = (chip->image[reg] & mask) | value;
  288. chip->image[reg] = tmp;
  289. if (!chip->calibrate_mute)
  290. snd_cs4231_dout(chip, reg, tmp);
  291. }
  292. static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
  293. unsigned char value)
  294. {
  295. snd_cs4231_dout(chip, reg, value);
  296. chip->image[reg] = value;
  297. mb();
  298. }
  299. static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  300. {
  301. snd_cs4231_ready(chip);
  302. #ifdef CONFIG_SND_DEBUG
  303. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  304. snd_printdd("in: auto calibration time out - reg = 0x%x\n",
  305. reg);
  306. #endif
  307. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  308. mb();
  309. return __cs4231_readb(chip, CS4231U(chip, REG));
  310. }
  311. /*
  312. * CS4231 detection / MCE routines
  313. */
  314. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  315. {
  316. int timeout;
  317. /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
  318. for (timeout = 5; timeout > 0; timeout--)
  319. __cs4231_readb(chip, CS4231U(chip, REGSEL));
  320. /* end of cleanup sequence */
  321. for (timeout = 500; timeout > 0; timeout--) {
  322. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  323. if ((val & CS4231_INIT) == 0)
  324. break;
  325. msleep(1);
  326. }
  327. }
  328. static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  329. {
  330. unsigned long flags;
  331. int timeout;
  332. spin_lock_irqsave(&chip->lock, flags);
  333. snd_cs4231_ready(chip);
  334. #ifdef CONFIG_SND_DEBUG
  335. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  336. snd_printdd("mce_up - auto calibration time out (0)\n");
  337. #endif
  338. chip->mce_bit |= CS4231_MCE;
  339. timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  340. if (timeout == 0x80)
  341. snd_printdd("mce_up [%p]: serious init problem - "
  342. "codec still busy\n",
  343. chip->port);
  344. if (!(timeout & CS4231_MCE))
  345. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
  346. CS4231U(chip, REGSEL));
  347. spin_unlock_irqrestore(&chip->lock, flags);
  348. }
  349. static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  350. {
  351. unsigned long flags, timeout;
  352. int reg;
  353. snd_cs4231_busy_wait(chip);
  354. spin_lock_irqsave(&chip->lock, flags);
  355. #ifdef CONFIG_SND_DEBUG
  356. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  357. snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
  358. CS4231U(chip, REGSEL));
  359. #endif
  360. chip->mce_bit &= ~CS4231_MCE;
  361. reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  362. __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
  363. CS4231U(chip, REGSEL));
  364. if (reg == 0x80)
  365. snd_printdd("mce_down [%p]: serious init problem "
  366. "- codec still busy\n", chip->port);
  367. if ((reg & CS4231_MCE) == 0) {
  368. spin_unlock_irqrestore(&chip->lock, flags);
  369. return;
  370. }
  371. /*
  372. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  373. */
  374. timeout = jiffies + msecs_to_jiffies(250);
  375. do {
  376. spin_unlock_irqrestore(&chip->lock, flags);
  377. msleep(1);
  378. spin_lock_irqsave(&chip->lock, flags);
  379. reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
  380. reg &= CS4231_CALIB_IN_PROGRESS;
  381. } while (reg && time_before(jiffies, timeout));
  382. spin_unlock_irqrestore(&chip->lock, flags);
  383. if (reg)
  384. snd_printk(KERN_ERR
  385. "mce_down - auto calibration time out (2)\n");
  386. }
  387. static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
  388. struct snd_pcm_substream *substream,
  389. unsigned int *periods_sent)
  390. {
  391. struct snd_pcm_runtime *runtime = substream->runtime;
  392. while (1) {
  393. unsigned int period_size = snd_pcm_lib_period_bytes(substream);
  394. unsigned int offset = period_size * (*periods_sent);
  395. BUG_ON(period_size >= (1 << 24));
  396. if (dma_cont->request(dma_cont,
  397. runtime->dma_addr + offset, period_size))
  398. return;
  399. (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
  400. }
  401. }
  402. static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
  403. unsigned int what, int on)
  404. {
  405. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  406. struct cs4231_dma_control *dma_cont;
  407. if (what & CS4231_PLAYBACK_ENABLE) {
  408. dma_cont = &chip->p_dma;
  409. if (on) {
  410. dma_cont->prepare(dma_cont, 0);
  411. dma_cont->enable(dma_cont, 1);
  412. snd_cs4231_advance_dma(dma_cont,
  413. chip->playback_substream,
  414. &chip->p_periods_sent);
  415. } else {
  416. dma_cont->enable(dma_cont, 0);
  417. }
  418. }
  419. if (what & CS4231_RECORD_ENABLE) {
  420. dma_cont = &chip->c_dma;
  421. if (on) {
  422. dma_cont->prepare(dma_cont, 1);
  423. dma_cont->enable(dma_cont, 1);
  424. snd_cs4231_advance_dma(dma_cont,
  425. chip->capture_substream,
  426. &chip->c_periods_sent);
  427. } else {
  428. dma_cont->enable(dma_cont, 0);
  429. }
  430. }
  431. }
  432. static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
  433. {
  434. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  435. int result = 0;
  436. switch (cmd) {
  437. case SNDRV_PCM_TRIGGER_START:
  438. case SNDRV_PCM_TRIGGER_STOP:
  439. {
  440. unsigned int what = 0;
  441. struct snd_pcm_substream *s;
  442. unsigned long flags;
  443. snd_pcm_group_for_each_entry(s, substream) {
  444. if (s == chip->playback_substream) {
  445. what |= CS4231_PLAYBACK_ENABLE;
  446. snd_pcm_trigger_done(s, substream);
  447. } else if (s == chip->capture_substream) {
  448. what |= CS4231_RECORD_ENABLE;
  449. snd_pcm_trigger_done(s, substream);
  450. }
  451. }
  452. spin_lock_irqsave(&chip->lock, flags);
  453. if (cmd == SNDRV_PCM_TRIGGER_START) {
  454. cs4231_dma_trigger(substream, what, 1);
  455. chip->image[CS4231_IFACE_CTRL] |= what;
  456. } else {
  457. cs4231_dma_trigger(substream, what, 0);
  458. chip->image[CS4231_IFACE_CTRL] &= ~what;
  459. }
  460. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  461. chip->image[CS4231_IFACE_CTRL]);
  462. spin_unlock_irqrestore(&chip->lock, flags);
  463. break;
  464. }
  465. default:
  466. result = -EINVAL;
  467. break;
  468. }
  469. return result;
  470. }
  471. /*
  472. * CODEC I/O
  473. */
  474. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  475. {
  476. int i;
  477. for (i = 0; i < 14; i++)
  478. if (rate == rates[i])
  479. return freq_bits[i];
  480. return freq_bits[13];
  481. }
  482. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
  483. int channels)
  484. {
  485. unsigned char rformat;
  486. rformat = CS4231_LINEAR_8;
  487. switch (format) {
  488. case SNDRV_PCM_FORMAT_MU_LAW:
  489. rformat = CS4231_ULAW_8;
  490. break;
  491. case SNDRV_PCM_FORMAT_A_LAW:
  492. rformat = CS4231_ALAW_8;
  493. break;
  494. case SNDRV_PCM_FORMAT_S16_LE:
  495. rformat = CS4231_LINEAR_16;
  496. break;
  497. case SNDRV_PCM_FORMAT_S16_BE:
  498. rformat = CS4231_LINEAR_16_BIG;
  499. break;
  500. case SNDRV_PCM_FORMAT_IMA_ADPCM:
  501. rformat = CS4231_ADPCM_16;
  502. break;
  503. }
  504. if (channels > 1)
  505. rformat |= CS4231_STEREO;
  506. return rformat;
  507. }
  508. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  509. {
  510. unsigned long flags;
  511. mute = mute ? 1 : 0;
  512. spin_lock_irqsave(&chip->lock, flags);
  513. if (chip->calibrate_mute == mute) {
  514. spin_unlock_irqrestore(&chip->lock, flags);
  515. return;
  516. }
  517. if (!mute) {
  518. snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
  519. chip->image[CS4231_LEFT_INPUT]);
  520. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
  521. chip->image[CS4231_RIGHT_INPUT]);
  522. snd_cs4231_dout(chip, CS4231_LOOPBACK,
  523. chip->image[CS4231_LOOPBACK]);
  524. }
  525. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
  526. mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  527. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  528. mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  529. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
  530. mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  531. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  532. mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  533. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
  534. mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  535. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
  536. mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  537. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
  538. mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  539. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
  540. mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  541. snd_cs4231_dout(chip, CS4231_MONO_CTRL,
  542. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  543. chip->calibrate_mute = mute;
  544. spin_unlock_irqrestore(&chip->lock, flags);
  545. }
  546. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  547. struct snd_pcm_hw_params *params,
  548. unsigned char pdfr)
  549. {
  550. unsigned long flags;
  551. mutex_lock(&chip->mce_mutex);
  552. snd_cs4231_calibrate_mute(chip, 1);
  553. snd_cs4231_mce_up(chip);
  554. spin_lock_irqsave(&chip->lock, flags);
  555. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  556. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  557. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  558. pdfr);
  559. spin_unlock_irqrestore(&chip->lock, flags);
  560. snd_cs4231_mce_down(chip);
  561. snd_cs4231_calibrate_mute(chip, 0);
  562. mutex_unlock(&chip->mce_mutex);
  563. }
  564. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  565. struct snd_pcm_hw_params *params,
  566. unsigned char cdfr)
  567. {
  568. unsigned long flags;
  569. mutex_lock(&chip->mce_mutex);
  570. snd_cs4231_calibrate_mute(chip, 1);
  571. snd_cs4231_mce_up(chip);
  572. spin_lock_irqsave(&chip->lock, flags);
  573. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  574. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  575. ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  576. (cdfr & 0x0f));
  577. spin_unlock_irqrestore(&chip->lock, flags);
  578. snd_cs4231_mce_down(chip);
  579. snd_cs4231_mce_up(chip);
  580. spin_lock_irqsave(&chip->lock, flags);
  581. }
  582. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  583. spin_unlock_irqrestore(&chip->lock, flags);
  584. snd_cs4231_mce_down(chip);
  585. snd_cs4231_calibrate_mute(chip, 0);
  586. mutex_unlock(&chip->mce_mutex);
  587. }
  588. /*
  589. * Timer interface
  590. */
  591. static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
  592. {
  593. struct snd_cs4231 *chip = snd_timer_chip(timer);
  594. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  595. }
  596. static int snd_cs4231_timer_start(struct snd_timer *timer)
  597. {
  598. unsigned long flags;
  599. unsigned int ticks;
  600. struct snd_cs4231 *chip = snd_timer_chip(timer);
  601. spin_lock_irqsave(&chip->lock, flags);
  602. ticks = timer->sticks;
  603. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  604. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  605. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  606. snd_cs4231_out(chip, CS4231_TIMER_HIGH,
  607. chip->image[CS4231_TIMER_HIGH] =
  608. (unsigned char) (ticks >> 8));
  609. snd_cs4231_out(chip, CS4231_TIMER_LOW,
  610. chip->image[CS4231_TIMER_LOW] =
  611. (unsigned char) ticks);
  612. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  613. chip->image[CS4231_ALT_FEATURE_1] |
  614. CS4231_TIMER_ENABLE);
  615. }
  616. spin_unlock_irqrestore(&chip->lock, flags);
  617. return 0;
  618. }
  619. static int snd_cs4231_timer_stop(struct snd_timer *timer)
  620. {
  621. unsigned long flags;
  622. struct snd_cs4231 *chip = snd_timer_chip(timer);
  623. spin_lock_irqsave(&chip->lock, flags);
  624. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
  625. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  626. chip->image[CS4231_ALT_FEATURE_1]);
  627. spin_unlock_irqrestore(&chip->lock, flags);
  628. return 0;
  629. }
  630. static void __init snd_cs4231_init(struct snd_cs4231 *chip)
  631. {
  632. unsigned long flags;
  633. snd_cs4231_mce_down(chip);
  634. #ifdef SNDRV_DEBUG_MCE
  635. snd_printdd("init: (1)\n");
  636. #endif
  637. snd_cs4231_mce_up(chip);
  638. spin_lock_irqsave(&chip->lock, flags);
  639. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  640. CS4231_PLAYBACK_PIO |
  641. CS4231_RECORD_ENABLE |
  642. CS4231_RECORD_PIO |
  643. CS4231_CALIB_MODE);
  644. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  645. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  646. spin_unlock_irqrestore(&chip->lock, flags);
  647. snd_cs4231_mce_down(chip);
  648. #ifdef SNDRV_DEBUG_MCE
  649. snd_printdd("init: (2)\n");
  650. #endif
  651. snd_cs4231_mce_up(chip);
  652. spin_lock_irqsave(&chip->lock, flags);
  653. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  654. chip->image[CS4231_ALT_FEATURE_1]);
  655. spin_unlock_irqrestore(&chip->lock, flags);
  656. snd_cs4231_mce_down(chip);
  657. #ifdef SNDRV_DEBUG_MCE
  658. snd_printdd("init: (3) - afei = 0x%x\n",
  659. chip->image[CS4231_ALT_FEATURE_1]);
  660. #endif
  661. spin_lock_irqsave(&chip->lock, flags);
  662. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
  663. chip->image[CS4231_ALT_FEATURE_2]);
  664. spin_unlock_irqrestore(&chip->lock, flags);
  665. snd_cs4231_mce_up(chip);
  666. spin_lock_irqsave(&chip->lock, flags);
  667. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  668. chip->image[CS4231_PLAYBK_FORMAT]);
  669. spin_unlock_irqrestore(&chip->lock, flags);
  670. snd_cs4231_mce_down(chip);
  671. #ifdef SNDRV_DEBUG_MCE
  672. snd_printdd("init: (4)\n");
  673. #endif
  674. snd_cs4231_mce_up(chip);
  675. spin_lock_irqsave(&chip->lock, flags);
  676. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  677. spin_unlock_irqrestore(&chip->lock, flags);
  678. snd_cs4231_mce_down(chip);
  679. #ifdef SNDRV_DEBUG_MCE
  680. snd_printdd("init: (5)\n");
  681. #endif
  682. }
  683. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  684. {
  685. unsigned long flags;
  686. mutex_lock(&chip->open_mutex);
  687. if ((chip->mode & mode)) {
  688. mutex_unlock(&chip->open_mutex);
  689. return -EAGAIN;
  690. }
  691. if (chip->mode & CS4231_MODE_OPEN) {
  692. chip->mode |= mode;
  693. mutex_unlock(&chip->open_mutex);
  694. return 0;
  695. }
  696. /* ok. now enable and ack CODEC IRQ */
  697. spin_lock_irqsave(&chip->lock, flags);
  698. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  699. CS4231_RECORD_IRQ |
  700. CS4231_TIMER_IRQ);
  701. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  702. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  703. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  704. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  705. CS4231_RECORD_IRQ |
  706. CS4231_TIMER_IRQ);
  707. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  708. spin_unlock_irqrestore(&chip->lock, flags);
  709. chip->mode = mode;
  710. mutex_unlock(&chip->open_mutex);
  711. return 0;
  712. }
  713. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  714. {
  715. unsigned long flags;
  716. mutex_lock(&chip->open_mutex);
  717. chip->mode &= ~mode;
  718. if (chip->mode & CS4231_MODE_OPEN) {
  719. mutex_unlock(&chip->open_mutex);
  720. return;
  721. }
  722. snd_cs4231_calibrate_mute(chip, 1);
  723. /* disable IRQ */
  724. spin_lock_irqsave(&chip->lock, flags);
  725. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  726. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  727. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  728. /* now disable record & playback */
  729. if (chip->image[CS4231_IFACE_CTRL] &
  730. (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  731. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  732. spin_unlock_irqrestore(&chip->lock, flags);
  733. snd_cs4231_mce_up(chip);
  734. spin_lock_irqsave(&chip->lock, flags);
  735. chip->image[CS4231_IFACE_CTRL] &=
  736. ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  737. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  738. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  739. chip->image[CS4231_IFACE_CTRL]);
  740. spin_unlock_irqrestore(&chip->lock, flags);
  741. snd_cs4231_mce_down(chip);
  742. spin_lock_irqsave(&chip->lock, flags);
  743. }
  744. /* clear IRQ again */
  745. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  746. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  747. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  748. spin_unlock_irqrestore(&chip->lock, flags);
  749. snd_cs4231_calibrate_mute(chip, 0);
  750. chip->mode = 0;
  751. mutex_unlock(&chip->open_mutex);
  752. }
  753. /*
  754. * timer open/close
  755. */
  756. static int snd_cs4231_timer_open(struct snd_timer *timer)
  757. {
  758. struct snd_cs4231 *chip = snd_timer_chip(timer);
  759. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  760. return 0;
  761. }
  762. static int snd_cs4231_timer_close(struct snd_timer *timer)
  763. {
  764. struct snd_cs4231 *chip = snd_timer_chip(timer);
  765. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  766. return 0;
  767. }
  768. static struct snd_timer_hardware snd_cs4231_timer_table = {
  769. .flags = SNDRV_TIMER_HW_AUTO,
  770. .resolution = 9945,
  771. .ticks = 65535,
  772. .open = snd_cs4231_timer_open,
  773. .close = snd_cs4231_timer_close,
  774. .c_resolution = snd_cs4231_timer_resolution,
  775. .start = snd_cs4231_timer_start,
  776. .stop = snd_cs4231_timer_stop,
  777. };
  778. /*
  779. * ok.. exported functions..
  780. */
  781. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  782. struct snd_pcm_hw_params *hw_params)
  783. {
  784. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  785. unsigned char new_pdfr;
  786. int err;
  787. err = snd_pcm_lib_malloc_pages(substream,
  788. params_buffer_bytes(hw_params));
  789. if (err < 0)
  790. return err;
  791. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  792. params_channels(hw_params)) |
  793. snd_cs4231_get_rate(params_rate(hw_params));
  794. snd_cs4231_playback_format(chip, hw_params, new_pdfr);
  795. return 0;
  796. }
  797. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  798. {
  799. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  800. struct snd_pcm_runtime *runtime = substream->runtime;
  801. unsigned long flags;
  802. spin_lock_irqsave(&chip->lock, flags);
  803. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  804. CS4231_PLAYBACK_PIO);
  805. BUG_ON(runtime->period_size > 0xffff + 1);
  806. chip->p_periods_sent = 0;
  807. spin_unlock_irqrestore(&chip->lock, flags);
  808. return 0;
  809. }
  810. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  811. struct snd_pcm_hw_params *hw_params)
  812. {
  813. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  814. unsigned char new_cdfr;
  815. int err;
  816. err = snd_pcm_lib_malloc_pages(substream,
  817. params_buffer_bytes(hw_params));
  818. if (err < 0)
  819. return err;
  820. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  821. params_channels(hw_params)) |
  822. snd_cs4231_get_rate(params_rate(hw_params));
  823. snd_cs4231_capture_format(chip, hw_params, new_cdfr);
  824. return 0;
  825. }
  826. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  827. {
  828. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  829. unsigned long flags;
  830. spin_lock_irqsave(&chip->lock, flags);
  831. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
  832. CS4231_RECORD_PIO);
  833. chip->c_periods_sent = 0;
  834. spin_unlock_irqrestore(&chip->lock, flags);
  835. return 0;
  836. }
  837. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  838. {
  839. unsigned long flags;
  840. unsigned char res;
  841. spin_lock_irqsave(&chip->lock, flags);
  842. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  843. spin_unlock_irqrestore(&chip->lock, flags);
  844. /* detect overrange only above 0dB; may be user selectable? */
  845. if (res & (0x08 | 0x02))
  846. chip->capture_substream->runtime->overrange++;
  847. }
  848. static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
  849. {
  850. if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
  851. snd_pcm_period_elapsed(chip->playback_substream);
  852. snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
  853. &chip->p_periods_sent);
  854. }
  855. }
  856. static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
  857. {
  858. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
  859. snd_pcm_period_elapsed(chip->capture_substream);
  860. snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
  861. &chip->c_periods_sent);
  862. }
  863. }
  864. static snd_pcm_uframes_t snd_cs4231_playback_pointer(
  865. struct snd_pcm_substream *substream)
  866. {
  867. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  868. struct cs4231_dma_control *dma_cont = &chip->p_dma;
  869. size_t ptr;
  870. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  871. return 0;
  872. ptr = dma_cont->address(dma_cont);
  873. if (ptr != 0)
  874. ptr -= substream->runtime->dma_addr;
  875. return bytes_to_frames(substream->runtime, ptr);
  876. }
  877. static snd_pcm_uframes_t snd_cs4231_capture_pointer(
  878. struct snd_pcm_substream *substream)
  879. {
  880. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  881. struct cs4231_dma_control *dma_cont = &chip->c_dma;
  882. size_t ptr;
  883. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  884. return 0;
  885. ptr = dma_cont->address(dma_cont);
  886. if (ptr != 0)
  887. ptr -= substream->runtime->dma_addr;
  888. return bytes_to_frames(substream->runtime, ptr);
  889. }
  890. static int __init snd_cs4231_probe(struct snd_cs4231 *chip)
  891. {
  892. unsigned long flags;
  893. int i;
  894. int id = 0;
  895. int vers = 0;
  896. unsigned char *ptr;
  897. for (i = 0; i < 50; i++) {
  898. mb();
  899. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  900. msleep(2);
  901. else {
  902. spin_lock_irqsave(&chip->lock, flags);
  903. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  904. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  905. vers = snd_cs4231_in(chip, CS4231_VERSION);
  906. spin_unlock_irqrestore(&chip->lock, flags);
  907. if (id == 0x0a)
  908. break; /* this is valid value */
  909. }
  910. }
  911. snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
  912. if (id != 0x0a)
  913. return -ENODEV; /* no valid device found */
  914. spin_lock_irqsave(&chip->lock, flags);
  915. /* clear any pendings IRQ */
  916. __cs4231_readb(chip, CS4231U(chip, STATUS));
  917. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
  918. mb();
  919. spin_unlock_irqrestore(&chip->lock, flags);
  920. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  921. chip->image[CS4231_IFACE_CTRL] =
  922. chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
  923. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  924. chip->image[CS4231_ALT_FEATURE_2] = 0x01;
  925. if (vers & 0x20)
  926. chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
  927. ptr = (unsigned char *) &chip->image;
  928. snd_cs4231_mce_down(chip);
  929. spin_lock_irqsave(&chip->lock, flags);
  930. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  931. snd_cs4231_out(chip, i, *ptr++);
  932. spin_unlock_irqrestore(&chip->lock, flags);
  933. snd_cs4231_mce_up(chip);
  934. snd_cs4231_mce_down(chip);
  935. mdelay(2);
  936. return 0; /* all things are ok.. */
  937. }
  938. static struct snd_pcm_hardware snd_cs4231_playback = {
  939. .info = SNDRV_PCM_INFO_MMAP |
  940. SNDRV_PCM_INFO_INTERLEAVED |
  941. SNDRV_PCM_INFO_MMAP_VALID |
  942. SNDRV_PCM_INFO_SYNC_START,
  943. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  944. SNDRV_PCM_FMTBIT_A_LAW |
  945. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  946. SNDRV_PCM_FMTBIT_U8 |
  947. SNDRV_PCM_FMTBIT_S16_LE |
  948. SNDRV_PCM_FMTBIT_S16_BE,
  949. .rates = SNDRV_PCM_RATE_KNOT |
  950. SNDRV_PCM_RATE_8000_48000,
  951. .rate_min = 5510,
  952. .rate_max = 48000,
  953. .channels_min = 1,
  954. .channels_max = 2,
  955. .buffer_bytes_max = 32 * 1024,
  956. .period_bytes_min = 64,
  957. .period_bytes_max = 32 * 1024,
  958. .periods_min = 1,
  959. .periods_max = 1024,
  960. };
  961. static struct snd_pcm_hardware snd_cs4231_capture = {
  962. .info = SNDRV_PCM_INFO_MMAP |
  963. SNDRV_PCM_INFO_INTERLEAVED |
  964. SNDRV_PCM_INFO_MMAP_VALID |
  965. SNDRV_PCM_INFO_SYNC_START,
  966. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  967. SNDRV_PCM_FMTBIT_A_LAW |
  968. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  969. SNDRV_PCM_FMTBIT_U8 |
  970. SNDRV_PCM_FMTBIT_S16_LE |
  971. SNDRV_PCM_FMTBIT_S16_BE,
  972. .rates = SNDRV_PCM_RATE_KNOT |
  973. SNDRV_PCM_RATE_8000_48000,
  974. .rate_min = 5510,
  975. .rate_max = 48000,
  976. .channels_min = 1,
  977. .channels_max = 2,
  978. .buffer_bytes_max = 32 * 1024,
  979. .period_bytes_min = 64,
  980. .period_bytes_max = 32 * 1024,
  981. .periods_min = 1,
  982. .periods_max = 1024,
  983. };
  984. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  985. {
  986. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  987. struct snd_pcm_runtime *runtime = substream->runtime;
  988. int err;
  989. runtime->hw = snd_cs4231_playback;
  990. err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
  991. if (err < 0) {
  992. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  993. return err;
  994. }
  995. chip->playback_substream = substream;
  996. chip->p_periods_sent = 0;
  997. snd_pcm_set_sync(substream);
  998. snd_cs4231_xrate(runtime);
  999. return 0;
  1000. }
  1001. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  1002. {
  1003. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1004. struct snd_pcm_runtime *runtime = substream->runtime;
  1005. int err;
  1006. runtime->hw = snd_cs4231_capture;
  1007. err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
  1008. if (err < 0) {
  1009. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1010. return err;
  1011. }
  1012. chip->capture_substream = substream;
  1013. chip->c_periods_sent = 0;
  1014. snd_pcm_set_sync(substream);
  1015. snd_cs4231_xrate(runtime);
  1016. return 0;
  1017. }
  1018. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1019. {
  1020. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1021. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1022. chip->playback_substream = NULL;
  1023. return 0;
  1024. }
  1025. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1026. {
  1027. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1028. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1029. chip->capture_substream = NULL;
  1030. return 0;
  1031. }
  1032. /* XXX We can do some power-management, in particular on EBUS using
  1033. * XXX the audio AUXIO register...
  1034. */
  1035. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1036. .open = snd_cs4231_playback_open,
  1037. .close = snd_cs4231_playback_close,
  1038. .ioctl = snd_pcm_lib_ioctl,
  1039. .hw_params = snd_cs4231_playback_hw_params,
  1040. .hw_free = snd_pcm_lib_free_pages,
  1041. .prepare = snd_cs4231_playback_prepare,
  1042. .trigger = snd_cs4231_trigger,
  1043. .pointer = snd_cs4231_playback_pointer,
  1044. };
  1045. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1046. .open = snd_cs4231_capture_open,
  1047. .close = snd_cs4231_capture_close,
  1048. .ioctl = snd_pcm_lib_ioctl,
  1049. .hw_params = snd_cs4231_capture_hw_params,
  1050. .hw_free = snd_pcm_lib_free_pages,
  1051. .prepare = snd_cs4231_capture_prepare,
  1052. .trigger = snd_cs4231_trigger,
  1053. .pointer = snd_cs4231_capture_pointer,
  1054. };
  1055. static int __init snd_cs4231_pcm(struct snd_card *card)
  1056. {
  1057. struct snd_cs4231 *chip = card->private_data;
  1058. struct snd_pcm *pcm;
  1059. int err;
  1060. err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
  1061. if (err < 0)
  1062. return err;
  1063. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1064. &snd_cs4231_playback_ops);
  1065. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1066. &snd_cs4231_capture_ops);
  1067. /* global setup */
  1068. pcm->private_data = chip;
  1069. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1070. strcpy(pcm->name, "CS4231");
  1071. chip->p_dma.preallocate(chip, pcm);
  1072. chip->pcm = pcm;
  1073. return 0;
  1074. }
  1075. static int __init snd_cs4231_timer(struct snd_card *card)
  1076. {
  1077. struct snd_cs4231 *chip = card->private_data;
  1078. struct snd_timer *timer;
  1079. struct snd_timer_id tid;
  1080. int err;
  1081. /* Timer initialization */
  1082. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1083. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1084. tid.card = card->number;
  1085. tid.device = 0;
  1086. tid.subdevice = 0;
  1087. err = snd_timer_new(card, "CS4231", &tid, &timer);
  1088. if (err < 0)
  1089. return err;
  1090. strcpy(timer->name, "CS4231");
  1091. timer->private_data = chip;
  1092. timer->hw = snd_cs4231_timer_table;
  1093. chip->timer = timer;
  1094. return 0;
  1095. }
  1096. /*
  1097. * MIXER part
  1098. */
  1099. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
  1100. struct snd_ctl_elem_info *uinfo)
  1101. {
  1102. static char *texts[4] = {
  1103. "Line", "CD", "Mic", "Mix"
  1104. };
  1105. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1106. uinfo->count = 2;
  1107. uinfo->value.enumerated.items = 4;
  1108. if (uinfo->value.enumerated.item > 3)
  1109. uinfo->value.enumerated.item = 3;
  1110. strcpy(uinfo->value.enumerated.name,
  1111. texts[uinfo->value.enumerated.item]);
  1112. return 0;
  1113. }
  1114. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
  1115. struct snd_ctl_elem_value *ucontrol)
  1116. {
  1117. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1118. unsigned long flags;
  1119. spin_lock_irqsave(&chip->lock, flags);
  1120. ucontrol->value.enumerated.item[0] =
  1121. (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1122. ucontrol->value.enumerated.item[1] =
  1123. (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1124. spin_unlock_irqrestore(&chip->lock, flags);
  1125. return 0;
  1126. }
  1127. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
  1128. struct snd_ctl_elem_value *ucontrol)
  1129. {
  1130. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1131. unsigned long flags;
  1132. unsigned short left, right;
  1133. int change;
  1134. if (ucontrol->value.enumerated.item[0] > 3 ||
  1135. ucontrol->value.enumerated.item[1] > 3)
  1136. return -EINVAL;
  1137. left = ucontrol->value.enumerated.item[0] << 6;
  1138. right = ucontrol->value.enumerated.item[1] << 6;
  1139. spin_lock_irqsave(&chip->lock, flags);
  1140. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1141. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1142. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1143. right != chip->image[CS4231_RIGHT_INPUT];
  1144. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1145. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1146. spin_unlock_irqrestore(&chip->lock, flags);
  1147. return change;
  1148. }
  1149. static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
  1150. struct snd_ctl_elem_info *uinfo)
  1151. {
  1152. int mask = (kcontrol->private_value >> 16) & 0xff;
  1153. uinfo->type = (mask == 1) ?
  1154. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1155. uinfo->count = 1;
  1156. uinfo->value.integer.min = 0;
  1157. uinfo->value.integer.max = mask;
  1158. return 0;
  1159. }
  1160. static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
  1161. struct snd_ctl_elem_value *ucontrol)
  1162. {
  1163. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1164. unsigned long flags;
  1165. int reg = kcontrol->private_value & 0xff;
  1166. int shift = (kcontrol->private_value >> 8) & 0xff;
  1167. int mask = (kcontrol->private_value >> 16) & 0xff;
  1168. int invert = (kcontrol->private_value >> 24) & 0xff;
  1169. spin_lock_irqsave(&chip->lock, flags);
  1170. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1171. spin_unlock_irqrestore(&chip->lock, flags);
  1172. if (invert)
  1173. ucontrol->value.integer.value[0] =
  1174. (mask - ucontrol->value.integer.value[0]);
  1175. return 0;
  1176. }
  1177. static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
  1178. struct snd_ctl_elem_value *ucontrol)
  1179. {
  1180. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1181. unsigned long flags;
  1182. int reg = kcontrol->private_value & 0xff;
  1183. int shift = (kcontrol->private_value >> 8) & 0xff;
  1184. int mask = (kcontrol->private_value >> 16) & 0xff;
  1185. int invert = (kcontrol->private_value >> 24) & 0xff;
  1186. int change;
  1187. unsigned short val;
  1188. val = (ucontrol->value.integer.value[0] & mask);
  1189. if (invert)
  1190. val = mask - val;
  1191. val <<= shift;
  1192. spin_lock_irqsave(&chip->lock, flags);
  1193. val = (chip->image[reg] & ~(mask << shift)) | val;
  1194. change = val != chip->image[reg];
  1195. snd_cs4231_out(chip, reg, val);
  1196. spin_unlock_irqrestore(&chip->lock, flags);
  1197. return change;
  1198. }
  1199. static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
  1200. struct snd_ctl_elem_info *uinfo)
  1201. {
  1202. int mask = (kcontrol->private_value >> 24) & 0xff;
  1203. uinfo->type = mask == 1 ?
  1204. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1205. uinfo->count = 2;
  1206. uinfo->value.integer.min = 0;
  1207. uinfo->value.integer.max = mask;
  1208. return 0;
  1209. }
  1210. static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
  1211. struct snd_ctl_elem_value *ucontrol)
  1212. {
  1213. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1214. unsigned long flags;
  1215. int left_reg = kcontrol->private_value & 0xff;
  1216. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1217. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1218. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1219. int mask = (kcontrol->private_value >> 24) & 0xff;
  1220. int invert = (kcontrol->private_value >> 22) & 1;
  1221. spin_lock_irqsave(&chip->lock, flags);
  1222. ucontrol->value.integer.value[0] =
  1223. (chip->image[left_reg] >> shift_left) & mask;
  1224. ucontrol->value.integer.value[1] =
  1225. (chip->image[right_reg] >> shift_right) & mask;
  1226. spin_unlock_irqrestore(&chip->lock, flags);
  1227. if (invert) {
  1228. ucontrol->value.integer.value[0] =
  1229. (mask - ucontrol->value.integer.value[0]);
  1230. ucontrol->value.integer.value[1] =
  1231. (mask - ucontrol->value.integer.value[1]);
  1232. }
  1233. return 0;
  1234. }
  1235. static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
  1236. struct snd_ctl_elem_value *ucontrol)
  1237. {
  1238. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1239. unsigned long flags;
  1240. int left_reg = kcontrol->private_value & 0xff;
  1241. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1242. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1243. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1244. int mask = (kcontrol->private_value >> 24) & 0xff;
  1245. int invert = (kcontrol->private_value >> 22) & 1;
  1246. int change;
  1247. unsigned short val1, val2;
  1248. val1 = ucontrol->value.integer.value[0] & mask;
  1249. val2 = ucontrol->value.integer.value[1] & mask;
  1250. if (invert) {
  1251. val1 = mask - val1;
  1252. val2 = mask - val2;
  1253. }
  1254. val1 <<= shift_left;
  1255. val2 <<= shift_right;
  1256. spin_lock_irqsave(&chip->lock, flags);
  1257. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1258. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1259. change = val1 != chip->image[left_reg];
  1260. change |= val2 != chip->image[right_reg];
  1261. snd_cs4231_out(chip, left_reg, val1);
  1262. snd_cs4231_out(chip, right_reg, val2);
  1263. spin_unlock_irqrestore(&chip->lock, flags);
  1264. return change;
  1265. }
  1266. #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
  1267. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1268. .info = snd_cs4231_info_single, \
  1269. .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
  1270. .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
  1271. #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
  1272. shift_right, mask, invert) \
  1273. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1274. .info = snd_cs4231_info_double, \
  1275. .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
  1276. .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
  1277. ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
  1278. static struct snd_kcontrol_new snd_cs4231_controls[] __initdata = {
  1279. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
  1280. CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1281. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
  1282. CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1283. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
  1284. CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1285. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
  1286. CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1287. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
  1288. CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1289. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
  1290. CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1291. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
  1292. CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1293. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
  1294. CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1295. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1296. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1297. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1298. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1299. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
  1300. 15, 0),
  1301. {
  1302. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1303. .name = "Capture Source",
  1304. .info = snd_cs4231_info_mux,
  1305. .get = snd_cs4231_get_mux,
  1306. .put = snd_cs4231_put_mux,
  1307. },
  1308. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
  1309. 1, 0),
  1310. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1311. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
  1312. /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
  1313. CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
  1314. CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
  1315. };
  1316. static int __init snd_cs4231_mixer(struct snd_card *card)
  1317. {
  1318. struct snd_cs4231 *chip = card->private_data;
  1319. int err, idx;
  1320. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1321. strcpy(card->mixername, chip->pcm->name);
  1322. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1323. err = snd_ctl_add(card,
  1324. snd_ctl_new1(&snd_cs4231_controls[idx], chip));
  1325. if (err < 0)
  1326. return err;
  1327. }
  1328. return 0;
  1329. }
  1330. static int dev;
  1331. static int __init cs4231_attach_begin(struct snd_card **rcard)
  1332. {
  1333. struct snd_card *card;
  1334. struct snd_cs4231 *chip;
  1335. *rcard = NULL;
  1336. if (dev >= SNDRV_CARDS)
  1337. return -ENODEV;
  1338. if (!enable[dev]) {
  1339. dev++;
  1340. return -ENOENT;
  1341. }
  1342. card = snd_card_new(index[dev], id[dev], THIS_MODULE,
  1343. sizeof(struct snd_cs4231));
  1344. if (card == NULL)
  1345. return -ENOMEM;
  1346. strcpy(card->driver, "CS4231");
  1347. strcpy(card->shortname, "Sun CS4231");
  1348. chip = card->private_data;
  1349. chip->card = card;
  1350. *rcard = card;
  1351. return 0;
  1352. }
  1353. static int __init cs4231_attach_finish(struct snd_card *card)
  1354. {
  1355. struct snd_cs4231 *chip = card->private_data;
  1356. int err;
  1357. err = snd_cs4231_pcm(card);
  1358. if (err < 0)
  1359. goto out_err;
  1360. err = snd_cs4231_mixer(card);
  1361. if (err < 0)
  1362. goto out_err;
  1363. err = snd_cs4231_timer(card);
  1364. if (err < 0)
  1365. goto out_err;
  1366. err = snd_card_register(card);
  1367. if (err < 0)
  1368. goto out_err;
  1369. chip->next = cs4231_list;
  1370. cs4231_list = chip;
  1371. dev++;
  1372. return 0;
  1373. out_err:
  1374. snd_card_free(card);
  1375. return err;
  1376. }
  1377. #ifdef SBUS_SUPPORT
  1378. static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
  1379. {
  1380. unsigned long flags;
  1381. unsigned char status;
  1382. u32 csr;
  1383. struct snd_cs4231 *chip = dev_id;
  1384. /*This is IRQ is not raised by the cs4231*/
  1385. if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
  1386. return IRQ_NONE;
  1387. /* ACK the APC interrupt. */
  1388. csr = sbus_readl(chip->port + APCCSR);
  1389. sbus_writel(csr, chip->port + APCCSR);
  1390. if ((csr & APC_PDMA_READY) &&
  1391. (csr & APC_PLAY_INT) &&
  1392. (csr & APC_XINT_PNVA) &&
  1393. !(csr & APC_XINT_EMPT))
  1394. snd_cs4231_play_callback(chip);
  1395. if ((csr & APC_CDMA_READY) &&
  1396. (csr & APC_CAPT_INT) &&
  1397. (csr & APC_XINT_CNVA) &&
  1398. !(csr & APC_XINT_EMPT))
  1399. snd_cs4231_capture_callback(chip);
  1400. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  1401. if (status & CS4231_TIMER_IRQ) {
  1402. if (chip->timer)
  1403. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1404. }
  1405. if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
  1406. snd_cs4231_overrange(chip);
  1407. /* ACK the CS4231 interrupt. */
  1408. spin_lock_irqsave(&chip->lock, flags);
  1409. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  1410. spin_unlock_irqrestore(&chip->lock, flags);
  1411. return IRQ_HANDLED;
  1412. }
  1413. /*
  1414. * SBUS DMA routines
  1415. */
  1416. static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
  1417. dma_addr_t bus_addr, size_t len)
  1418. {
  1419. unsigned long flags;
  1420. u32 test, csr;
  1421. int err;
  1422. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1423. if (len >= (1 << 24))
  1424. return -EINVAL;
  1425. spin_lock_irqsave(&base->lock, flags);
  1426. csr = sbus_readl(base->regs + APCCSR);
  1427. err = -EINVAL;
  1428. test = APC_CDMA_READY;
  1429. if (base->dir == APC_PLAY)
  1430. test = APC_PDMA_READY;
  1431. if (!(csr & test))
  1432. goto out;
  1433. err = -EBUSY;
  1434. test = APC_XINT_CNVA;
  1435. if (base->dir == APC_PLAY)
  1436. test = APC_XINT_PNVA;
  1437. if (!(csr & test))
  1438. goto out;
  1439. err = 0;
  1440. sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
  1441. sbus_writel(len, base->regs + base->dir + APCNC);
  1442. out:
  1443. spin_unlock_irqrestore(&base->lock, flags);
  1444. return err;
  1445. }
  1446. static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
  1447. {
  1448. unsigned long flags;
  1449. u32 csr, test;
  1450. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1451. spin_lock_irqsave(&base->lock, flags);
  1452. csr = sbus_readl(base->regs + APCCSR);
  1453. test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
  1454. APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
  1455. APC_XINT_PENA;
  1456. if (base->dir == APC_RECORD)
  1457. test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
  1458. APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
  1459. csr |= test;
  1460. sbus_writel(csr, base->regs + APCCSR);
  1461. spin_unlock_irqrestore(&base->lock, flags);
  1462. }
  1463. static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1464. {
  1465. unsigned long flags;
  1466. u32 csr, shift;
  1467. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1468. spin_lock_irqsave(&base->lock, flags);
  1469. if (!on) {
  1470. sbus_writel(0, base->regs + base->dir + APCNC);
  1471. sbus_writel(0, base->regs + base->dir + APCNVA);
  1472. if (base->dir == APC_PLAY) {
  1473. sbus_writel(0, base->regs + base->dir + APCC);
  1474. sbus_writel(0, base->regs + base->dir + APCVA);
  1475. }
  1476. udelay(1200);
  1477. }
  1478. csr = sbus_readl(base->regs + APCCSR);
  1479. shift = 0;
  1480. if (base->dir == APC_PLAY)
  1481. shift = 1;
  1482. if (on)
  1483. csr &= ~(APC_CPAUSE << shift);
  1484. else
  1485. csr |= (APC_CPAUSE << shift);
  1486. sbus_writel(csr, base->regs + APCCSR);
  1487. if (on)
  1488. csr |= (APC_CDMA_READY << shift);
  1489. else
  1490. csr &= ~(APC_CDMA_READY << shift);
  1491. sbus_writel(csr, base->regs + APCCSR);
  1492. spin_unlock_irqrestore(&base->lock, flags);
  1493. }
  1494. static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
  1495. {
  1496. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1497. return sbus_readl(base->regs + base->dir + APCVA);
  1498. }
  1499. static void sbus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
  1500. {
  1501. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
  1502. snd_dma_sbus_data(chip->dev_u.sdev),
  1503. 64 * 1024, 128 * 1024);
  1504. }
  1505. /*
  1506. * Init and exit routines
  1507. */
  1508. static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
  1509. {
  1510. if (chip->irq[0])
  1511. free_irq(chip->irq[0], chip);
  1512. if (chip->port)
  1513. sbus_iounmap(chip->port, chip->regs_size);
  1514. return 0;
  1515. }
  1516. static int snd_cs4231_sbus_dev_free(struct snd_device *device)
  1517. {
  1518. struct snd_cs4231 *cp = device->device_data;
  1519. return snd_cs4231_sbus_free(cp);
  1520. }
  1521. static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
  1522. .dev_free = snd_cs4231_sbus_dev_free,
  1523. };
  1524. static int __init snd_cs4231_sbus_create(struct snd_card *card,
  1525. struct sbus_dev *sdev,
  1526. int dev)
  1527. {
  1528. struct snd_cs4231 *chip = card->private_data;
  1529. int err;
  1530. spin_lock_init(&chip->lock);
  1531. spin_lock_init(&chip->c_dma.sbus_info.lock);
  1532. spin_lock_init(&chip->p_dma.sbus_info.lock);
  1533. mutex_init(&chip->mce_mutex);
  1534. mutex_init(&chip->open_mutex);
  1535. chip->dev_u.sdev = sdev;
  1536. chip->regs_size = sdev->reg_addrs[0].reg_size;
  1537. memcpy(&chip->image, &snd_cs4231_original_image,
  1538. sizeof(snd_cs4231_original_image));
  1539. chip->port = sbus_ioremap(&sdev->resource[0], 0,
  1540. chip->regs_size, "cs4231");
  1541. if (!chip->port) {
  1542. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1543. return -EIO;
  1544. }
  1545. chip->c_dma.sbus_info.regs = chip->port;
  1546. chip->p_dma.sbus_info.regs = chip->port;
  1547. chip->c_dma.sbus_info.dir = APC_RECORD;
  1548. chip->p_dma.sbus_info.dir = APC_PLAY;
  1549. chip->p_dma.prepare = sbus_dma_prepare;
  1550. chip->p_dma.enable = sbus_dma_enable;
  1551. chip->p_dma.request = sbus_dma_request;
  1552. chip->p_dma.address = sbus_dma_addr;
  1553. chip->p_dma.preallocate = sbus_dma_preallocate;
  1554. chip->c_dma.prepare = sbus_dma_prepare;
  1555. chip->c_dma.enable = sbus_dma_enable;
  1556. chip->c_dma.request = sbus_dma_request;
  1557. chip->c_dma.address = sbus_dma_addr;
  1558. chip->c_dma.preallocate = sbus_dma_preallocate;
  1559. if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
  1560. IRQF_SHARED, "cs4231", chip)) {
  1561. snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
  1562. dev, sdev->irqs[0]);
  1563. snd_cs4231_sbus_free(chip);
  1564. return -EBUSY;
  1565. }
  1566. chip->irq[0] = sdev->irqs[0];
  1567. if (snd_cs4231_probe(chip) < 0) {
  1568. snd_cs4231_sbus_free(chip);
  1569. return -ENODEV;
  1570. }
  1571. snd_cs4231_init(chip);
  1572. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1573. chip, &snd_cs4231_sbus_dev_ops)) < 0) {
  1574. snd_cs4231_sbus_free(chip);
  1575. return err;
  1576. }
  1577. return 0;
  1578. }
  1579. static int __init cs4231_sbus_attach(struct sbus_dev *sdev)
  1580. {
  1581. struct resource *rp = &sdev->resource[0];
  1582. struct snd_card *card;
  1583. int err;
  1584. err = cs4231_attach_begin(&card);
  1585. if (err)
  1586. return err;
  1587. sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
  1588. card->shortname,
  1589. rp->flags & 0xffL,
  1590. (unsigned long long)rp->start,
  1591. sdev->irqs[0]);
  1592. err = snd_cs4231_sbus_create(card, sdev, dev);
  1593. if (err < 0) {
  1594. snd_card_free(card);
  1595. return err;
  1596. }
  1597. return cs4231_attach_finish(card);
  1598. }
  1599. #endif
  1600. #ifdef EBUS_SUPPORT
  1601. static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
  1602. void *cookie)
  1603. {
  1604. struct snd_cs4231 *chip = cookie;
  1605. snd_cs4231_play_callback(chip);
  1606. }
  1607. static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
  1608. int event, void *cookie)
  1609. {
  1610. struct snd_cs4231 *chip = cookie;
  1611. snd_cs4231_capture_callback(chip);
  1612. }
  1613. /*
  1614. * EBUS DMA wrappers
  1615. */
  1616. static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
  1617. dma_addr_t bus_addr, size_t len)
  1618. {
  1619. return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
  1620. }
  1621. static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1622. {
  1623. ebus_dma_enable(&dma_cont->ebus_info, on);
  1624. }
  1625. static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
  1626. {
  1627. ebus_dma_prepare(&dma_cont->ebus_info, dir);
  1628. }
  1629. static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
  1630. {
  1631. return ebus_dma_addr(&dma_cont->ebus_info);
  1632. }
  1633. static void _ebus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
  1634. {
  1635. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1636. snd_dma_pci_data(chip->dev_u.pdev),
  1637. 64*1024, 128*1024);
  1638. }
  1639. /*
  1640. * Init and exit routines
  1641. */
  1642. static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
  1643. {
  1644. if (chip->c_dma.ebus_info.regs) {
  1645. ebus_dma_unregister(&chip->c_dma.ebus_info);
  1646. iounmap(chip->c_dma.ebus_info.regs);
  1647. }
  1648. if (chip->p_dma.ebus_info.regs) {
  1649. ebus_dma_unregister(&chip->p_dma.ebus_info);
  1650. iounmap(chip->p_dma.ebus_info.regs);
  1651. }
  1652. if (chip->port)
  1653. iounmap(chip->port);
  1654. return 0;
  1655. }
  1656. static int snd_cs4231_ebus_dev_free(struct snd_device *device)
  1657. {
  1658. struct snd_cs4231 *cp = device->device_data;
  1659. return snd_cs4231_ebus_free(cp);
  1660. }
  1661. static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
  1662. .dev_free = snd_cs4231_ebus_dev_free,
  1663. };
  1664. static int __init snd_cs4231_ebus_create(struct snd_card *card,
  1665. struct linux_ebus_device *edev,
  1666. int dev)
  1667. {
  1668. struct snd_cs4231 *chip = card->private_data;
  1669. int err;
  1670. spin_lock_init(&chip->lock);
  1671. spin_lock_init(&chip->c_dma.ebus_info.lock);
  1672. spin_lock_init(&chip->p_dma.ebus_info.lock);
  1673. mutex_init(&chip->mce_mutex);
  1674. mutex_init(&chip->open_mutex);
  1675. chip->flags |= CS4231_FLAG_EBUS;
  1676. chip->dev_u.pdev = edev->bus->self;
  1677. memcpy(&chip->image, &snd_cs4231_original_image,
  1678. sizeof(snd_cs4231_original_image));
  1679. strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
  1680. chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1681. chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
  1682. chip->c_dma.ebus_info.client_cookie = chip;
  1683. chip->c_dma.ebus_info.irq = edev->irqs[0];
  1684. strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
  1685. chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1686. chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
  1687. chip->p_dma.ebus_info.client_cookie = chip;
  1688. chip->p_dma.ebus_info.irq = edev->irqs[1];
  1689. chip->p_dma.prepare = _ebus_dma_prepare;
  1690. chip->p_dma.enable = _ebus_dma_enable;
  1691. chip->p_dma.request = _ebus_dma_request;
  1692. chip->p_dma.address = _ebus_dma_addr;
  1693. chip->p_dma.preallocate = _ebus_dma_preallocate;
  1694. chip->c_dma.prepare = _ebus_dma_prepare;
  1695. chip->c_dma.enable = _ebus_dma_enable;
  1696. chip->c_dma.request = _ebus_dma_request;
  1697. chip->c_dma.address = _ebus_dma_addr;
  1698. chip->c_dma.preallocate = _ebus_dma_preallocate;
  1699. chip->port = ioremap(edev->resource[0].start, 0x10);
  1700. chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10);
  1701. chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10);
  1702. if (!chip->port || !chip->p_dma.ebus_info.regs ||
  1703. !chip->c_dma.ebus_info.regs) {
  1704. snd_cs4231_ebus_free(chip);
  1705. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1706. return -EIO;
  1707. }
  1708. if (ebus_dma_register(&chip->c_dma.ebus_info)) {
  1709. snd_cs4231_ebus_free(chip);
  1710. snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
  1711. dev);
  1712. return -EBUSY;
  1713. }
  1714. if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
  1715. snd_cs4231_ebus_free(chip);
  1716. snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
  1717. dev);
  1718. return -EBUSY;
  1719. }
  1720. if (ebus_dma_register(&chip->p_dma.ebus_info)) {
  1721. snd_cs4231_ebus_free(chip);
  1722. snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
  1723. dev);
  1724. return -EBUSY;
  1725. }
  1726. if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
  1727. snd_cs4231_ebus_free(chip);
  1728. snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
  1729. return -EBUSY;
  1730. }
  1731. if (snd_cs4231_probe(chip) < 0) {
  1732. snd_cs4231_ebus_free(chip);
  1733. return -ENODEV;
  1734. }
  1735. snd_cs4231_init(chip);
  1736. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1737. chip, &snd_cs4231_ebus_dev_ops)) < 0) {
  1738. snd_cs4231_ebus_free(chip);
  1739. return err;
  1740. }
  1741. return 0;
  1742. }
  1743. static int __init cs4231_ebus_attach(struct linux_ebus_device *edev)
  1744. {
  1745. struct snd_card *card;
  1746. int err;
  1747. err = cs4231_attach_begin(&card);
  1748. if (err)
  1749. return err;
  1750. sprintf(card->longname, "%s at 0x%lx, irq %d",
  1751. card->shortname,
  1752. edev->resource[0].start,
  1753. edev->irqs[0]);
  1754. err = snd_cs4231_ebus_create(card, edev, dev);
  1755. if (err < 0) {
  1756. snd_card_free(card);
  1757. return err;
  1758. }
  1759. return cs4231_attach_finish(card);
  1760. }
  1761. #endif
  1762. static int __init cs4231_init(void)
  1763. {
  1764. #ifdef SBUS_SUPPORT
  1765. struct sbus_bus *sbus;
  1766. struct sbus_dev *sdev;
  1767. #endif
  1768. #ifdef EBUS_SUPPORT
  1769. struct linux_ebus *ebus;
  1770. struct linux_ebus_device *edev;
  1771. #endif
  1772. int found;
  1773. found = 0;
  1774. #ifdef SBUS_SUPPORT
  1775. for_all_sbusdev(sdev, sbus) {
  1776. if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
  1777. if (cs4231_sbus_attach(sdev) == 0)
  1778. found++;
  1779. }
  1780. }
  1781. #endif
  1782. #ifdef EBUS_SUPPORT
  1783. for_each_ebus(ebus) {
  1784. for_each_ebusdev(edev, ebus) {
  1785. int match = 0;
  1786. if (!strcmp(edev->prom_node->name, "SUNW,CS4231")) {
  1787. match = 1;
  1788. } else if (!strcmp(edev->prom_node->name, "audio")) {
  1789. const char *compat;
  1790. compat = of_get_property(edev->prom_node,
  1791. "compatible", NULL);
  1792. if (compat && !strcmp(compat, "SUNW,CS4231"))
  1793. match = 1;
  1794. }
  1795. if (match &&
  1796. cs4231_ebus_attach(edev) == 0)
  1797. found++;
  1798. }
  1799. }
  1800. #endif
  1801. return (found > 0) ? 0 : -EIO;
  1802. }
  1803. static void __exit cs4231_exit(void)
  1804. {
  1805. struct snd_cs4231 *p = cs4231_list;
  1806. while (p != NULL) {
  1807. struct snd_cs4231 *next = p->next;
  1808. snd_card_free(p->card);
  1809. p = next;
  1810. }
  1811. cs4231_list = NULL;
  1812. }
  1813. module_init(cs4231_init);
  1814. module_exit(cs4231_exit);