oxygen_pcm.c 20 KB

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  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "oxygen.h"
  25. static const struct snd_pcm_hardware oxygen_stereo_hardware = {
  26. .info = SNDRV_PCM_INFO_MMAP |
  27. SNDRV_PCM_INFO_MMAP_VALID |
  28. SNDRV_PCM_INFO_INTERLEAVED |
  29. SNDRV_PCM_INFO_PAUSE |
  30. SNDRV_PCM_INFO_SYNC_START,
  31. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  32. SNDRV_PCM_FMTBIT_S32_LE,
  33. .rates = SNDRV_PCM_RATE_32000 |
  34. SNDRV_PCM_RATE_44100 |
  35. SNDRV_PCM_RATE_48000 |
  36. SNDRV_PCM_RATE_64000 |
  37. SNDRV_PCM_RATE_88200 |
  38. SNDRV_PCM_RATE_96000 |
  39. SNDRV_PCM_RATE_176400 |
  40. SNDRV_PCM_RATE_192000,
  41. .rate_min = 32000,
  42. .rate_max = 192000,
  43. .channels_min = 2,
  44. .channels_max = 2,
  45. .buffer_bytes_max = 256 * 1024,
  46. .period_bytes_min = 128,
  47. .period_bytes_max = 128 * 1024,
  48. .periods_min = 2,
  49. .periods_max = 2048,
  50. };
  51. static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
  52. .info = SNDRV_PCM_INFO_MMAP |
  53. SNDRV_PCM_INFO_MMAP_VALID |
  54. SNDRV_PCM_INFO_INTERLEAVED |
  55. SNDRV_PCM_INFO_PAUSE |
  56. SNDRV_PCM_INFO_SYNC_START,
  57. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  58. SNDRV_PCM_FMTBIT_S32_LE,
  59. .rates = SNDRV_PCM_RATE_32000 |
  60. SNDRV_PCM_RATE_44100 |
  61. SNDRV_PCM_RATE_48000 |
  62. SNDRV_PCM_RATE_64000 |
  63. SNDRV_PCM_RATE_88200 |
  64. SNDRV_PCM_RATE_96000 |
  65. SNDRV_PCM_RATE_176400 |
  66. SNDRV_PCM_RATE_192000,
  67. .rate_min = 32000,
  68. .rate_max = 192000,
  69. .channels_min = 2,
  70. .channels_max = 8,
  71. .buffer_bytes_max = 2048 * 1024,
  72. .period_bytes_min = 128,
  73. .period_bytes_max = 256 * 1024,
  74. .periods_min = 2,
  75. .periods_max = 16384,
  76. };
  77. static const struct snd_pcm_hardware oxygen_ac97_hardware = {
  78. .info = SNDRV_PCM_INFO_MMAP |
  79. SNDRV_PCM_INFO_MMAP_VALID |
  80. SNDRV_PCM_INFO_INTERLEAVED |
  81. SNDRV_PCM_INFO_PAUSE |
  82. SNDRV_PCM_INFO_SYNC_START,
  83. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  84. .rates = SNDRV_PCM_RATE_48000,
  85. .rate_min = 48000,
  86. .rate_max = 48000,
  87. .channels_min = 2,
  88. .channels_max = 2,
  89. .buffer_bytes_max = 256 * 1024,
  90. .period_bytes_min = 128,
  91. .period_bytes_max = 128 * 1024,
  92. .periods_min = 2,
  93. .periods_max = 2048,
  94. };
  95. static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
  96. [PCM_A] = &oxygen_stereo_hardware,
  97. [PCM_B] = &oxygen_stereo_hardware,
  98. [PCM_C] = &oxygen_stereo_hardware,
  99. [PCM_SPDIF] = &oxygen_stereo_hardware,
  100. [PCM_MULTICH] = &oxygen_multichannel_hardware,
  101. [PCM_AC97] = &oxygen_ac97_hardware,
  102. };
  103. static inline unsigned int
  104. oxygen_substream_channel(struct snd_pcm_substream *substream)
  105. {
  106. return (unsigned int)(uintptr_t)substream->runtime->private_data;
  107. }
  108. static int oxygen_open(struct snd_pcm_substream *substream,
  109. unsigned int channel)
  110. {
  111. struct oxygen *chip = snd_pcm_substream_chip(substream);
  112. struct snd_pcm_runtime *runtime = substream->runtime;
  113. int err;
  114. runtime->private_data = (void *)(uintptr_t)channel;
  115. if (channel == PCM_B && chip->has_ac97_1 &&
  116. (chip->model->pcm_dev_cfg & CAPTURE_2_FROM_AC97_1))
  117. runtime->hw = oxygen_ac97_hardware;
  118. else
  119. runtime->hw = *oxygen_hardware[channel];
  120. switch (channel) {
  121. case PCM_C:
  122. runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
  123. SNDRV_PCM_RATE_64000);
  124. runtime->hw.rate_min = 44100;
  125. break;
  126. case PCM_MULTICH:
  127. runtime->hw.channels_max = chip->model->dac_channels;
  128. break;
  129. }
  130. if (chip->model->pcm_hardware_filter)
  131. chip->model->pcm_hardware_filter(channel, &runtime->hw);
  132. err = snd_pcm_hw_constraint_step(runtime, 0,
  133. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  134. if (err < 0)
  135. return err;
  136. err = snd_pcm_hw_constraint_step(runtime, 0,
  137. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  138. if (err < 0)
  139. return err;
  140. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  141. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  142. if (err < 0)
  143. return err;
  144. }
  145. if (runtime->hw.channels_max > 2) {
  146. err = snd_pcm_hw_constraint_step(runtime, 0,
  147. SNDRV_PCM_HW_PARAM_CHANNELS,
  148. 2);
  149. if (err < 0)
  150. return err;
  151. }
  152. snd_pcm_set_sync(substream);
  153. chip->streams[channel] = substream;
  154. mutex_lock(&chip->mutex);
  155. chip->pcm_active |= 1 << channel;
  156. if (channel == PCM_SPDIF) {
  157. chip->spdif_pcm_bits = chip->spdif_bits;
  158. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
  159. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  160. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  161. SNDRV_CTL_EVENT_MASK_INFO,
  162. &chip->controls[CONTROL_SPDIF_PCM]->id);
  163. }
  164. mutex_unlock(&chip->mutex);
  165. return 0;
  166. }
  167. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  168. {
  169. return oxygen_open(substream, PCM_A);
  170. }
  171. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  172. {
  173. return oxygen_open(substream, PCM_B);
  174. }
  175. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  176. {
  177. return oxygen_open(substream, PCM_C);
  178. }
  179. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  180. {
  181. return oxygen_open(substream, PCM_SPDIF);
  182. }
  183. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  184. {
  185. return oxygen_open(substream, PCM_MULTICH);
  186. }
  187. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  188. {
  189. return oxygen_open(substream, PCM_AC97);
  190. }
  191. static int oxygen_close(struct snd_pcm_substream *substream)
  192. {
  193. struct oxygen *chip = snd_pcm_substream_chip(substream);
  194. unsigned int channel = oxygen_substream_channel(substream);
  195. mutex_lock(&chip->mutex);
  196. chip->pcm_active &= ~(1 << channel);
  197. if (channel == PCM_SPDIF) {
  198. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
  199. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  200. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  201. SNDRV_CTL_EVENT_MASK_INFO,
  202. &chip->controls[CONTROL_SPDIF_PCM]->id);
  203. }
  204. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  205. oxygen_update_spdif_source(chip);
  206. mutex_unlock(&chip->mutex);
  207. chip->streams[channel] = NULL;
  208. return 0;
  209. }
  210. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  211. {
  212. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  213. return OXYGEN_FORMAT_24;
  214. else
  215. return OXYGEN_FORMAT_16;
  216. }
  217. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  218. {
  219. switch (params_rate(hw_params)) {
  220. case 32000:
  221. return OXYGEN_RATE_32000;
  222. case 44100:
  223. return OXYGEN_RATE_44100;
  224. default: /* 48000 */
  225. return OXYGEN_RATE_48000;
  226. case 64000:
  227. return OXYGEN_RATE_64000;
  228. case 88200:
  229. return OXYGEN_RATE_88200;
  230. case 96000:
  231. return OXYGEN_RATE_96000;
  232. case 176400:
  233. return OXYGEN_RATE_176400;
  234. case 192000:
  235. return OXYGEN_RATE_192000;
  236. }
  237. }
  238. static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
  239. {
  240. if (params_rate(hw_params) <= 96000)
  241. return OXYGEN_I2S_MCLK_256;
  242. else
  243. return OXYGEN_I2S_MCLK_128;
  244. }
  245. static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
  246. {
  247. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  248. return OXYGEN_I2S_BITS_24;
  249. else
  250. return OXYGEN_I2S_BITS_16;
  251. }
  252. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  253. {
  254. switch (params_channels(hw_params)) {
  255. default: /* 2 */
  256. return OXYGEN_PLAY_CHANNELS_2;
  257. case 4:
  258. return OXYGEN_PLAY_CHANNELS_4;
  259. case 6:
  260. return OXYGEN_PLAY_CHANNELS_6;
  261. case 8:
  262. return OXYGEN_PLAY_CHANNELS_8;
  263. }
  264. }
  265. static const unsigned int channel_base_registers[PCM_COUNT] = {
  266. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  267. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  268. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  269. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  270. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  271. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  272. };
  273. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  274. struct snd_pcm_hw_params *hw_params)
  275. {
  276. struct oxygen *chip = snd_pcm_substream_chip(substream);
  277. unsigned int channel = oxygen_substream_channel(substream);
  278. int err;
  279. err = snd_pcm_lib_malloc_pages(substream,
  280. params_buffer_bytes(hw_params));
  281. if (err < 0)
  282. return err;
  283. oxygen_write32(chip, channel_base_registers[channel],
  284. (u32)substream->runtime->dma_addr);
  285. if (channel == PCM_MULTICH) {
  286. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  287. params_buffer_bytes(hw_params) / 4 - 1);
  288. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  289. params_period_bytes(hw_params) / 4 - 1);
  290. } else {
  291. oxygen_write16(chip, channel_base_registers[channel] + 4,
  292. params_buffer_bytes(hw_params) / 4 - 1);
  293. oxygen_write16(chip, channel_base_registers[channel] + 6,
  294. params_period_bytes(hw_params) / 4 - 1);
  295. }
  296. return 0;
  297. }
  298. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  299. struct snd_pcm_hw_params *hw_params)
  300. {
  301. struct oxygen *chip = snd_pcm_substream_chip(substream);
  302. int err;
  303. err = oxygen_hw_params(substream, hw_params);
  304. if (err < 0)
  305. return err;
  306. spin_lock_irq(&chip->reg_lock);
  307. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  308. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  309. OXYGEN_REC_FORMAT_A_MASK);
  310. oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
  311. oxygen_rate(hw_params) |
  312. oxygen_i2s_mclk(hw_params) |
  313. chip->model->adc_i2s_format |
  314. oxygen_i2s_bits(hw_params),
  315. OXYGEN_I2S_RATE_MASK |
  316. OXYGEN_I2S_FORMAT_MASK |
  317. OXYGEN_I2S_MCLK_MASK |
  318. OXYGEN_I2S_BITS_MASK);
  319. spin_unlock_irq(&chip->reg_lock);
  320. mutex_lock(&chip->mutex);
  321. chip->model->set_adc_params(chip, hw_params);
  322. mutex_unlock(&chip->mutex);
  323. return 0;
  324. }
  325. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  326. struct snd_pcm_hw_params *hw_params)
  327. {
  328. struct oxygen *chip = snd_pcm_substream_chip(substream);
  329. int is_ac97;
  330. int err;
  331. err = oxygen_hw_params(substream, hw_params);
  332. if (err < 0)
  333. return err;
  334. is_ac97 = chip->has_ac97_1 &&
  335. (chip->model->pcm_dev_cfg & CAPTURE_2_FROM_AC97_1);
  336. spin_lock_irq(&chip->reg_lock);
  337. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  338. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  339. OXYGEN_REC_FORMAT_B_MASK);
  340. if (!is_ac97)
  341. oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
  342. oxygen_rate(hw_params) |
  343. oxygen_i2s_mclk(hw_params) |
  344. chip->model->adc_i2s_format |
  345. oxygen_i2s_bits(hw_params),
  346. OXYGEN_I2S_RATE_MASK |
  347. OXYGEN_I2S_FORMAT_MASK |
  348. OXYGEN_I2S_MCLK_MASK |
  349. OXYGEN_I2S_BITS_MASK);
  350. spin_unlock_irq(&chip->reg_lock);
  351. if (!is_ac97) {
  352. mutex_lock(&chip->mutex);
  353. chip->model->set_adc_params(chip, hw_params);
  354. mutex_unlock(&chip->mutex);
  355. }
  356. return 0;
  357. }
  358. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  359. struct snd_pcm_hw_params *hw_params)
  360. {
  361. struct oxygen *chip = snd_pcm_substream_chip(substream);
  362. int err;
  363. err = oxygen_hw_params(substream, hw_params);
  364. if (err < 0)
  365. return err;
  366. spin_lock_irq(&chip->reg_lock);
  367. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  368. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  369. OXYGEN_REC_FORMAT_C_MASK);
  370. spin_unlock_irq(&chip->reg_lock);
  371. return 0;
  372. }
  373. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  374. struct snd_pcm_hw_params *hw_params)
  375. {
  376. struct oxygen *chip = snd_pcm_substream_chip(substream);
  377. int err;
  378. err = oxygen_hw_params(substream, hw_params);
  379. if (err < 0)
  380. return err;
  381. spin_lock_irq(&chip->reg_lock);
  382. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  383. OXYGEN_SPDIF_OUT_ENABLE);
  384. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  385. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  386. OXYGEN_SPDIF_FORMAT_MASK);
  387. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  388. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  389. OXYGEN_SPDIF_OUT_RATE_MASK);
  390. oxygen_update_spdif_source(chip);
  391. spin_unlock_irq(&chip->reg_lock);
  392. return 0;
  393. }
  394. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  395. struct snd_pcm_hw_params *hw_params)
  396. {
  397. struct oxygen *chip = snd_pcm_substream_chip(substream);
  398. int err;
  399. err = oxygen_hw_params(substream, hw_params);
  400. if (err < 0)
  401. return err;
  402. spin_lock_irq(&chip->reg_lock);
  403. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  404. oxygen_play_channels(hw_params),
  405. OXYGEN_PLAY_CHANNELS_MASK);
  406. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  407. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  408. OXYGEN_MULTICH_FORMAT_MASK);
  409. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  410. oxygen_rate(hw_params) |
  411. chip->model->dac_i2s_format |
  412. oxygen_i2s_bits(hw_params),
  413. OXYGEN_I2S_RATE_MASK |
  414. OXYGEN_I2S_FORMAT_MASK |
  415. OXYGEN_I2S_BITS_MASK);
  416. oxygen_update_dac_routing(chip);
  417. oxygen_update_spdif_source(chip);
  418. spin_unlock_irq(&chip->reg_lock);
  419. mutex_lock(&chip->mutex);
  420. chip->model->set_dac_params(chip, hw_params);
  421. mutex_unlock(&chip->mutex);
  422. return 0;
  423. }
  424. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  425. {
  426. struct oxygen *chip = snd_pcm_substream_chip(substream);
  427. unsigned int channel = oxygen_substream_channel(substream);
  428. spin_lock_irq(&chip->reg_lock);
  429. chip->interrupt_mask &= ~(1 << channel);
  430. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  431. spin_unlock_irq(&chip->reg_lock);
  432. return snd_pcm_lib_free_pages(substream);
  433. }
  434. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  435. {
  436. struct oxygen *chip = snd_pcm_substream_chip(substream);
  437. spin_lock_irq(&chip->reg_lock);
  438. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  439. OXYGEN_SPDIF_OUT_ENABLE);
  440. spin_unlock_irq(&chip->reg_lock);
  441. return oxygen_hw_free(substream);
  442. }
  443. static int oxygen_prepare(struct snd_pcm_substream *substream)
  444. {
  445. struct oxygen *chip = snd_pcm_substream_chip(substream);
  446. unsigned int channel = oxygen_substream_channel(substream);
  447. unsigned int channel_mask = 1 << channel;
  448. spin_lock_irq(&chip->reg_lock);
  449. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  450. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  451. chip->interrupt_mask |= channel_mask;
  452. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  453. spin_unlock_irq(&chip->reg_lock);
  454. return 0;
  455. }
  456. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  457. {
  458. struct oxygen *chip = snd_pcm_substream_chip(substream);
  459. struct snd_pcm_substream *s;
  460. unsigned int mask = 0;
  461. int pausing;
  462. switch (cmd) {
  463. case SNDRV_PCM_TRIGGER_STOP:
  464. case SNDRV_PCM_TRIGGER_START:
  465. pausing = 0;
  466. break;
  467. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  468. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  469. pausing = 1;
  470. break;
  471. default:
  472. return -EINVAL;
  473. }
  474. snd_pcm_group_for_each_entry(s, substream) {
  475. if (snd_pcm_substream_chip(s) == chip) {
  476. mask |= 1 << oxygen_substream_channel(s);
  477. snd_pcm_trigger_done(s, substream);
  478. }
  479. }
  480. spin_lock(&chip->reg_lock);
  481. if (!pausing) {
  482. if (cmd == SNDRV_PCM_TRIGGER_START)
  483. chip->pcm_running |= mask;
  484. else
  485. chip->pcm_running &= ~mask;
  486. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  487. } else {
  488. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  489. oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  490. else
  491. oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  492. }
  493. spin_unlock(&chip->reg_lock);
  494. return 0;
  495. }
  496. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  497. {
  498. struct oxygen *chip = snd_pcm_substream_chip(substream);
  499. struct snd_pcm_runtime *runtime = substream->runtime;
  500. unsigned int channel = oxygen_substream_channel(substream);
  501. u32 curr_addr;
  502. /* no spinlock, this read should be atomic */
  503. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  504. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  505. }
  506. static struct snd_pcm_ops oxygen_rec_a_ops = {
  507. .open = oxygen_rec_a_open,
  508. .close = oxygen_close,
  509. .ioctl = snd_pcm_lib_ioctl,
  510. .hw_params = oxygen_rec_a_hw_params,
  511. .hw_free = oxygen_hw_free,
  512. .prepare = oxygen_prepare,
  513. .trigger = oxygen_trigger,
  514. .pointer = oxygen_pointer,
  515. };
  516. static struct snd_pcm_ops oxygen_rec_b_ops = {
  517. .open = oxygen_rec_b_open,
  518. .close = oxygen_close,
  519. .ioctl = snd_pcm_lib_ioctl,
  520. .hw_params = oxygen_rec_b_hw_params,
  521. .hw_free = oxygen_hw_free,
  522. .prepare = oxygen_prepare,
  523. .trigger = oxygen_trigger,
  524. .pointer = oxygen_pointer,
  525. };
  526. static struct snd_pcm_ops oxygen_rec_c_ops = {
  527. .open = oxygen_rec_c_open,
  528. .close = oxygen_close,
  529. .ioctl = snd_pcm_lib_ioctl,
  530. .hw_params = oxygen_rec_c_hw_params,
  531. .hw_free = oxygen_hw_free,
  532. .prepare = oxygen_prepare,
  533. .trigger = oxygen_trigger,
  534. .pointer = oxygen_pointer,
  535. };
  536. static struct snd_pcm_ops oxygen_spdif_ops = {
  537. .open = oxygen_spdif_open,
  538. .close = oxygen_close,
  539. .ioctl = snd_pcm_lib_ioctl,
  540. .hw_params = oxygen_spdif_hw_params,
  541. .hw_free = oxygen_spdif_hw_free,
  542. .prepare = oxygen_prepare,
  543. .trigger = oxygen_trigger,
  544. .pointer = oxygen_pointer,
  545. };
  546. static struct snd_pcm_ops oxygen_multich_ops = {
  547. .open = oxygen_multich_open,
  548. .close = oxygen_close,
  549. .ioctl = snd_pcm_lib_ioctl,
  550. .hw_params = oxygen_multich_hw_params,
  551. .hw_free = oxygen_hw_free,
  552. .prepare = oxygen_prepare,
  553. .trigger = oxygen_trigger,
  554. .pointer = oxygen_pointer,
  555. };
  556. static struct snd_pcm_ops oxygen_ac97_ops = {
  557. .open = oxygen_ac97_open,
  558. .close = oxygen_close,
  559. .ioctl = snd_pcm_lib_ioctl,
  560. .hw_params = oxygen_hw_params,
  561. .hw_free = oxygen_hw_free,
  562. .prepare = oxygen_prepare,
  563. .trigger = oxygen_trigger,
  564. .pointer = oxygen_pointer,
  565. };
  566. static void oxygen_pcm_free(struct snd_pcm *pcm)
  567. {
  568. snd_pcm_lib_preallocate_free_for_all(pcm);
  569. }
  570. int oxygen_pcm_init(struct oxygen *chip)
  571. {
  572. struct snd_pcm *pcm;
  573. int outs, ins;
  574. int err;
  575. outs = !!(chip->model->pcm_dev_cfg & PLAYBACK_0_TO_I2S);
  576. ins = !!(chip->model->pcm_dev_cfg & (CAPTURE_0_FROM_I2S_1 |
  577. CAPTURE_0_FROM_I2S_2));
  578. if (outs | ins) {
  579. err = snd_pcm_new(chip->card, "Analog", 0, outs, ins, &pcm);
  580. if (err < 0)
  581. return err;
  582. if (outs)
  583. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  584. &oxygen_multich_ops);
  585. if (chip->model->pcm_dev_cfg & CAPTURE_0_FROM_I2S_1)
  586. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  587. &oxygen_rec_a_ops);
  588. else if (chip->model->pcm_dev_cfg & CAPTURE_0_FROM_I2S_2)
  589. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  590. &oxygen_rec_b_ops);
  591. pcm->private_data = chip;
  592. pcm->private_free = oxygen_pcm_free;
  593. strcpy(pcm->name, "Analog");
  594. if (outs)
  595. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  596. SNDRV_DMA_TYPE_DEV,
  597. snd_dma_pci_data(chip->pci),
  598. 512 * 1024, 2048 * 1024);
  599. if (ins)
  600. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  601. SNDRV_DMA_TYPE_DEV,
  602. snd_dma_pci_data(chip->pci),
  603. 128 * 1024, 256 * 1024);
  604. }
  605. outs = !!(chip->model->pcm_dev_cfg & PLAYBACK_1_TO_SPDIF);
  606. ins = !!(chip->model->pcm_dev_cfg & CAPTURE_1_FROM_SPDIF);
  607. if (outs | ins) {
  608. err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
  609. if (err < 0)
  610. return err;
  611. if (outs)
  612. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  613. &oxygen_spdif_ops);
  614. if (ins)
  615. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  616. &oxygen_rec_c_ops);
  617. pcm->private_data = chip;
  618. pcm->private_free = oxygen_pcm_free;
  619. strcpy(pcm->name, "Digital");
  620. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  621. snd_dma_pci_data(chip->pci),
  622. 128 * 1024, 256 * 1024);
  623. }
  624. if (chip->has_ac97_1) {
  625. outs = !!(chip->model->pcm_dev_cfg & PLAYBACK_2_TO_AC97_1);
  626. ins = !!(chip->model->pcm_dev_cfg & CAPTURE_2_FROM_AC97_1);
  627. } else {
  628. outs = 0;
  629. ins = !!(chip->model->pcm_dev_cfg & CAPTURE_2_FROM_I2S_2);
  630. }
  631. if (outs | ins) {
  632. err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
  633. 2, outs, ins, &pcm);
  634. if (err < 0)
  635. return err;
  636. if (outs) {
  637. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  638. &oxygen_ac97_ops);
  639. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  640. OXYGEN_REC_B_ROUTE_AC97_1,
  641. OXYGEN_REC_B_ROUTE_MASK);
  642. }
  643. if (ins)
  644. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  645. &oxygen_rec_b_ops);
  646. pcm->private_data = chip;
  647. pcm->private_free = oxygen_pcm_free;
  648. strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
  649. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  650. snd_dma_pci_data(chip->pci),
  651. 128 * 1024, 256 * 1024);
  652. }
  653. return 0;
  654. }