dsp_spos.c 54 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  15. *
  16. */
  17. /*
  18. * 2002-07 Benny Sjostrand benny@hostmobility.com
  19. */
  20. #include <asm/io.h>
  21. #include <linux/delay.h>
  22. #include <linux/pm.h>
  23. #include <linux/init.h>
  24. #include <linux/slab.h>
  25. #include <linux/vmalloc.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include <sound/asoundef.h>
  31. #include <sound/cs46xx.h>
  32. #include "cs46xx_lib.h"
  33. #include "dsp_spos.h"
  34. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  35. struct dsp_scb_descriptor * fg_entry);
  36. static enum wide_opcode wide_opcodes[] = {
  37. WIDE_FOR_BEGIN_LOOP,
  38. WIDE_FOR_BEGIN_LOOP2,
  39. WIDE_COND_GOTO_ADDR,
  40. WIDE_COND_GOTO_CALL,
  41. WIDE_TBEQ_COND_GOTO_ADDR,
  42. WIDE_TBEQ_COND_CALL_ADDR,
  43. WIDE_TBEQ_NCOND_GOTO_ADDR,
  44. WIDE_TBEQ_NCOND_CALL_ADDR,
  45. WIDE_TBEQ_COND_GOTO1_ADDR,
  46. WIDE_TBEQ_COND_CALL1_ADDR,
  47. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  48. WIDE_TBEQ_NCOND_CALL1_ADDR
  49. };
  50. static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
  51. u32 overlay_begin_address)
  52. {
  53. unsigned int i = 0, j, nreallocated = 0;
  54. u32 hival,loval,address;
  55. u32 mop_operands,mop_type,wide_op;
  56. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  57. snd_assert( ((size % 2) == 0), return -EINVAL);
  58. while (i < size) {
  59. loval = data[i++];
  60. hival = data[i++];
  61. if (ins->code.offset > 0) {
  62. mop_operands = (hival >> 6) & 0x03fff;
  63. mop_type = mop_operands >> 10;
  64. /* check for wide type instruction */
  65. if (mop_type == 0 &&
  66. (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
  67. (mop_operands & WIDE_INSTR_MASK) != 0) {
  68. wide_op = loval & 0x7f;
  69. for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
  70. if (wide_opcodes[j] == wide_op) {
  71. /* need to reallocate instruction */
  72. address = (hival & 0x00FFF) << 5;
  73. address |= loval >> 15;
  74. snd_printdd("handle_wideop[1]: %05x:%05x addr %04x\n",hival,loval,address);
  75. if ( !(address & 0x8000) ) {
  76. address += (ins->code.offset / 2) - overlay_begin_address;
  77. } else {
  78. snd_printdd("handle_wideop[1]: ROM symbol not reallocated\n");
  79. }
  80. hival &= 0xFF000;
  81. loval &= 0x07FFF;
  82. hival |= ( (address >> 5) & 0x00FFF);
  83. loval |= ( (address << 15) & 0xF8000);
  84. address = (hival & 0x00FFF) << 5;
  85. address |= loval >> 15;
  86. snd_printdd("handle_wideop:[2] %05x:%05x addr %04x\n",hival,loval,address);
  87. nreallocated ++;
  88. } /* wide_opcodes[j] == wide_op */
  89. } /* for */
  90. } /* mod_type == 0 ... */
  91. } /* ins->code.offset > 0 */
  92. ins->code.data[ins->code.size++] = loval;
  93. ins->code.data[ins->code.size++] = hival;
  94. }
  95. snd_printdd("dsp_spos: %d instructions reallocated\n",nreallocated);
  96. return nreallocated;
  97. }
  98. static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
  99. {
  100. int i;
  101. for (i = 0;i < module->nsegments; ++i) {
  102. if (module->segments[i].segment_type == seg_type) {
  103. return (module->segments + i);
  104. }
  105. }
  106. return NULL;
  107. };
  108. static int find_free_symbol_index (struct dsp_spos_instance * ins)
  109. {
  110. int index = ins->symbol_table.nsymbols,i;
  111. for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
  112. if (ins->symbol_table.symbols[i].deleted) {
  113. index = i;
  114. break;
  115. }
  116. }
  117. return index;
  118. }
  119. static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  120. {
  121. int i;
  122. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  123. if (module->symbol_table.nsymbols > 0) {
  124. if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
  125. module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
  126. module->overlay_begin_address = module->symbol_table.symbols[0].address;
  127. }
  128. }
  129. for (i = 0;i < module->symbol_table.nsymbols; ++i) {
  130. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  131. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  132. return -ENOMEM;
  133. }
  134. if (cs46xx_dsp_lookup_symbol(chip,
  135. module->symbol_table.symbols[i].symbol_name,
  136. module->symbol_table.symbols[i].symbol_type) == NULL) {
  137. ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
  138. ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
  139. ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
  140. ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
  141. if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
  142. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  143. ins->symbol_table.nsymbols++;
  144. } else {
  145. /* if (0) printk ("dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
  146. module->symbol_table.symbols[i].symbol_name); */
  147. }
  148. }
  149. return 0;
  150. }
  151. static struct dsp_symbol_entry *
  152. add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
  153. {
  154. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  155. struct dsp_symbol_entry * symbol = NULL;
  156. int index;
  157. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  158. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  159. return NULL;
  160. }
  161. if (cs46xx_dsp_lookup_symbol(chip,
  162. symbol_name,
  163. type) != NULL) {
  164. snd_printk(KERN_ERR "dsp_spos: symbol <%s> duplicated\n", symbol_name);
  165. return NULL;
  166. }
  167. index = find_free_symbol_index (ins);
  168. strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
  169. ins->symbol_table.symbols[index].address = address;
  170. ins->symbol_table.symbols[index].symbol_type = type;
  171. ins->symbol_table.symbols[index].module = NULL;
  172. ins->symbol_table.symbols[index].deleted = 0;
  173. symbol = (ins->symbol_table.symbols + index);
  174. if (index > ins->symbol_table.highest_frag_index)
  175. ins->symbol_table.highest_frag_index = index;
  176. if (index == ins->symbol_table.nsymbols)
  177. ins->symbol_table.nsymbols++; /* no frag. in list */
  178. return symbol;
  179. }
  180. struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
  181. {
  182. struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
  183. if (ins == NULL)
  184. return NULL;
  185. /* better to use vmalloc for this big table */
  186. ins->symbol_table.nsymbols = 0;
  187. ins->symbol_table.symbols = vmalloc(sizeof(struct dsp_symbol_entry) *
  188. DSP_MAX_SYMBOLS);
  189. ins->symbol_table.highest_frag_index = 0;
  190. if (ins->symbol_table.symbols == NULL) {
  191. cs46xx_dsp_spos_destroy(chip);
  192. goto error;
  193. }
  194. ins->code.offset = 0;
  195. ins->code.size = 0;
  196. ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
  197. if (ins->code.data == NULL) {
  198. cs46xx_dsp_spos_destroy(chip);
  199. goto error;
  200. }
  201. ins->nscb = 0;
  202. ins->ntask = 0;
  203. ins->nmodules = 0;
  204. ins->modules = kmalloc(sizeof(struct dsp_module_desc) * DSP_MAX_MODULES, GFP_KERNEL);
  205. if (ins->modules == NULL) {
  206. cs46xx_dsp_spos_destroy(chip);
  207. goto error;
  208. }
  209. /* default SPDIF input sample rate
  210. to 48000 khz */
  211. ins->spdif_in_sample_rate = 48000;
  212. /* maximize volume */
  213. ins->dac_volume_right = 0x8000;
  214. ins->dac_volume_left = 0x8000;
  215. ins->spdif_input_volume_right = 0x8000;
  216. ins->spdif_input_volume_left = 0x8000;
  217. /* set left and right validity bits and
  218. default channel status */
  219. ins->spdif_csuv_default =
  220. ins->spdif_csuv_stream =
  221. /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
  222. /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
  223. /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
  224. /* left and right validity bits */ (1 << 13) | (1 << 12);
  225. return ins;
  226. error:
  227. kfree(ins);
  228. return NULL;
  229. }
  230. void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
  231. {
  232. int i;
  233. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  234. snd_assert(ins != NULL, return);
  235. mutex_lock(&chip->spos_mutex);
  236. for (i = 0; i < ins->nscb; ++i) {
  237. if (ins->scbs[i].deleted) continue;
  238. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  239. }
  240. kfree(ins->code.data);
  241. vfree(ins->symbol_table.symbols);
  242. kfree(ins->modules);
  243. kfree(ins);
  244. mutex_unlock(&chip->spos_mutex);
  245. }
  246. static int dsp_load_parameter(struct snd_cs46xx *chip,
  247. struct dsp_segment_desc *parameter)
  248. {
  249. u32 doffset, dsize;
  250. if (!parameter) {
  251. snd_printdd("dsp_spos: module got no parameter segment\n");
  252. return 0;
  253. }
  254. doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
  255. dsize = parameter->size * 4;
  256. snd_printdd("dsp_spos: "
  257. "downloading parameter data to chip (%08x-%08x)\n",
  258. doffset,doffset + dsize);
  259. if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
  260. snd_printk(KERN_ERR "dsp_spos: "
  261. "failed to download parameter data to DSP\n");
  262. return -EINVAL;
  263. }
  264. return 0;
  265. }
  266. static int dsp_load_sample(struct snd_cs46xx *chip,
  267. struct dsp_segment_desc *sample)
  268. {
  269. u32 doffset, dsize;
  270. if (!sample) {
  271. snd_printdd("dsp_spos: module got no sample segment\n");
  272. return 0;
  273. }
  274. doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
  275. dsize = sample->size * 4;
  276. snd_printdd("dsp_spos: downloading sample data to chip (%08x-%08x)\n",
  277. doffset,doffset + dsize);
  278. if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
  279. snd_printk(KERN_ERR "dsp_spos: failed to sample data to DSP\n");
  280. return -EINVAL;
  281. }
  282. return 0;
  283. }
  284. int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  285. {
  286. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  287. struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
  288. u32 doffset, dsize;
  289. int err;
  290. if (ins->nmodules == DSP_MAX_MODULES - 1) {
  291. snd_printk(KERN_ERR "dsp_spos: to many modules loaded into DSP\n");
  292. return -ENOMEM;
  293. }
  294. snd_printdd("dsp_spos: loading module %s into DSP\n", module->module_name);
  295. if (ins->nmodules == 0) {
  296. snd_printdd("dsp_spos: clearing parameter area\n");
  297. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
  298. }
  299. err = dsp_load_parameter(chip, get_segment_desc(module,
  300. SEGTYPE_SP_PARAMETER));
  301. if (err < 0)
  302. return err;
  303. if (ins->nmodules == 0) {
  304. snd_printdd("dsp_spos: clearing sample area\n");
  305. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
  306. }
  307. err = dsp_load_sample(chip, get_segment_desc(module,
  308. SEGTYPE_SP_SAMPLE));
  309. if (err < 0)
  310. return err;
  311. if (ins->nmodules == 0) {
  312. snd_printdd("dsp_spos: clearing code area\n");
  313. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  314. }
  315. if (code == NULL) {
  316. snd_printdd("dsp_spos: module got no code segment\n");
  317. } else {
  318. if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
  319. snd_printk(KERN_ERR "dsp_spos: no space available in DSP\n");
  320. return -ENOMEM;
  321. }
  322. module->load_address = ins->code.offset;
  323. module->overlay_begin_address = 0x000;
  324. /* if module has a code segment it must have
  325. symbol table */
  326. snd_assert(module->symbol_table.symbols != NULL ,return -ENOMEM);
  327. if (add_symbols(chip,module)) {
  328. snd_printk(KERN_ERR "dsp_spos: failed to load symbol table\n");
  329. return -ENOMEM;
  330. }
  331. doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
  332. dsize = code->size * 4;
  333. snd_printdd("dsp_spos: downloading code to chip (%08x-%08x)\n",
  334. doffset,doffset + dsize);
  335. module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
  336. if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
  337. snd_printk(KERN_ERR "dsp_spos: failed to download code to DSP\n");
  338. return -EINVAL;
  339. }
  340. ins->code.offset += code->size;
  341. }
  342. /* NOTE: module segments and symbol table must be
  343. statically allocated. Case that module data is
  344. not generated by the ospparser */
  345. ins->modules[ins->nmodules] = *module;
  346. ins->nmodules++;
  347. return 0;
  348. }
  349. struct dsp_symbol_entry *
  350. cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
  351. {
  352. int i;
  353. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  354. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  355. if (ins->symbol_table.symbols[i].deleted)
  356. continue;
  357. if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
  358. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  359. return (ins->symbol_table.symbols + i);
  360. }
  361. }
  362. #if 0
  363. printk ("dsp_spos: symbol <%s> type %02x not found\n",
  364. symbol_name,symbol_type);
  365. #endif
  366. return NULL;
  367. }
  368. #ifdef CONFIG_PROC_FS
  369. static struct dsp_symbol_entry *
  370. cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
  371. {
  372. int i;
  373. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  374. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  375. if (ins->symbol_table.symbols[i].deleted)
  376. continue;
  377. if (ins->symbol_table.symbols[i].address == address &&
  378. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  379. return (ins->symbol_table.symbols + i);
  380. }
  381. }
  382. return NULL;
  383. }
  384. static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
  385. struct snd_info_buffer *buffer)
  386. {
  387. struct snd_cs46xx *chip = entry->private_data;
  388. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  389. int i;
  390. snd_iprintf(buffer, "SYMBOLS:\n");
  391. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  392. char *module_str = "system";
  393. if (ins->symbol_table.symbols[i].deleted)
  394. continue;
  395. if (ins->symbol_table.symbols[i].module != NULL) {
  396. module_str = ins->symbol_table.symbols[i].module->module_name;
  397. }
  398. snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
  399. ins->symbol_table.symbols[i].address,
  400. ins->symbol_table.symbols[i].symbol_type,
  401. ins->symbol_table.symbols[i].symbol_name,
  402. module_str);
  403. }
  404. }
  405. static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
  406. struct snd_info_buffer *buffer)
  407. {
  408. struct snd_cs46xx *chip = entry->private_data;
  409. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  410. int i,j;
  411. mutex_lock(&chip->spos_mutex);
  412. snd_iprintf(buffer, "MODULES:\n");
  413. for ( i = 0; i < ins->nmodules; ++i ) {
  414. snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
  415. snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
  416. snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
  417. for (j = 0; j < ins->modules[i].nsegments; ++ j) {
  418. struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
  419. snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
  420. desc->segment_type,desc->offset, desc->size);
  421. }
  422. }
  423. mutex_unlock(&chip->spos_mutex);
  424. }
  425. static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
  426. struct snd_info_buffer *buffer)
  427. {
  428. struct snd_cs46xx *chip = entry->private_data;
  429. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  430. int i, j, col;
  431. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  432. mutex_lock(&chip->spos_mutex);
  433. snd_iprintf(buffer, "TASK TREES:\n");
  434. for ( i = 0; i < ins->ntask; ++i) {
  435. snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
  436. for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
  437. u32 val;
  438. if (col == 4) {
  439. snd_iprintf(buffer,"\n");
  440. col = 0;
  441. }
  442. val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
  443. snd_iprintf(buffer,"%08x ",val);
  444. }
  445. }
  446. snd_iprintf(buffer,"\n");
  447. mutex_unlock(&chip->spos_mutex);
  448. }
  449. static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
  450. struct snd_info_buffer *buffer)
  451. {
  452. struct snd_cs46xx *chip = entry->private_data;
  453. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  454. int i;
  455. mutex_lock(&chip->spos_mutex);
  456. snd_iprintf(buffer, "SCB's:\n");
  457. for ( i = 0; i < ins->nscb; ++i) {
  458. if (ins->scbs[i].deleted)
  459. continue;
  460. snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
  461. if (ins->scbs[i].parent_scb_ptr != NULL) {
  462. snd_iprintf(buffer,"parent [%s:%04x] ",
  463. ins->scbs[i].parent_scb_ptr->scb_name,
  464. ins->scbs[i].parent_scb_ptr->address);
  465. } else snd_iprintf(buffer,"parent [none] ");
  466. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  467. ins->scbs[i].sub_list_ptr->scb_name,
  468. ins->scbs[i].sub_list_ptr->address,
  469. ins->scbs[i].next_scb_ptr->scb_name,
  470. ins->scbs[i].next_scb_ptr->address,
  471. ins->scbs[i].task_entry->symbol_name,
  472. ins->scbs[i].task_entry->address);
  473. }
  474. snd_iprintf(buffer,"\n");
  475. mutex_unlock(&chip->spos_mutex);
  476. }
  477. static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
  478. struct snd_info_buffer *buffer)
  479. {
  480. struct snd_cs46xx *chip = entry->private_data;
  481. /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
  482. unsigned int i, col = 0;
  483. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  484. struct dsp_symbol_entry * symbol;
  485. for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
  486. if (col == 4) {
  487. snd_iprintf(buffer,"\n");
  488. col = 0;
  489. }
  490. if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
  491. col = 0;
  492. snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
  493. }
  494. if (col == 0) {
  495. snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
  496. }
  497. snd_iprintf(buffer,"%08X ",readl(dst + i));
  498. }
  499. }
  500. static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
  501. struct snd_info_buffer *buffer)
  502. {
  503. struct snd_cs46xx *chip = entry->private_data;
  504. int i,col = 0;
  505. void __iomem *dst = chip->region.idx[2].remap_addr;
  506. snd_iprintf(buffer,"PCMREADER:\n");
  507. for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
  508. if (col == 4) {
  509. snd_iprintf(buffer,"\n");
  510. col = 0;
  511. }
  512. if (col == 0) {
  513. snd_iprintf(buffer, "%04X ",i);
  514. }
  515. snd_iprintf(buffer,"%08X ",readl(dst + i));
  516. }
  517. snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
  518. col = 0;
  519. for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
  520. if (col == 4) {
  521. snd_iprintf(buffer,"\n");
  522. col = 0;
  523. }
  524. if (col == 0) {
  525. snd_iprintf(buffer, "%04X ",i);
  526. }
  527. snd_iprintf(buffer,"%08X ",readl(dst + i));
  528. }
  529. snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
  530. col = 0;
  531. for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
  532. if (col == 4) {
  533. snd_iprintf(buffer,"\n");
  534. col = 0;
  535. }
  536. if (col == 0) {
  537. snd_iprintf(buffer, "%04X ",i);
  538. }
  539. snd_iprintf(buffer,"%08X ",readl(dst + i));
  540. }
  541. snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
  542. col = 0;
  543. for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
  544. if (col == 4) {
  545. snd_iprintf(buffer,"\n");
  546. col = 0;
  547. }
  548. if (col == 0) {
  549. snd_iprintf(buffer, "%04X ",i);
  550. }
  551. snd_iprintf(buffer,"%08X ",readl(dst + i));
  552. }
  553. snd_iprintf(buffer,"\n...\n");
  554. col = 0;
  555. for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
  556. if (col == 4) {
  557. snd_iprintf(buffer,"\n");
  558. col = 0;
  559. }
  560. if (col == 0) {
  561. snd_iprintf(buffer, "%04X ",i);
  562. }
  563. snd_iprintf(buffer,"%08X ",readl(dst + i));
  564. }
  565. snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
  566. col = 0;
  567. for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
  568. if (col == 4) {
  569. snd_iprintf(buffer,"\n");
  570. col = 0;
  571. }
  572. if (col == 0) {
  573. snd_iprintf(buffer, "%04X ",i);
  574. }
  575. snd_iprintf(buffer,"%08X ",readl(dst + i));
  576. }
  577. snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
  578. col = 0;
  579. for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
  580. if (col == 4) {
  581. snd_iprintf(buffer,"\n");
  582. col = 0;
  583. }
  584. if (col == 0) {
  585. snd_iprintf(buffer, "%04X ",i);
  586. }
  587. snd_iprintf(buffer,"%08X ",readl(dst + i));
  588. }
  589. #if 0
  590. snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
  591. col = 0;
  592. for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
  593. if (col == 4) {
  594. snd_iprintf(buffer,"\n");
  595. col = 0;
  596. }
  597. if (col == 0) {
  598. snd_iprintf(buffer, "%04X ",i);
  599. }
  600. snd_iprintf(buffer,"%08X ",readl(dst + i));
  601. }
  602. #endif
  603. snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
  604. col = 0;
  605. for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
  606. if (col == 4) {
  607. snd_iprintf(buffer,"\n");
  608. col = 0;
  609. }
  610. if (col == 0) {
  611. snd_iprintf(buffer, "%04X ",i);
  612. }
  613. snd_iprintf(buffer,"%08X ",readl(dst + i));
  614. }
  615. snd_iprintf(buffer,"\n");
  616. }
  617. int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
  618. {
  619. struct snd_info_entry *entry;
  620. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  621. int i;
  622. ins->snd_card = card;
  623. if ((entry = snd_info_create_card_entry(card, "dsp", card->proc_root)) != NULL) {
  624. entry->content = SNDRV_INFO_CONTENT_TEXT;
  625. entry->mode = S_IFDIR | S_IRUGO | S_IXUGO;
  626. if (snd_info_register(entry) < 0) {
  627. snd_info_free_entry(entry);
  628. entry = NULL;
  629. }
  630. }
  631. ins->proc_dsp_dir = entry;
  632. if (!ins->proc_dsp_dir)
  633. return -ENOMEM;
  634. if ((entry = snd_info_create_card_entry(card, "spos_symbols", ins->proc_dsp_dir)) != NULL) {
  635. entry->content = SNDRV_INFO_CONTENT_TEXT;
  636. entry->private_data = chip;
  637. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  638. entry->c.text.read = cs46xx_dsp_proc_symbol_table_read;
  639. if (snd_info_register(entry) < 0) {
  640. snd_info_free_entry(entry);
  641. entry = NULL;
  642. }
  643. }
  644. ins->proc_sym_info_entry = entry;
  645. if ((entry = snd_info_create_card_entry(card, "spos_modules", ins->proc_dsp_dir)) != NULL) {
  646. entry->content = SNDRV_INFO_CONTENT_TEXT;
  647. entry->private_data = chip;
  648. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  649. entry->c.text.read = cs46xx_dsp_proc_modules_read;
  650. if (snd_info_register(entry) < 0) {
  651. snd_info_free_entry(entry);
  652. entry = NULL;
  653. }
  654. }
  655. ins->proc_modules_info_entry = entry;
  656. if ((entry = snd_info_create_card_entry(card, "parameter", ins->proc_dsp_dir)) != NULL) {
  657. entry->content = SNDRV_INFO_CONTENT_TEXT;
  658. entry->private_data = chip;
  659. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  660. entry->c.text.read = cs46xx_dsp_proc_parameter_dump_read;
  661. if (snd_info_register(entry) < 0) {
  662. snd_info_free_entry(entry);
  663. entry = NULL;
  664. }
  665. }
  666. ins->proc_parameter_dump_info_entry = entry;
  667. if ((entry = snd_info_create_card_entry(card, "sample", ins->proc_dsp_dir)) != NULL) {
  668. entry->content = SNDRV_INFO_CONTENT_TEXT;
  669. entry->private_data = chip;
  670. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  671. entry->c.text.read = cs46xx_dsp_proc_sample_dump_read;
  672. if (snd_info_register(entry) < 0) {
  673. snd_info_free_entry(entry);
  674. entry = NULL;
  675. }
  676. }
  677. ins->proc_sample_dump_info_entry = entry;
  678. if ((entry = snd_info_create_card_entry(card, "task_tree", ins->proc_dsp_dir)) != NULL) {
  679. entry->content = SNDRV_INFO_CONTENT_TEXT;
  680. entry->private_data = chip;
  681. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  682. entry->c.text.read = cs46xx_dsp_proc_task_tree_read;
  683. if (snd_info_register(entry) < 0) {
  684. snd_info_free_entry(entry);
  685. entry = NULL;
  686. }
  687. }
  688. ins->proc_task_info_entry = entry;
  689. if ((entry = snd_info_create_card_entry(card, "scb_info", ins->proc_dsp_dir)) != NULL) {
  690. entry->content = SNDRV_INFO_CONTENT_TEXT;
  691. entry->private_data = chip;
  692. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  693. entry->c.text.read = cs46xx_dsp_proc_scb_read;
  694. if (snd_info_register(entry) < 0) {
  695. snd_info_free_entry(entry);
  696. entry = NULL;
  697. }
  698. }
  699. ins->proc_scb_info_entry = entry;
  700. mutex_lock(&chip->spos_mutex);
  701. /* register/update SCB's entries on proc */
  702. for (i = 0; i < ins->nscb; ++i) {
  703. if (ins->scbs[i].deleted) continue;
  704. cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
  705. }
  706. mutex_unlock(&chip->spos_mutex);
  707. return 0;
  708. }
  709. int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
  710. {
  711. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  712. int i;
  713. snd_info_free_entry(ins->proc_sym_info_entry);
  714. ins->proc_sym_info_entry = NULL;
  715. snd_info_free_entry(ins->proc_modules_info_entry);
  716. ins->proc_modules_info_entry = NULL;
  717. snd_info_free_entry(ins->proc_parameter_dump_info_entry);
  718. ins->proc_parameter_dump_info_entry = NULL;
  719. snd_info_free_entry(ins->proc_sample_dump_info_entry);
  720. ins->proc_sample_dump_info_entry = NULL;
  721. snd_info_free_entry(ins->proc_scb_info_entry);
  722. ins->proc_scb_info_entry = NULL;
  723. snd_info_free_entry(ins->proc_task_info_entry);
  724. ins->proc_task_info_entry = NULL;
  725. mutex_lock(&chip->spos_mutex);
  726. for (i = 0; i < ins->nscb; ++i) {
  727. if (ins->scbs[i].deleted) continue;
  728. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  729. }
  730. mutex_unlock(&chip->spos_mutex);
  731. snd_info_free_entry(ins->proc_dsp_dir);
  732. ins->proc_dsp_dir = NULL;
  733. return 0;
  734. }
  735. #endif /* CONFIG_PROC_FS */
  736. static int debug_tree;
  737. static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
  738. u32 dest, int size)
  739. {
  740. void __iomem *spdst = chip->region.idx[1].remap_addr +
  741. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  742. int i;
  743. for (i = 0; i < size; ++i) {
  744. if (debug_tree) printk ("addr %p, val %08x\n",spdst,task_data[i]);
  745. writel(task_data[i],spdst);
  746. spdst += sizeof(u32);
  747. }
  748. }
  749. static int debug_scb;
  750. static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
  751. {
  752. void __iomem *spdst = chip->region.idx[1].remap_addr +
  753. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  754. int i;
  755. for (i = 0; i < 0x10; ++i) {
  756. if (debug_scb) printk ("addr %p, val %08x\n",spdst,scb_data[i]);
  757. writel(scb_data[i],spdst);
  758. spdst += sizeof(u32);
  759. }
  760. }
  761. static int find_free_scb_index (struct dsp_spos_instance * ins)
  762. {
  763. int index = ins->nscb, i;
  764. for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
  765. if (ins->scbs[i].deleted) {
  766. index = i;
  767. break;
  768. }
  769. }
  770. return index;
  771. }
  772. static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
  773. {
  774. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  775. struct dsp_scb_descriptor * desc = NULL;
  776. int index;
  777. if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
  778. snd_printk(KERN_ERR "dsp_spos: got no place for other SCB\n");
  779. return NULL;
  780. }
  781. index = find_free_scb_index (ins);
  782. strcpy(ins->scbs[index].scb_name, name);
  783. ins->scbs[index].address = dest;
  784. ins->scbs[index].index = index;
  785. ins->scbs[index].proc_info = NULL;
  786. ins->scbs[index].ref_count = 1;
  787. ins->scbs[index].deleted = 0;
  788. spin_lock_init(&ins->scbs[index].lock);
  789. desc = (ins->scbs + index);
  790. ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
  791. if (index > ins->scb_highest_frag_index)
  792. ins->scb_highest_frag_index = index;
  793. if (index == ins->nscb)
  794. ins->nscb++;
  795. return desc;
  796. }
  797. static struct dsp_task_descriptor *
  798. _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
  799. {
  800. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  801. struct dsp_task_descriptor * desc = NULL;
  802. if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
  803. snd_printk(KERN_ERR "dsp_spos: got no place for other TASK\n");
  804. return NULL;
  805. }
  806. if (name)
  807. strcpy(ins->tasks[ins->ntask].task_name, name);
  808. else
  809. strcpy(ins->tasks[ins->ntask].task_name, "(NULL)");
  810. ins->tasks[ins->ntask].address = dest;
  811. ins->tasks[ins->ntask].size = size;
  812. /* quick find in list */
  813. ins->tasks[ins->ntask].index = ins->ntask;
  814. desc = (ins->tasks + ins->ntask);
  815. ins->ntask++;
  816. if (name)
  817. add_symbol (chip,name,dest,SYMBOL_PARAMETER);
  818. return desc;
  819. }
  820. struct dsp_scb_descriptor *
  821. cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
  822. {
  823. struct dsp_scb_descriptor * desc;
  824. desc = _map_scb (chip,name,dest);
  825. if (desc) {
  826. desc->data = scb_data;
  827. _dsp_create_scb(chip,scb_data,dest);
  828. } else {
  829. snd_printk(KERN_ERR "dsp_spos: failed to map SCB\n");
  830. }
  831. return desc;
  832. }
  833. static struct dsp_task_descriptor *
  834. cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
  835. u32 dest, int size)
  836. {
  837. struct dsp_task_descriptor * desc;
  838. desc = _map_task_tree (chip,name,dest,size);
  839. if (desc) {
  840. desc->data = task_data;
  841. _dsp_create_task_tree(chip,task_data,dest,size);
  842. } else {
  843. snd_printk(KERN_ERR "dsp_spos: failed to map TASK\n");
  844. }
  845. return desc;
  846. }
  847. int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
  848. {
  849. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  850. struct dsp_symbol_entry * fg_task_tree_header_code;
  851. struct dsp_symbol_entry * task_tree_header_code;
  852. struct dsp_symbol_entry * task_tree_thread;
  853. struct dsp_symbol_entry * null_algorithm;
  854. struct dsp_symbol_entry * magic_snoop_task;
  855. struct dsp_scb_descriptor * timing_master_scb;
  856. struct dsp_scb_descriptor * codec_out_scb;
  857. struct dsp_scb_descriptor * codec_in_scb;
  858. struct dsp_scb_descriptor * src_task_scb;
  859. struct dsp_scb_descriptor * master_mix_scb;
  860. struct dsp_scb_descriptor * rear_mix_scb;
  861. struct dsp_scb_descriptor * record_mix_scb;
  862. struct dsp_scb_descriptor * write_back_scb;
  863. struct dsp_scb_descriptor * vari_decimate_scb;
  864. struct dsp_scb_descriptor * rear_codec_out_scb;
  865. struct dsp_scb_descriptor * clfe_codec_out_scb;
  866. struct dsp_scb_descriptor * magic_snoop_scb;
  867. int fifo_addr, fifo_span, valid_slots;
  868. static struct dsp_spos_control_block sposcb = {
  869. /* 0 */ HFG_TREE_SCB,HFG_STACK,
  870. /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
  871. /* 2 */ DSP_SPOS_DC,0,
  872. /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
  873. /* 4 */ 0,0,
  874. /* 5 */ DSP_SPOS_UU,0,
  875. /* 6 */ FG_TASK_HEADER_ADDR,0,
  876. /* 7 */ 0,0,
  877. /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
  878. /* 9 */ 0,
  879. /* A */ 0,HFG_FIRST_EXECUTE_MODE,
  880. /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
  881. /* C */ DSP_SPOS_DC_DC,
  882. /* D */ DSP_SPOS_DC_DC,
  883. /* E */ DSP_SPOS_DC_DC,
  884. /* F */ DSP_SPOS_DC_DC
  885. };
  886. cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
  887. null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
  888. if (null_algorithm == NULL) {
  889. snd_printk(KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  890. return -EIO;
  891. }
  892. fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
  893. if (fg_task_tree_header_code == NULL) {
  894. snd_printk(KERN_ERR "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
  895. return -EIO;
  896. }
  897. task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
  898. if (task_tree_header_code == NULL) {
  899. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
  900. return -EIO;
  901. }
  902. task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
  903. if (task_tree_thread == NULL) {
  904. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREETHREAD not found\n");
  905. return -EIO;
  906. }
  907. magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
  908. if (magic_snoop_task == NULL) {
  909. snd_printk(KERN_ERR "dsp_spos: symbol MAGICSNOOPTASK not found\n");
  910. return -EIO;
  911. }
  912. {
  913. /* create the null SCB */
  914. static struct dsp_generic_scb null_scb = {
  915. { 0, 0, 0, 0 },
  916. { 0, 0, 0, 0, 0 },
  917. NULL_SCB_ADDR, NULL_SCB_ADDR,
  918. 0, 0, 0, 0, 0,
  919. {
  920. 0,0,
  921. 0,0,
  922. }
  923. };
  924. null_scb.entry_point = null_algorithm->address;
  925. ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
  926. ins->the_null_scb->task_entry = null_algorithm;
  927. ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
  928. ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
  929. ins->the_null_scb->parent_scb_ptr = NULL;
  930. cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
  931. }
  932. {
  933. /* setup foreground task tree */
  934. static struct dsp_task_tree_control_block fg_task_tree_hdr = {
  935. { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
  936. DSP_SPOS_DC_DC,
  937. DSP_SPOS_DC_DC,
  938. 0x0000,DSP_SPOS_DC,
  939. DSP_SPOS_DC, DSP_SPOS_DC,
  940. DSP_SPOS_DC_DC,
  941. DSP_SPOS_DC_DC,
  942. DSP_SPOS_DC_DC,
  943. DSP_SPOS_DC,DSP_SPOS_DC },
  944. {
  945. BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
  946. 0,
  947. FG_TASK_HEADER_ADDR + TCBData,
  948. },
  949. {
  950. 4,0,
  951. 1,0,
  952. 2,SPOSCB_ADDR + HFGFlags,
  953. 0,0,
  954. FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
  955. },
  956. {
  957. DSP_SPOS_DC,0,
  958. DSP_SPOS_DC,DSP_SPOS_DC,
  959. DSP_SPOS_DC,DSP_SPOS_DC,
  960. DSP_SPOS_DC,DSP_SPOS_DC,
  961. DSP_SPOS_DC,DSP_SPOS_DC,
  962. DSP_SPOS_DCDC,
  963. DSP_SPOS_UU,1,
  964. DSP_SPOS_DCDC,
  965. DSP_SPOS_DCDC,
  966. DSP_SPOS_DCDC,
  967. DSP_SPOS_DCDC,
  968. DSP_SPOS_DCDC,
  969. DSP_SPOS_DCDC,
  970. DSP_SPOS_DCDC,
  971. DSP_SPOS_DCDC,
  972. DSP_SPOS_DCDC,
  973. DSP_SPOS_DCDC,
  974. DSP_SPOS_DCDC,
  975. DSP_SPOS_DCDC,
  976. DSP_SPOS_DCDC,
  977. DSP_SPOS_DCDC,
  978. DSP_SPOS_DCDC,
  979. DSP_SPOS_DCDC,
  980. DSP_SPOS_DCDC,
  981. DSP_SPOS_DCDC,
  982. DSP_SPOS_DCDC,
  983. DSP_SPOS_DCDC,
  984. DSP_SPOS_DCDC,
  985. DSP_SPOS_DCDC,
  986. DSP_SPOS_DCDC,
  987. DSP_SPOS_DCDC,
  988. DSP_SPOS_DCDC,
  989. DSP_SPOS_DCDC,
  990. DSP_SPOS_DCDC,
  991. DSP_SPOS_DCDC
  992. },
  993. {
  994. FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  995. 0,0
  996. }
  997. };
  998. fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
  999. fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1000. cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
  1001. }
  1002. {
  1003. /* setup foreground task tree */
  1004. static struct dsp_task_tree_control_block bg_task_tree_hdr = {
  1005. { DSP_SPOS_DC_DC,
  1006. DSP_SPOS_DC_DC,
  1007. DSP_SPOS_DC_DC,
  1008. DSP_SPOS_DC, DSP_SPOS_DC,
  1009. DSP_SPOS_DC, DSP_SPOS_DC,
  1010. DSP_SPOS_DC_DC,
  1011. DSP_SPOS_DC_DC,
  1012. DSP_SPOS_DC_DC,
  1013. DSP_SPOS_DC,DSP_SPOS_DC },
  1014. {
  1015. NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
  1016. 0,
  1017. BG_TREE_SCB_ADDR + TCBData,
  1018. },
  1019. {
  1020. 9999,0,
  1021. 0,1,
  1022. 0,SPOSCB_ADDR + HFGFlags,
  1023. 0,0,
  1024. BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
  1025. },
  1026. {
  1027. DSP_SPOS_DC,0,
  1028. DSP_SPOS_DC,DSP_SPOS_DC,
  1029. DSP_SPOS_DC,DSP_SPOS_DC,
  1030. DSP_SPOS_DC,DSP_SPOS_DC,
  1031. DSP_SPOS_DC,DSP_SPOS_DC,
  1032. DSP_SPOS_DCDC,
  1033. DSP_SPOS_UU,1,
  1034. DSP_SPOS_DCDC,
  1035. DSP_SPOS_DCDC,
  1036. DSP_SPOS_DCDC,
  1037. DSP_SPOS_DCDC,
  1038. DSP_SPOS_DCDC,
  1039. DSP_SPOS_DCDC,
  1040. DSP_SPOS_DCDC,
  1041. DSP_SPOS_DCDC,
  1042. DSP_SPOS_DCDC,
  1043. DSP_SPOS_DCDC,
  1044. DSP_SPOS_DCDC,
  1045. DSP_SPOS_DCDC,
  1046. DSP_SPOS_DCDC,
  1047. DSP_SPOS_DCDC,
  1048. DSP_SPOS_DCDC,
  1049. DSP_SPOS_DCDC,
  1050. DSP_SPOS_DCDC,
  1051. DSP_SPOS_DCDC,
  1052. DSP_SPOS_DCDC,
  1053. DSP_SPOS_DCDC,
  1054. DSP_SPOS_DCDC,
  1055. DSP_SPOS_DCDC,
  1056. DSP_SPOS_DCDC,
  1057. DSP_SPOS_DCDC,
  1058. DSP_SPOS_DCDC,
  1059. DSP_SPOS_DCDC,
  1060. DSP_SPOS_DCDC,
  1061. DSP_SPOS_DCDC
  1062. },
  1063. {
  1064. BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1065. 0,0
  1066. }
  1067. };
  1068. bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
  1069. bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1070. cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
  1071. }
  1072. /* create timing master SCB */
  1073. timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
  1074. /* create the CODEC output task */
  1075. codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
  1076. MASTERMIX_SCB_ADDR,
  1077. CODECOUT_SCB_ADDR,timing_master_scb,
  1078. SCB_ON_PARENT_SUBLIST_SCB);
  1079. if (!codec_out_scb) goto _fail_end;
  1080. /* create the master mix SCB */
  1081. master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
  1082. MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
  1083. codec_out_scb,
  1084. SCB_ON_PARENT_SUBLIST_SCB);
  1085. ins->master_mix_scb = master_mix_scb;
  1086. if (!master_mix_scb) goto _fail_end;
  1087. /* create codec in */
  1088. codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
  1089. CODEC_INPUT_BUF1,
  1090. CODECIN_SCB_ADDR,codec_out_scb,
  1091. SCB_ON_PARENT_NEXT_SCB);
  1092. if (!codec_in_scb) goto _fail_end;
  1093. ins->codec_in_scb = codec_in_scb;
  1094. /* create write back scb */
  1095. write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
  1096. WRITE_BACK_BUF1,WRITE_BACK_SPB,
  1097. WRITEBACK_SCB_ADDR,
  1098. timing_master_scb,
  1099. SCB_ON_PARENT_NEXT_SCB);
  1100. if (!write_back_scb) goto _fail_end;
  1101. {
  1102. static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
  1103. 0x00020000,
  1104. 0x0000ffff
  1105. };
  1106. if (!cs46xx_dsp_create_task_tree(chip, NULL,
  1107. (u32 *)&mix2_ostream_spb,
  1108. WRITE_BACK_SPB, 2))
  1109. goto _fail_end;
  1110. }
  1111. /* input sample converter */
  1112. vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
  1113. VARI_DECIMATE_BUF0,
  1114. VARI_DECIMATE_BUF1,
  1115. VARIDECIMATE_SCB_ADDR,
  1116. write_back_scb,
  1117. SCB_ON_PARENT_SUBLIST_SCB);
  1118. if (!vari_decimate_scb) goto _fail_end;
  1119. /* create the record mixer SCB */
  1120. record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
  1121. MIX_SAMPLE_BUF2,
  1122. RECORD_MIXER_SCB_ADDR,
  1123. vari_decimate_scb,
  1124. SCB_ON_PARENT_SUBLIST_SCB);
  1125. ins->record_mixer_scb = record_mix_scb;
  1126. if (!record_mix_scb) goto _fail_end;
  1127. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  1128. snd_assert (chip->nr_ac97_codecs == 1 || chip->nr_ac97_codecs == 2);
  1129. if (chip->nr_ac97_codecs == 1) {
  1130. /* output on slot 5 and 11
  1131. on primary CODEC */
  1132. fifo_addr = 0x20;
  1133. fifo_span = 0x60;
  1134. /* enable slot 5 and 11 */
  1135. valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
  1136. } else {
  1137. /* output on slot 7 and 8
  1138. on secondary CODEC */
  1139. fifo_addr = 0x40;
  1140. fifo_span = 0x10;
  1141. /* enable slot 7 and 8 */
  1142. valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
  1143. }
  1144. /* create CODEC tasklet for rear speakers output*/
  1145. rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
  1146. REAR_MIXER_SCB_ADDR,
  1147. REAR_CODECOUT_SCB_ADDR,codec_in_scb,
  1148. SCB_ON_PARENT_NEXT_SCB);
  1149. if (!rear_codec_out_scb) goto _fail_end;
  1150. /* create the rear PCM channel mixer SCB */
  1151. rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
  1152. MIX_SAMPLE_BUF3,
  1153. REAR_MIXER_SCB_ADDR,
  1154. rear_codec_out_scb,
  1155. SCB_ON_PARENT_SUBLIST_SCB);
  1156. ins->rear_mix_scb = rear_mix_scb;
  1157. if (!rear_mix_scb) goto _fail_end;
  1158. if (chip->nr_ac97_codecs == 2) {
  1159. /* create CODEC tasklet for rear Center/LFE output
  1160. slot 6 and 9 on seconadry CODEC */
  1161. clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
  1162. CLFE_MIXER_SCB_ADDR,
  1163. CLFE_CODEC_SCB_ADDR,
  1164. rear_codec_out_scb,
  1165. SCB_ON_PARENT_NEXT_SCB);
  1166. if (!clfe_codec_out_scb) goto _fail_end;
  1167. /* create the rear PCM channel mixer SCB */
  1168. ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
  1169. MIX_SAMPLE_BUF4,
  1170. CLFE_MIXER_SCB_ADDR,
  1171. clfe_codec_out_scb,
  1172. SCB_ON_PARENT_SUBLIST_SCB);
  1173. if (!ins->center_lfe_mix_scb) goto _fail_end;
  1174. /* enable slot 6 and 9 */
  1175. valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
  1176. } else {
  1177. clfe_codec_out_scb = rear_codec_out_scb;
  1178. ins->center_lfe_mix_scb = rear_mix_scb;
  1179. }
  1180. /* enable slots depending on CODEC configuration */
  1181. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  1182. /* the magic snooper */
  1183. magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
  1184. OUTPUT_SNOOP_BUFFER,
  1185. codec_out_scb,
  1186. clfe_codec_out_scb,
  1187. SCB_ON_PARENT_NEXT_SCB);
  1188. if (!magic_snoop_scb) goto _fail_end;
  1189. ins->ref_snoop_scb = magic_snoop_scb;
  1190. /* SP IO access */
  1191. if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
  1192. magic_snoop_scb,
  1193. SCB_ON_PARENT_NEXT_SCB))
  1194. goto _fail_end;
  1195. /* SPDIF input sampel rate converter */
  1196. src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
  1197. ins->spdif_in_sample_rate,
  1198. SRC_OUTPUT_BUF1,
  1199. SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
  1200. master_mix_scb,
  1201. SCB_ON_PARENT_SUBLIST_SCB,1);
  1202. if (!src_task_scb) goto _fail_end;
  1203. cs46xx_src_unlink(chip,src_task_scb);
  1204. /* NOTE: when we now how to detect the SPDIF input
  1205. sample rate we will use this SRC to adjust it */
  1206. ins->spdif_in_src = src_task_scb;
  1207. cs46xx_dsp_async_init(chip,timing_master_scb);
  1208. return 0;
  1209. _fail_end:
  1210. snd_printk(KERN_ERR "dsp_spos: failed to setup SCB's in DSP\n");
  1211. return -EINVAL;
  1212. }
  1213. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  1214. struct dsp_scb_descriptor * fg_entry)
  1215. {
  1216. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1217. struct dsp_symbol_entry * s16_async_codec_input_task;
  1218. struct dsp_symbol_entry * spdifo_task;
  1219. struct dsp_symbol_entry * spdifi_task;
  1220. struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
  1221. s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
  1222. if (s16_async_codec_input_task == NULL) {
  1223. snd_printk(KERN_ERR "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
  1224. return -EIO;
  1225. }
  1226. spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
  1227. if (spdifo_task == NULL) {
  1228. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFOTASK not found\n");
  1229. return -EIO;
  1230. }
  1231. spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
  1232. if (spdifi_task == NULL) {
  1233. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFITASK not found\n");
  1234. return -EIO;
  1235. }
  1236. {
  1237. /* 0xBC0 */
  1238. struct dsp_spdifoscb spdifo_scb = {
  1239. /* 0 */ DSP_SPOS_UUUU,
  1240. {
  1241. /* 1 */ 0xb0,
  1242. /* 2 */ 0,
  1243. /* 3 */ 0,
  1244. /* 4 */ 0,
  1245. },
  1246. /* NOTE: the SPDIF output task read samples in mono
  1247. format, the AsynchFGTxSCB task writes to buffer
  1248. in stereo format
  1249. */
  1250. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
  1251. /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
  1252. /* 7 */ 0,0,
  1253. /* 8 */ 0,
  1254. /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
  1255. /* A */ spdifo_task->address,
  1256. SPDIFO_SCB_INST + SPDIFOFIFOPointer,
  1257. {
  1258. /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
  1259. /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
  1260. },
  1261. /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
  1262. /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
  1263. /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
  1264. };
  1265. /* 0xBB0 */
  1266. struct dsp_spdifiscb spdifi_scb = {
  1267. /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
  1268. /* 1 */ 0,
  1269. /* 2 */ 0,
  1270. /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
  1271. /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
  1272. /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
  1273. /* 6 */ DSP_SPOS_UUUU, /* Free3 */
  1274. /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
  1275. /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
  1276. /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
  1277. /* A */ spdifi_task->address,
  1278. SPDIFI_SCB_INST + SPDIFIFIFOPointer,
  1279. /* NOTE: The SPDIF input task write the sample in mono
  1280. format from the HW FIFO, the AsynchFGRxSCB task reads
  1281. them in stereo
  1282. */
  1283. /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
  1284. /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1285. /* D */ 0x8048,0,
  1286. /* E */ 0x01f0,0x0001,
  1287. /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
  1288. };
  1289. /* 0xBA0 */
  1290. struct dsp_async_codec_input_scb async_codec_input_scb = {
  1291. /* 0 */ DSP_SPOS_UUUU,
  1292. /* 1 */ 0,
  1293. /* 2 */ 0,
  1294. /* 3 */ 1,4000,
  1295. /* 4 */ 0x0118,0x0001,
  1296. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
  1297. /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1298. /* 7 */ DSP_SPOS_UU,0x3,
  1299. /* 8 */ DSP_SPOS_UUUU,
  1300. /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
  1301. /* A */ s16_async_codec_input_task->address,
  1302. HFG_TREE_SCB + AsyncCIOFIFOPointer,
  1303. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  1304. /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
  1305. #ifdef UseASER1Input
  1306. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1307. Init. 0000:8042: for ASER1
  1308. 0000:8044: for ASER2 */
  1309. /* D */ 0x8042,0,
  1310. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1311. Init 1 stero:8050 ASER1
  1312. Init 0 mono:8070 ASER2
  1313. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1314. /* E */ 0x0100,0x0001,
  1315. #endif
  1316. #ifdef UseASER2Input
  1317. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1318. Init. 0000:8042: for ASER1
  1319. 0000:8044: for ASER2 */
  1320. /* D */ 0x8044,0,
  1321. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1322. Init 1 stero:8050 ASER1
  1323. Init 0 mono:8070 ASER2
  1324. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1325. /* E */ 0x0110,0x0001,
  1326. #endif
  1327. /* short AsyncCIOutputBufModulo:AsyncCIFree;
  1328. AsyncCIOutputBufModulo: The modulo size for
  1329. the output buffer of this task */
  1330. /* F */ 0, /* DSP_SPOS_UUUU */
  1331. };
  1332. spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
  1333. snd_assert(spdifo_scb_desc, return -EIO);
  1334. spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
  1335. snd_assert(spdifi_scb_desc, return -EIO);
  1336. async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
  1337. snd_assert(async_codec_scb_desc, return -EIO);
  1338. async_codec_scb_desc->parent_scb_ptr = NULL;
  1339. async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
  1340. async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
  1341. async_codec_scb_desc->task_entry = s16_async_codec_input_task;
  1342. spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
  1343. spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
  1344. spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
  1345. spdifi_scb_desc->task_entry = spdifi_task;
  1346. spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
  1347. spdifo_scb_desc->next_scb_ptr = fg_entry;
  1348. spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
  1349. spdifo_scb_desc->task_entry = spdifo_task;
  1350. /* this one is faked, as the parnet of SPDIFO task
  1351. is the FG task tree */
  1352. fg_entry->parent_scb_ptr = spdifo_scb_desc;
  1353. /* for proc fs */
  1354. cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
  1355. cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
  1356. cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
  1357. /* Async MASTER ENABLE, affects both SPDIF input and output */
  1358. snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
  1359. }
  1360. return 0;
  1361. }
  1362. static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
  1363. {
  1364. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1365. /* set SPDIF output FIFO slot */
  1366. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
  1367. /* SPDIF output MASTER ENABLE */
  1368. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
  1369. /* right and left validate bit */
  1370. /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
  1371. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
  1372. /* clear fifo pointer */
  1373. cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
  1374. /* monitor state */
  1375. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
  1376. }
  1377. int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
  1378. {
  1379. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1380. /* if hw-ctrl already enabled, turn off to reset logic ... */
  1381. cs46xx_dsp_disable_spdif_hw (chip);
  1382. udelay(50);
  1383. /* set SPDIF output FIFO slot */
  1384. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
  1385. /* SPDIF output MASTER ENABLE */
  1386. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
  1387. /* right and left validate bit */
  1388. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1389. /* monitor state */
  1390. ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
  1391. return 0;
  1392. }
  1393. int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
  1394. {
  1395. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1396. /* turn on amplifier */
  1397. chip->active_ctrl(chip, 1);
  1398. chip->amplifier_ctrl(chip, 1);
  1399. snd_assert (ins->asynch_rx_scb == NULL,return -EINVAL);
  1400. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1401. mutex_lock(&chip->spos_mutex);
  1402. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
  1403. /* time countdown enable */
  1404. cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
  1405. /* NOTE: 80000005 value is just magic. With all values
  1406. that I've tested this one seem to give the best result.
  1407. Got no explication why. (Benny) */
  1408. /* SPDIF input MASTER ENABLE */
  1409. cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
  1410. ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
  1411. }
  1412. /* create and start the asynchronous receiver SCB */
  1413. ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
  1414. ASYNCRX_SCB_ADDR,
  1415. SPDIFI_SCB_INST,
  1416. SPDIFI_IP_OUTPUT_BUFFER1,
  1417. ins->spdif_in_src,
  1418. SCB_ON_PARENT_SUBLIST_SCB);
  1419. spin_lock_irq(&chip->reg_lock);
  1420. /* reset SPDIF input sample buffer pointer */
  1421. /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
  1422. (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
  1423. /* reset FIFO ptr */
  1424. /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
  1425. cs46xx_src_link(chip,ins->spdif_in_src);
  1426. /* unmute SRC volume */
  1427. cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
  1428. spin_unlock_irq(&chip->reg_lock);
  1429. /* set SPDIF input sample rate and unmute
  1430. NOTE: only 48khz support for SPDIF input this time */
  1431. /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
  1432. /* monitor state */
  1433. ins->spdif_status_in = 1;
  1434. mutex_unlock(&chip->spos_mutex);
  1435. return 0;
  1436. }
  1437. int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
  1438. {
  1439. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1440. snd_assert (ins->asynch_rx_scb != NULL, return -EINVAL);
  1441. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1442. mutex_lock(&chip->spos_mutex);
  1443. /* Remove the asynchronous receiver SCB */
  1444. cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
  1445. ins->asynch_rx_scb = NULL;
  1446. cs46xx_src_unlink(chip,ins->spdif_in_src);
  1447. /* monitor state */
  1448. ins->spdif_status_in = 0;
  1449. mutex_unlock(&chip->spos_mutex);
  1450. /* restore amplifier */
  1451. chip->active_ctrl(chip, -1);
  1452. chip->amplifier_ctrl(chip, -1);
  1453. return 0;
  1454. }
  1455. int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
  1456. {
  1457. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1458. snd_assert (ins->pcm_input == NULL,return -EINVAL);
  1459. snd_assert (ins->ref_snoop_scb != NULL,return -EINVAL);
  1460. mutex_lock(&chip->spos_mutex);
  1461. ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
  1462. "PCMSerialInput_Wave");
  1463. mutex_unlock(&chip->spos_mutex);
  1464. return 0;
  1465. }
  1466. int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
  1467. {
  1468. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1469. snd_assert (ins->pcm_input != NULL,return -EINVAL);
  1470. mutex_lock(&chip->spos_mutex);
  1471. cs46xx_dsp_remove_scb (chip,ins->pcm_input);
  1472. ins->pcm_input = NULL;
  1473. mutex_unlock(&chip->spos_mutex);
  1474. return 0;
  1475. }
  1476. int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
  1477. {
  1478. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1479. snd_assert (ins->adc_input == NULL,return -EINVAL);
  1480. snd_assert (ins->codec_in_scb != NULL,return -EINVAL);
  1481. mutex_lock(&chip->spos_mutex);
  1482. ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
  1483. "PCMSerialInput_ADC");
  1484. mutex_unlock(&chip->spos_mutex);
  1485. return 0;
  1486. }
  1487. int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
  1488. {
  1489. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1490. snd_assert (ins->adc_input != NULL,return -EINVAL);
  1491. mutex_lock(&chip->spos_mutex);
  1492. cs46xx_dsp_remove_scb (chip,ins->adc_input);
  1493. ins->adc_input = NULL;
  1494. mutex_unlock(&chip->spos_mutex);
  1495. return 0;
  1496. }
  1497. int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
  1498. {
  1499. u32 temp;
  1500. int i;
  1501. /* santiy check the parameters. (These numbers are not 100% correct. They are
  1502. a rough guess from looking at the controller spec.) */
  1503. if (address < 0x8000 || address >= 0x9000)
  1504. return -EINVAL;
  1505. /* initialize the SP_IO_WRITE SCB with the data. */
  1506. temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
  1507. snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
  1508. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
  1509. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
  1510. /* Poke this location to tell the task to start */
  1511. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
  1512. /* Verify that the task ran */
  1513. for (i=0; i<25; i++) {
  1514. udelay(125);
  1515. temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
  1516. if (temp == 0x00000000)
  1517. break;
  1518. }
  1519. if (i == 25) {
  1520. snd_printk(KERN_ERR "dsp_spos: SPIOWriteTask not responding\n");
  1521. return -EBUSY;
  1522. }
  1523. return 0;
  1524. }
  1525. int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1526. {
  1527. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1528. struct dsp_scb_descriptor * scb;
  1529. mutex_lock(&chip->spos_mutex);
  1530. /* main output */
  1531. scb = ins->master_mix_scb->sub_list_ptr;
  1532. while (scb != ins->the_null_scb) {
  1533. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1534. scb = scb->next_scb_ptr;
  1535. }
  1536. /* rear output */
  1537. scb = ins->rear_mix_scb->sub_list_ptr;
  1538. while (scb != ins->the_null_scb) {
  1539. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1540. scb = scb->next_scb_ptr;
  1541. }
  1542. ins->dac_volume_left = left;
  1543. ins->dac_volume_right = right;
  1544. mutex_unlock(&chip->spos_mutex);
  1545. return 0;
  1546. }
  1547. int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1548. {
  1549. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1550. mutex_lock(&chip->spos_mutex);
  1551. if (ins->asynch_rx_scb != NULL)
  1552. cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
  1553. left,right);
  1554. ins->spdif_input_volume_left = left;
  1555. ins->spdif_input_volume_right = right;
  1556. mutex_unlock(&chip->spos_mutex);
  1557. return 0;
  1558. }
  1559. #ifdef CONFIG_PM
  1560. int cs46xx_dsp_resume(struct snd_cs46xx * chip)
  1561. {
  1562. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1563. int i, err;
  1564. /* clear parameter, sample and code areas */
  1565. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET,
  1566. DSP_PARAMETER_BYTE_SIZE);
  1567. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET,
  1568. DSP_SAMPLE_BYTE_SIZE);
  1569. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  1570. for (i = 0; i < ins->nmodules; i++) {
  1571. struct dsp_module_desc *module = &ins->modules[i];
  1572. struct dsp_segment_desc *seg;
  1573. u32 doffset, dsize;
  1574. seg = get_segment_desc(module, SEGTYPE_SP_PARAMETER);
  1575. err = dsp_load_parameter(chip, seg);
  1576. if (err < 0)
  1577. return err;
  1578. seg = get_segment_desc(module, SEGTYPE_SP_SAMPLE);
  1579. err = dsp_load_sample(chip, seg);
  1580. if (err < 0)
  1581. return err;
  1582. seg = get_segment_desc(module, SEGTYPE_SP_PROGRAM);
  1583. if (!seg)
  1584. continue;
  1585. doffset = seg->offset * 4 + module->load_address * 4
  1586. + DSP_CODE_BYTE_OFFSET;
  1587. dsize = seg->size * 4;
  1588. err = snd_cs46xx_download(chip,
  1589. ins->code.data + module->load_address,
  1590. doffset, dsize);
  1591. if (err < 0)
  1592. return err;
  1593. }
  1594. for (i = 0; i < ins->ntask; i++) {
  1595. struct dsp_task_descriptor *t = &ins->tasks[i];
  1596. _dsp_create_task_tree(chip, t->data, t->address, t->size);
  1597. }
  1598. for (i = 0; i < ins->nscb; i++) {
  1599. struct dsp_scb_descriptor *s = &ins->scbs[i];
  1600. if (s->deleted)
  1601. continue;
  1602. _dsp_create_scb(chip, s->data, s->address);
  1603. }
  1604. return 0;
  1605. }
  1606. #endif