smp.h 2.7 KB

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  1. /*
  2. * include/asm-s390/smp.h
  3. *
  4. * S390 version
  5. * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
  6. * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
  7. * Martin Schwidefsky (schwidefsky@de.ibm.com)
  8. * Heiko Carstens (heiko.carstens@de.ibm.com)
  9. */
  10. #ifndef __ASM_SMP_H
  11. #define __ASM_SMP_H
  12. #include <linux/threads.h>
  13. #include <linux/cpumask.h>
  14. #include <linux/bitops.h>
  15. #if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
  16. #include <asm/lowcore.h>
  17. #include <asm/sigp.h>
  18. #include <asm/ptrace.h>
  19. /*
  20. s390 specific smp.c headers
  21. */
  22. typedef struct
  23. {
  24. int intresting;
  25. sigp_ccode ccode;
  26. __u32 status;
  27. __u16 cpu;
  28. } sigp_info;
  29. extern void machine_restart_smp(char *);
  30. extern void machine_halt_smp(void);
  31. extern void machine_power_off_smp(void);
  32. #define NO_PROC_ID 0xFF /* No processor magic marker */
  33. /*
  34. * This magic constant controls our willingness to transfer
  35. * a process across CPUs. Such a transfer incurs misses on the L1
  36. * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
  37. * gut feeling is this will vary by board in value. For a board
  38. * with separate L2 cache it probably depends also on the RSS, and
  39. * for a board with shared L2 cache it ought to decay fast as other
  40. * processes are run.
  41. */
  42. #define PROC_CHANGE_PENALTY 20 /* Schedule penalty */
  43. #define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
  44. static inline __u16 hard_smp_processor_id(void)
  45. {
  46. __u16 cpu_address;
  47. asm volatile("stap %0" : "=m" (cpu_address));
  48. return cpu_address;
  49. }
  50. /*
  51. * returns 1 if cpu is in stopped/check stopped state or not operational
  52. * returns 0 otherwise
  53. */
  54. static inline int
  55. smp_cpu_not_running(int cpu)
  56. {
  57. __u32 status;
  58. switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
  59. case sigp_order_code_accepted:
  60. case sigp_status_stored:
  61. /* Check for stopped and check stop state */
  62. if (status & 0x50)
  63. return 1;
  64. break;
  65. case sigp_not_operational:
  66. return 1;
  67. default:
  68. break;
  69. }
  70. return 0;
  71. }
  72. #define cpu_logical_map(cpu) (cpu)
  73. extern int __cpu_disable (void);
  74. extern void __cpu_die (unsigned int cpu);
  75. extern void cpu_die (void) __attribute__ ((noreturn));
  76. extern int __cpu_up (unsigned int cpu);
  77. extern struct mutex smp_cpu_state_mutex;
  78. extern int smp_cpu_polarization[];
  79. extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
  80. void *info, int wait);
  81. #endif
  82. #ifndef CONFIG_SMP
  83. static inline void smp_send_stop(void)
  84. {
  85. /* Disable all interrupts/machine checks */
  86. __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
  87. }
  88. #define hard_smp_processor_id() 0
  89. #define smp_cpu_not_running(cpu) 1
  90. #endif
  91. extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
  92. #endif