iTCO_wdt.c 24 KB

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  1. /*
  2. * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
  3. *
  4. * (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  12. * provide warranty for any of this software. This material is
  13. * provided "AS-IS" and at no charge.
  14. *
  15. * The TCO watchdog is implemented in the following I/O controller hubs:
  16. * (See the intel documentation on http://developer.intel.com.)
  17. * 82801AA (ICH) : document number 290655-003, 290677-014,
  18. * 82801AB (ICHO) : document number 290655-003, 290677-014,
  19. * 82801BA (ICH2) : document number 290687-002, 298242-027,
  20. * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
  21. * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
  22. * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
  23. * 82801DB (ICH4) : document number 290744-001, 290745-020,
  24. * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
  25. * 82801E (C-ICH) : document number 273599-001, 273645-002,
  26. * 82801EB (ICH5) : document number 252516-001, 252517-003,
  27. * 82801ER (ICH5R) : document number 252516-001, 252517-003,
  28. * 82801FB (ICH6) : document number 301473-002, 301474-007,
  29. * 82801FR (ICH6R) : document number 301473-002, 301474-007,
  30. * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
  31. * 82801FW (ICH6W) : document number 301473-001, 301474-007,
  32. * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
  33. * 82801GB (ICH7) : document number 307013-002, 307014-009,
  34. * 82801GR (ICH7R) : document number 307013-002, 307014-009,
  35. * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
  36. * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
  37. * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
  38. * 82801HB (ICH8) : document number 313056-003, 313057-009,
  39. * 82801HR (ICH8R) : document number 313056-003, 313057-009,
  40. * 82801HBM (ICH8M) : document number 313056-003, 313057-009,
  41. * 82801HH (ICH8DH) : document number 313056-003, 313057-009,
  42. * 82801HO (ICH8DO) : document number 313056-003, 313057-009,
  43. * 82801HEM (ICH8M-E) : document number 313056-003, 313057-009,
  44. * 82801IB (ICH9) : document number 316972-001, 316973-001,
  45. * 82801IR (ICH9R) : document number 316972-001, 316973-001,
  46. * 82801IH (ICH9DH) : document number 316972-001, 316973-001,
  47. * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
  48. * 631xESB (631xESB) : document number 313082-001, 313075-005,
  49. * 632xESB (632xESB) : document number 313082-001, 313075-005
  50. */
  51. /*
  52. * Includes, defines, variables, module parameters, ...
  53. */
  54. /* Module and version information */
  55. #define DRV_NAME "iTCO_wdt"
  56. #define DRV_VERSION "1.02"
  57. #define DRV_RELDATE "26-Jul-2007"
  58. #define PFX DRV_NAME ": "
  59. /* Includes */
  60. #include <linux/module.h> /* For module specific items */
  61. #include <linux/moduleparam.h> /* For new moduleparam's */
  62. #include <linux/types.h> /* For standard types (like size_t) */
  63. #include <linux/errno.h> /* For the -ENODEV/... values */
  64. #include <linux/kernel.h> /* For printk/panic/... */
  65. #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */
  66. #include <linux/watchdog.h> /* For the watchdog specific items */
  67. #include <linux/init.h> /* For __init/__exit/... */
  68. #include <linux/fs.h> /* For file operations */
  69. #include <linux/platform_device.h> /* For platform_driver framework */
  70. #include <linux/pci.h> /* For pci functions */
  71. #include <linux/ioport.h> /* For io-port access */
  72. #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
  73. #include <asm/uaccess.h> /* For copy_to_user/put_user/... */
  74. #include <asm/io.h> /* For inb/outb/... */
  75. /* TCO related info */
  76. enum iTCO_chipsets {
  77. TCO_ICH = 0, /* ICH */
  78. TCO_ICH0, /* ICH0 */
  79. TCO_ICH2, /* ICH2 */
  80. TCO_ICH2M, /* ICH2-M */
  81. TCO_ICH3, /* ICH3-S */
  82. TCO_ICH3M, /* ICH3-M */
  83. TCO_ICH4, /* ICH4 */
  84. TCO_ICH4M, /* ICH4-M */
  85. TCO_CICH, /* C-ICH */
  86. TCO_ICH5, /* ICH5 & ICH5R */
  87. TCO_6300ESB, /* 6300ESB */
  88. TCO_ICH6, /* ICH6 & ICH6R */
  89. TCO_ICH6M, /* ICH6-M */
  90. TCO_ICH6W, /* ICH6W & ICH6RW */
  91. TCO_ICH7, /* ICH7 & ICH7R */
  92. TCO_ICH7M, /* ICH7-M */
  93. TCO_ICH7MDH, /* ICH7-M DH */
  94. TCO_ICH8, /* ICH8 & ICH8R */
  95. TCO_ICH8ME, /* ICH8M-E */
  96. TCO_ICH8DH, /* ICH8DH */
  97. TCO_ICH8DO, /* ICH8DO */
  98. TCO_ICH8M, /* ICH8M */
  99. TCO_ICH9, /* ICH9 */
  100. TCO_ICH9R, /* ICH9R */
  101. TCO_ICH9DH, /* ICH9DH */
  102. TCO_631XESB, /* 631xESB/632xESB */
  103. };
  104. static struct {
  105. char *name;
  106. unsigned int iTCO_version;
  107. } iTCO_chipset_info[] __devinitdata = {
  108. {"ICH", 1},
  109. {"ICH0", 1},
  110. {"ICH2", 1},
  111. {"ICH2-M", 1},
  112. {"ICH3-S", 1},
  113. {"ICH3-M", 1},
  114. {"ICH4", 1},
  115. {"ICH4-M", 1},
  116. {"C-ICH", 1},
  117. {"ICH5 or ICH5R", 1},
  118. {"6300ESB", 1},
  119. {"ICH6 or ICH6R", 2},
  120. {"ICH6-M", 2},
  121. {"ICH6W or ICH6RW", 2},
  122. {"ICH7 or ICH7R", 2},
  123. {"ICH7-M", 2},
  124. {"ICH7-M DH", 2},
  125. {"ICH8 or ICH8R", 2},
  126. {"ICH8M-E", 2},
  127. {"ICH8DH", 2},
  128. {"ICH8DO", 2},
  129. {"ICH8M", 2},
  130. {"ICH9", 2},
  131. {"ICH9R", 2},
  132. {"ICH9DH", 2},
  133. {"631xESB/632xESB", 2},
  134. {NULL,0}
  135. };
  136. #define ITCO_PCI_DEVICE(dev, data) \
  137. .vendor = PCI_VENDOR_ID_INTEL, \
  138. .device = dev, \
  139. .subvendor = PCI_ANY_ID, \
  140. .subdevice = PCI_ANY_ID, \
  141. .class = 0, \
  142. .class_mask = 0, \
  143. .driver_data = data
  144. /*
  145. * This data only exists for exporting the supported PCI ids
  146. * via MODULE_DEVICE_TABLE. We do not actually register a
  147. * pci_driver, because the I/O Controller Hub has also other
  148. * functions that probably will be registered by other drivers.
  149. */
  150. static struct pci_device_id iTCO_wdt_pci_tbl[] = {
  151. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH )},
  152. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0 )},
  153. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2 )},
  154. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M )},
  155. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3 )},
  156. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M )},
  157. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4 )},
  158. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M )},
  159. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH )},
  160. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5 )},
  161. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
  162. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6 )},
  163. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M )},
  164. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W )},
  165. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7 )},
  166. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M )},
  167. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
  168. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8 )},
  169. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME )},
  170. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH )},
  171. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO )},
  172. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M )},
  173. { ITCO_PCI_DEVICE(0x2918, TCO_ICH9 )},
  174. { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R )},
  175. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH )},
  176. { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
  177. { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
  178. { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
  179. { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
  180. { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
  181. { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
  182. { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
  183. { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
  184. { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
  185. { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
  186. { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
  187. { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
  188. { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
  189. { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
  190. { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
  191. { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
  192. { 0, }, /* End of list */
  193. };
  194. MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl);
  195. /* Address definitions for the TCO */
  196. #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */
  197. #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */
  198. #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */
  199. #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
  200. #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
  201. #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
  202. #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
  203. #define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
  204. #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
  205. #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
  206. #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
  207. /* internal variables */
  208. static unsigned long is_active;
  209. static char expect_release;
  210. static struct { /* this is private data for the iTCO_wdt device */
  211. unsigned int iTCO_version; /* TCO version/generation */
  212. unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
  213. unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */
  214. spinlock_t io_lock; /* the lock for io operations */
  215. struct pci_dev *pdev; /* the PCI-device */
  216. } iTCO_wdt_private;
  217. static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */
  218. /* module parameters */
  219. #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
  220. static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
  221. module_param(heartbeat, int, 0);
  222. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  223. static int nowayout = WATCHDOG_NOWAYOUT;
  224. module_param(nowayout, int, 0);
  225. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  226. /* iTCO Vendor Specific Support hooks */
  227. #ifdef CONFIG_ITCO_VENDOR_SUPPORT
  228. extern void iTCO_vendor_pre_start(unsigned long, unsigned int);
  229. extern void iTCO_vendor_pre_stop(unsigned long);
  230. extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int);
  231. extern void iTCO_vendor_pre_set_heartbeat(unsigned int);
  232. extern int iTCO_vendor_check_noreboot_on(void);
  233. #else
  234. #define iTCO_vendor_pre_start(acpibase, heartbeat) {}
  235. #define iTCO_vendor_pre_stop(acpibase) {}
  236. #define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {}
  237. #define iTCO_vendor_pre_set_heartbeat(heartbeat) {}
  238. #define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */
  239. #endif
  240. /*
  241. * Some TCO specific functions
  242. */
  243. static inline unsigned int seconds_to_ticks(int seconds)
  244. {
  245. /* the internal timer is stored as ticks which decrement
  246. * every 0.6 seconds */
  247. return (seconds * 10) / 6;
  248. }
  249. static void iTCO_wdt_set_NO_REBOOT_bit(void)
  250. {
  251. u32 val32;
  252. /* Set the NO_REBOOT bit: this disables reboots */
  253. if (iTCO_wdt_private.iTCO_version == 2) {
  254. val32 = readl(iTCO_wdt_private.gcs);
  255. val32 |= 0x00000020;
  256. writel(val32, iTCO_wdt_private.gcs);
  257. } else if (iTCO_wdt_private.iTCO_version == 1) {
  258. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  259. val32 |= 0x00000002;
  260. pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
  261. }
  262. }
  263. static int iTCO_wdt_unset_NO_REBOOT_bit(void)
  264. {
  265. int ret = 0;
  266. u32 val32;
  267. /* Unset the NO_REBOOT bit: this enables reboots */
  268. if (iTCO_wdt_private.iTCO_version == 2) {
  269. val32 = readl(iTCO_wdt_private.gcs);
  270. val32 &= 0xffffffdf;
  271. writel(val32, iTCO_wdt_private.gcs);
  272. val32 = readl(iTCO_wdt_private.gcs);
  273. if (val32 & 0x00000020)
  274. ret = -EIO;
  275. } else if (iTCO_wdt_private.iTCO_version == 1) {
  276. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  277. val32 &= 0xfffffffd;
  278. pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
  279. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  280. if (val32 & 0x00000002)
  281. ret = -EIO;
  282. }
  283. return ret; /* returns: 0 = OK, -EIO = Error */
  284. }
  285. static int iTCO_wdt_start(void)
  286. {
  287. unsigned int val;
  288. spin_lock(&iTCO_wdt_private.io_lock);
  289. iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
  290. /* disable chipset's NO_REBOOT bit */
  291. if (iTCO_wdt_unset_NO_REBOOT_bit()) {
  292. spin_unlock(&iTCO_wdt_private.io_lock);
  293. printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
  294. return -EIO;
  295. }
  296. /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
  297. val = inw(TCO1_CNT);
  298. val &= 0xf7ff;
  299. outw(val, TCO1_CNT);
  300. val = inw(TCO1_CNT);
  301. spin_unlock(&iTCO_wdt_private.io_lock);
  302. if (val & 0x0800)
  303. return -1;
  304. return 0;
  305. }
  306. static int iTCO_wdt_stop(void)
  307. {
  308. unsigned int val;
  309. spin_lock(&iTCO_wdt_private.io_lock);
  310. iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
  311. /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
  312. val = inw(TCO1_CNT);
  313. val |= 0x0800;
  314. outw(val, TCO1_CNT);
  315. val = inw(TCO1_CNT);
  316. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  317. iTCO_wdt_set_NO_REBOOT_bit();
  318. spin_unlock(&iTCO_wdt_private.io_lock);
  319. if ((val & 0x0800) == 0)
  320. return -1;
  321. return 0;
  322. }
  323. static int iTCO_wdt_keepalive(void)
  324. {
  325. spin_lock(&iTCO_wdt_private.io_lock);
  326. iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
  327. /* Reload the timer by writing to the TCO Timer Counter register */
  328. if (iTCO_wdt_private.iTCO_version == 2) {
  329. outw(0x01, TCO_RLD);
  330. } else if (iTCO_wdt_private.iTCO_version == 1) {
  331. outb(0x01, TCO_RLD);
  332. }
  333. spin_unlock(&iTCO_wdt_private.io_lock);
  334. return 0;
  335. }
  336. static int iTCO_wdt_set_heartbeat(int t)
  337. {
  338. unsigned int val16;
  339. unsigned char val8;
  340. unsigned int tmrval;
  341. tmrval = seconds_to_ticks(t);
  342. /* from the specs: */
  343. /* "Values of 0h-3h are ignored and should not be attempted" */
  344. if (tmrval < 0x04)
  345. return -EINVAL;
  346. if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
  347. ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
  348. return -EINVAL;
  349. iTCO_vendor_pre_set_heartbeat(tmrval);
  350. /* Write new heartbeat to watchdog */
  351. if (iTCO_wdt_private.iTCO_version == 2) {
  352. spin_lock(&iTCO_wdt_private.io_lock);
  353. val16 = inw(TCOv2_TMR);
  354. val16 &= 0xfc00;
  355. val16 |= tmrval;
  356. outw(val16, TCOv2_TMR);
  357. val16 = inw(TCOv2_TMR);
  358. spin_unlock(&iTCO_wdt_private.io_lock);
  359. if ((val16 & 0x3ff) != tmrval)
  360. return -EINVAL;
  361. } else if (iTCO_wdt_private.iTCO_version == 1) {
  362. spin_lock(&iTCO_wdt_private.io_lock);
  363. val8 = inb(TCOv1_TMR);
  364. val8 &= 0xc0;
  365. val8 |= (tmrval & 0xff);
  366. outb(val8, TCOv1_TMR);
  367. val8 = inb(TCOv1_TMR);
  368. spin_unlock(&iTCO_wdt_private.io_lock);
  369. if ((val8 & 0x3f) != tmrval)
  370. return -EINVAL;
  371. }
  372. heartbeat = t;
  373. return 0;
  374. }
  375. static int iTCO_wdt_get_timeleft (int *time_left)
  376. {
  377. unsigned int val16;
  378. unsigned char val8;
  379. /* read the TCO Timer */
  380. if (iTCO_wdt_private.iTCO_version == 2) {
  381. spin_lock(&iTCO_wdt_private.io_lock);
  382. val16 = inw(TCO_RLD);
  383. val16 &= 0x3ff;
  384. spin_unlock(&iTCO_wdt_private.io_lock);
  385. *time_left = (val16 * 6) / 10;
  386. } else if (iTCO_wdt_private.iTCO_version == 1) {
  387. spin_lock(&iTCO_wdt_private.io_lock);
  388. val8 = inb(TCO_RLD);
  389. val8 &= 0x3f;
  390. spin_unlock(&iTCO_wdt_private.io_lock);
  391. *time_left = (val8 * 6) / 10;
  392. } else
  393. return -EINVAL;
  394. return 0;
  395. }
  396. /*
  397. * /dev/watchdog handling
  398. */
  399. static int iTCO_wdt_open (struct inode *inode, struct file *file)
  400. {
  401. /* /dev/watchdog can only be opened once */
  402. if (test_and_set_bit(0, &is_active))
  403. return -EBUSY;
  404. /*
  405. * Reload and activate timer
  406. */
  407. iTCO_wdt_keepalive();
  408. iTCO_wdt_start();
  409. return nonseekable_open(inode, file);
  410. }
  411. static int iTCO_wdt_release (struct inode *inode, struct file *file)
  412. {
  413. /*
  414. * Shut off the timer.
  415. */
  416. if (expect_release == 42) {
  417. iTCO_wdt_stop();
  418. } else {
  419. printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
  420. iTCO_wdt_keepalive();
  421. }
  422. clear_bit(0, &is_active);
  423. expect_release = 0;
  424. return 0;
  425. }
  426. static ssize_t iTCO_wdt_write (struct file *file, const char __user *data,
  427. size_t len, loff_t * ppos)
  428. {
  429. /* See if we got the magic character 'V' and reload the timer */
  430. if (len) {
  431. if (!nowayout) {
  432. size_t i;
  433. /* note: just in case someone wrote the magic character
  434. * five months ago... */
  435. expect_release = 0;
  436. /* scan to see whether or not we got the magic character */
  437. for (i = 0; i != len; i++) {
  438. char c;
  439. if (get_user(c, data+i))
  440. return -EFAULT;
  441. if (c == 'V')
  442. expect_release = 42;
  443. }
  444. }
  445. /* someone wrote to us, we should reload the timer */
  446. iTCO_wdt_keepalive();
  447. }
  448. return len;
  449. }
  450. static int iTCO_wdt_ioctl (struct inode *inode, struct file *file,
  451. unsigned int cmd, unsigned long arg)
  452. {
  453. int new_options, retval = -EINVAL;
  454. int new_heartbeat;
  455. void __user *argp = (void __user *)arg;
  456. int __user *p = argp;
  457. static struct watchdog_info ident = {
  458. .options = WDIOF_SETTIMEOUT |
  459. WDIOF_KEEPALIVEPING |
  460. WDIOF_MAGICCLOSE,
  461. .firmware_version = 0,
  462. .identity = DRV_NAME,
  463. };
  464. switch (cmd) {
  465. case WDIOC_GETSUPPORT:
  466. return copy_to_user(argp, &ident,
  467. sizeof (ident)) ? -EFAULT : 0;
  468. case WDIOC_GETSTATUS:
  469. case WDIOC_GETBOOTSTATUS:
  470. return put_user(0, p);
  471. case WDIOC_KEEPALIVE:
  472. iTCO_wdt_keepalive();
  473. return 0;
  474. case WDIOC_SETOPTIONS:
  475. {
  476. if (get_user(new_options, p))
  477. return -EFAULT;
  478. if (new_options & WDIOS_DISABLECARD) {
  479. iTCO_wdt_stop();
  480. retval = 0;
  481. }
  482. if (new_options & WDIOS_ENABLECARD) {
  483. iTCO_wdt_keepalive();
  484. iTCO_wdt_start();
  485. retval = 0;
  486. }
  487. return retval;
  488. }
  489. case WDIOC_SETTIMEOUT:
  490. {
  491. if (get_user(new_heartbeat, p))
  492. return -EFAULT;
  493. if (iTCO_wdt_set_heartbeat(new_heartbeat))
  494. return -EINVAL;
  495. iTCO_wdt_keepalive();
  496. /* Fall */
  497. }
  498. case WDIOC_GETTIMEOUT:
  499. return put_user(heartbeat, p);
  500. case WDIOC_GETTIMELEFT:
  501. {
  502. int time_left;
  503. if (iTCO_wdt_get_timeleft(&time_left))
  504. return -EINVAL;
  505. return put_user(time_left, p);
  506. }
  507. default:
  508. return -ENOTTY;
  509. }
  510. }
  511. /*
  512. * Kernel Interfaces
  513. */
  514. static const struct file_operations iTCO_wdt_fops = {
  515. .owner = THIS_MODULE,
  516. .llseek = no_llseek,
  517. .write = iTCO_wdt_write,
  518. .ioctl = iTCO_wdt_ioctl,
  519. .open = iTCO_wdt_open,
  520. .release = iTCO_wdt_release,
  521. };
  522. static struct miscdevice iTCO_wdt_miscdev = {
  523. .minor = WATCHDOG_MINOR,
  524. .name = "watchdog",
  525. .fops = &iTCO_wdt_fops,
  526. };
  527. /*
  528. * Init & exit routines
  529. */
  530. static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev)
  531. {
  532. int ret;
  533. u32 base_address;
  534. unsigned long RCBA;
  535. unsigned long val32;
  536. /*
  537. * Find the ACPI/PM base I/O address which is the base
  538. * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
  539. * ACPIBASE is bits [15:7] from 0x40-0x43
  540. */
  541. pci_read_config_dword(pdev, 0x40, &base_address);
  542. base_address &= 0x0000ff80;
  543. if (base_address == 0x00000000) {
  544. /* Something's wrong here, ACPIBASE has to be set */
  545. printk(KERN_ERR PFX "failed to get TCOBASE address\n");
  546. pci_dev_put(pdev);
  547. return -ENODEV;
  548. }
  549. iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version;
  550. iTCO_wdt_private.ACPIBASE = base_address;
  551. iTCO_wdt_private.pdev = pdev;
  552. /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */
  553. /* To get access to it you have to read RCBA from PCI Config space 0xf0
  554. and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */
  555. if (iTCO_wdt_private.iTCO_version == 2) {
  556. pci_read_config_dword(pdev, 0xf0, &base_address);
  557. RCBA = base_address & 0xffffc000;
  558. iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4);
  559. }
  560. /* Check chipset's NO_REBOOT bit */
  561. if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
  562. printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
  563. ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
  564. goto out;
  565. }
  566. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  567. iTCO_wdt_set_NO_REBOOT_bit();
  568. /* Set the TCO_EN bit in SMI_EN register */
  569. if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
  570. printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
  571. SMI_EN );
  572. ret = -EIO;
  573. goto out;
  574. }
  575. val32 = inl(SMI_EN);
  576. val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
  577. outl(val32, SMI_EN);
  578. release_region(SMI_EN, 4);
  579. /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */
  580. if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) {
  581. printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n",
  582. TCOBASE);
  583. ret = -EIO;
  584. goto out;
  585. }
  586. printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
  587. iTCO_chipset_info[ent->driver_data].name,
  588. iTCO_chipset_info[ent->driver_data].iTCO_version,
  589. TCOBASE);
  590. /* Clear out the (probably old) status */
  591. outb(0, TCO1_STS);
  592. outb(3, TCO2_STS);
  593. /* Make sure the watchdog is not running */
  594. iTCO_wdt_stop();
  595. /* Check that the heartbeat value is within it's range ; if not reset to the default */
  596. if (iTCO_wdt_set_heartbeat(heartbeat)) {
  597. iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
  598. printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n",
  599. heartbeat);
  600. }
  601. ret = misc_register(&iTCO_wdt_miscdev);
  602. if (ret != 0) {
  603. printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
  604. WATCHDOG_MINOR, ret);
  605. goto unreg_region;
  606. }
  607. printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
  608. heartbeat, nowayout);
  609. return 0;
  610. unreg_region:
  611. release_region (TCOBASE, 0x20);
  612. out:
  613. if (iTCO_wdt_private.iTCO_version == 2)
  614. iounmap(iTCO_wdt_private.gcs);
  615. pci_dev_put(iTCO_wdt_private.pdev);
  616. iTCO_wdt_private.ACPIBASE = 0;
  617. return ret;
  618. }
  619. static void __devexit iTCO_wdt_cleanup(void)
  620. {
  621. /* Stop the timer before we leave */
  622. if (!nowayout)
  623. iTCO_wdt_stop();
  624. /* Deregister */
  625. misc_deregister(&iTCO_wdt_miscdev);
  626. release_region(TCOBASE, 0x20);
  627. if (iTCO_wdt_private.iTCO_version == 2)
  628. iounmap(iTCO_wdt_private.gcs);
  629. pci_dev_put(iTCO_wdt_private.pdev);
  630. iTCO_wdt_private.ACPIBASE = 0;
  631. }
  632. static int __devinit iTCO_wdt_probe(struct platform_device *dev)
  633. {
  634. int found = 0;
  635. struct pci_dev *pdev = NULL;
  636. const struct pci_device_id *ent;
  637. spin_lock_init(&iTCO_wdt_private.io_lock);
  638. for_each_pci_dev(pdev) {
  639. ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
  640. if (ent) {
  641. if (!(iTCO_wdt_init(pdev, ent, dev))) {
  642. found++;
  643. break;
  644. }
  645. }
  646. }
  647. if (!found) {
  648. printk(KERN_INFO PFX "No card detected\n");
  649. return -ENODEV;
  650. }
  651. return 0;
  652. }
  653. static int __devexit iTCO_wdt_remove(struct platform_device *dev)
  654. {
  655. if (iTCO_wdt_private.ACPIBASE)
  656. iTCO_wdt_cleanup();
  657. return 0;
  658. }
  659. static void iTCO_wdt_shutdown(struct platform_device *dev)
  660. {
  661. iTCO_wdt_stop();
  662. }
  663. #define iTCO_wdt_suspend NULL
  664. #define iTCO_wdt_resume NULL
  665. static struct platform_driver iTCO_wdt_driver = {
  666. .probe = iTCO_wdt_probe,
  667. .remove = __devexit_p(iTCO_wdt_remove),
  668. .shutdown = iTCO_wdt_shutdown,
  669. .suspend = iTCO_wdt_suspend,
  670. .resume = iTCO_wdt_resume,
  671. .driver = {
  672. .owner = THIS_MODULE,
  673. .name = DRV_NAME,
  674. },
  675. };
  676. static int __init iTCO_wdt_init_module(void)
  677. {
  678. int err;
  679. printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n",
  680. DRV_VERSION, DRV_RELDATE);
  681. err = platform_driver_register(&iTCO_wdt_driver);
  682. if (err)
  683. return err;
  684. iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0);
  685. if (IS_ERR(iTCO_wdt_platform_device)) {
  686. err = PTR_ERR(iTCO_wdt_platform_device);
  687. goto unreg_platform_driver;
  688. }
  689. return 0;
  690. unreg_platform_driver:
  691. platform_driver_unregister(&iTCO_wdt_driver);
  692. return err;
  693. }
  694. static void __exit iTCO_wdt_cleanup_module(void)
  695. {
  696. platform_device_unregister(iTCO_wdt_platform_device);
  697. platform_driver_unregister(&iTCO_wdt_driver);
  698. printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
  699. }
  700. module_init(iTCO_wdt_init_module);
  701. module_exit(iTCO_wdt_cleanup_module);
  702. MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
  703. MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
  704. MODULE_VERSION(DRV_VERSION);
  705. MODULE_LICENSE("GPL");
  706. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);