cg14.c 15 KB

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  1. /* cg14.c: CGFOURTEEN frame buffer driver
  2. *
  3. * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
  4. * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
  5. * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
  6. *
  7. * Driver layout based loosely on tgafb.c, see that file for credits.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/errno.h>
  12. #include <linux/string.h>
  13. #include <linux/slab.h>
  14. #include <linux/delay.h>
  15. #include <linux/init.h>
  16. #include <linux/fb.h>
  17. #include <linux/mm.h>
  18. #include <linux/uaccess.h>
  19. #include <asm/io.h>
  20. #include <asm/prom.h>
  21. #include <asm/of_device.h>
  22. #include <asm/fbio.h>
  23. #include "sbuslib.h"
  24. /*
  25. * Local functions.
  26. */
  27. static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
  28. unsigned, struct fb_info *);
  29. static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
  30. static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
  31. static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);
  32. /*
  33. * Frame buffer operations
  34. */
  35. static struct fb_ops cg14_ops = {
  36. .owner = THIS_MODULE,
  37. .fb_setcolreg = cg14_setcolreg,
  38. .fb_pan_display = cg14_pan_display,
  39. .fb_fillrect = cfb_fillrect,
  40. .fb_copyarea = cfb_copyarea,
  41. .fb_imageblit = cfb_imageblit,
  42. .fb_mmap = cg14_mmap,
  43. .fb_ioctl = cg14_ioctl,
  44. #ifdef CONFIG_COMPAT
  45. .fb_compat_ioctl = sbusfb_compat_ioctl,
  46. #endif
  47. };
  48. #define CG14_MCR_INTENABLE_SHIFT 7
  49. #define CG14_MCR_INTENABLE_MASK 0x80
  50. #define CG14_MCR_VIDENABLE_SHIFT 6
  51. #define CG14_MCR_VIDENABLE_MASK 0x40
  52. #define CG14_MCR_PIXMODE_SHIFT 4
  53. #define CG14_MCR_PIXMODE_MASK 0x30
  54. #define CG14_MCR_TMR_SHIFT 2
  55. #define CG14_MCR_TMR_MASK 0x0c
  56. #define CG14_MCR_TMENABLE_SHIFT 1
  57. #define CG14_MCR_TMENABLE_MASK 0x02
  58. #define CG14_MCR_RESET_SHIFT 0
  59. #define CG14_MCR_RESET_MASK 0x01
  60. #define CG14_REV_REVISION_SHIFT 4
  61. #define CG14_REV_REVISION_MASK 0xf0
  62. #define CG14_REV_IMPL_SHIFT 0
  63. #define CG14_REV_IMPL_MASK 0x0f
  64. #define CG14_VBR_FRAMEBASE_SHIFT 12
  65. #define CG14_VBR_FRAMEBASE_MASK 0x00fff000
  66. #define CG14_VMCR1_SETUP_SHIFT 0
  67. #define CG14_VMCR1_SETUP_MASK 0x000001ff
  68. #define CG14_VMCR1_VCONFIG_SHIFT 9
  69. #define CG14_VMCR1_VCONFIG_MASK 0x00000e00
  70. #define CG14_VMCR2_REFRESH_SHIFT 0
  71. #define CG14_VMCR2_REFRESH_MASK 0x00000001
  72. #define CG14_VMCR2_TESTROWCNT_SHIFT 1
  73. #define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
  74. #define CG14_VMCR2_FBCONFIG_SHIFT 2
  75. #define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
  76. #define CG14_VCR_REFRESHREQ_SHIFT 0
  77. #define CG14_VCR_REFRESHREQ_MASK 0x000003ff
  78. #define CG14_VCR1_REFRESHENA_SHIFT 10
  79. #define CG14_VCR1_REFRESHENA_MASK 0x00000400
  80. #define CG14_VCA_CAD_SHIFT 0
  81. #define CG14_VCA_CAD_MASK 0x000003ff
  82. #define CG14_VCA_VERS_SHIFT 10
  83. #define CG14_VCA_VERS_MASK 0x00000c00
  84. #define CG14_VCA_RAMSPEED_SHIFT 12
  85. #define CG14_VCA_RAMSPEED_MASK 0x00001000
  86. #define CG14_VCA_8MB_SHIFT 13
  87. #define CG14_VCA_8MB_MASK 0x00002000
  88. #define CG14_MCR_PIXMODE_8 0
  89. #define CG14_MCR_PIXMODE_16 2
  90. #define CG14_MCR_PIXMODE_32 3
  91. struct cg14_regs{
  92. u8 mcr; /* Master Control Reg */
  93. u8 ppr; /* Packed Pixel Reg */
  94. u8 tms[2]; /* Test Mode Status Regs */
  95. u8 msr; /* Master Status Reg */
  96. u8 fsr; /* Fault Status Reg */
  97. u8 rev; /* Revision & Impl */
  98. u8 ccr; /* Clock Control Reg */
  99. u32 tmr; /* Test Mode Read Back */
  100. u8 mod; /* Monitor Operation Data Reg */
  101. u8 acr; /* Aux Control */
  102. u8 xxx0[6];
  103. u16 hct; /* Hor Counter */
  104. u16 vct; /* Vert Counter */
  105. u16 hbs; /* Hor Blank Start */
  106. u16 hbc; /* Hor Blank Clear */
  107. u16 hss; /* Hor Sync Start */
  108. u16 hsc; /* Hor Sync Clear */
  109. u16 csc; /* Composite Sync Clear */
  110. u16 vbs; /* Vert Blank Start */
  111. u16 vbc; /* Vert Blank Clear */
  112. u16 vss; /* Vert Sync Start */
  113. u16 vsc; /* Vert Sync Clear */
  114. u16 xcs;
  115. u16 xcc;
  116. u16 fsa; /* Fault Status Address */
  117. u16 adr; /* Address Registers */
  118. u8 xxx1[0xce];
  119. u8 pcg[0x100]; /* Pixel Clock Generator */
  120. u32 vbr; /* Frame Base Row */
  121. u32 vmcr; /* VBC Master Control */
  122. u32 vcr; /* VBC refresh */
  123. u32 vca; /* VBC Config */
  124. };
  125. #define CG14_CCR_ENABLE 0x04
  126. #define CG14_CCR_SELECT 0x02 /* HW/Full screen */
  127. struct cg14_cursor {
  128. u32 cpl0[32]; /* Enable plane 0 */
  129. u32 cpl1[32]; /* Color selection plane */
  130. u8 ccr; /* Cursor Control Reg */
  131. u8 xxx0[3];
  132. u16 cursx; /* Cursor x,y position */
  133. u16 cursy; /* Cursor x,y position */
  134. u32 color0;
  135. u32 color1;
  136. u32 xxx1[0x1bc];
  137. u32 cpl0i[32]; /* Enable plane 0 autoinc */
  138. u32 cpl1i[32]; /* Color selection autoinc */
  139. };
  140. struct cg14_dac {
  141. u8 addr; /* Address Register */
  142. u8 xxx0[255];
  143. u8 glut; /* Gamma table */
  144. u8 xxx1[255];
  145. u8 select; /* Register Select */
  146. u8 xxx2[255];
  147. u8 mode; /* Mode Register */
  148. };
  149. struct cg14_xlut{
  150. u8 x_xlut [256];
  151. u8 x_xlutd [256];
  152. u8 xxx0[0x600];
  153. u8 x_xlut_inc [256];
  154. u8 x_xlutd_inc [256];
  155. };
  156. /* Color look up table (clut) */
  157. /* Each one of these arrays hold the color lookup table (for 256
  158. * colors) for each MDI page (I assume then there should be 4 MDI
  159. * pages, I still wonder what they are. I have seen NeXTStep split
  160. * the screen in four parts, while operating in 24 bits mode. Each
  161. * integer holds 4 values: alpha value (transparency channel, thanks
  162. * go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
  163. *
  164. * I currently use the clut instead of the Xlut
  165. */
  166. struct cg14_clut {
  167. u32 c_clut [256];
  168. u32 c_clutd [256]; /* i wonder what the 'd' is for */
  169. u32 c_clut_inc [256];
  170. u32 c_clutd_inc [256];
  171. };
  172. #define CG14_MMAP_ENTRIES 16
  173. struct cg14_par {
  174. spinlock_t lock;
  175. struct cg14_regs __iomem *regs;
  176. struct cg14_clut __iomem *clut;
  177. struct cg14_cursor __iomem *cursor;
  178. u32 flags;
  179. #define CG14_FLAG_BLANKED 0x00000001
  180. unsigned long physbase;
  181. unsigned long iospace;
  182. unsigned long fbsize;
  183. struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
  184. int mode;
  185. int ramsize;
  186. };
  187. static void __cg14_reset(struct cg14_par *par)
  188. {
  189. struct cg14_regs __iomem *regs = par->regs;
  190. u8 val;
  191. val = sbus_readb(&regs->mcr);
  192. val &= ~(CG14_MCR_PIXMODE_MASK);
  193. sbus_writeb(val, &regs->mcr);
  194. }
  195. static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  196. {
  197. struct cg14_par *par = (struct cg14_par *) info->par;
  198. unsigned long flags;
  199. /* We just use this to catch switches out of
  200. * graphics mode.
  201. */
  202. spin_lock_irqsave(&par->lock, flags);
  203. __cg14_reset(par);
  204. spin_unlock_irqrestore(&par->lock, flags);
  205. if (var->xoffset || var->yoffset || var->vmode)
  206. return -EINVAL;
  207. return 0;
  208. }
  209. /**
  210. * cg14_setcolreg - Optional function. Sets a color register.
  211. * @regno: boolean, 0 copy local, 1 get_user() function
  212. * @red: frame buffer colormap structure
  213. * @green: The green value which can be up to 16 bits wide
  214. * @blue: The blue value which can be up to 16 bits wide.
  215. * @transp: If supported the alpha value which can be up to 16 bits wide.
  216. * @info: frame buffer info structure
  217. */
  218. static int cg14_setcolreg(unsigned regno,
  219. unsigned red, unsigned green, unsigned blue,
  220. unsigned transp, struct fb_info *info)
  221. {
  222. struct cg14_par *par = (struct cg14_par *) info->par;
  223. struct cg14_clut __iomem *clut = par->clut;
  224. unsigned long flags;
  225. u32 val;
  226. if (regno >= 256)
  227. return 1;
  228. red >>= 8;
  229. green >>= 8;
  230. blue >>= 8;
  231. val = (red | (green << 8) | (blue << 16));
  232. spin_lock_irqsave(&par->lock, flags);
  233. sbus_writel(val, &clut->c_clut[regno]);
  234. spin_unlock_irqrestore(&par->lock, flags);
  235. return 0;
  236. }
  237. static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
  238. {
  239. struct cg14_par *par = (struct cg14_par *) info->par;
  240. return sbusfb_mmap_helper(par->mmap_map,
  241. par->physbase, par->fbsize,
  242. par->iospace, vma);
  243. }
  244. static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  245. {
  246. struct cg14_par *par = (struct cg14_par *) info->par;
  247. struct cg14_regs __iomem *regs = par->regs;
  248. struct mdi_cfginfo kmdi, __user *mdii;
  249. unsigned long flags;
  250. int cur_mode, mode, ret = 0;
  251. switch (cmd) {
  252. case MDI_RESET:
  253. spin_lock_irqsave(&par->lock, flags);
  254. __cg14_reset(par);
  255. spin_unlock_irqrestore(&par->lock, flags);
  256. break;
  257. case MDI_GET_CFGINFO:
  258. memset(&kmdi, 0, sizeof(kmdi));
  259. spin_lock_irqsave(&par->lock, flags);
  260. kmdi.mdi_type = FBTYPE_MDICOLOR;
  261. kmdi.mdi_height = info->var.yres;
  262. kmdi.mdi_width = info->var.xres;
  263. kmdi.mdi_mode = par->mode;
  264. kmdi.mdi_pixfreq = 72; /* FIXME */
  265. kmdi.mdi_size = par->ramsize;
  266. spin_unlock_irqrestore(&par->lock, flags);
  267. mdii = (struct mdi_cfginfo __user *) arg;
  268. if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
  269. ret = -EFAULT;
  270. break;
  271. case MDI_SET_PIXELMODE:
  272. if (get_user(mode, (int __user *) arg)) {
  273. ret = -EFAULT;
  274. break;
  275. }
  276. spin_lock_irqsave(&par->lock, flags);
  277. cur_mode = sbus_readb(&regs->mcr);
  278. cur_mode &= ~CG14_MCR_PIXMODE_MASK;
  279. switch(mode) {
  280. case MDI_32_PIX:
  281. cur_mode |= (CG14_MCR_PIXMODE_32 <<
  282. CG14_MCR_PIXMODE_SHIFT);
  283. break;
  284. case MDI_16_PIX:
  285. cur_mode |= (CG14_MCR_PIXMODE_16 <<
  286. CG14_MCR_PIXMODE_SHIFT);
  287. break;
  288. case MDI_8_PIX:
  289. break;
  290. default:
  291. ret = -ENOSYS;
  292. break;
  293. };
  294. if (!ret) {
  295. sbus_writeb(cur_mode, &regs->mcr);
  296. par->mode = mode;
  297. }
  298. spin_unlock_irqrestore(&par->lock, flags);
  299. break;
  300. default:
  301. ret = sbusfb_ioctl_helper(cmd, arg, info,
  302. FBTYPE_MDICOLOR, 8, par->fbsize);
  303. break;
  304. };
  305. return ret;
  306. }
  307. /*
  308. * Initialisation
  309. */
  310. static void __devinit cg14_init_fix(struct fb_info *info, int linebytes,
  311. struct device_node *dp)
  312. {
  313. const char *name = dp->name;
  314. strlcpy(info->fix.id, name, sizeof(info->fix.id));
  315. info->fix.type = FB_TYPE_PACKED_PIXELS;
  316. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  317. info->fix.line_length = linebytes;
  318. info->fix.accel = FB_ACCEL_SUN_CG14;
  319. }
  320. static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] __devinitdata = {
  321. {
  322. .voff = CG14_REGS,
  323. .poff = 0x80000000,
  324. .size = 0x1000
  325. },
  326. {
  327. .voff = CG14_XLUT,
  328. .poff = 0x80003000,
  329. .size = 0x1000
  330. },
  331. {
  332. .voff = CG14_CLUT1,
  333. .poff = 0x80004000,
  334. .size = 0x1000
  335. },
  336. {
  337. .voff = CG14_CLUT2,
  338. .poff = 0x80005000,
  339. .size = 0x1000
  340. },
  341. {
  342. .voff = CG14_CLUT3,
  343. .poff = 0x80006000,
  344. .size = 0x1000
  345. },
  346. {
  347. .voff = CG3_MMAP_OFFSET - 0x7000,
  348. .poff = 0x80000000,
  349. .size = 0x7000
  350. },
  351. {
  352. .voff = CG3_MMAP_OFFSET,
  353. .poff = 0x00000000,
  354. .size = SBUS_MMAP_FBSIZE(1)
  355. },
  356. {
  357. .voff = MDI_CURSOR_MAP,
  358. .poff = 0x80001000,
  359. .size = 0x1000
  360. },
  361. {
  362. .voff = MDI_CHUNKY_BGR_MAP,
  363. .poff = 0x01000000,
  364. .size = 0x400000
  365. },
  366. {
  367. .voff = MDI_PLANAR_X16_MAP,
  368. .poff = 0x02000000,
  369. .size = 0x200000
  370. },
  371. {
  372. .voff = MDI_PLANAR_C16_MAP,
  373. .poff = 0x02800000,
  374. .size = 0x200000
  375. },
  376. {
  377. .voff = MDI_PLANAR_X32_MAP,
  378. .poff = 0x03000000,
  379. .size = 0x100000
  380. },
  381. {
  382. .voff = MDI_PLANAR_B32_MAP,
  383. .poff = 0x03400000,
  384. .size = 0x100000
  385. },
  386. {
  387. .voff = MDI_PLANAR_G32_MAP,
  388. .poff = 0x03800000,
  389. .size = 0x100000
  390. },
  391. {
  392. .voff = MDI_PLANAR_R32_MAP,
  393. .poff = 0x03c00000,
  394. .size = 0x100000
  395. },
  396. { .size = 0 }
  397. };
  398. static void cg14_unmap_regs(struct of_device *op, struct fb_info *info,
  399. struct cg14_par *par)
  400. {
  401. if (par->regs)
  402. of_iounmap(&op->resource[0],
  403. par->regs, sizeof(struct cg14_regs));
  404. if (par->clut)
  405. of_iounmap(&op->resource[0],
  406. par->clut, sizeof(struct cg14_clut));
  407. if (par->cursor)
  408. of_iounmap(&op->resource[0],
  409. par->cursor, sizeof(struct cg14_cursor));
  410. if (info->screen_base)
  411. of_iounmap(&op->resource[1],
  412. info->screen_base, par->fbsize);
  413. }
  414. static int __devinit cg14_probe(struct of_device *op, const struct of_device_id *match)
  415. {
  416. struct device_node *dp = op->node;
  417. struct fb_info *info;
  418. struct cg14_par *par;
  419. int is_8mb, linebytes, i, err;
  420. info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);
  421. err = -ENOMEM;
  422. if (!info)
  423. goto out_err;
  424. par = info->par;
  425. spin_lock_init(&par->lock);
  426. sbusfb_fill_var(&info->var, dp->node, 8);
  427. info->var.red.length = 8;
  428. info->var.green.length = 8;
  429. info->var.blue.length = 8;
  430. linebytes = of_getintprop_default(dp, "linebytes",
  431. info->var.xres);
  432. par->fbsize = PAGE_ALIGN(linebytes * info->var.yres);
  433. if (!strcmp(dp->parent->name, "sbus") ||
  434. !strcmp(dp->parent->name, "sbi")) {
  435. par->physbase = op->resource[0].start;
  436. par->iospace = op->resource[0].flags & IORESOURCE_BITS;
  437. } else {
  438. par->physbase = op->resource[1].start;
  439. par->iospace = op->resource[0].flags & IORESOURCE_BITS;
  440. }
  441. par->regs = of_ioremap(&op->resource[0], 0,
  442. sizeof(struct cg14_regs), "cg14 regs");
  443. par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
  444. sizeof(struct cg14_clut), "cg14 clut");
  445. par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
  446. sizeof(struct cg14_cursor), "cg14 cursor");
  447. info->screen_base = of_ioremap(&op->resource[1], 0,
  448. par->fbsize, "cg14 ram");
  449. if (!par->regs || !par->clut || !par->cursor || !info->screen_base)
  450. goto out_unmap_regs;
  451. is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
  452. (8 * 1024 * 1024));
  453. BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
  454. memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));
  455. for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
  456. struct sbus_mmap_map *map = &par->mmap_map[i];
  457. if (!map->size)
  458. break;
  459. if (map->poff & 0x80000000)
  460. map->poff = (map->poff & 0x7fffffff) +
  461. (op->resource[0].start -
  462. op->resource[1].start);
  463. if (is_8mb &&
  464. map->size >= 0x100000 &&
  465. map->size <= 0x400000)
  466. map->size *= 2;
  467. }
  468. par->mode = MDI_8_PIX;
  469. par->ramsize = (is_8mb ? 0x800000 : 0x400000);
  470. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  471. info->fbops = &cg14_ops;
  472. __cg14_reset(par);
  473. if (fb_alloc_cmap(&info->cmap, 256, 0))
  474. goto out_unmap_regs;
  475. fb_set_cmap(&info->cmap, info);
  476. cg14_init_fix(info, linebytes, dp);
  477. err = register_framebuffer(info);
  478. if (err < 0)
  479. goto out_dealloc_cmap;
  480. dev_set_drvdata(&op->dev, info);
  481. printk("%s: cgfourteen at %lx:%lx, %dMB\n",
  482. dp->full_name,
  483. par->iospace, par->physbase,
  484. par->ramsize >> 20);
  485. return 0;
  486. out_dealloc_cmap:
  487. fb_dealloc_cmap(&info->cmap);
  488. out_unmap_regs:
  489. cg14_unmap_regs(op, info, par);
  490. out_err:
  491. return err;
  492. }
  493. static int __devexit cg14_remove(struct of_device *op)
  494. {
  495. struct fb_info *info = dev_get_drvdata(&op->dev);
  496. struct cg14_par *par = info->par;
  497. unregister_framebuffer(info);
  498. fb_dealloc_cmap(&info->cmap);
  499. cg14_unmap_regs(op, info, par);
  500. framebuffer_release(info);
  501. dev_set_drvdata(&op->dev, NULL);
  502. return 0;
  503. }
  504. static struct of_device_id cg14_match[] = {
  505. {
  506. .name = "cgfourteen",
  507. },
  508. {},
  509. };
  510. MODULE_DEVICE_TABLE(of, cg14_match);
  511. static struct of_platform_driver cg14_driver = {
  512. .name = "cg14",
  513. .match_table = cg14_match,
  514. .probe = cg14_probe,
  515. .remove = __devexit_p(cg14_remove),
  516. };
  517. int __init cg14_init(void)
  518. {
  519. if (fb_get_options("cg14fb", NULL))
  520. return -ENODEV;
  521. return of_register_driver(&cg14_driver, &of_bus_type);
  522. }
  523. void __exit cg14_exit(void)
  524. {
  525. of_unregister_driver(&cg14_driver);
  526. }
  527. module_init(cg14_init);
  528. module_exit(cg14_exit);
  529. MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
  530. MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
  531. MODULE_VERSION("2.0");
  532. MODULE_LICENSE("GPL");