qeth_core_main.c 122 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm-s390/ebcdic.h>
  21. #include <asm-s390/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. static DEFINE_PER_CPU(char[256], qeth_core_dbf_txt_buf);
  26. #define QETH_DBF_TXT_BUF qeth_core_dbf_txt_buf
  27. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  28. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  29. /* N P A M L V H */
  30. [QETH_DBF_SETUP] = {"qeth_setup",
  31. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_QERR] = {"qeth_qerr",
  33. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_TRACE] = {"qeth_trace",
  35. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  36. [QETH_DBF_MSG] = {"qeth_msg",
  37. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  38. [QETH_DBF_SENSE] = {"qeth_sense",
  39. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_MISC] = {"qeth_misc",
  41. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  42. [QETH_DBF_CTRL] = {"qeth_control",
  43. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  44. };
  45. EXPORT_SYMBOL_GPL(qeth_dbf);
  46. struct qeth_card_list_struct qeth_core_card_list;
  47. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  48. static struct device *qeth_core_root_dev;
  49. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  50. static struct lock_class_key qdio_out_skb_queue_key;
  51. static void qeth_send_control_data_cb(struct qeth_channel *,
  52. struct qeth_cmd_buffer *);
  53. static int qeth_issue_next_read(struct qeth_card *);
  54. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  55. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  56. static void qeth_free_buffer_pool(struct qeth_card *);
  57. static int qeth_qdio_establish(struct qeth_card *);
  58. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  59. struct qdio_buffer *buffer, int is_tso,
  60. int *next_element_to_fill)
  61. {
  62. struct skb_frag_struct *frag;
  63. int fragno;
  64. unsigned long addr;
  65. int element, cnt, dlen;
  66. fragno = skb_shinfo(skb)->nr_frags;
  67. element = *next_element_to_fill;
  68. dlen = 0;
  69. if (is_tso)
  70. buffer->element[element].flags =
  71. SBAL_FLAGS_MIDDLE_FRAG;
  72. else
  73. buffer->element[element].flags =
  74. SBAL_FLAGS_FIRST_FRAG;
  75. dlen = skb->len - skb->data_len;
  76. if (dlen) {
  77. buffer->element[element].addr = skb->data;
  78. buffer->element[element].length = dlen;
  79. element++;
  80. }
  81. for (cnt = 0; cnt < fragno; cnt++) {
  82. frag = &skb_shinfo(skb)->frags[cnt];
  83. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  84. frag->page_offset;
  85. buffer->element[element].addr = (char *)addr;
  86. buffer->element[element].length = frag->size;
  87. if (cnt < (fragno - 1))
  88. buffer->element[element].flags =
  89. SBAL_FLAGS_MIDDLE_FRAG;
  90. else
  91. buffer->element[element].flags =
  92. SBAL_FLAGS_LAST_FRAG;
  93. element++;
  94. }
  95. *next_element_to_fill = element;
  96. }
  97. static inline const char *qeth_get_cardname(struct qeth_card *card)
  98. {
  99. if (card->info.guestlan) {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSAE:
  102. return " Guest LAN QDIO";
  103. case QETH_CARD_TYPE_IQD:
  104. return " Guest LAN Hiper";
  105. default:
  106. return " unknown";
  107. }
  108. } else {
  109. switch (card->info.type) {
  110. case QETH_CARD_TYPE_OSAE:
  111. return " OSD Express";
  112. case QETH_CARD_TYPE_IQD:
  113. return " HiperSockets";
  114. case QETH_CARD_TYPE_OSN:
  115. return " OSN QDIO";
  116. default:
  117. return " unknown";
  118. }
  119. }
  120. return " n/a";
  121. }
  122. /* max length to be returned: 14 */
  123. const char *qeth_get_cardname_short(struct qeth_card *card)
  124. {
  125. if (card->info.guestlan) {
  126. switch (card->info.type) {
  127. case QETH_CARD_TYPE_OSAE:
  128. return "GuestLAN QDIO";
  129. case QETH_CARD_TYPE_IQD:
  130. return "GuestLAN Hiper";
  131. default:
  132. return "unknown";
  133. }
  134. } else {
  135. switch (card->info.type) {
  136. case QETH_CARD_TYPE_OSAE:
  137. switch (card->info.link_type) {
  138. case QETH_LINK_TYPE_FAST_ETH:
  139. return "OSD_100";
  140. case QETH_LINK_TYPE_HSTR:
  141. return "HSTR";
  142. case QETH_LINK_TYPE_GBIT_ETH:
  143. return "OSD_1000";
  144. case QETH_LINK_TYPE_10GBIT_ETH:
  145. return "OSD_10GIG";
  146. case QETH_LINK_TYPE_LANE_ETH100:
  147. return "OSD_FE_LANE";
  148. case QETH_LINK_TYPE_LANE_TR:
  149. return "OSD_TR_LANE";
  150. case QETH_LINK_TYPE_LANE_ETH1000:
  151. return "OSD_GbE_LANE";
  152. case QETH_LINK_TYPE_LANE:
  153. return "OSD_ATM_LANE";
  154. default:
  155. return "OSD_Express";
  156. }
  157. case QETH_CARD_TYPE_IQD:
  158. return "HiperSockets";
  159. case QETH_CARD_TYPE_OSN:
  160. return "OSN";
  161. default:
  162. return "unknown";
  163. }
  164. }
  165. return "n/a";
  166. }
  167. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  168. int clear_start_mask)
  169. {
  170. unsigned long flags;
  171. spin_lock_irqsave(&card->thread_mask_lock, flags);
  172. card->thread_allowed_mask = threads;
  173. if (clear_start_mask)
  174. card->thread_start_mask &= threads;
  175. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  176. wake_up(&card->wait_q);
  177. }
  178. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  179. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  180. {
  181. unsigned long flags;
  182. int rc = 0;
  183. spin_lock_irqsave(&card->thread_mask_lock, flags);
  184. rc = (card->thread_running_mask & threads);
  185. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  186. return rc;
  187. }
  188. EXPORT_SYMBOL_GPL(qeth_threads_running);
  189. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  190. {
  191. return wait_event_interruptible(card->wait_q,
  192. qeth_threads_running(card, threads) == 0);
  193. }
  194. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  195. void qeth_clear_working_pool_list(struct qeth_card *card)
  196. {
  197. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  198. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  199. list_for_each_entry_safe(pool_entry, tmp,
  200. &card->qdio.in_buf_pool.entry_list, list){
  201. list_del(&pool_entry->list);
  202. }
  203. }
  204. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  205. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  206. {
  207. struct qeth_buffer_pool_entry *pool_entry;
  208. void *ptr;
  209. int i, j;
  210. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  211. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  212. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  213. if (!pool_entry) {
  214. qeth_free_buffer_pool(card);
  215. return -ENOMEM;
  216. }
  217. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  218. ptr = (void *) __get_free_page(GFP_KERNEL);
  219. if (!ptr) {
  220. while (j > 0)
  221. free_page((unsigned long)
  222. pool_entry->elements[--j]);
  223. kfree(pool_entry);
  224. qeth_free_buffer_pool(card);
  225. return -ENOMEM;
  226. }
  227. pool_entry->elements[j] = ptr;
  228. }
  229. list_add(&pool_entry->init_list,
  230. &card->qdio.init_pool.entry_list);
  231. }
  232. return 0;
  233. }
  234. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  235. {
  236. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  237. if ((card->state != CARD_STATE_DOWN) &&
  238. (card->state != CARD_STATE_RECOVER))
  239. return -EPERM;
  240. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  241. qeth_clear_working_pool_list(card);
  242. qeth_free_buffer_pool(card);
  243. card->qdio.in_buf_pool.buf_count = bufcnt;
  244. card->qdio.init_pool.buf_count = bufcnt;
  245. return qeth_alloc_buffer_pool(card);
  246. }
  247. int qeth_set_large_send(struct qeth_card *card,
  248. enum qeth_large_send_types type)
  249. {
  250. int rc = 0;
  251. if (card->dev == NULL) {
  252. card->options.large_send = type;
  253. return 0;
  254. }
  255. if (card->state == CARD_STATE_UP)
  256. netif_tx_disable(card->dev);
  257. card->options.large_send = type;
  258. switch (card->options.large_send) {
  259. case QETH_LARGE_SEND_EDDP:
  260. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  261. NETIF_F_HW_CSUM;
  262. break;
  263. case QETH_LARGE_SEND_TSO:
  264. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  265. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  266. NETIF_F_HW_CSUM;
  267. } else {
  268. PRINT_WARN("TSO not supported on %s. "
  269. "large_send set to 'no'.\n",
  270. card->dev->name);
  271. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  272. NETIF_F_HW_CSUM);
  273. card->options.large_send = QETH_LARGE_SEND_NO;
  274. rc = -EOPNOTSUPP;
  275. }
  276. break;
  277. default: /* includes QETH_LARGE_SEND_NO */
  278. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  279. NETIF_F_HW_CSUM);
  280. break;
  281. }
  282. if (card->state == CARD_STATE_UP)
  283. netif_wake_queue(card->dev);
  284. return rc;
  285. }
  286. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  287. static int qeth_issue_next_read(struct qeth_card *card)
  288. {
  289. int rc;
  290. struct qeth_cmd_buffer *iob;
  291. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  292. if (card->read.state != CH_STATE_UP)
  293. return -EIO;
  294. iob = qeth_get_buffer(&card->read);
  295. if (!iob) {
  296. PRINT_WARN("issue_next_read failed: no iob available!\n");
  297. return -ENOMEM;
  298. }
  299. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  300. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  301. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  302. (addr_t) iob, 0, 0);
  303. if (rc) {
  304. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  305. atomic_set(&card->read.irq_pending, 0);
  306. qeth_schedule_recovery(card);
  307. wake_up(&card->wait_q);
  308. }
  309. return rc;
  310. }
  311. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  312. {
  313. struct qeth_reply *reply;
  314. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  315. if (reply) {
  316. atomic_set(&reply->refcnt, 1);
  317. atomic_set(&reply->received, 0);
  318. reply->card = card;
  319. };
  320. return reply;
  321. }
  322. static void qeth_get_reply(struct qeth_reply *reply)
  323. {
  324. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  325. atomic_inc(&reply->refcnt);
  326. }
  327. static void qeth_put_reply(struct qeth_reply *reply)
  328. {
  329. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  330. if (atomic_dec_and_test(&reply->refcnt))
  331. kfree(reply);
  332. }
  333. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  334. struct qeth_card *card)
  335. {
  336. char *ipa_name;
  337. int com = cmd->hdr.command;
  338. ipa_name = qeth_get_ipa_cmd_name(com);
  339. if (rc)
  340. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  341. ipa_name, com, QETH_CARD_IFNAME(card),
  342. rc, qeth_get_ipa_msg(rc));
  343. else
  344. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  345. ipa_name, com, QETH_CARD_IFNAME(card));
  346. }
  347. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  348. struct qeth_cmd_buffer *iob)
  349. {
  350. struct qeth_ipa_cmd *cmd = NULL;
  351. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  352. if (IS_IPA(iob->data)) {
  353. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  354. if (IS_IPA_REPLY(cmd)) {
  355. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  356. cmd->hdr.command > IPA_CMD_MODCCID)
  357. qeth_issue_ipa_msg(cmd,
  358. cmd->hdr.return_code, card);
  359. return cmd;
  360. } else {
  361. switch (cmd->hdr.command) {
  362. case IPA_CMD_STOPLAN:
  363. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  364. "there is a network problem or "
  365. "someone pulled the cable or "
  366. "disabled the port.\n",
  367. QETH_CARD_IFNAME(card),
  368. card->info.chpid);
  369. card->lan_online = 0;
  370. if (card->dev && netif_carrier_ok(card->dev))
  371. netif_carrier_off(card->dev);
  372. return NULL;
  373. case IPA_CMD_STARTLAN:
  374. PRINT_INFO("Link reestablished on %s "
  375. "(CHPID 0x%X). Scheduling "
  376. "IP address reset.\n",
  377. QETH_CARD_IFNAME(card),
  378. card->info.chpid);
  379. netif_carrier_on(card->dev);
  380. card->lan_online = 1;
  381. qeth_schedule_recovery(card);
  382. return NULL;
  383. case IPA_CMD_MODCCID:
  384. return cmd;
  385. case IPA_CMD_REGISTER_LOCAL_ADDR:
  386. QETH_DBF_TEXT(TRACE, 3, "irla");
  387. break;
  388. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  389. QETH_DBF_TEXT(TRACE, 3, "urla");
  390. break;
  391. default:
  392. PRINT_WARN("Received data is IPA "
  393. "but not a reply!\n");
  394. break;
  395. }
  396. }
  397. }
  398. return cmd;
  399. }
  400. void qeth_clear_ipacmd_list(struct qeth_card *card)
  401. {
  402. struct qeth_reply *reply, *r;
  403. unsigned long flags;
  404. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  405. spin_lock_irqsave(&card->lock, flags);
  406. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  407. qeth_get_reply(reply);
  408. reply->rc = -EIO;
  409. atomic_inc(&reply->received);
  410. list_del_init(&reply->list);
  411. wake_up(&reply->wait_q);
  412. qeth_put_reply(reply);
  413. }
  414. spin_unlock_irqrestore(&card->lock, flags);
  415. }
  416. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  417. static int qeth_check_idx_response(unsigned char *buffer)
  418. {
  419. if (!buffer)
  420. return 0;
  421. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  422. if ((buffer[2] & 0xc0) == 0xc0) {
  423. PRINT_WARN("received an IDX TERMINATE "
  424. "with cause code 0x%02x%s\n",
  425. buffer[4],
  426. ((buffer[4] == 0x22) ?
  427. " -- try another portname" : ""));
  428. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  429. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  430. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  431. return -EIO;
  432. }
  433. return 0;
  434. }
  435. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  436. __u32 len)
  437. {
  438. struct qeth_card *card;
  439. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  440. card = CARD_FROM_CDEV(channel->ccwdev);
  441. if (channel == &card->read)
  442. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  443. else
  444. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  445. channel->ccw.count = len;
  446. channel->ccw.cda = (__u32) __pa(iob);
  447. }
  448. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  449. {
  450. __u8 index;
  451. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  452. index = channel->io_buf_no;
  453. do {
  454. if (channel->iob[index].state == BUF_STATE_FREE) {
  455. channel->iob[index].state = BUF_STATE_LOCKED;
  456. channel->io_buf_no = (channel->io_buf_no + 1) %
  457. QETH_CMD_BUFFER_NO;
  458. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  459. return channel->iob + index;
  460. }
  461. index = (index + 1) % QETH_CMD_BUFFER_NO;
  462. } while (index != channel->io_buf_no);
  463. return NULL;
  464. }
  465. void qeth_release_buffer(struct qeth_channel *channel,
  466. struct qeth_cmd_buffer *iob)
  467. {
  468. unsigned long flags;
  469. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  470. spin_lock_irqsave(&channel->iob_lock, flags);
  471. memset(iob->data, 0, QETH_BUFSIZE);
  472. iob->state = BUF_STATE_FREE;
  473. iob->callback = qeth_send_control_data_cb;
  474. iob->rc = 0;
  475. spin_unlock_irqrestore(&channel->iob_lock, flags);
  476. }
  477. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  478. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  479. {
  480. struct qeth_cmd_buffer *buffer = NULL;
  481. unsigned long flags;
  482. spin_lock_irqsave(&channel->iob_lock, flags);
  483. buffer = __qeth_get_buffer(channel);
  484. spin_unlock_irqrestore(&channel->iob_lock, flags);
  485. return buffer;
  486. }
  487. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  488. {
  489. struct qeth_cmd_buffer *buffer;
  490. wait_event(channel->wait_q,
  491. ((buffer = qeth_get_buffer(channel)) != NULL));
  492. return buffer;
  493. }
  494. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  495. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  496. {
  497. int cnt;
  498. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  499. qeth_release_buffer(channel, &channel->iob[cnt]);
  500. channel->buf_no = 0;
  501. channel->io_buf_no = 0;
  502. }
  503. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  504. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  505. struct qeth_cmd_buffer *iob)
  506. {
  507. struct qeth_card *card;
  508. struct qeth_reply *reply, *r;
  509. struct qeth_ipa_cmd *cmd;
  510. unsigned long flags;
  511. int keep_reply;
  512. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  513. card = CARD_FROM_CDEV(channel->ccwdev);
  514. if (qeth_check_idx_response(iob->data)) {
  515. qeth_clear_ipacmd_list(card);
  516. qeth_schedule_recovery(card);
  517. goto out;
  518. }
  519. cmd = qeth_check_ipa_data(card, iob);
  520. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  521. goto out;
  522. /*in case of OSN : check if cmd is set */
  523. if (card->info.type == QETH_CARD_TYPE_OSN &&
  524. cmd &&
  525. cmd->hdr.command != IPA_CMD_STARTLAN &&
  526. card->osn_info.assist_cb != NULL) {
  527. card->osn_info.assist_cb(card->dev, cmd);
  528. goto out;
  529. }
  530. spin_lock_irqsave(&card->lock, flags);
  531. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  532. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  533. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  534. qeth_get_reply(reply);
  535. list_del_init(&reply->list);
  536. spin_unlock_irqrestore(&card->lock, flags);
  537. keep_reply = 0;
  538. if (reply->callback != NULL) {
  539. if (cmd) {
  540. reply->offset = (__u16)((char *)cmd -
  541. (char *)iob->data);
  542. keep_reply = reply->callback(card,
  543. reply,
  544. (unsigned long)cmd);
  545. } else
  546. keep_reply = reply->callback(card,
  547. reply,
  548. (unsigned long)iob);
  549. }
  550. if (cmd)
  551. reply->rc = (u16) cmd->hdr.return_code;
  552. else if (iob->rc)
  553. reply->rc = iob->rc;
  554. if (keep_reply) {
  555. spin_lock_irqsave(&card->lock, flags);
  556. list_add_tail(&reply->list,
  557. &card->cmd_waiter_list);
  558. spin_unlock_irqrestore(&card->lock, flags);
  559. } else {
  560. atomic_inc(&reply->received);
  561. wake_up(&reply->wait_q);
  562. }
  563. qeth_put_reply(reply);
  564. goto out;
  565. }
  566. }
  567. spin_unlock_irqrestore(&card->lock, flags);
  568. out:
  569. memcpy(&card->seqno.pdu_hdr_ack,
  570. QETH_PDU_HEADER_SEQ_NO(iob->data),
  571. QETH_SEQ_NO_LENGTH);
  572. qeth_release_buffer(channel, iob);
  573. }
  574. static int qeth_setup_channel(struct qeth_channel *channel)
  575. {
  576. int cnt;
  577. QETH_DBF_TEXT(SETUP, 2, "setupch");
  578. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  579. channel->iob[cnt].data = (char *)
  580. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  581. if (channel->iob[cnt].data == NULL)
  582. break;
  583. channel->iob[cnt].state = BUF_STATE_FREE;
  584. channel->iob[cnt].channel = channel;
  585. channel->iob[cnt].callback = qeth_send_control_data_cb;
  586. channel->iob[cnt].rc = 0;
  587. }
  588. if (cnt < QETH_CMD_BUFFER_NO) {
  589. while (cnt-- > 0)
  590. kfree(channel->iob[cnt].data);
  591. return -ENOMEM;
  592. }
  593. channel->buf_no = 0;
  594. channel->io_buf_no = 0;
  595. atomic_set(&channel->irq_pending, 0);
  596. spin_lock_init(&channel->iob_lock);
  597. init_waitqueue_head(&channel->wait_q);
  598. return 0;
  599. }
  600. static int qeth_set_thread_start_bit(struct qeth_card *card,
  601. unsigned long thread)
  602. {
  603. unsigned long flags;
  604. spin_lock_irqsave(&card->thread_mask_lock, flags);
  605. if (!(card->thread_allowed_mask & thread) ||
  606. (card->thread_start_mask & thread)) {
  607. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  608. return -EPERM;
  609. }
  610. card->thread_start_mask |= thread;
  611. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  612. return 0;
  613. }
  614. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  615. {
  616. unsigned long flags;
  617. spin_lock_irqsave(&card->thread_mask_lock, flags);
  618. card->thread_start_mask &= ~thread;
  619. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  620. wake_up(&card->wait_q);
  621. }
  622. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  623. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  624. {
  625. unsigned long flags;
  626. spin_lock_irqsave(&card->thread_mask_lock, flags);
  627. card->thread_running_mask &= ~thread;
  628. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  629. wake_up(&card->wait_q);
  630. }
  631. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  632. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  633. {
  634. unsigned long flags;
  635. int rc = 0;
  636. spin_lock_irqsave(&card->thread_mask_lock, flags);
  637. if (card->thread_start_mask & thread) {
  638. if ((card->thread_allowed_mask & thread) &&
  639. !(card->thread_running_mask & thread)) {
  640. rc = 1;
  641. card->thread_start_mask &= ~thread;
  642. card->thread_running_mask |= thread;
  643. } else
  644. rc = -EPERM;
  645. }
  646. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  647. return rc;
  648. }
  649. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  650. {
  651. int rc = 0;
  652. wait_event(card->wait_q,
  653. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  654. return rc;
  655. }
  656. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  657. void qeth_schedule_recovery(struct qeth_card *card)
  658. {
  659. QETH_DBF_TEXT(TRACE, 2, "startrec");
  660. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  661. schedule_work(&card->kernel_thread_starter);
  662. }
  663. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  664. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  665. {
  666. int dstat, cstat;
  667. char *sense;
  668. sense = (char *) irb->ecw;
  669. cstat = irb->scsw.cstat;
  670. dstat = irb->scsw.dstat;
  671. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  672. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  673. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  674. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  675. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  676. cdev->dev.bus_id, dstat, cstat);
  677. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  678. 16, 1, irb, 64, 1);
  679. return 1;
  680. }
  681. if (dstat & DEV_STAT_UNIT_CHECK) {
  682. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  683. SENSE_RESETTING_EVENT_FLAG) {
  684. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  685. return 1;
  686. }
  687. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  688. SENSE_COMMAND_REJECT_FLAG) {
  689. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  690. return 0;
  691. }
  692. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  693. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  694. return 1;
  695. }
  696. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  697. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  698. return 0;
  699. }
  700. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  701. return 1;
  702. }
  703. return 0;
  704. }
  705. static long __qeth_check_irb_error(struct ccw_device *cdev,
  706. unsigned long intparm, struct irb *irb)
  707. {
  708. if (!IS_ERR(irb))
  709. return 0;
  710. switch (PTR_ERR(irb)) {
  711. case -EIO:
  712. PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
  713. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  714. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  715. break;
  716. case -ETIMEDOUT:
  717. PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
  718. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  719. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  720. if (intparm == QETH_RCD_PARM) {
  721. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  722. if (card && (card->data.ccwdev == cdev)) {
  723. card->data.state = CH_STATE_DOWN;
  724. wake_up(&card->wait_q);
  725. }
  726. }
  727. break;
  728. default:
  729. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  730. cdev->dev.bus_id);
  731. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  732. QETH_DBF_TEXT(TRACE, 2, " rc???");
  733. }
  734. return PTR_ERR(irb);
  735. }
  736. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  737. struct irb *irb)
  738. {
  739. int rc;
  740. int cstat, dstat;
  741. struct qeth_cmd_buffer *buffer;
  742. struct qeth_channel *channel;
  743. struct qeth_card *card;
  744. struct qeth_cmd_buffer *iob;
  745. __u8 index;
  746. QETH_DBF_TEXT(TRACE, 5, "irq");
  747. if (__qeth_check_irb_error(cdev, intparm, irb))
  748. return;
  749. cstat = irb->scsw.cstat;
  750. dstat = irb->scsw.dstat;
  751. card = CARD_FROM_CDEV(cdev);
  752. if (!card)
  753. return;
  754. if (card->read.ccwdev == cdev) {
  755. channel = &card->read;
  756. QETH_DBF_TEXT(TRACE, 5, "read");
  757. } else if (card->write.ccwdev == cdev) {
  758. channel = &card->write;
  759. QETH_DBF_TEXT(TRACE, 5, "write");
  760. } else {
  761. channel = &card->data;
  762. QETH_DBF_TEXT(TRACE, 5, "data");
  763. }
  764. atomic_set(&channel->irq_pending, 0);
  765. if (irb->scsw.fctl & (SCSW_FCTL_CLEAR_FUNC))
  766. channel->state = CH_STATE_STOPPED;
  767. if (irb->scsw.fctl & (SCSW_FCTL_HALT_FUNC))
  768. channel->state = CH_STATE_HALTED;
  769. /*let's wake up immediately on data channel*/
  770. if ((channel == &card->data) && (intparm != 0) &&
  771. (intparm != QETH_RCD_PARM))
  772. goto out;
  773. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  774. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  775. /* we don't have to handle this further */
  776. intparm = 0;
  777. }
  778. if (intparm == QETH_HALT_CHANNEL_PARM) {
  779. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  780. /* we don't have to handle this further */
  781. intparm = 0;
  782. }
  783. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  784. (dstat & DEV_STAT_UNIT_CHECK) ||
  785. (cstat)) {
  786. if (irb->esw.esw0.erw.cons) {
  787. /* TODO: we should make this s390dbf */
  788. PRINT_WARN("sense data available on channel %s.\n",
  789. CHANNEL_ID(channel));
  790. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  791. print_hex_dump(KERN_WARNING, "qeth: irb ",
  792. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  793. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  794. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  795. }
  796. if (intparm == QETH_RCD_PARM) {
  797. channel->state = CH_STATE_DOWN;
  798. goto out;
  799. }
  800. rc = qeth_get_problem(cdev, irb);
  801. if (rc) {
  802. qeth_schedule_recovery(card);
  803. goto out;
  804. }
  805. }
  806. if (intparm == QETH_RCD_PARM) {
  807. channel->state = CH_STATE_RCD_DONE;
  808. goto out;
  809. }
  810. if (intparm) {
  811. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  812. buffer->state = BUF_STATE_PROCESSED;
  813. }
  814. if (channel == &card->data)
  815. return;
  816. if (channel == &card->read &&
  817. channel->state == CH_STATE_UP)
  818. qeth_issue_next_read(card);
  819. iob = channel->iob;
  820. index = channel->buf_no;
  821. while (iob[index].state == BUF_STATE_PROCESSED) {
  822. if (iob[index].callback != NULL)
  823. iob[index].callback(channel, iob + index);
  824. index = (index + 1) % QETH_CMD_BUFFER_NO;
  825. }
  826. channel->buf_no = index;
  827. out:
  828. wake_up(&card->wait_q);
  829. return;
  830. }
  831. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  832. struct qeth_qdio_out_buffer *buf)
  833. {
  834. int i;
  835. struct sk_buff *skb;
  836. /* is PCI flag set on buffer? */
  837. if (buf->buffer->element[0].flags & 0x40)
  838. atomic_dec(&queue->set_pci_flags_count);
  839. skb = skb_dequeue(&buf->skb_list);
  840. while (skb) {
  841. atomic_dec(&skb->users);
  842. dev_kfree_skb_any(skb);
  843. skb = skb_dequeue(&buf->skb_list);
  844. }
  845. qeth_eddp_buf_release_contexts(buf);
  846. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  847. buf->buffer->element[i].length = 0;
  848. buf->buffer->element[i].addr = NULL;
  849. buf->buffer->element[i].flags = 0;
  850. }
  851. buf->next_element_to_fill = 0;
  852. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  853. }
  854. void qeth_clear_qdio_buffers(struct qeth_card *card)
  855. {
  856. int i, j;
  857. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  858. /* clear outbound buffers to free skbs */
  859. for (i = 0; i < card->qdio.no_out_queues; ++i)
  860. if (card->qdio.out_qs[i]) {
  861. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  862. qeth_clear_output_buffer(card->qdio.out_qs[i],
  863. &card->qdio.out_qs[i]->bufs[j]);
  864. }
  865. }
  866. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  867. static void qeth_free_buffer_pool(struct qeth_card *card)
  868. {
  869. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  870. int i = 0;
  871. QETH_DBF_TEXT(TRACE, 5, "freepool");
  872. list_for_each_entry_safe(pool_entry, tmp,
  873. &card->qdio.init_pool.entry_list, init_list){
  874. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  875. free_page((unsigned long)pool_entry->elements[i]);
  876. list_del(&pool_entry->init_list);
  877. kfree(pool_entry);
  878. }
  879. }
  880. static void qeth_free_qdio_buffers(struct qeth_card *card)
  881. {
  882. int i, j;
  883. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  884. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  885. QETH_QDIO_UNINITIALIZED)
  886. return;
  887. kfree(card->qdio.in_q);
  888. card->qdio.in_q = NULL;
  889. /* inbound buffer pool */
  890. qeth_free_buffer_pool(card);
  891. /* free outbound qdio_qs */
  892. if (card->qdio.out_qs) {
  893. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  894. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  895. qeth_clear_output_buffer(card->qdio.out_qs[i],
  896. &card->qdio.out_qs[i]->bufs[j]);
  897. kfree(card->qdio.out_qs[i]);
  898. }
  899. kfree(card->qdio.out_qs);
  900. card->qdio.out_qs = NULL;
  901. }
  902. }
  903. static void qeth_clean_channel(struct qeth_channel *channel)
  904. {
  905. int cnt;
  906. QETH_DBF_TEXT(SETUP, 2, "freech");
  907. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  908. kfree(channel->iob[cnt].data);
  909. }
  910. static int qeth_is_1920_device(struct qeth_card *card)
  911. {
  912. int single_queue = 0;
  913. struct ccw_device *ccwdev;
  914. struct channelPath_dsc {
  915. u8 flags;
  916. u8 lsn;
  917. u8 desc;
  918. u8 chpid;
  919. u8 swla;
  920. u8 zeroes;
  921. u8 chla;
  922. u8 chpp;
  923. } *chp_dsc;
  924. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  925. ccwdev = card->data.ccwdev;
  926. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  927. if (chp_dsc != NULL) {
  928. /* CHPP field bit 6 == 1 -> single queue */
  929. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  930. kfree(chp_dsc);
  931. }
  932. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  933. return single_queue;
  934. }
  935. static void qeth_init_qdio_info(struct qeth_card *card)
  936. {
  937. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  938. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  939. /* inbound */
  940. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  941. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  942. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  943. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  944. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  945. }
  946. static void qeth_set_intial_options(struct qeth_card *card)
  947. {
  948. card->options.route4.type = NO_ROUTER;
  949. card->options.route6.type = NO_ROUTER;
  950. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  951. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  952. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  953. card->options.fake_broadcast = 0;
  954. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  955. card->options.fake_ll = 0;
  956. card->options.performance_stats = 0;
  957. card->options.rx_sg_cb = QETH_RX_SG_CB;
  958. }
  959. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  960. {
  961. unsigned long flags;
  962. int rc = 0;
  963. spin_lock_irqsave(&card->thread_mask_lock, flags);
  964. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  965. (u8) card->thread_start_mask,
  966. (u8) card->thread_allowed_mask,
  967. (u8) card->thread_running_mask);
  968. rc = (card->thread_start_mask & thread);
  969. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  970. return rc;
  971. }
  972. static void qeth_start_kernel_thread(struct work_struct *work)
  973. {
  974. struct qeth_card *card = container_of(work, struct qeth_card,
  975. kernel_thread_starter);
  976. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  977. if (card->read.state != CH_STATE_UP &&
  978. card->write.state != CH_STATE_UP)
  979. return;
  980. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  981. kthread_run(card->discipline.recover, (void *) card,
  982. "qeth_recover");
  983. }
  984. static int qeth_setup_card(struct qeth_card *card)
  985. {
  986. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  987. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  988. card->read.state = CH_STATE_DOWN;
  989. card->write.state = CH_STATE_DOWN;
  990. card->data.state = CH_STATE_DOWN;
  991. card->state = CARD_STATE_DOWN;
  992. card->lan_online = 0;
  993. card->use_hard_stop = 0;
  994. card->dev = NULL;
  995. spin_lock_init(&card->vlanlock);
  996. spin_lock_init(&card->mclock);
  997. card->vlangrp = NULL;
  998. spin_lock_init(&card->lock);
  999. spin_lock_init(&card->ip_lock);
  1000. spin_lock_init(&card->thread_mask_lock);
  1001. card->thread_start_mask = 0;
  1002. card->thread_allowed_mask = 0;
  1003. card->thread_running_mask = 0;
  1004. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1005. INIT_LIST_HEAD(&card->ip_list);
  1006. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1007. if (!card->ip_tbd_list) {
  1008. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1009. return -ENOMEM;
  1010. }
  1011. INIT_LIST_HEAD(card->ip_tbd_list);
  1012. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1013. init_waitqueue_head(&card->wait_q);
  1014. /* intial options */
  1015. qeth_set_intial_options(card);
  1016. /* IP address takeover */
  1017. INIT_LIST_HEAD(&card->ipato.entries);
  1018. card->ipato.enabled = 0;
  1019. card->ipato.invert4 = 0;
  1020. card->ipato.invert6 = 0;
  1021. /* init QDIO stuff */
  1022. qeth_init_qdio_info(card);
  1023. return 0;
  1024. }
  1025. static struct qeth_card *qeth_alloc_card(void)
  1026. {
  1027. struct qeth_card *card;
  1028. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1029. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1030. if (!card)
  1031. return NULL;
  1032. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1033. if (qeth_setup_channel(&card->read)) {
  1034. kfree(card);
  1035. return NULL;
  1036. }
  1037. if (qeth_setup_channel(&card->write)) {
  1038. qeth_clean_channel(&card->read);
  1039. kfree(card);
  1040. return NULL;
  1041. }
  1042. card->options.layer2 = -1;
  1043. return card;
  1044. }
  1045. static int qeth_determine_card_type(struct qeth_card *card)
  1046. {
  1047. int i = 0;
  1048. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1049. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1050. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1051. while (known_devices[i][4]) {
  1052. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1053. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1054. card->info.type = known_devices[i][4];
  1055. card->qdio.no_out_queues = known_devices[i][8];
  1056. card->info.is_multicast_different = known_devices[i][9];
  1057. if (qeth_is_1920_device(card)) {
  1058. PRINT_INFO("Priority Queueing not able "
  1059. "due to hardware limitations!\n");
  1060. card->qdio.no_out_queues = 1;
  1061. card->qdio.default_out_queue = 0;
  1062. }
  1063. return 0;
  1064. }
  1065. i++;
  1066. }
  1067. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1068. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1069. return -ENOENT;
  1070. }
  1071. static int qeth_clear_channel(struct qeth_channel *channel)
  1072. {
  1073. unsigned long flags;
  1074. struct qeth_card *card;
  1075. int rc;
  1076. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1077. card = CARD_FROM_CDEV(channel->ccwdev);
  1078. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1079. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1080. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1081. if (rc)
  1082. return rc;
  1083. rc = wait_event_interruptible_timeout(card->wait_q,
  1084. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1085. if (rc == -ERESTARTSYS)
  1086. return rc;
  1087. if (channel->state != CH_STATE_STOPPED)
  1088. return -ETIME;
  1089. channel->state = CH_STATE_DOWN;
  1090. return 0;
  1091. }
  1092. static int qeth_halt_channel(struct qeth_channel *channel)
  1093. {
  1094. unsigned long flags;
  1095. struct qeth_card *card;
  1096. int rc;
  1097. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1098. card = CARD_FROM_CDEV(channel->ccwdev);
  1099. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1100. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1101. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1102. if (rc)
  1103. return rc;
  1104. rc = wait_event_interruptible_timeout(card->wait_q,
  1105. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1106. if (rc == -ERESTARTSYS)
  1107. return rc;
  1108. if (channel->state != CH_STATE_HALTED)
  1109. return -ETIME;
  1110. return 0;
  1111. }
  1112. static int qeth_halt_channels(struct qeth_card *card)
  1113. {
  1114. int rc1 = 0, rc2 = 0, rc3 = 0;
  1115. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1116. rc1 = qeth_halt_channel(&card->read);
  1117. rc2 = qeth_halt_channel(&card->write);
  1118. rc3 = qeth_halt_channel(&card->data);
  1119. if (rc1)
  1120. return rc1;
  1121. if (rc2)
  1122. return rc2;
  1123. return rc3;
  1124. }
  1125. static int qeth_clear_channels(struct qeth_card *card)
  1126. {
  1127. int rc1 = 0, rc2 = 0, rc3 = 0;
  1128. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1129. rc1 = qeth_clear_channel(&card->read);
  1130. rc2 = qeth_clear_channel(&card->write);
  1131. rc3 = qeth_clear_channel(&card->data);
  1132. if (rc1)
  1133. return rc1;
  1134. if (rc2)
  1135. return rc2;
  1136. return rc3;
  1137. }
  1138. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1139. {
  1140. int rc = 0;
  1141. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1142. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1143. if (halt)
  1144. rc = qeth_halt_channels(card);
  1145. if (rc)
  1146. return rc;
  1147. return qeth_clear_channels(card);
  1148. }
  1149. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1150. {
  1151. int rc = 0;
  1152. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1153. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1154. QETH_QDIO_CLEANING)) {
  1155. case QETH_QDIO_ESTABLISHED:
  1156. if (card->info.type == QETH_CARD_TYPE_IQD)
  1157. rc = qdio_cleanup(CARD_DDEV(card),
  1158. QDIO_FLAG_CLEANUP_USING_HALT);
  1159. else
  1160. rc = qdio_cleanup(CARD_DDEV(card),
  1161. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1162. if (rc)
  1163. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1164. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1165. break;
  1166. case QETH_QDIO_CLEANING:
  1167. return rc;
  1168. default:
  1169. break;
  1170. }
  1171. rc = qeth_clear_halt_card(card, use_halt);
  1172. if (rc)
  1173. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1174. card->state = CARD_STATE_DOWN;
  1175. return rc;
  1176. }
  1177. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1178. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1179. int *length)
  1180. {
  1181. struct ciw *ciw;
  1182. char *rcd_buf;
  1183. int ret;
  1184. struct qeth_channel *channel = &card->data;
  1185. unsigned long flags;
  1186. /*
  1187. * scan for RCD command in extended SenseID data
  1188. */
  1189. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1190. if (!ciw || ciw->cmd == 0)
  1191. return -EOPNOTSUPP;
  1192. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1193. if (!rcd_buf)
  1194. return -ENOMEM;
  1195. channel->ccw.cmd_code = ciw->cmd;
  1196. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1197. channel->ccw.count = ciw->count;
  1198. channel->ccw.flags = CCW_FLAG_SLI;
  1199. channel->state = CH_STATE_RCD;
  1200. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1201. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1202. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1203. QETH_RCD_TIMEOUT);
  1204. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1205. if (!ret)
  1206. wait_event(card->wait_q,
  1207. (channel->state == CH_STATE_RCD_DONE ||
  1208. channel->state == CH_STATE_DOWN));
  1209. if (channel->state == CH_STATE_DOWN)
  1210. ret = -EIO;
  1211. else
  1212. channel->state = CH_STATE_DOWN;
  1213. if (ret) {
  1214. kfree(rcd_buf);
  1215. *buffer = NULL;
  1216. *length = 0;
  1217. } else {
  1218. *length = ciw->count;
  1219. *buffer = rcd_buf;
  1220. }
  1221. return ret;
  1222. }
  1223. static int qeth_get_unitaddr(struct qeth_card *card)
  1224. {
  1225. int length;
  1226. char *prcd;
  1227. int rc;
  1228. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1229. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1230. if (rc) {
  1231. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1232. CARD_DDEV_ID(card), rc);
  1233. return rc;
  1234. }
  1235. card->info.chpid = prcd[30];
  1236. card->info.unit_addr2 = prcd[31];
  1237. card->info.cula = prcd[63];
  1238. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1239. (prcd[0x11] == _ascebc['M']));
  1240. kfree(prcd);
  1241. return 0;
  1242. }
  1243. static void qeth_init_tokens(struct qeth_card *card)
  1244. {
  1245. card->token.issuer_rm_w = 0x00010103UL;
  1246. card->token.cm_filter_w = 0x00010108UL;
  1247. card->token.cm_connection_w = 0x0001010aUL;
  1248. card->token.ulp_filter_w = 0x0001010bUL;
  1249. card->token.ulp_connection_w = 0x0001010dUL;
  1250. }
  1251. static void qeth_init_func_level(struct qeth_card *card)
  1252. {
  1253. if (card->ipato.enabled) {
  1254. if (card->info.type == QETH_CARD_TYPE_IQD)
  1255. card->info.func_level =
  1256. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1257. else
  1258. card->info.func_level =
  1259. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1260. } else {
  1261. if (card->info.type == QETH_CARD_TYPE_IQD)
  1262. /*FIXME:why do we have same values for dis and ena for
  1263. osae??? */
  1264. card->info.func_level =
  1265. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1266. else
  1267. card->info.func_level =
  1268. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1269. }
  1270. }
  1271. static inline __u16 qeth_raw_devno_from_bus_id(char *id)
  1272. {
  1273. id += (strlen(id) - 4);
  1274. return (__u16) simple_strtoul(id, &id, 16);
  1275. }
  1276. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1277. void (*idx_reply_cb)(struct qeth_channel *,
  1278. struct qeth_cmd_buffer *))
  1279. {
  1280. struct qeth_cmd_buffer *iob;
  1281. unsigned long flags;
  1282. int rc;
  1283. struct qeth_card *card;
  1284. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1285. card = CARD_FROM_CDEV(channel->ccwdev);
  1286. iob = qeth_get_buffer(channel);
  1287. iob->callback = idx_reply_cb;
  1288. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1289. channel->ccw.count = QETH_BUFSIZE;
  1290. channel->ccw.cda = (__u32) __pa(iob->data);
  1291. wait_event(card->wait_q,
  1292. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1293. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1294. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1295. rc = ccw_device_start(channel->ccwdev,
  1296. &channel->ccw, (addr_t) iob, 0, 0);
  1297. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1298. if (rc) {
  1299. PRINT_ERR("Error2 in activating channel rc=%d\n", rc);
  1300. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1301. atomic_set(&channel->irq_pending, 0);
  1302. wake_up(&card->wait_q);
  1303. return rc;
  1304. }
  1305. rc = wait_event_interruptible_timeout(card->wait_q,
  1306. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1307. if (rc == -ERESTARTSYS)
  1308. return rc;
  1309. if (channel->state != CH_STATE_UP) {
  1310. rc = -ETIME;
  1311. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1312. qeth_clear_cmd_buffers(channel);
  1313. } else
  1314. rc = 0;
  1315. return rc;
  1316. }
  1317. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1318. void (*idx_reply_cb)(struct qeth_channel *,
  1319. struct qeth_cmd_buffer *))
  1320. {
  1321. struct qeth_card *card;
  1322. struct qeth_cmd_buffer *iob;
  1323. unsigned long flags;
  1324. __u16 temp;
  1325. __u8 tmp;
  1326. int rc;
  1327. card = CARD_FROM_CDEV(channel->ccwdev);
  1328. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1329. iob = qeth_get_buffer(channel);
  1330. iob->callback = idx_reply_cb;
  1331. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1332. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1333. channel->ccw.cda = (__u32) __pa(iob->data);
  1334. if (channel == &card->write) {
  1335. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1336. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1337. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1338. card->seqno.trans_hdr++;
  1339. } else {
  1340. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1341. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1342. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1343. }
  1344. tmp = ((__u8)card->info.portno) | 0x80;
  1345. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1346. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1347. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1348. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1349. &card->info.func_level, sizeof(__u16));
  1350. temp = qeth_raw_devno_from_bus_id(CARD_DDEV_ID(card));
  1351. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp, 2);
  1352. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1353. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1354. wait_event(card->wait_q,
  1355. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1356. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1357. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1358. rc = ccw_device_start(channel->ccwdev,
  1359. &channel->ccw, (addr_t) iob, 0, 0);
  1360. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1361. if (rc) {
  1362. PRINT_ERR("Error1 in activating channel. rc=%d\n", rc);
  1363. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1364. atomic_set(&channel->irq_pending, 0);
  1365. wake_up(&card->wait_q);
  1366. return rc;
  1367. }
  1368. rc = wait_event_interruptible_timeout(card->wait_q,
  1369. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1370. if (rc == -ERESTARTSYS)
  1371. return rc;
  1372. if (channel->state != CH_STATE_ACTIVATING) {
  1373. PRINT_WARN("IDX activate timed out!\n");
  1374. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1375. qeth_clear_cmd_buffers(channel);
  1376. return -ETIME;
  1377. }
  1378. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1379. }
  1380. static int qeth_peer_func_level(int level)
  1381. {
  1382. if ((level & 0xff) == 8)
  1383. return (level & 0xff) + 0x400;
  1384. if (((level >> 8) & 3) == 1)
  1385. return (level & 0xff) + 0x200;
  1386. return level;
  1387. }
  1388. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1389. struct qeth_cmd_buffer *iob)
  1390. {
  1391. struct qeth_card *card;
  1392. __u16 temp;
  1393. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1394. if (channel->state == CH_STATE_DOWN) {
  1395. channel->state = CH_STATE_ACTIVATING;
  1396. goto out;
  1397. }
  1398. card = CARD_FROM_CDEV(channel->ccwdev);
  1399. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1400. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1401. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1402. "adapter exclusively used by another host\n",
  1403. CARD_WDEV_ID(card));
  1404. else
  1405. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1406. "negative reply\n", CARD_WDEV_ID(card));
  1407. goto out;
  1408. }
  1409. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1410. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1411. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1412. "function level mismatch "
  1413. "(sent: 0x%x, received: 0x%x)\n",
  1414. CARD_WDEV_ID(card), card->info.func_level, temp);
  1415. goto out;
  1416. }
  1417. channel->state = CH_STATE_UP;
  1418. out:
  1419. qeth_release_buffer(channel, iob);
  1420. }
  1421. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1422. struct qeth_cmd_buffer *iob)
  1423. {
  1424. struct qeth_card *card;
  1425. __u16 temp;
  1426. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1427. if (channel->state == CH_STATE_DOWN) {
  1428. channel->state = CH_STATE_ACTIVATING;
  1429. goto out;
  1430. }
  1431. card = CARD_FROM_CDEV(channel->ccwdev);
  1432. if (qeth_check_idx_response(iob->data))
  1433. goto out;
  1434. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1435. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1436. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1437. "adapter exclusively used by another host\n",
  1438. CARD_RDEV_ID(card));
  1439. else
  1440. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1441. "negative reply\n", CARD_RDEV_ID(card));
  1442. goto out;
  1443. }
  1444. /**
  1445. * temporary fix for microcode bug
  1446. * to revert it,replace OR by AND
  1447. */
  1448. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1449. (card->info.type == QETH_CARD_TYPE_OSAE))
  1450. card->info.portname_required = 1;
  1451. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1452. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1453. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1454. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1455. CARD_RDEV_ID(card), card->info.func_level, temp);
  1456. goto out;
  1457. }
  1458. memcpy(&card->token.issuer_rm_r,
  1459. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1460. QETH_MPC_TOKEN_LENGTH);
  1461. memcpy(&card->info.mcl_level[0],
  1462. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1463. channel->state = CH_STATE_UP;
  1464. out:
  1465. qeth_release_buffer(channel, iob);
  1466. }
  1467. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1468. struct qeth_cmd_buffer *iob)
  1469. {
  1470. qeth_setup_ccw(&card->write, iob->data, len);
  1471. iob->callback = qeth_release_buffer;
  1472. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1473. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1474. card->seqno.trans_hdr++;
  1475. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1476. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1477. card->seqno.pdu_hdr++;
  1478. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1479. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1480. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1481. }
  1482. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1483. int qeth_send_control_data(struct qeth_card *card, int len,
  1484. struct qeth_cmd_buffer *iob,
  1485. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1486. unsigned long),
  1487. void *reply_param)
  1488. {
  1489. int rc;
  1490. unsigned long flags;
  1491. struct qeth_reply *reply = NULL;
  1492. unsigned long timeout;
  1493. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1494. reply = qeth_alloc_reply(card);
  1495. if (!reply) {
  1496. PRINT_WARN("Could not alloc qeth_reply!\n");
  1497. return -ENOMEM;
  1498. }
  1499. reply->callback = reply_cb;
  1500. reply->param = reply_param;
  1501. if (card->state == CARD_STATE_DOWN)
  1502. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1503. else
  1504. reply->seqno = card->seqno.ipa++;
  1505. init_waitqueue_head(&reply->wait_q);
  1506. spin_lock_irqsave(&card->lock, flags);
  1507. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1508. spin_unlock_irqrestore(&card->lock, flags);
  1509. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1510. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1511. qeth_prepare_control_data(card, len, iob);
  1512. if (IS_IPA(iob->data))
  1513. timeout = jiffies + QETH_IPA_TIMEOUT;
  1514. else
  1515. timeout = jiffies + QETH_TIMEOUT;
  1516. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1517. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1518. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1519. (addr_t) iob, 0, 0);
  1520. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1521. if (rc) {
  1522. PRINT_WARN("qeth_send_control_data: "
  1523. "ccw_device_start rc = %i\n", rc);
  1524. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1525. spin_lock_irqsave(&card->lock, flags);
  1526. list_del_init(&reply->list);
  1527. qeth_put_reply(reply);
  1528. spin_unlock_irqrestore(&card->lock, flags);
  1529. qeth_release_buffer(iob->channel, iob);
  1530. atomic_set(&card->write.irq_pending, 0);
  1531. wake_up(&card->wait_q);
  1532. return rc;
  1533. }
  1534. while (!atomic_read(&reply->received)) {
  1535. if (time_after(jiffies, timeout)) {
  1536. spin_lock_irqsave(&reply->card->lock, flags);
  1537. list_del_init(&reply->list);
  1538. spin_unlock_irqrestore(&reply->card->lock, flags);
  1539. reply->rc = -ETIME;
  1540. atomic_inc(&reply->received);
  1541. wake_up(&reply->wait_q);
  1542. }
  1543. cpu_relax();
  1544. };
  1545. rc = reply->rc;
  1546. qeth_put_reply(reply);
  1547. return rc;
  1548. }
  1549. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1550. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1551. unsigned long data)
  1552. {
  1553. struct qeth_cmd_buffer *iob;
  1554. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1555. iob = (struct qeth_cmd_buffer *) data;
  1556. memcpy(&card->token.cm_filter_r,
  1557. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1558. QETH_MPC_TOKEN_LENGTH);
  1559. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1560. return 0;
  1561. }
  1562. static int qeth_cm_enable(struct qeth_card *card)
  1563. {
  1564. int rc;
  1565. struct qeth_cmd_buffer *iob;
  1566. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1567. iob = qeth_wait_for_buffer(&card->write);
  1568. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1569. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1570. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1571. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1572. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1573. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1574. qeth_cm_enable_cb, NULL);
  1575. return rc;
  1576. }
  1577. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1578. unsigned long data)
  1579. {
  1580. struct qeth_cmd_buffer *iob;
  1581. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1582. iob = (struct qeth_cmd_buffer *) data;
  1583. memcpy(&card->token.cm_connection_r,
  1584. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1585. QETH_MPC_TOKEN_LENGTH);
  1586. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1587. return 0;
  1588. }
  1589. static int qeth_cm_setup(struct qeth_card *card)
  1590. {
  1591. int rc;
  1592. struct qeth_cmd_buffer *iob;
  1593. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1594. iob = qeth_wait_for_buffer(&card->write);
  1595. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1596. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1597. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1598. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1599. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1600. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1601. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1602. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1603. qeth_cm_setup_cb, NULL);
  1604. return rc;
  1605. }
  1606. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1607. {
  1608. switch (card->info.type) {
  1609. case QETH_CARD_TYPE_UNKNOWN:
  1610. return 1500;
  1611. case QETH_CARD_TYPE_IQD:
  1612. return card->info.max_mtu;
  1613. case QETH_CARD_TYPE_OSAE:
  1614. switch (card->info.link_type) {
  1615. case QETH_LINK_TYPE_HSTR:
  1616. case QETH_LINK_TYPE_LANE_TR:
  1617. return 2000;
  1618. default:
  1619. return 1492;
  1620. }
  1621. default:
  1622. return 1500;
  1623. }
  1624. }
  1625. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1626. {
  1627. switch (cardtype) {
  1628. case QETH_CARD_TYPE_UNKNOWN:
  1629. case QETH_CARD_TYPE_OSAE:
  1630. case QETH_CARD_TYPE_OSN:
  1631. return 61440;
  1632. case QETH_CARD_TYPE_IQD:
  1633. return 57344;
  1634. default:
  1635. return 1500;
  1636. }
  1637. }
  1638. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1639. {
  1640. switch (cardtype) {
  1641. case QETH_CARD_TYPE_IQD:
  1642. return 1;
  1643. default:
  1644. return 0;
  1645. }
  1646. }
  1647. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1648. {
  1649. switch (framesize) {
  1650. case 0x4000:
  1651. return 8192;
  1652. case 0x6000:
  1653. return 16384;
  1654. case 0xa000:
  1655. return 32768;
  1656. case 0xffff:
  1657. return 57344;
  1658. default:
  1659. return 0;
  1660. }
  1661. }
  1662. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1663. {
  1664. switch (card->info.type) {
  1665. case QETH_CARD_TYPE_OSAE:
  1666. return ((mtu >= 576) && (mtu <= 61440));
  1667. case QETH_CARD_TYPE_IQD:
  1668. return ((mtu >= 576) &&
  1669. (mtu <= card->info.max_mtu + 4096 - 32));
  1670. case QETH_CARD_TYPE_OSN:
  1671. case QETH_CARD_TYPE_UNKNOWN:
  1672. default:
  1673. return 1;
  1674. }
  1675. }
  1676. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1677. unsigned long data)
  1678. {
  1679. __u16 mtu, framesize;
  1680. __u16 len;
  1681. __u8 link_type;
  1682. struct qeth_cmd_buffer *iob;
  1683. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1684. iob = (struct qeth_cmd_buffer *) data;
  1685. memcpy(&card->token.ulp_filter_r,
  1686. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1687. QETH_MPC_TOKEN_LENGTH);
  1688. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1689. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1690. mtu = qeth_get_mtu_outof_framesize(framesize);
  1691. if (!mtu) {
  1692. iob->rc = -EINVAL;
  1693. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1694. return 0;
  1695. }
  1696. card->info.max_mtu = mtu;
  1697. card->info.initial_mtu = mtu;
  1698. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1699. } else {
  1700. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1701. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1702. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1703. }
  1704. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1705. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1706. memcpy(&link_type,
  1707. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1708. card->info.link_type = link_type;
  1709. } else
  1710. card->info.link_type = 0;
  1711. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1712. return 0;
  1713. }
  1714. static int qeth_ulp_enable(struct qeth_card *card)
  1715. {
  1716. int rc;
  1717. char prot_type;
  1718. struct qeth_cmd_buffer *iob;
  1719. /*FIXME: trace view callbacks*/
  1720. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1721. iob = qeth_wait_for_buffer(&card->write);
  1722. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1723. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1724. (__u8) card->info.portno;
  1725. if (card->options.layer2)
  1726. if (card->info.type == QETH_CARD_TYPE_OSN)
  1727. prot_type = QETH_PROT_OSN2;
  1728. else
  1729. prot_type = QETH_PROT_LAYER2;
  1730. else
  1731. prot_type = QETH_PROT_TCPIP;
  1732. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1733. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1734. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1735. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1736. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1737. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1738. card->info.portname, 9);
  1739. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1740. qeth_ulp_enable_cb, NULL);
  1741. return rc;
  1742. }
  1743. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1744. unsigned long data)
  1745. {
  1746. struct qeth_cmd_buffer *iob;
  1747. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1748. iob = (struct qeth_cmd_buffer *) data;
  1749. memcpy(&card->token.ulp_connection_r,
  1750. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1751. QETH_MPC_TOKEN_LENGTH);
  1752. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1753. return 0;
  1754. }
  1755. static int qeth_ulp_setup(struct qeth_card *card)
  1756. {
  1757. int rc;
  1758. __u16 temp;
  1759. struct qeth_cmd_buffer *iob;
  1760. struct ccw_dev_id dev_id;
  1761. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1762. iob = qeth_wait_for_buffer(&card->write);
  1763. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1764. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1765. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1766. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1767. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1768. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1769. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1770. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1771. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1772. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1773. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1774. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1775. qeth_ulp_setup_cb, NULL);
  1776. return rc;
  1777. }
  1778. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1779. {
  1780. int i, j;
  1781. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1782. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1783. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1784. return 0;
  1785. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1786. GFP_KERNEL);
  1787. if (!card->qdio.in_q)
  1788. goto out_nomem;
  1789. QETH_DBF_TEXT(SETUP, 2, "inq");
  1790. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1791. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1792. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1793. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1794. card->qdio.in_q->bufs[i].buffer =
  1795. &card->qdio.in_q->qdio_bufs[i];
  1796. /* inbound buffer pool */
  1797. if (qeth_alloc_buffer_pool(card))
  1798. goto out_freeinq;
  1799. /* outbound */
  1800. card->qdio.out_qs =
  1801. kmalloc(card->qdio.no_out_queues *
  1802. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1803. if (!card->qdio.out_qs)
  1804. goto out_freepool;
  1805. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1806. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1807. GFP_KERNEL);
  1808. if (!card->qdio.out_qs[i])
  1809. goto out_freeoutq;
  1810. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1811. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1812. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1813. card->qdio.out_qs[i]->queue_no = i;
  1814. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1815. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1816. card->qdio.out_qs[i]->bufs[j].buffer =
  1817. &card->qdio.out_qs[i]->qdio_bufs[j];
  1818. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1819. skb_list);
  1820. lockdep_set_class(
  1821. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1822. &qdio_out_skb_queue_key);
  1823. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1824. }
  1825. }
  1826. return 0;
  1827. out_freeoutq:
  1828. while (i > 0)
  1829. kfree(card->qdio.out_qs[--i]);
  1830. kfree(card->qdio.out_qs);
  1831. card->qdio.out_qs = NULL;
  1832. out_freepool:
  1833. qeth_free_buffer_pool(card);
  1834. out_freeinq:
  1835. kfree(card->qdio.in_q);
  1836. card->qdio.in_q = NULL;
  1837. out_nomem:
  1838. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1839. return -ENOMEM;
  1840. }
  1841. static void qeth_create_qib_param_field(struct qeth_card *card,
  1842. char *param_field)
  1843. {
  1844. param_field[0] = _ascebc['P'];
  1845. param_field[1] = _ascebc['C'];
  1846. param_field[2] = _ascebc['I'];
  1847. param_field[3] = _ascebc['T'];
  1848. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1849. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1850. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1851. }
  1852. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1853. char *param_field)
  1854. {
  1855. param_field[16] = _ascebc['B'];
  1856. param_field[17] = _ascebc['L'];
  1857. param_field[18] = _ascebc['K'];
  1858. param_field[19] = _ascebc['T'];
  1859. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1860. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1861. *((unsigned int *) (&param_field[28])) =
  1862. card->info.blkt.inter_packet_jumbo;
  1863. }
  1864. static int qeth_qdio_activate(struct qeth_card *card)
  1865. {
  1866. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1867. return qdio_activate(CARD_DDEV(card), 0);
  1868. }
  1869. static int qeth_dm_act(struct qeth_card *card)
  1870. {
  1871. int rc;
  1872. struct qeth_cmd_buffer *iob;
  1873. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1874. iob = qeth_wait_for_buffer(&card->write);
  1875. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1876. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1877. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1878. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1879. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1880. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1881. return rc;
  1882. }
  1883. static int qeth_mpc_initialize(struct qeth_card *card)
  1884. {
  1885. int rc;
  1886. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1887. rc = qeth_issue_next_read(card);
  1888. if (rc) {
  1889. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1890. return rc;
  1891. }
  1892. rc = qeth_cm_enable(card);
  1893. if (rc) {
  1894. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1895. goto out_qdio;
  1896. }
  1897. rc = qeth_cm_setup(card);
  1898. if (rc) {
  1899. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1900. goto out_qdio;
  1901. }
  1902. rc = qeth_ulp_enable(card);
  1903. if (rc) {
  1904. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1905. goto out_qdio;
  1906. }
  1907. rc = qeth_ulp_setup(card);
  1908. if (rc) {
  1909. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1910. goto out_qdio;
  1911. }
  1912. rc = qeth_alloc_qdio_buffers(card);
  1913. if (rc) {
  1914. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1915. goto out_qdio;
  1916. }
  1917. rc = qeth_qdio_establish(card);
  1918. if (rc) {
  1919. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1920. qeth_free_qdio_buffers(card);
  1921. goto out_qdio;
  1922. }
  1923. rc = qeth_qdio_activate(card);
  1924. if (rc) {
  1925. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1926. goto out_qdio;
  1927. }
  1928. rc = qeth_dm_act(card);
  1929. if (rc) {
  1930. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1931. goto out_qdio;
  1932. }
  1933. return 0;
  1934. out_qdio:
  1935. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1936. return rc;
  1937. }
  1938. static void qeth_print_status_with_portname(struct qeth_card *card)
  1939. {
  1940. char dbf_text[15];
  1941. int i;
  1942. sprintf(dbf_text, "%s", card->info.portname + 1);
  1943. for (i = 0; i < 8; i++)
  1944. dbf_text[i] =
  1945. (char) _ebcasc[(__u8) dbf_text[i]];
  1946. dbf_text[8] = 0;
  1947. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1948. "with link type %s (portname: %s)\n",
  1949. CARD_RDEV_ID(card),
  1950. CARD_WDEV_ID(card),
  1951. CARD_DDEV_ID(card),
  1952. qeth_get_cardname(card),
  1953. (card->info.mcl_level[0]) ? " (level: " : "",
  1954. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1955. (card->info.mcl_level[0]) ? ")" : "",
  1956. qeth_get_cardname_short(card),
  1957. dbf_text);
  1958. }
  1959. static void qeth_print_status_no_portname(struct qeth_card *card)
  1960. {
  1961. if (card->info.portname[0])
  1962. PRINT_INFO("Device %s/%s/%s is a%s "
  1963. "card%s%s%s\nwith link type %s "
  1964. "(no portname needed by interface).\n",
  1965. CARD_RDEV_ID(card),
  1966. CARD_WDEV_ID(card),
  1967. CARD_DDEV_ID(card),
  1968. qeth_get_cardname(card),
  1969. (card->info.mcl_level[0]) ? " (level: " : "",
  1970. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1971. (card->info.mcl_level[0]) ? ")" : "",
  1972. qeth_get_cardname_short(card));
  1973. else
  1974. PRINT_INFO("Device %s/%s/%s is a%s "
  1975. "card%s%s%s\nwith link type %s.\n",
  1976. CARD_RDEV_ID(card),
  1977. CARD_WDEV_ID(card),
  1978. CARD_DDEV_ID(card),
  1979. qeth_get_cardname(card),
  1980. (card->info.mcl_level[0]) ? " (level: " : "",
  1981. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1982. (card->info.mcl_level[0]) ? ")" : "",
  1983. qeth_get_cardname_short(card));
  1984. }
  1985. void qeth_print_status_message(struct qeth_card *card)
  1986. {
  1987. switch (card->info.type) {
  1988. case QETH_CARD_TYPE_OSAE:
  1989. /* VM will use a non-zero first character
  1990. * to indicate a HiperSockets like reporting
  1991. * of the level OSA sets the first character to zero
  1992. * */
  1993. if (!card->info.mcl_level[0]) {
  1994. sprintf(card->info.mcl_level, "%02x%02x",
  1995. card->info.mcl_level[2],
  1996. card->info.mcl_level[3]);
  1997. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  1998. break;
  1999. }
  2000. /* fallthrough */
  2001. case QETH_CARD_TYPE_IQD:
  2002. if (card->info.guestlan) {
  2003. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2004. card->info.mcl_level[0]];
  2005. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2006. card->info.mcl_level[1]];
  2007. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2008. card->info.mcl_level[2]];
  2009. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2010. card->info.mcl_level[3]];
  2011. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2012. }
  2013. break;
  2014. default:
  2015. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2016. }
  2017. if (card->info.portname_required)
  2018. qeth_print_status_with_portname(card);
  2019. else
  2020. qeth_print_status_no_portname(card);
  2021. }
  2022. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2023. void qeth_put_buffer_pool_entry(struct qeth_card *card,
  2024. struct qeth_buffer_pool_entry *entry)
  2025. {
  2026. QETH_DBF_TEXT(TRACE, 6, "ptbfplen");
  2027. list_add_tail(&entry->list, &card->qdio.in_buf_pool.entry_list);
  2028. }
  2029. EXPORT_SYMBOL_GPL(qeth_put_buffer_pool_entry);
  2030. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2031. {
  2032. struct qeth_buffer_pool_entry *entry;
  2033. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2034. list_for_each_entry(entry,
  2035. &card->qdio.init_pool.entry_list, init_list) {
  2036. qeth_put_buffer_pool_entry(card, entry);
  2037. }
  2038. }
  2039. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2040. struct qeth_card *card)
  2041. {
  2042. struct list_head *plh;
  2043. struct qeth_buffer_pool_entry *entry;
  2044. int i, free;
  2045. struct page *page;
  2046. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2047. return NULL;
  2048. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2049. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2050. free = 1;
  2051. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2052. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2053. free = 0;
  2054. break;
  2055. }
  2056. }
  2057. if (free) {
  2058. list_del_init(&entry->list);
  2059. return entry;
  2060. }
  2061. }
  2062. /* no free buffer in pool so take first one and swap pages */
  2063. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2064. struct qeth_buffer_pool_entry, list);
  2065. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2066. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2067. page = alloc_page(GFP_ATOMIC);
  2068. if (!page) {
  2069. return NULL;
  2070. } else {
  2071. free_page((unsigned long)entry->elements[i]);
  2072. entry->elements[i] = page_address(page);
  2073. if (card->options.performance_stats)
  2074. card->perf_stats.sg_alloc_page_rx++;
  2075. }
  2076. }
  2077. }
  2078. list_del_init(&entry->list);
  2079. return entry;
  2080. }
  2081. static int qeth_init_input_buffer(struct qeth_card *card,
  2082. struct qeth_qdio_buffer *buf)
  2083. {
  2084. struct qeth_buffer_pool_entry *pool_entry;
  2085. int i;
  2086. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2087. if (!pool_entry)
  2088. return 1;
  2089. /*
  2090. * since the buffer is accessed only from the input_tasklet
  2091. * there shouldn't be a need to synchronize; also, since we use
  2092. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2093. * buffers
  2094. */
  2095. BUG_ON(!pool_entry);
  2096. buf->pool_entry = pool_entry;
  2097. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2098. buf->buffer->element[i].length = PAGE_SIZE;
  2099. buf->buffer->element[i].addr = pool_entry->elements[i];
  2100. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2101. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2102. else
  2103. buf->buffer->element[i].flags = 0;
  2104. }
  2105. return 0;
  2106. }
  2107. int qeth_init_qdio_queues(struct qeth_card *card)
  2108. {
  2109. int i, j;
  2110. int rc;
  2111. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2112. /* inbound queue */
  2113. memset(card->qdio.in_q->qdio_bufs, 0,
  2114. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2115. qeth_initialize_working_pool_list(card);
  2116. /*give only as many buffers to hardware as we have buffer pool entries*/
  2117. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2118. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2119. card->qdio.in_q->next_buf_to_init =
  2120. card->qdio.in_buf_pool.buf_count - 1;
  2121. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2122. card->qdio.in_buf_pool.buf_count - 1, NULL);
  2123. if (rc) {
  2124. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2125. return rc;
  2126. }
  2127. rc = qdio_synchronize(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0);
  2128. if (rc) {
  2129. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2130. return rc;
  2131. }
  2132. /* outbound queue */
  2133. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2134. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2135. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2136. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2137. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2138. &card->qdio.out_qs[i]->bufs[j]);
  2139. }
  2140. card->qdio.out_qs[i]->card = card;
  2141. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2142. card->qdio.out_qs[i]->do_pack = 0;
  2143. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2144. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2145. atomic_set(&card->qdio.out_qs[i]->state,
  2146. QETH_OUT_Q_UNLOCKED);
  2147. }
  2148. return 0;
  2149. }
  2150. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2151. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2152. {
  2153. switch (link_type) {
  2154. case QETH_LINK_TYPE_HSTR:
  2155. return 2;
  2156. default:
  2157. return 1;
  2158. }
  2159. }
  2160. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2161. struct qeth_ipa_cmd *cmd, __u8 command,
  2162. enum qeth_prot_versions prot)
  2163. {
  2164. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2165. cmd->hdr.command = command;
  2166. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2167. cmd->hdr.seqno = card->seqno.ipa;
  2168. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2169. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2170. if (card->options.layer2)
  2171. cmd->hdr.prim_version_no = 2;
  2172. else
  2173. cmd->hdr.prim_version_no = 1;
  2174. cmd->hdr.param_count = 1;
  2175. cmd->hdr.prot_version = prot;
  2176. cmd->hdr.ipa_supported = 0;
  2177. cmd->hdr.ipa_enabled = 0;
  2178. }
  2179. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2180. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2181. {
  2182. struct qeth_cmd_buffer *iob;
  2183. struct qeth_ipa_cmd *cmd;
  2184. iob = qeth_wait_for_buffer(&card->write);
  2185. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2186. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2187. return iob;
  2188. }
  2189. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2190. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2191. char prot_type)
  2192. {
  2193. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2194. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2195. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2196. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2197. }
  2198. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2199. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2200. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2201. unsigned long),
  2202. void *reply_param)
  2203. {
  2204. int rc;
  2205. char prot_type;
  2206. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2207. if (card->options.layer2)
  2208. if (card->info.type == QETH_CARD_TYPE_OSN)
  2209. prot_type = QETH_PROT_OSN2;
  2210. else
  2211. prot_type = QETH_PROT_LAYER2;
  2212. else
  2213. prot_type = QETH_PROT_TCPIP;
  2214. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2215. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2216. iob, reply_cb, reply_param);
  2217. return rc;
  2218. }
  2219. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2220. static int qeth_send_startstoplan(struct qeth_card *card,
  2221. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2222. {
  2223. int rc;
  2224. struct qeth_cmd_buffer *iob;
  2225. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2226. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2227. return rc;
  2228. }
  2229. int qeth_send_startlan(struct qeth_card *card)
  2230. {
  2231. int rc;
  2232. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2233. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2234. return rc;
  2235. }
  2236. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2237. int qeth_send_stoplan(struct qeth_card *card)
  2238. {
  2239. int rc = 0;
  2240. /*
  2241. * TODO: according to the IPA format document page 14,
  2242. * TCP/IP (we!) never issue a STOPLAN
  2243. * is this right ?!?
  2244. */
  2245. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2246. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2247. return rc;
  2248. }
  2249. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2250. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2251. struct qeth_reply *reply, unsigned long data)
  2252. {
  2253. struct qeth_ipa_cmd *cmd;
  2254. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2255. cmd = (struct qeth_ipa_cmd *) data;
  2256. if (cmd->hdr.return_code == 0)
  2257. cmd->hdr.return_code =
  2258. cmd->data.setadapterparms.hdr.return_code;
  2259. return 0;
  2260. }
  2261. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2262. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2263. struct qeth_reply *reply, unsigned long data)
  2264. {
  2265. struct qeth_ipa_cmd *cmd;
  2266. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2267. cmd = (struct qeth_ipa_cmd *) data;
  2268. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2269. card->info.link_type =
  2270. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2271. card->options.adp.supported_funcs =
  2272. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2273. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2274. }
  2275. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2276. __u32 command, __u32 cmdlen)
  2277. {
  2278. struct qeth_cmd_buffer *iob;
  2279. struct qeth_ipa_cmd *cmd;
  2280. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2281. QETH_PROT_IPV4);
  2282. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2283. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2284. cmd->data.setadapterparms.hdr.command_code = command;
  2285. cmd->data.setadapterparms.hdr.used_total = 1;
  2286. cmd->data.setadapterparms.hdr.seq_no = 1;
  2287. return iob;
  2288. }
  2289. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2290. int qeth_query_setadapterparms(struct qeth_card *card)
  2291. {
  2292. int rc;
  2293. struct qeth_cmd_buffer *iob;
  2294. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2295. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2296. sizeof(struct qeth_ipacmd_setadpparms));
  2297. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2298. return rc;
  2299. }
  2300. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2301. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2302. unsigned int siga_error, const char *dbftext)
  2303. {
  2304. if (qdio_error || siga_error) {
  2305. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2306. QETH_DBF_TEXT(QERR, 2, dbftext);
  2307. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2308. buf->element[15].flags & 0xff);
  2309. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2310. buf->element[14].flags & 0xff);
  2311. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2312. QETH_DBF_TEXT_(QERR, 2, " serr=%X", siga_error);
  2313. return 1;
  2314. }
  2315. return 0;
  2316. }
  2317. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2318. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2319. {
  2320. struct qeth_qdio_q *queue = card->qdio.in_q;
  2321. int count;
  2322. int i;
  2323. int rc;
  2324. int newcount = 0;
  2325. QETH_DBF_TEXT(TRACE, 6, "queinbuf");
  2326. count = (index < queue->next_buf_to_init)?
  2327. card->qdio.in_buf_pool.buf_count -
  2328. (queue->next_buf_to_init - index) :
  2329. card->qdio.in_buf_pool.buf_count -
  2330. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2331. /* only requeue at a certain threshold to avoid SIGAs */
  2332. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2333. for (i = queue->next_buf_to_init;
  2334. i < queue->next_buf_to_init + count; ++i) {
  2335. if (qeth_init_input_buffer(card,
  2336. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2337. break;
  2338. } else {
  2339. newcount++;
  2340. }
  2341. }
  2342. if (newcount < count) {
  2343. /* we are in memory shortage so we switch back to
  2344. traditional skb allocation and drop packages */
  2345. if (!atomic_read(&card->force_alloc_skb) &&
  2346. net_ratelimit())
  2347. PRINT_WARN("Switch to alloc skb\n");
  2348. atomic_set(&card->force_alloc_skb, 3);
  2349. count = newcount;
  2350. } else {
  2351. if ((atomic_read(&card->force_alloc_skb) == 1) &&
  2352. net_ratelimit())
  2353. PRINT_WARN("Switch to sg\n");
  2354. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2355. }
  2356. /*
  2357. * according to old code it should be avoided to requeue all
  2358. * 128 buffers in order to benefit from PCI avoidance.
  2359. * this function keeps at least one buffer (the buffer at
  2360. * 'index') un-requeued -> this buffer is the first buffer that
  2361. * will be requeued the next time
  2362. */
  2363. if (card->options.performance_stats) {
  2364. card->perf_stats.inbound_do_qdio_cnt++;
  2365. card->perf_stats.inbound_do_qdio_start_time =
  2366. qeth_get_micros();
  2367. }
  2368. rc = do_QDIO(CARD_DDEV(card),
  2369. QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT,
  2370. 0, queue->next_buf_to_init, count, NULL);
  2371. if (card->options.performance_stats)
  2372. card->perf_stats.inbound_do_qdio_time +=
  2373. qeth_get_micros() -
  2374. card->perf_stats.inbound_do_qdio_start_time;
  2375. if (rc) {
  2376. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2377. "return %i (device %s).\n",
  2378. rc, CARD_DDEV_ID(card));
  2379. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2380. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2381. }
  2382. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2383. QDIO_MAX_BUFFERS_PER_Q;
  2384. }
  2385. }
  2386. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2387. static int qeth_handle_send_error(struct qeth_card *card,
  2388. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err,
  2389. unsigned int siga_err)
  2390. {
  2391. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2392. int cc = siga_err & 3;
  2393. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2394. qeth_check_qdio_errors(buffer->buffer, qdio_err, siga_err, "qouterr");
  2395. switch (cc) {
  2396. case 0:
  2397. if (qdio_err) {
  2398. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2399. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2400. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2401. (u16)qdio_err, (u8)sbalf15);
  2402. return QETH_SEND_ERROR_LINK_FAILURE;
  2403. }
  2404. return QETH_SEND_ERROR_NONE;
  2405. case 2:
  2406. if (siga_err & QDIO_SIGA_ERROR_B_BIT_SET) {
  2407. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2408. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2409. return QETH_SEND_ERROR_KICK_IT;
  2410. }
  2411. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2412. return QETH_SEND_ERROR_RETRY;
  2413. return QETH_SEND_ERROR_LINK_FAILURE;
  2414. /* look at qdio_error and sbalf 15 */
  2415. case 1:
  2416. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2417. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2418. return QETH_SEND_ERROR_LINK_FAILURE;
  2419. case 3:
  2420. default:
  2421. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2422. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2423. return QETH_SEND_ERROR_KICK_IT;
  2424. }
  2425. }
  2426. /*
  2427. * Switched to packing state if the number of used buffers on a queue
  2428. * reaches a certain limit.
  2429. */
  2430. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2431. {
  2432. if (!queue->do_pack) {
  2433. if (atomic_read(&queue->used_buffers)
  2434. >= QETH_HIGH_WATERMARK_PACK){
  2435. /* switch non-PACKING -> PACKING */
  2436. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2437. if (queue->card->options.performance_stats)
  2438. queue->card->perf_stats.sc_dp_p++;
  2439. queue->do_pack = 1;
  2440. }
  2441. }
  2442. }
  2443. /*
  2444. * Switches from packing to non-packing mode. If there is a packing
  2445. * buffer on the queue this buffer will be prepared to be flushed.
  2446. * In that case 1 is returned to inform the caller. If no buffer
  2447. * has to be flushed, zero is returned.
  2448. */
  2449. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2450. {
  2451. struct qeth_qdio_out_buffer *buffer;
  2452. int flush_count = 0;
  2453. if (queue->do_pack) {
  2454. if (atomic_read(&queue->used_buffers)
  2455. <= QETH_LOW_WATERMARK_PACK) {
  2456. /* switch PACKING -> non-PACKING */
  2457. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2458. if (queue->card->options.performance_stats)
  2459. queue->card->perf_stats.sc_p_dp++;
  2460. queue->do_pack = 0;
  2461. /* flush packing buffers */
  2462. buffer = &queue->bufs[queue->next_buf_to_fill];
  2463. if ((atomic_read(&buffer->state) ==
  2464. QETH_QDIO_BUF_EMPTY) &&
  2465. (buffer->next_element_to_fill > 0)) {
  2466. atomic_set(&buffer->state,
  2467. QETH_QDIO_BUF_PRIMED);
  2468. flush_count++;
  2469. queue->next_buf_to_fill =
  2470. (queue->next_buf_to_fill + 1) %
  2471. QDIO_MAX_BUFFERS_PER_Q;
  2472. }
  2473. }
  2474. }
  2475. return flush_count;
  2476. }
  2477. /*
  2478. * Called to flush a packing buffer if no more pci flags are on the queue.
  2479. * Checks if there is a packing buffer and prepares it to be flushed.
  2480. * In that case returns 1, otherwise zero.
  2481. */
  2482. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2483. {
  2484. struct qeth_qdio_out_buffer *buffer;
  2485. buffer = &queue->bufs[queue->next_buf_to_fill];
  2486. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2487. (buffer->next_element_to_fill > 0)) {
  2488. /* it's a packing buffer */
  2489. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2490. queue->next_buf_to_fill =
  2491. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2492. return 1;
  2493. }
  2494. return 0;
  2495. }
  2496. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int,
  2497. int index, int count)
  2498. {
  2499. struct qeth_qdio_out_buffer *buf;
  2500. int rc;
  2501. int i;
  2502. unsigned int qdio_flags;
  2503. QETH_DBF_TEXT(TRACE, 6, "flushbuf");
  2504. for (i = index; i < index + count; ++i) {
  2505. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2506. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2507. SBAL_FLAGS_LAST_ENTRY;
  2508. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2509. continue;
  2510. if (!queue->do_pack) {
  2511. if ((atomic_read(&queue->used_buffers) >=
  2512. (QETH_HIGH_WATERMARK_PACK -
  2513. QETH_WATERMARK_PACK_FUZZ)) &&
  2514. !atomic_read(&queue->set_pci_flags_count)) {
  2515. /* it's likely that we'll go to packing
  2516. * mode soon */
  2517. atomic_inc(&queue->set_pci_flags_count);
  2518. buf->buffer->element[0].flags |= 0x40;
  2519. }
  2520. } else {
  2521. if (!atomic_read(&queue->set_pci_flags_count)) {
  2522. /*
  2523. * there's no outstanding PCI any more, so we
  2524. * have to request a PCI to be sure the the PCI
  2525. * will wake at some time in the future then we
  2526. * can flush packed buffers that might still be
  2527. * hanging around, which can happen if no
  2528. * further send was requested by the stack
  2529. */
  2530. atomic_inc(&queue->set_pci_flags_count);
  2531. buf->buffer->element[0].flags |= 0x40;
  2532. }
  2533. }
  2534. }
  2535. queue->card->dev->trans_start = jiffies;
  2536. if (queue->card->options.performance_stats) {
  2537. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2538. queue->card->perf_stats.outbound_do_qdio_start_time =
  2539. qeth_get_micros();
  2540. }
  2541. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2542. if (under_int)
  2543. qdio_flags |= QDIO_FLAG_UNDER_INTERRUPT;
  2544. if (atomic_read(&queue->set_pci_flags_count))
  2545. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2546. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2547. queue->queue_no, index, count, NULL);
  2548. if (queue->card->options.performance_stats)
  2549. queue->card->perf_stats.outbound_do_qdio_time +=
  2550. qeth_get_micros() -
  2551. queue->card->perf_stats.outbound_do_qdio_start_time;
  2552. if (rc) {
  2553. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2554. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2555. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2556. queue->card->stats.tx_errors += count;
  2557. /* this must not happen under normal circumstances. if it
  2558. * happens something is really wrong -> recover */
  2559. qeth_schedule_recovery(queue->card);
  2560. return;
  2561. }
  2562. atomic_add(count, &queue->used_buffers);
  2563. if (queue->card->options.performance_stats)
  2564. queue->card->perf_stats.bufs_sent += count;
  2565. }
  2566. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2567. {
  2568. int index;
  2569. int flush_cnt = 0;
  2570. int q_was_packing = 0;
  2571. /*
  2572. * check if weed have to switch to non-packing mode or if
  2573. * we have to get a pci flag out on the queue
  2574. */
  2575. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2576. !atomic_read(&queue->set_pci_flags_count)) {
  2577. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2578. QETH_OUT_Q_UNLOCKED) {
  2579. /*
  2580. * If we get in here, there was no action in
  2581. * do_send_packet. So, we check if there is a
  2582. * packing buffer to be flushed here.
  2583. */
  2584. netif_stop_queue(queue->card->dev);
  2585. index = queue->next_buf_to_fill;
  2586. q_was_packing = queue->do_pack;
  2587. /* queue->do_pack may change */
  2588. barrier();
  2589. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2590. if (!flush_cnt &&
  2591. !atomic_read(&queue->set_pci_flags_count))
  2592. flush_cnt +=
  2593. qeth_flush_buffers_on_no_pci(queue);
  2594. if (queue->card->options.performance_stats &&
  2595. q_was_packing)
  2596. queue->card->perf_stats.bufs_sent_pack +=
  2597. flush_cnt;
  2598. if (flush_cnt)
  2599. qeth_flush_buffers(queue, 1, index, flush_cnt);
  2600. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2601. }
  2602. }
  2603. }
  2604. void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status,
  2605. unsigned int qdio_error, unsigned int siga_error,
  2606. unsigned int __queue, int first_element, int count,
  2607. unsigned long card_ptr)
  2608. {
  2609. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2610. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2611. struct qeth_qdio_out_buffer *buffer;
  2612. int i;
  2613. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2614. if (status & QDIO_STATUS_LOOK_FOR_ERROR) {
  2615. if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) {
  2616. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2617. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2618. QETH_DBF_TEXT_(TRACE, 2, "%08x", status);
  2619. netif_stop_queue(card->dev);
  2620. qeth_schedule_recovery(card);
  2621. return;
  2622. }
  2623. }
  2624. if (card->options.performance_stats) {
  2625. card->perf_stats.outbound_handler_cnt++;
  2626. card->perf_stats.outbound_handler_start_time =
  2627. qeth_get_micros();
  2628. }
  2629. for (i = first_element; i < (first_element + count); ++i) {
  2630. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2631. /*we only handle the KICK_IT error by doing a recovery */
  2632. if (qeth_handle_send_error(card, buffer,
  2633. qdio_error, siga_error)
  2634. == QETH_SEND_ERROR_KICK_IT){
  2635. netif_stop_queue(card->dev);
  2636. qeth_schedule_recovery(card);
  2637. return;
  2638. }
  2639. qeth_clear_output_buffer(queue, buffer);
  2640. }
  2641. atomic_sub(count, &queue->used_buffers);
  2642. /* check if we need to do something on this outbound queue */
  2643. if (card->info.type != QETH_CARD_TYPE_IQD)
  2644. qeth_check_outbound_queue(queue);
  2645. netif_wake_queue(queue->card->dev);
  2646. if (card->options.performance_stats)
  2647. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2648. card->perf_stats.outbound_handler_start_time;
  2649. }
  2650. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2651. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2652. {
  2653. int cast_type = RTN_UNSPEC;
  2654. if (card->info.type == QETH_CARD_TYPE_OSN)
  2655. return cast_type;
  2656. if (skb->dst && skb->dst->neighbour) {
  2657. cast_type = skb->dst->neighbour->type;
  2658. if ((cast_type == RTN_BROADCAST) ||
  2659. (cast_type == RTN_MULTICAST) ||
  2660. (cast_type == RTN_ANYCAST))
  2661. return cast_type;
  2662. else
  2663. return RTN_UNSPEC;
  2664. }
  2665. /* try something else */
  2666. if (skb->protocol == ETH_P_IPV6)
  2667. return (skb_network_header(skb)[24] == 0xff) ?
  2668. RTN_MULTICAST : 0;
  2669. else if (skb->protocol == ETH_P_IP)
  2670. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2671. RTN_MULTICAST : 0;
  2672. /* ... */
  2673. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2674. return RTN_BROADCAST;
  2675. else {
  2676. u16 hdr_mac;
  2677. hdr_mac = *((u16 *)skb->data);
  2678. /* tr multicast? */
  2679. switch (card->info.link_type) {
  2680. case QETH_LINK_TYPE_HSTR:
  2681. case QETH_LINK_TYPE_LANE_TR:
  2682. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2683. (hdr_mac == QETH_TR_MAC_C))
  2684. return RTN_MULTICAST;
  2685. break;
  2686. /* eth or so multicast? */
  2687. default:
  2688. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2689. (hdr_mac == QETH_ETH_MAC_V6))
  2690. return RTN_MULTICAST;
  2691. }
  2692. }
  2693. return cast_type;
  2694. }
  2695. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2696. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2697. int ipv, int cast_type)
  2698. {
  2699. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2700. return card->qdio.default_out_queue;
  2701. switch (card->qdio.no_out_queues) {
  2702. case 4:
  2703. if (cast_type && card->info.is_multicast_different)
  2704. return card->info.is_multicast_different &
  2705. (card->qdio.no_out_queues - 1);
  2706. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2707. const u8 tos = ip_hdr(skb)->tos;
  2708. if (card->qdio.do_prio_queueing ==
  2709. QETH_PRIO_Q_ING_TOS) {
  2710. if (tos & IP_TOS_NOTIMPORTANT)
  2711. return 3;
  2712. if (tos & IP_TOS_HIGHRELIABILITY)
  2713. return 2;
  2714. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2715. return 1;
  2716. if (tos & IP_TOS_LOWDELAY)
  2717. return 0;
  2718. }
  2719. if (card->qdio.do_prio_queueing ==
  2720. QETH_PRIO_Q_ING_PREC)
  2721. return 3 - (tos >> 6);
  2722. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2723. /* TODO: IPv6!!! */
  2724. }
  2725. return card->qdio.default_out_queue;
  2726. case 1: /* fallthrough for single-out-queue 1920-device */
  2727. default:
  2728. return card->qdio.default_out_queue;
  2729. }
  2730. }
  2731. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2732. static void __qeth_free_new_skb(struct sk_buff *orig_skb,
  2733. struct sk_buff *new_skb)
  2734. {
  2735. if (orig_skb != new_skb)
  2736. dev_kfree_skb_any(new_skb);
  2737. }
  2738. static inline struct sk_buff *qeth_realloc_headroom(struct qeth_card *card,
  2739. struct sk_buff *skb, int size)
  2740. {
  2741. struct sk_buff *new_skb = skb;
  2742. if (skb_headroom(skb) >= size)
  2743. return skb;
  2744. new_skb = skb_realloc_headroom(skb, size);
  2745. if (!new_skb)
  2746. PRINT_ERR("Could not realloc headroom for qeth_hdr "
  2747. "on interface %s", QETH_CARD_IFNAME(card));
  2748. return new_skb;
  2749. }
  2750. struct sk_buff *qeth_prepare_skb(struct qeth_card *card, struct sk_buff *skb,
  2751. struct qeth_hdr **hdr)
  2752. {
  2753. struct sk_buff *new_skb;
  2754. QETH_DBF_TEXT(TRACE, 6, "prepskb");
  2755. new_skb = qeth_realloc_headroom(card, skb,
  2756. sizeof(struct qeth_hdr));
  2757. if (!new_skb)
  2758. return NULL;
  2759. *hdr = ((struct qeth_hdr *)qeth_push_skb(card, new_skb,
  2760. sizeof(struct qeth_hdr)));
  2761. if (*hdr == NULL) {
  2762. __qeth_free_new_skb(skb, new_skb);
  2763. return NULL;
  2764. }
  2765. return new_skb;
  2766. }
  2767. EXPORT_SYMBOL_GPL(qeth_prepare_skb);
  2768. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2769. struct sk_buff *skb, int elems)
  2770. {
  2771. int elements_needed = 0;
  2772. if (skb_shinfo(skb)->nr_frags > 0)
  2773. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2774. if (elements_needed == 0)
  2775. elements_needed = 1 + (((((unsigned long) hdr) % PAGE_SIZE)
  2776. + skb->len) >> PAGE_SHIFT);
  2777. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2778. PRINT_ERR("Invalid size of IP packet "
  2779. "(Number=%d / Length=%d). Discarded.\n",
  2780. (elements_needed+elems), skb->len);
  2781. return 0;
  2782. }
  2783. return elements_needed;
  2784. }
  2785. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2786. static void __qeth_fill_buffer(struct sk_buff *skb, struct qdio_buffer *buffer,
  2787. int is_tso, int *next_element_to_fill)
  2788. {
  2789. int length = skb->len;
  2790. int length_here;
  2791. int element;
  2792. char *data;
  2793. int first_lap ;
  2794. element = *next_element_to_fill;
  2795. data = skb->data;
  2796. first_lap = (is_tso == 0 ? 1 : 0);
  2797. while (length > 0) {
  2798. /* length_here is the remaining amount of data in this page */
  2799. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2800. if (length < length_here)
  2801. length_here = length;
  2802. buffer->element[element].addr = data;
  2803. buffer->element[element].length = length_here;
  2804. length -= length_here;
  2805. if (!length) {
  2806. if (first_lap)
  2807. buffer->element[element].flags = 0;
  2808. else
  2809. buffer->element[element].flags =
  2810. SBAL_FLAGS_LAST_FRAG;
  2811. } else {
  2812. if (first_lap)
  2813. buffer->element[element].flags =
  2814. SBAL_FLAGS_FIRST_FRAG;
  2815. else
  2816. buffer->element[element].flags =
  2817. SBAL_FLAGS_MIDDLE_FRAG;
  2818. }
  2819. data += length_here;
  2820. element++;
  2821. first_lap = 0;
  2822. }
  2823. *next_element_to_fill = element;
  2824. }
  2825. static int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2826. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb)
  2827. {
  2828. struct qdio_buffer *buffer;
  2829. struct qeth_hdr_tso *hdr;
  2830. int flush_cnt = 0, hdr_len, large_send = 0;
  2831. QETH_DBF_TEXT(TRACE, 6, "qdfillbf");
  2832. buffer = buf->buffer;
  2833. atomic_inc(&skb->users);
  2834. skb_queue_tail(&buf->skb_list, skb);
  2835. hdr = (struct qeth_hdr_tso *) skb->data;
  2836. /*check first on TSO ....*/
  2837. if (hdr->hdr.hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2838. int element = buf->next_element_to_fill;
  2839. hdr_len = sizeof(struct qeth_hdr_tso) + hdr->ext.dg_hdr_len;
  2840. /*fill first buffer entry only with header information */
  2841. buffer->element[element].addr = skb->data;
  2842. buffer->element[element].length = hdr_len;
  2843. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2844. buf->next_element_to_fill++;
  2845. skb->data += hdr_len;
  2846. skb->len -= hdr_len;
  2847. large_send = 1;
  2848. }
  2849. if (skb_shinfo(skb)->nr_frags == 0)
  2850. __qeth_fill_buffer(skb, buffer, large_send,
  2851. (int *)&buf->next_element_to_fill);
  2852. else
  2853. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2854. (int *)&buf->next_element_to_fill);
  2855. if (!queue->do_pack) {
  2856. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2857. /* set state to PRIMED -> will be flushed */
  2858. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2859. flush_cnt = 1;
  2860. } else {
  2861. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2862. if (queue->card->options.performance_stats)
  2863. queue->card->perf_stats.skbs_sent_pack++;
  2864. if (buf->next_element_to_fill >=
  2865. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2866. /*
  2867. * packed buffer if full -> set state PRIMED
  2868. * -> will be flushed
  2869. */
  2870. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2871. flush_cnt = 1;
  2872. }
  2873. }
  2874. return flush_cnt;
  2875. }
  2876. int qeth_do_send_packet_fast(struct qeth_card *card,
  2877. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2878. struct qeth_hdr *hdr, int elements_needed,
  2879. struct qeth_eddp_context *ctx)
  2880. {
  2881. struct qeth_qdio_out_buffer *buffer;
  2882. int buffers_needed = 0;
  2883. int flush_cnt = 0;
  2884. int index;
  2885. QETH_DBF_TEXT(TRACE, 6, "dosndpfa");
  2886. /* spin until we get the queue ... */
  2887. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2888. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2889. /* ... now we've got the queue */
  2890. index = queue->next_buf_to_fill;
  2891. buffer = &queue->bufs[queue->next_buf_to_fill];
  2892. /*
  2893. * check if buffer is empty to make sure that we do not 'overtake'
  2894. * ourselves and try to fill a buffer that is already primed
  2895. */
  2896. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2897. goto out;
  2898. if (ctx == NULL)
  2899. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2900. QDIO_MAX_BUFFERS_PER_Q;
  2901. else {
  2902. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2903. ctx);
  2904. if (buffers_needed < 0)
  2905. goto out;
  2906. queue->next_buf_to_fill =
  2907. (queue->next_buf_to_fill + buffers_needed) %
  2908. QDIO_MAX_BUFFERS_PER_Q;
  2909. }
  2910. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2911. if (ctx == NULL) {
  2912. qeth_fill_buffer(queue, buffer, skb);
  2913. qeth_flush_buffers(queue, 0, index, 1);
  2914. } else {
  2915. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2916. WARN_ON(buffers_needed != flush_cnt);
  2917. qeth_flush_buffers(queue, 0, index, flush_cnt);
  2918. }
  2919. return 0;
  2920. out:
  2921. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2922. return -EBUSY;
  2923. }
  2924. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2925. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2926. struct sk_buff *skb, struct qeth_hdr *hdr,
  2927. int elements_needed, struct qeth_eddp_context *ctx)
  2928. {
  2929. struct qeth_qdio_out_buffer *buffer;
  2930. int start_index;
  2931. int flush_count = 0;
  2932. int do_pack = 0;
  2933. int tmp;
  2934. int rc = 0;
  2935. QETH_DBF_TEXT(TRACE, 6, "dosndpkt");
  2936. /* spin until we get the queue ... */
  2937. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2938. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2939. start_index = queue->next_buf_to_fill;
  2940. buffer = &queue->bufs[queue->next_buf_to_fill];
  2941. /*
  2942. * check if buffer is empty to make sure that we do not 'overtake'
  2943. * ourselves and try to fill a buffer that is already primed
  2944. */
  2945. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2946. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2947. return -EBUSY;
  2948. }
  2949. /* check if we need to switch packing state of this queue */
  2950. qeth_switch_to_packing_if_needed(queue);
  2951. if (queue->do_pack) {
  2952. do_pack = 1;
  2953. if (ctx == NULL) {
  2954. /* does packet fit in current buffer? */
  2955. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2956. buffer->next_element_to_fill) < elements_needed) {
  2957. /* ... no -> set state PRIMED */
  2958. atomic_set(&buffer->state,
  2959. QETH_QDIO_BUF_PRIMED);
  2960. flush_count++;
  2961. queue->next_buf_to_fill =
  2962. (queue->next_buf_to_fill + 1) %
  2963. QDIO_MAX_BUFFERS_PER_Q;
  2964. buffer = &queue->bufs[queue->next_buf_to_fill];
  2965. /* we did a step forward, so check buffer state
  2966. * again */
  2967. if (atomic_read(&buffer->state) !=
  2968. QETH_QDIO_BUF_EMPTY){
  2969. qeth_flush_buffers(queue, 0,
  2970. start_index, flush_count);
  2971. atomic_set(&queue->state,
  2972. QETH_OUT_Q_UNLOCKED);
  2973. return -EBUSY;
  2974. }
  2975. }
  2976. } else {
  2977. /* check if we have enough elements (including following
  2978. * free buffers) to handle eddp context */
  2979. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2980. < 0) {
  2981. if (net_ratelimit())
  2982. PRINT_WARN("eddp tx_dropped 1\n");
  2983. rc = -EBUSY;
  2984. goto out;
  2985. }
  2986. }
  2987. }
  2988. if (ctx == NULL)
  2989. tmp = qeth_fill_buffer(queue, buffer, skb);
  2990. else {
  2991. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2992. queue->next_buf_to_fill);
  2993. if (tmp < 0) {
  2994. PRINT_ERR("eddp tx_dropped 2\n");
  2995. rc = -EBUSY;
  2996. goto out;
  2997. }
  2998. }
  2999. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3000. QDIO_MAX_BUFFERS_PER_Q;
  3001. flush_count += tmp;
  3002. out:
  3003. if (flush_count)
  3004. qeth_flush_buffers(queue, 0, start_index, flush_count);
  3005. else if (!atomic_read(&queue->set_pci_flags_count))
  3006. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3007. /*
  3008. * queue->state will go from LOCKED -> UNLOCKED or from
  3009. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3010. * (switch packing state or flush buffer to get another pci flag out).
  3011. * In that case we will enter this loop
  3012. */
  3013. while (atomic_dec_return(&queue->state)) {
  3014. flush_count = 0;
  3015. start_index = queue->next_buf_to_fill;
  3016. /* check if we can go back to non-packing state */
  3017. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3018. /*
  3019. * check if we need to flush a packing buffer to get a pci
  3020. * flag out on the queue
  3021. */
  3022. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3023. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3024. if (flush_count)
  3025. qeth_flush_buffers(queue, 0, start_index, flush_count);
  3026. }
  3027. /* at this point the queue is UNLOCKED again */
  3028. if (queue->card->options.performance_stats && do_pack)
  3029. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3030. return rc;
  3031. }
  3032. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3033. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3034. struct qeth_reply *reply, unsigned long data)
  3035. {
  3036. struct qeth_ipa_cmd *cmd;
  3037. struct qeth_ipacmd_setadpparms *setparms;
  3038. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  3039. cmd = (struct qeth_ipa_cmd *) data;
  3040. setparms = &(cmd->data.setadapterparms);
  3041. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3042. if (cmd->hdr.return_code) {
  3043. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3044. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3045. }
  3046. card->info.promisc_mode = setparms->data.mode;
  3047. return 0;
  3048. }
  3049. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3050. {
  3051. enum qeth_ipa_promisc_modes mode;
  3052. struct net_device *dev = card->dev;
  3053. struct qeth_cmd_buffer *iob;
  3054. struct qeth_ipa_cmd *cmd;
  3055. QETH_DBF_TEXT(TRACE, 4, "setprom");
  3056. if (((dev->flags & IFF_PROMISC) &&
  3057. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3058. (!(dev->flags & IFF_PROMISC) &&
  3059. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3060. return;
  3061. mode = SET_PROMISC_MODE_OFF;
  3062. if (dev->flags & IFF_PROMISC)
  3063. mode = SET_PROMISC_MODE_ON;
  3064. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3065. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3066. sizeof(struct qeth_ipacmd_setadpparms));
  3067. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3068. cmd->data.setadapterparms.data.mode = mode;
  3069. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3070. }
  3071. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3072. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3073. {
  3074. struct qeth_card *card;
  3075. char dbf_text[15];
  3076. card = netdev_priv(dev);
  3077. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3078. sprintf(dbf_text, "%8x", new_mtu);
  3079. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3080. if (new_mtu < 64)
  3081. return -EINVAL;
  3082. if (new_mtu > 65535)
  3083. return -EINVAL;
  3084. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3085. (!qeth_mtu_is_valid(card, new_mtu)))
  3086. return -EINVAL;
  3087. dev->mtu = new_mtu;
  3088. return 0;
  3089. }
  3090. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3091. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3092. {
  3093. struct qeth_card *card;
  3094. card = netdev_priv(dev);
  3095. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3096. return &card->stats;
  3097. }
  3098. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3099. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3100. struct qeth_reply *reply, unsigned long data)
  3101. {
  3102. struct qeth_ipa_cmd *cmd;
  3103. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3104. cmd = (struct qeth_ipa_cmd *) data;
  3105. if (!card->options.layer2 ||
  3106. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3107. memcpy(card->dev->dev_addr,
  3108. &cmd->data.setadapterparms.data.change_addr.addr,
  3109. OSA_ADDR_LEN);
  3110. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3111. }
  3112. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3113. return 0;
  3114. }
  3115. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3116. {
  3117. int rc;
  3118. struct qeth_cmd_buffer *iob;
  3119. struct qeth_ipa_cmd *cmd;
  3120. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3121. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3122. sizeof(struct qeth_ipacmd_setadpparms));
  3123. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3124. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3125. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3126. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3127. card->dev->dev_addr, OSA_ADDR_LEN);
  3128. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3129. NULL);
  3130. return rc;
  3131. }
  3132. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3133. void qeth_tx_timeout(struct net_device *dev)
  3134. {
  3135. struct qeth_card *card;
  3136. card = netdev_priv(dev);
  3137. card->stats.tx_errors++;
  3138. qeth_schedule_recovery(card);
  3139. }
  3140. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3141. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3142. {
  3143. struct qeth_card *card = netdev_priv(dev);
  3144. int rc = 0;
  3145. switch (regnum) {
  3146. case MII_BMCR: /* Basic mode control register */
  3147. rc = BMCR_FULLDPLX;
  3148. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3149. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3150. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3151. rc |= BMCR_SPEED100;
  3152. break;
  3153. case MII_BMSR: /* Basic mode status register */
  3154. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3155. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3156. BMSR_100BASE4;
  3157. break;
  3158. case MII_PHYSID1: /* PHYS ID 1 */
  3159. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3160. dev->dev_addr[2];
  3161. rc = (rc >> 5) & 0xFFFF;
  3162. break;
  3163. case MII_PHYSID2: /* PHYS ID 2 */
  3164. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3165. break;
  3166. case MII_ADVERTISE: /* Advertisement control reg */
  3167. rc = ADVERTISE_ALL;
  3168. break;
  3169. case MII_LPA: /* Link partner ability reg */
  3170. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3171. LPA_100BASE4 | LPA_LPACK;
  3172. break;
  3173. case MII_EXPANSION: /* Expansion register */
  3174. break;
  3175. case MII_DCOUNTER: /* disconnect counter */
  3176. break;
  3177. case MII_FCSCOUNTER: /* false carrier counter */
  3178. break;
  3179. case MII_NWAYTEST: /* N-way auto-neg test register */
  3180. break;
  3181. case MII_RERRCOUNTER: /* rx error counter */
  3182. rc = card->stats.rx_errors;
  3183. break;
  3184. case MII_SREVISION: /* silicon revision */
  3185. break;
  3186. case MII_RESV1: /* reserved 1 */
  3187. break;
  3188. case MII_LBRERROR: /* loopback, rx, bypass error */
  3189. break;
  3190. case MII_PHYADDR: /* physical address */
  3191. break;
  3192. case MII_RESV2: /* reserved 2 */
  3193. break;
  3194. case MII_TPISTATUS: /* TPI status for 10mbps */
  3195. break;
  3196. case MII_NCONFIG: /* network interface config */
  3197. break;
  3198. default:
  3199. break;
  3200. }
  3201. return rc;
  3202. }
  3203. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3204. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3205. struct qeth_cmd_buffer *iob, int len,
  3206. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3207. unsigned long),
  3208. void *reply_param)
  3209. {
  3210. u16 s1, s2;
  3211. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3212. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3213. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3214. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3215. /* adjust PDU length fields in IPA_PDU_HEADER */
  3216. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3217. s2 = (u32) len;
  3218. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3219. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3220. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3221. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3222. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3223. reply_cb, reply_param);
  3224. }
  3225. static int qeth_snmp_command_cb(struct qeth_card *card,
  3226. struct qeth_reply *reply, unsigned long sdata)
  3227. {
  3228. struct qeth_ipa_cmd *cmd;
  3229. struct qeth_arp_query_info *qinfo;
  3230. struct qeth_snmp_cmd *snmp;
  3231. unsigned char *data;
  3232. __u16 data_len;
  3233. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3234. cmd = (struct qeth_ipa_cmd *) sdata;
  3235. data = (unsigned char *)((char *)cmd - reply->offset);
  3236. qinfo = (struct qeth_arp_query_info *) reply->param;
  3237. snmp = &cmd->data.setadapterparms.data.snmp;
  3238. if (cmd->hdr.return_code) {
  3239. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3240. return 0;
  3241. }
  3242. if (cmd->data.setadapterparms.hdr.return_code) {
  3243. cmd->hdr.return_code =
  3244. cmd->data.setadapterparms.hdr.return_code;
  3245. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3246. return 0;
  3247. }
  3248. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3249. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3250. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3251. else
  3252. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3253. /* check if there is enough room in userspace */
  3254. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3255. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3256. cmd->hdr.return_code = -ENOMEM;
  3257. return 0;
  3258. }
  3259. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3260. cmd->data.setadapterparms.hdr.used_total);
  3261. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3262. cmd->data.setadapterparms.hdr.seq_no);
  3263. /*copy entries to user buffer*/
  3264. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3265. memcpy(qinfo->udata + qinfo->udata_offset,
  3266. (char *)snmp,
  3267. data_len + offsetof(struct qeth_snmp_cmd, data));
  3268. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3269. } else {
  3270. memcpy(qinfo->udata + qinfo->udata_offset,
  3271. (char *)&snmp->request, data_len);
  3272. }
  3273. qinfo->udata_offset += data_len;
  3274. /* check if all replies received ... */
  3275. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3276. cmd->data.setadapterparms.hdr.used_total);
  3277. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3278. cmd->data.setadapterparms.hdr.seq_no);
  3279. if (cmd->data.setadapterparms.hdr.seq_no <
  3280. cmd->data.setadapterparms.hdr.used_total)
  3281. return 1;
  3282. return 0;
  3283. }
  3284. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3285. {
  3286. struct qeth_cmd_buffer *iob;
  3287. struct qeth_ipa_cmd *cmd;
  3288. struct qeth_snmp_ureq *ureq;
  3289. int req_len;
  3290. struct qeth_arp_query_info qinfo = {0, };
  3291. int rc = 0;
  3292. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3293. if (card->info.guestlan)
  3294. return -EOPNOTSUPP;
  3295. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3296. (!card->options.layer2)) {
  3297. PRINT_WARN("SNMP Query MIBS not supported "
  3298. "on %s!\n", QETH_CARD_IFNAME(card));
  3299. return -EOPNOTSUPP;
  3300. }
  3301. /* skip 4 bytes (data_len struct member) to get req_len */
  3302. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3303. return -EFAULT;
  3304. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3305. if (!ureq) {
  3306. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3307. return -ENOMEM;
  3308. }
  3309. if (copy_from_user(ureq, udata,
  3310. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3311. kfree(ureq);
  3312. return -EFAULT;
  3313. }
  3314. qinfo.udata_len = ureq->hdr.data_len;
  3315. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3316. if (!qinfo.udata) {
  3317. kfree(ureq);
  3318. return -ENOMEM;
  3319. }
  3320. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3321. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3322. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3323. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3324. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3325. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3326. qeth_snmp_command_cb, (void *)&qinfo);
  3327. if (rc)
  3328. PRINT_WARN("SNMP command failed on %s: (0x%x)\n",
  3329. QETH_CARD_IFNAME(card), rc);
  3330. else {
  3331. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3332. rc = -EFAULT;
  3333. }
  3334. kfree(ureq);
  3335. kfree(qinfo.udata);
  3336. return rc;
  3337. }
  3338. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3339. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3340. {
  3341. switch (card->info.type) {
  3342. case QETH_CARD_TYPE_IQD:
  3343. return 2;
  3344. default:
  3345. return 0;
  3346. }
  3347. }
  3348. static int qeth_qdio_establish(struct qeth_card *card)
  3349. {
  3350. struct qdio_initialize init_data;
  3351. char *qib_param_field;
  3352. struct qdio_buffer **in_sbal_ptrs;
  3353. struct qdio_buffer **out_sbal_ptrs;
  3354. int i, j, k;
  3355. int rc = 0;
  3356. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3357. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3358. GFP_KERNEL);
  3359. if (!qib_param_field)
  3360. return -ENOMEM;
  3361. qeth_create_qib_param_field(card, qib_param_field);
  3362. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3363. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3364. GFP_KERNEL);
  3365. if (!in_sbal_ptrs) {
  3366. kfree(qib_param_field);
  3367. return -ENOMEM;
  3368. }
  3369. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3370. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3371. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3372. out_sbal_ptrs =
  3373. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3374. sizeof(void *), GFP_KERNEL);
  3375. if (!out_sbal_ptrs) {
  3376. kfree(in_sbal_ptrs);
  3377. kfree(qib_param_field);
  3378. return -ENOMEM;
  3379. }
  3380. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3381. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3382. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3383. card->qdio.out_qs[i]->bufs[j].buffer);
  3384. }
  3385. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3386. init_data.cdev = CARD_DDEV(card);
  3387. init_data.q_format = qeth_get_qdio_q_format(card);
  3388. init_data.qib_param_field_format = 0;
  3389. init_data.qib_param_field = qib_param_field;
  3390. init_data.min_input_threshold = QETH_MIN_INPUT_THRESHOLD;
  3391. init_data.max_input_threshold = QETH_MAX_INPUT_THRESHOLD;
  3392. init_data.min_output_threshold = QETH_MIN_OUTPUT_THRESHOLD;
  3393. init_data.max_output_threshold = QETH_MAX_OUTPUT_THRESHOLD;
  3394. init_data.no_input_qs = 1;
  3395. init_data.no_output_qs = card->qdio.no_out_queues;
  3396. init_data.input_handler = card->discipline.input_handler;
  3397. init_data.output_handler = card->discipline.output_handler;
  3398. init_data.int_parm = (unsigned long) card;
  3399. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3400. QDIO_OUTBOUND_0COPY_SBALS |
  3401. QDIO_USE_OUTBOUND_PCIS;
  3402. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3403. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3404. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3405. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3406. rc = qdio_initialize(&init_data);
  3407. if (rc)
  3408. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3409. }
  3410. kfree(out_sbal_ptrs);
  3411. kfree(in_sbal_ptrs);
  3412. kfree(qib_param_field);
  3413. return rc;
  3414. }
  3415. static void qeth_core_free_card(struct qeth_card *card)
  3416. {
  3417. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3418. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3419. qeth_clean_channel(&card->read);
  3420. qeth_clean_channel(&card->write);
  3421. if (card->dev)
  3422. free_netdev(card->dev);
  3423. kfree(card->ip_tbd_list);
  3424. qeth_free_qdio_buffers(card);
  3425. kfree(card);
  3426. }
  3427. static struct ccw_device_id qeth_ids[] = {
  3428. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3429. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3430. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3431. {},
  3432. };
  3433. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3434. static struct ccw_driver qeth_ccw_driver = {
  3435. .name = "qeth",
  3436. .ids = qeth_ids,
  3437. .probe = ccwgroup_probe_ccwdev,
  3438. .remove = ccwgroup_remove_ccwdev,
  3439. };
  3440. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3441. unsigned long driver_id)
  3442. {
  3443. const char *start, *end;
  3444. char bus_ids[3][BUS_ID_SIZE], *argv[3];
  3445. int i;
  3446. start = buf;
  3447. for (i = 0; i < 3; i++) {
  3448. static const char delim[] = { ',', ',', '\n' };
  3449. int len;
  3450. end = strchr(start, delim[i]);
  3451. if (!end)
  3452. return -EINVAL;
  3453. len = min_t(ptrdiff_t, BUS_ID_SIZE, end - start);
  3454. strncpy(bus_ids[i], start, len);
  3455. bus_ids[i][len] = '\0';
  3456. start = end + 1;
  3457. argv[i] = bus_ids[i];
  3458. }
  3459. return (ccwgroup_create(root_dev, driver_id,
  3460. &qeth_ccw_driver, 3, argv));
  3461. }
  3462. int qeth_core_hardsetup_card(struct qeth_card *card)
  3463. {
  3464. int retries = 3;
  3465. int mpno;
  3466. int rc;
  3467. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3468. atomic_set(&card->force_alloc_skb, 0);
  3469. retry:
  3470. if (retries < 3) {
  3471. PRINT_WARN("Retrying to do IDX activates.\n");
  3472. ccw_device_set_offline(CARD_DDEV(card));
  3473. ccw_device_set_offline(CARD_WDEV(card));
  3474. ccw_device_set_offline(CARD_RDEV(card));
  3475. ccw_device_set_online(CARD_RDEV(card));
  3476. ccw_device_set_online(CARD_WDEV(card));
  3477. ccw_device_set_online(CARD_DDEV(card));
  3478. }
  3479. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3480. if (rc == -ERESTARTSYS) {
  3481. QETH_DBF_TEXT(SETUP, 2, "break1");
  3482. return rc;
  3483. } else if (rc) {
  3484. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3485. if (--retries < 0)
  3486. goto out;
  3487. else
  3488. goto retry;
  3489. }
  3490. rc = qeth_get_unitaddr(card);
  3491. if (rc) {
  3492. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3493. return rc;
  3494. }
  3495. mpno = QETH_MAX_PORTNO;
  3496. if (card->info.portno > mpno) {
  3497. PRINT_ERR("Device %s does not offer port number %d \n.",
  3498. CARD_BUS_ID(card), card->info.portno);
  3499. rc = -ENODEV;
  3500. goto out;
  3501. }
  3502. qeth_init_tokens(card);
  3503. qeth_init_func_level(card);
  3504. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3505. if (rc == -ERESTARTSYS) {
  3506. QETH_DBF_TEXT(SETUP, 2, "break2");
  3507. return rc;
  3508. } else if (rc) {
  3509. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3510. if (--retries < 0)
  3511. goto out;
  3512. else
  3513. goto retry;
  3514. }
  3515. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3516. if (rc == -ERESTARTSYS) {
  3517. QETH_DBF_TEXT(SETUP, 2, "break3");
  3518. return rc;
  3519. } else if (rc) {
  3520. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3521. if (--retries < 0)
  3522. goto out;
  3523. else
  3524. goto retry;
  3525. }
  3526. rc = qeth_mpc_initialize(card);
  3527. if (rc) {
  3528. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3529. goto out;
  3530. }
  3531. return 0;
  3532. out:
  3533. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3534. return rc;
  3535. }
  3536. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3537. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3538. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3539. {
  3540. struct page *page = virt_to_page(element->addr);
  3541. if (*pskb == NULL) {
  3542. /* the upper protocol layers assume that there is data in the
  3543. * skb itself. Copy a small amount (64 bytes) to make them
  3544. * happy. */
  3545. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3546. if (!(*pskb))
  3547. return -ENOMEM;
  3548. skb_reserve(*pskb, ETH_HLEN);
  3549. if (data_len <= 64) {
  3550. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3551. data_len);
  3552. } else {
  3553. get_page(page);
  3554. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3555. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3556. data_len - 64);
  3557. (*pskb)->data_len += data_len - 64;
  3558. (*pskb)->len += data_len - 64;
  3559. (*pskb)->truesize += data_len - 64;
  3560. (*pfrag)++;
  3561. }
  3562. } else {
  3563. get_page(page);
  3564. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3565. (*pskb)->data_len += data_len;
  3566. (*pskb)->len += data_len;
  3567. (*pskb)->truesize += data_len;
  3568. (*pfrag)++;
  3569. }
  3570. return 0;
  3571. }
  3572. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3573. struct qdio_buffer *buffer,
  3574. struct qdio_buffer_element **__element, int *__offset,
  3575. struct qeth_hdr **hdr)
  3576. {
  3577. struct qdio_buffer_element *element = *__element;
  3578. int offset = *__offset;
  3579. struct sk_buff *skb = NULL;
  3580. int skb_len;
  3581. void *data_ptr;
  3582. int data_len;
  3583. int headroom = 0;
  3584. int use_rx_sg = 0;
  3585. int frag = 0;
  3586. QETH_DBF_TEXT(TRACE, 6, "nextskb");
  3587. /* qeth_hdr must not cross element boundaries */
  3588. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3589. if (qeth_is_last_sbale(element))
  3590. return NULL;
  3591. element++;
  3592. offset = 0;
  3593. if (element->length < sizeof(struct qeth_hdr))
  3594. return NULL;
  3595. }
  3596. *hdr = element->addr + offset;
  3597. offset += sizeof(struct qeth_hdr);
  3598. if (card->options.layer2) {
  3599. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3600. skb_len = (*hdr)->hdr.osn.pdu_length;
  3601. headroom = sizeof(struct qeth_hdr);
  3602. } else {
  3603. skb_len = (*hdr)->hdr.l2.pkt_length;
  3604. }
  3605. } else {
  3606. skb_len = (*hdr)->hdr.l3.length;
  3607. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3608. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3609. headroom = TR_HLEN;
  3610. else
  3611. headroom = ETH_HLEN;
  3612. }
  3613. if (!skb_len)
  3614. return NULL;
  3615. if ((skb_len >= card->options.rx_sg_cb) &&
  3616. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3617. (!atomic_read(&card->force_alloc_skb))) {
  3618. use_rx_sg = 1;
  3619. } else {
  3620. skb = dev_alloc_skb(skb_len + headroom);
  3621. if (!skb)
  3622. goto no_mem;
  3623. if (headroom)
  3624. skb_reserve(skb, headroom);
  3625. }
  3626. data_ptr = element->addr + offset;
  3627. while (skb_len) {
  3628. data_len = min(skb_len, (int)(element->length - offset));
  3629. if (data_len) {
  3630. if (use_rx_sg) {
  3631. if (qeth_create_skb_frag(element, &skb, offset,
  3632. &frag, data_len))
  3633. goto no_mem;
  3634. } else {
  3635. memcpy(skb_put(skb, data_len), data_ptr,
  3636. data_len);
  3637. }
  3638. }
  3639. skb_len -= data_len;
  3640. if (skb_len) {
  3641. if (qeth_is_last_sbale(element)) {
  3642. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3643. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3644. CARD_BUS_ID(card));
  3645. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3646. QETH_DBF_TEXT_(QERR, 2, "%s",
  3647. CARD_BUS_ID(card));
  3648. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3649. dev_kfree_skb_any(skb);
  3650. card->stats.rx_errors++;
  3651. return NULL;
  3652. }
  3653. element++;
  3654. offset = 0;
  3655. data_ptr = element->addr;
  3656. } else {
  3657. offset += data_len;
  3658. }
  3659. }
  3660. *__element = element;
  3661. *__offset = offset;
  3662. if (use_rx_sg && card->options.performance_stats) {
  3663. card->perf_stats.sg_skbs_rx++;
  3664. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3665. }
  3666. return skb;
  3667. no_mem:
  3668. if (net_ratelimit()) {
  3669. PRINT_WARN("No memory for packet received on %s.\n",
  3670. QETH_CARD_IFNAME(card));
  3671. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3672. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3673. }
  3674. card->stats.rx_dropped++;
  3675. return NULL;
  3676. }
  3677. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3678. static void qeth_unregister_dbf_views(void)
  3679. {
  3680. int x;
  3681. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3682. debug_unregister(qeth_dbf[x].id);
  3683. qeth_dbf[x].id = NULL;
  3684. }
  3685. }
  3686. static int qeth_register_dbf_views(void)
  3687. {
  3688. int ret;
  3689. int x;
  3690. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3691. /* register the areas */
  3692. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3693. qeth_dbf[x].pages,
  3694. qeth_dbf[x].areas,
  3695. qeth_dbf[x].len);
  3696. if (qeth_dbf[x].id == NULL) {
  3697. qeth_unregister_dbf_views();
  3698. return -ENOMEM;
  3699. }
  3700. /* register a view */
  3701. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3702. if (ret) {
  3703. qeth_unregister_dbf_views();
  3704. return ret;
  3705. }
  3706. /* set a passing level */
  3707. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3708. }
  3709. return 0;
  3710. }
  3711. int qeth_core_load_discipline(struct qeth_card *card,
  3712. enum qeth_discipline_id discipline)
  3713. {
  3714. int rc = 0;
  3715. switch (discipline) {
  3716. case QETH_DISCIPLINE_LAYER3:
  3717. card->discipline.ccwgdriver = try_then_request_module(
  3718. symbol_get(qeth_l3_ccwgroup_driver),
  3719. "qeth_l3");
  3720. break;
  3721. case QETH_DISCIPLINE_LAYER2:
  3722. card->discipline.ccwgdriver = try_then_request_module(
  3723. symbol_get(qeth_l2_ccwgroup_driver),
  3724. "qeth_l2");
  3725. break;
  3726. }
  3727. if (!card->discipline.ccwgdriver) {
  3728. PRINT_ERR("Support for discipline %d not present\n",
  3729. discipline);
  3730. rc = -EINVAL;
  3731. }
  3732. return rc;
  3733. }
  3734. void qeth_core_free_discipline(struct qeth_card *card)
  3735. {
  3736. if (card->options.layer2)
  3737. symbol_put(qeth_l2_ccwgroup_driver);
  3738. else
  3739. symbol_put(qeth_l3_ccwgroup_driver);
  3740. card->discipline.ccwgdriver = NULL;
  3741. }
  3742. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3743. {
  3744. struct qeth_card *card;
  3745. struct device *dev;
  3746. int rc;
  3747. unsigned long flags;
  3748. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3749. dev = &gdev->dev;
  3750. if (!get_device(dev))
  3751. return -ENODEV;
  3752. QETH_DBF_TEXT_(SETUP, 2, "%s", gdev->dev.bus_id);
  3753. card = qeth_alloc_card();
  3754. if (!card) {
  3755. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3756. rc = -ENOMEM;
  3757. goto err_dev;
  3758. }
  3759. card->read.ccwdev = gdev->cdev[0];
  3760. card->write.ccwdev = gdev->cdev[1];
  3761. card->data.ccwdev = gdev->cdev[2];
  3762. dev_set_drvdata(&gdev->dev, card);
  3763. card->gdev = gdev;
  3764. gdev->cdev[0]->handler = qeth_irq;
  3765. gdev->cdev[1]->handler = qeth_irq;
  3766. gdev->cdev[2]->handler = qeth_irq;
  3767. rc = qeth_determine_card_type(card);
  3768. if (rc) {
  3769. PRINT_WARN("%s: not a valid card type\n", __func__);
  3770. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3771. goto err_card;
  3772. }
  3773. rc = qeth_setup_card(card);
  3774. if (rc) {
  3775. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3776. goto err_card;
  3777. }
  3778. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3779. rc = qeth_core_create_osn_attributes(dev);
  3780. if (rc)
  3781. goto err_card;
  3782. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3783. if (rc) {
  3784. qeth_core_remove_osn_attributes(dev);
  3785. goto err_card;
  3786. }
  3787. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3788. if (rc) {
  3789. qeth_core_free_discipline(card);
  3790. qeth_core_remove_osn_attributes(dev);
  3791. goto err_card;
  3792. }
  3793. } else {
  3794. rc = qeth_core_create_device_attributes(dev);
  3795. if (rc)
  3796. goto err_card;
  3797. }
  3798. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3799. list_add_tail(&card->list, &qeth_core_card_list.list);
  3800. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3801. return 0;
  3802. err_card:
  3803. qeth_core_free_card(card);
  3804. err_dev:
  3805. put_device(dev);
  3806. return rc;
  3807. }
  3808. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3809. {
  3810. unsigned long flags;
  3811. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3812. if (card->discipline.ccwgdriver) {
  3813. card->discipline.ccwgdriver->remove(gdev);
  3814. qeth_core_free_discipline(card);
  3815. }
  3816. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3817. qeth_core_remove_osn_attributes(&gdev->dev);
  3818. } else {
  3819. qeth_core_remove_device_attributes(&gdev->dev);
  3820. }
  3821. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3822. list_del(&card->list);
  3823. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3824. qeth_core_free_card(card);
  3825. dev_set_drvdata(&gdev->dev, NULL);
  3826. put_device(&gdev->dev);
  3827. return;
  3828. }
  3829. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3830. {
  3831. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3832. int rc = 0;
  3833. int def_discipline;
  3834. if (!card->discipline.ccwgdriver) {
  3835. if (card->info.type == QETH_CARD_TYPE_IQD)
  3836. def_discipline = QETH_DISCIPLINE_LAYER3;
  3837. else
  3838. def_discipline = QETH_DISCIPLINE_LAYER2;
  3839. rc = qeth_core_load_discipline(card, def_discipline);
  3840. if (rc)
  3841. goto err;
  3842. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3843. if (rc)
  3844. goto err;
  3845. }
  3846. rc = card->discipline.ccwgdriver->set_online(gdev);
  3847. err:
  3848. return rc;
  3849. }
  3850. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3851. {
  3852. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3853. return card->discipline.ccwgdriver->set_offline(gdev);
  3854. }
  3855. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3856. {
  3857. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3858. if (card->discipline.ccwgdriver &&
  3859. card->discipline.ccwgdriver->shutdown)
  3860. card->discipline.ccwgdriver->shutdown(gdev);
  3861. }
  3862. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3863. .owner = THIS_MODULE,
  3864. .name = "qeth",
  3865. .driver_id = 0xD8C5E3C8,
  3866. .probe = qeth_core_probe_device,
  3867. .remove = qeth_core_remove_device,
  3868. .set_online = qeth_core_set_online,
  3869. .set_offline = qeth_core_set_offline,
  3870. .shutdown = qeth_core_shutdown,
  3871. };
  3872. static ssize_t
  3873. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3874. size_t count)
  3875. {
  3876. int err;
  3877. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3878. qeth_core_ccwgroup_driver.driver_id);
  3879. if (err)
  3880. return err;
  3881. else
  3882. return count;
  3883. }
  3884. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3885. static struct {
  3886. const char str[ETH_GSTRING_LEN];
  3887. } qeth_ethtool_stats_keys[] = {
  3888. /* 0 */{"rx skbs"},
  3889. {"rx buffers"},
  3890. {"tx skbs"},
  3891. {"tx buffers"},
  3892. {"tx skbs no packing"},
  3893. {"tx buffers no packing"},
  3894. {"tx skbs packing"},
  3895. {"tx buffers packing"},
  3896. {"tx sg skbs"},
  3897. {"tx sg frags"},
  3898. /* 10 */{"rx sg skbs"},
  3899. {"rx sg frags"},
  3900. {"rx sg page allocs"},
  3901. {"tx large kbytes"},
  3902. {"tx large count"},
  3903. {"tx pk state ch n->p"},
  3904. {"tx pk state ch p->n"},
  3905. {"tx pk watermark low"},
  3906. {"tx pk watermark high"},
  3907. {"queue 0 buffer usage"},
  3908. /* 20 */{"queue 1 buffer usage"},
  3909. {"queue 2 buffer usage"},
  3910. {"queue 3 buffer usage"},
  3911. {"rx handler time"},
  3912. {"rx handler count"},
  3913. {"rx do_QDIO time"},
  3914. {"rx do_QDIO count"},
  3915. {"tx handler time"},
  3916. {"tx handler count"},
  3917. {"tx time"},
  3918. /* 30 */{"tx count"},
  3919. {"tx do_QDIO time"},
  3920. {"tx do_QDIO count"},
  3921. };
  3922. int qeth_core_get_stats_count(struct net_device *dev)
  3923. {
  3924. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3925. }
  3926. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3927. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3928. struct ethtool_stats *stats, u64 *data)
  3929. {
  3930. struct qeth_card *card = netdev_priv(dev);
  3931. data[0] = card->stats.rx_packets -
  3932. card->perf_stats.initial_rx_packets;
  3933. data[1] = card->perf_stats.bufs_rec;
  3934. data[2] = card->stats.tx_packets -
  3935. card->perf_stats.initial_tx_packets;
  3936. data[3] = card->perf_stats.bufs_sent;
  3937. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3938. - card->perf_stats.skbs_sent_pack;
  3939. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3940. data[6] = card->perf_stats.skbs_sent_pack;
  3941. data[7] = card->perf_stats.bufs_sent_pack;
  3942. data[8] = card->perf_stats.sg_skbs_sent;
  3943. data[9] = card->perf_stats.sg_frags_sent;
  3944. data[10] = card->perf_stats.sg_skbs_rx;
  3945. data[11] = card->perf_stats.sg_frags_rx;
  3946. data[12] = card->perf_stats.sg_alloc_page_rx;
  3947. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3948. data[14] = card->perf_stats.large_send_cnt;
  3949. data[15] = card->perf_stats.sc_dp_p;
  3950. data[16] = card->perf_stats.sc_p_dp;
  3951. data[17] = QETH_LOW_WATERMARK_PACK;
  3952. data[18] = QETH_HIGH_WATERMARK_PACK;
  3953. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3954. data[20] = (card->qdio.no_out_queues > 1) ?
  3955. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3956. data[21] = (card->qdio.no_out_queues > 2) ?
  3957. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3958. data[22] = (card->qdio.no_out_queues > 3) ?
  3959. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3960. data[23] = card->perf_stats.inbound_time;
  3961. data[24] = card->perf_stats.inbound_cnt;
  3962. data[25] = card->perf_stats.inbound_do_qdio_time;
  3963. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3964. data[27] = card->perf_stats.outbound_handler_time;
  3965. data[28] = card->perf_stats.outbound_handler_cnt;
  3966. data[29] = card->perf_stats.outbound_time;
  3967. data[30] = card->perf_stats.outbound_cnt;
  3968. data[31] = card->perf_stats.outbound_do_qdio_time;
  3969. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3970. }
  3971. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3972. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3973. {
  3974. switch (stringset) {
  3975. case ETH_SS_STATS:
  3976. memcpy(data, &qeth_ethtool_stats_keys,
  3977. sizeof(qeth_ethtool_stats_keys));
  3978. break;
  3979. default:
  3980. WARN_ON(1);
  3981. break;
  3982. }
  3983. }
  3984. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3985. void qeth_core_get_drvinfo(struct net_device *dev,
  3986. struct ethtool_drvinfo *info)
  3987. {
  3988. struct qeth_card *card = netdev_priv(dev);
  3989. if (card->options.layer2)
  3990. strcpy(info->driver, "qeth_l2");
  3991. else
  3992. strcpy(info->driver, "qeth_l3");
  3993. strcpy(info->version, "1.0");
  3994. strcpy(info->fw_version, card->info.mcl_level);
  3995. sprintf(info->bus_info, "%s/%s/%s",
  3996. CARD_RDEV_ID(card),
  3997. CARD_WDEV_ID(card),
  3998. CARD_DDEV_ID(card));
  3999. }
  4000. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4001. static int __init qeth_core_init(void)
  4002. {
  4003. int rc;
  4004. PRINT_INFO("loading core functions\n");
  4005. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4006. rwlock_init(&qeth_core_card_list.rwlock);
  4007. rc = qeth_register_dbf_views();
  4008. if (rc)
  4009. goto out_err;
  4010. rc = ccw_driver_register(&qeth_ccw_driver);
  4011. if (rc)
  4012. goto ccw_err;
  4013. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4014. if (rc)
  4015. goto ccwgroup_err;
  4016. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4017. &driver_attr_group);
  4018. if (rc)
  4019. goto driver_err;
  4020. qeth_core_root_dev = s390_root_dev_register("qeth");
  4021. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4022. if (rc)
  4023. goto register_err;
  4024. return 0;
  4025. register_err:
  4026. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4027. &driver_attr_group);
  4028. driver_err:
  4029. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4030. ccwgroup_err:
  4031. ccw_driver_unregister(&qeth_ccw_driver);
  4032. ccw_err:
  4033. qeth_unregister_dbf_views();
  4034. out_err:
  4035. PRINT_ERR("Initialization failed with code %d\n", rc);
  4036. return rc;
  4037. }
  4038. static void __exit qeth_core_exit(void)
  4039. {
  4040. s390_root_dev_unregister(qeth_core_root_dev);
  4041. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4042. &driver_attr_group);
  4043. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4044. ccw_driver_unregister(&qeth_ccw_driver);
  4045. qeth_unregister_dbf_views();
  4046. PRINT_INFO("core functions removed\n");
  4047. }
  4048. module_init(qeth_core_init);
  4049. module_exit(qeth_core_exit);
  4050. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4051. MODULE_DESCRIPTION("qeth core functions");
  4052. MODULE_LICENSE("GPL");