iwl3945-base.c 234 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779578057815782578357845785578657875788578957905791579257935794579557965797579857995800580158025803580458055806580758085809581058115812581358145815581658175818581958205821582258235824582558265827582858295830583158325833583458355836583758385839584058415842584358445845584658475848584958505851585258535854585558565857585858595860586158625863586458655866586758685869587058715872587358745875587658775878587958805881588258835884588558865887588858895890589158925893589458955896589758985899590059015902590359045905590659075908590959105911591259135914591559165917591859195920592159225923592459255926592759285929593059315932593359345935593659375938593959405941594259435944594559465947594859495950595159525953595459555956595759585959596059615962596359645965596659675968596959705971597259735974597559765977597859795980598159825983598459855986598759885989599059915992599359945995599659975998599960006001600260036004600560066007600860096010601160126013601460156016601760186019602060216022602360246025602660276028602960306031603260336034603560366037603860396040604160426043604460456046604760486049605060516052605360546055605660576058605960606061606260636064606560666067606860696070607160726073607460756076607760786079608060816082608360846085608660876088608960906091609260936094609560966097609860996100610161026103610461056106610761086109611061116112611361146115611661176118611961206121612261236124612561266127612861296130613161326133613461356136613761386139614061416142614361446145614661476148614961506151615261536154615561566157615861596160616161626163616461656166616761686169617061716172617361746175617661776178617961806181618261836184618561866187618861896190619161926193619461956196619761986199620062016202620362046205620662076208620962106211621262136214621562166217621862196220622162226223622462256226622762286229623062316232623362346235623662376238623962406241624262436244624562466247624862496250625162526253625462556256625762586259626062616262626362646265626662676268626962706271627262736274627562766277627862796280628162826283628462856286628762886289629062916292629362946295629662976298629963006301630263036304630563066307630863096310631163126313631463156316631763186319632063216322632363246325632663276328632963306331633263336334633563366337633863396340634163426343634463456346634763486349635063516352635363546355635663576358635963606361636263636364636563666367636863696370637163726373637463756376637763786379638063816382638363846385638663876388638963906391639263936394639563966397639863996400640164026403640464056406640764086409641064116412641364146415641664176418641964206421642264236424642564266427642864296430643164326433643464356436643764386439644064416442644364446445644664476448644964506451645264536454645564566457645864596460646164626463646464656466646764686469647064716472647364746475647664776478647964806481648264836484648564866487648864896490649164926493649464956496649764986499650065016502650365046505650665076508650965106511651265136514651565166517651865196520652165226523652465256526652765286529653065316532653365346535653665376538653965406541654265436544654565466547654865496550655165526553655465556556655765586559656065616562656365646565656665676568656965706571657265736574657565766577657865796580658165826583658465856586658765886589659065916592659365946595659665976598659966006601660266036604660566066607660866096610661166126613661466156616661766186619662066216622662366246625662666276628662966306631663266336634663566366637663866396640664166426643664466456646664766486649665066516652665366546655665666576658665966606661666266636664666566666667666866696670667166726673667466756676667766786679668066816682668366846685668666876688668966906691669266936694669566966697669866996700670167026703670467056706670767086709671067116712671367146715671667176718671967206721672267236724672567266727672867296730673167326733673467356736673767386739674067416742674367446745674667476748674967506751675267536754675567566757675867596760676167626763676467656766676767686769677067716772677367746775677667776778677967806781678267836784678567866787678867896790679167926793679467956796679767986799680068016802680368046805680668076808680968106811681268136814681568166817681868196820682168226823682468256826682768286829683068316832683368346835683668376838683968406841684268436844684568466847684868496850685168526853685468556856685768586859686068616862686368646865686668676868686968706871687268736874687568766877687868796880688168826883688468856886688768886889689068916892689368946895689668976898689969006901690269036904690569066907690869096910691169126913691469156916691769186919692069216922692369246925692669276928692969306931693269336934693569366937693869396940694169426943694469456946694769486949695069516952695369546955695669576958695969606961696269636964696569666967696869696970697169726973697469756976697769786979698069816982698369846985698669876988698969906991699269936994699569966997699869997000700170027003700470057006700770087009701070117012701370147015701670177018701970207021702270237024702570267027702870297030703170327033703470357036703770387039704070417042704370447045704670477048704970507051705270537054705570567057705870597060706170627063706470657066706770687069707070717072707370747075707670777078707970807081708270837084708570867087708870897090709170927093709470957096709770987099710071017102710371047105710671077108710971107111711271137114711571167117711871197120712171227123712471257126712771287129713071317132713371347135713671377138713971407141714271437144714571467147714871497150715171527153715471557156715771587159716071617162716371647165716671677168716971707171717271737174717571767177717871797180718171827183718471857186718771887189719071917192719371947195719671977198719972007201720272037204720572067207720872097210721172127213721472157216721772187219722072217222722372247225722672277228722972307231723272337234723572367237723872397240724172427243724472457246724772487249725072517252725372547255725672577258725972607261726272637264726572667267726872697270727172727273727472757276727772787279728072817282728372847285728672877288728972907291729272937294729572967297729872997300730173027303730473057306730773087309731073117312731373147315731673177318731973207321732273237324732573267327732873297330733173327333733473357336733773387339734073417342734373447345734673477348734973507351735273537354735573567357735873597360736173627363736473657366736773687369737073717372737373747375737673777378737973807381738273837384738573867387738873897390739173927393739473957396739773987399740074017402740374047405740674077408740974107411741274137414741574167417741874197420742174227423742474257426742774287429743074317432743374347435743674377438743974407441744274437444744574467447744874497450745174527453745474557456745774587459746074617462746374647465746674677468746974707471747274737474747574767477747874797480748174827483748474857486748774887489749074917492749374947495749674977498749975007501750275037504750575067507750875097510751175127513751475157516751775187519752075217522752375247525752675277528752975307531753275337534753575367537753875397540754175427543754475457546754775487549755075517552755375547555755675577558755975607561756275637564756575667567756875697570757175727573757475757576757775787579758075817582758375847585758675877588758975907591759275937594759575967597759875997600760176027603760476057606760776087609761076117612761376147615761676177618761976207621762276237624762576267627762876297630763176327633763476357636763776387639764076417642764376447645764676477648764976507651765276537654765576567657765876597660766176627663766476657666766776687669767076717672767376747675767676777678767976807681768276837684768576867687768876897690769176927693769476957696769776987699770077017702770377047705770677077708770977107711771277137714771577167717771877197720772177227723772477257726772777287729773077317732773377347735773677377738773977407741774277437744774577467747774877497750775177527753775477557756775777587759776077617762776377647765776677677768776977707771777277737774777577767777777877797780778177827783778477857786778777887789779077917792779377947795779677977798779978007801780278037804780578067807780878097810781178127813781478157816781778187819782078217822782378247825782678277828782978307831783278337834783578367837783878397840784178427843784478457846784778487849785078517852785378547855785678577858785978607861786278637864786578667867786878697870787178727873787478757876787778787879788078817882788378847885788678877888788978907891789278937894789578967897789878997900790179027903790479057906790779087909791079117912791379147915791679177918791979207921792279237924792579267927792879297930793179327933793479357936793779387939794079417942794379447945794679477948794979507951795279537954795579567957795879597960796179627963796479657966796779687969797079717972797379747975797679777978797979807981798279837984798579867987798879897990799179927993799479957996799779987999800080018002800380048005800680078008800980108011801280138014801580168017801880198020802180228023802480258026802780288029803080318032803380348035803680378038803980408041804280438044804580468047804880498050805180528053805480558056805780588059806080618062806380648065806680678068806980708071807280738074807580768077807880798080808180828083808480858086808780888089809080918092809380948095809680978098809981008101810281038104810581068107810881098110811181128113811481158116811781188119812081218122812381248125812681278128812981308131813281338134813581368137813881398140814181428143814481458146814781488149815081518152815381548155815681578158815981608161816281638164816581668167816881698170817181728173817481758176817781788179818081818182818381848185818681878188818981908191819281938194819581968197819881998200820182028203820482058206820782088209821082118212821382148215821682178218821982208221822282238224822582268227822882298230823182328233823482358236823782388239824082418242824382448245824682478248824982508251825282538254825582568257825882598260826182628263826482658266826782688269827082718272827382748275827682778278827982808281828282838284828582868287828882898290829182928293829482958296829782988299830083018302830383048305830683078308830983108311831283138314831583168317831883198320832183228323832483258326832783288329833083318332833383348335833683378338833983408341834283438344834583468347834883498350835183528353835483558356835783588359836083618362836383648365836683678368836983708371837283738374837583768377837883798380838183828383838483858386
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  69. */
  70. #define DRV_DESCRIPTION \
  71. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  72. #ifdef CONFIG_IWL3945_DEBUG
  73. #define VD "d"
  74. #else
  75. #define VD
  76. #endif
  77. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  78. #define VS "s"
  79. #else
  80. #define VS
  81. #endif
  82. #define IWLWIFI_VERSION "1.2.26k" VD VS
  83. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT);
  88. MODULE_LICENSE("GPL");
  89. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  90. {
  91. u16 fc = le16_to_cpu(hdr->frame_control);
  92. int hdr_len = ieee80211_get_hdrlen(fc);
  93. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  94. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  95. return NULL;
  96. }
  97. static const struct ieee80211_supported_band *iwl3945_get_band(
  98. struct iwl3945_priv *priv, enum ieee80211_band band)
  99. {
  100. return priv->hw->wiphy->bands[band];
  101. }
  102. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  103. {
  104. /* Single white space is for Linksys APs */
  105. if (essid_len == 1 && essid[0] == ' ')
  106. return 1;
  107. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  108. while (essid_len) {
  109. essid_len--;
  110. if (essid[essid_len] != '\0')
  111. return 0;
  112. }
  113. return 1;
  114. }
  115. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  116. {
  117. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  118. const char *s = essid;
  119. char *d = escaped;
  120. if (iwl3945_is_empty_essid(essid, essid_len)) {
  121. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  122. return escaped;
  123. }
  124. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  125. while (essid_len--) {
  126. if (*s == '\0') {
  127. *d++ = '\\';
  128. *d++ = '0';
  129. s++;
  130. } else
  131. *d++ = *s++;
  132. }
  133. *d = '\0';
  134. return escaped;
  135. }
  136. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  137. * DMA services
  138. *
  139. * Theory of operation
  140. *
  141. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  142. * of buffer descriptors, each of which points to one or more data buffers for
  143. * the device to read from or fill. Driver and device exchange status of each
  144. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  145. * entries in each circular buffer, to protect against confusing empty and full
  146. * queue states.
  147. *
  148. * The device reads or writes the data in the queues via the device's several
  149. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  150. *
  151. * For Tx queue, there are low mark and high mark limits. If, after queuing
  152. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  153. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  154. * Tx queue resumed.
  155. *
  156. * The 3945 operates with six queues: One receive queue, one transmit queue
  157. * (#4) for sending commands to the device firmware, and four transmit queues
  158. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  159. ***************************************************/
  160. int iwl3945_queue_space(const struct iwl3945_queue *q)
  161. {
  162. int s = q->read_ptr - q->write_ptr;
  163. if (q->read_ptr > q->write_ptr)
  164. s -= q->n_bd;
  165. if (s <= 0)
  166. s += q->n_window;
  167. /* keep some reserve to not confuse empty and full situations */
  168. s -= 2;
  169. if (s < 0)
  170. s = 0;
  171. return s;
  172. }
  173. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  174. {
  175. return q->write_ptr > q->read_ptr ?
  176. (i >= q->read_ptr && i < q->write_ptr) :
  177. !(i < q->read_ptr && i >= q->write_ptr);
  178. }
  179. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  180. {
  181. /* This is for scan command, the big buffer at end of command array */
  182. if (is_huge)
  183. return q->n_window; /* must be power of 2 */
  184. /* Otherwise, use normal size buffers */
  185. return index & (q->n_window - 1);
  186. }
  187. /**
  188. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  189. */
  190. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  191. int count, int slots_num, u32 id)
  192. {
  193. q->n_bd = count;
  194. q->n_window = slots_num;
  195. q->id = id;
  196. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  197. * and iwl_queue_dec_wrap are broken. */
  198. BUG_ON(!is_power_of_2(count));
  199. /* slots_num must be power-of-two size, otherwise
  200. * get_cmd_index is broken. */
  201. BUG_ON(!is_power_of_2(slots_num));
  202. q->low_mark = q->n_window / 4;
  203. if (q->low_mark < 4)
  204. q->low_mark = 4;
  205. q->high_mark = q->n_window / 8;
  206. if (q->high_mark < 2)
  207. q->high_mark = 2;
  208. q->write_ptr = q->read_ptr = 0;
  209. return 0;
  210. }
  211. /**
  212. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  213. */
  214. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  215. struct iwl3945_tx_queue *txq, u32 id)
  216. {
  217. struct pci_dev *dev = priv->pci_dev;
  218. /* Driver private data, only for Tx (not command) queues,
  219. * not shared with device. */
  220. if (id != IWL_CMD_QUEUE_NUM) {
  221. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  222. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  223. if (!txq->txb) {
  224. IWL_ERROR("kmalloc for auxiliary BD "
  225. "structures failed\n");
  226. goto error;
  227. }
  228. } else
  229. txq->txb = NULL;
  230. /* Circular buffer of transmit frame descriptors (TFDs),
  231. * shared with device */
  232. txq->bd = pci_alloc_consistent(dev,
  233. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  234. &txq->q.dma_addr);
  235. if (!txq->bd) {
  236. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  237. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  238. goto error;
  239. }
  240. txq->q.id = id;
  241. return 0;
  242. error:
  243. if (txq->txb) {
  244. kfree(txq->txb);
  245. txq->txb = NULL;
  246. }
  247. return -ENOMEM;
  248. }
  249. /**
  250. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  251. */
  252. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  253. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  254. {
  255. struct pci_dev *dev = priv->pci_dev;
  256. int len;
  257. int rc = 0;
  258. /*
  259. * Alloc buffer array for commands (Tx or other types of commands).
  260. * For the command queue (#4), allocate command space + one big
  261. * command for scan, since scan command is very huge; the system will
  262. * not have two scans at the same time, so only one is needed.
  263. * For data Tx queues (all other queues), no super-size command
  264. * space is needed.
  265. */
  266. len = sizeof(struct iwl3945_cmd) * slots_num;
  267. if (txq_id == IWL_CMD_QUEUE_NUM)
  268. len += IWL_MAX_SCAN_SIZE;
  269. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  270. if (!txq->cmd)
  271. return -ENOMEM;
  272. /* Alloc driver data array and TFD circular buffer */
  273. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  274. if (rc) {
  275. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  276. return -ENOMEM;
  277. }
  278. txq->need_update = 0;
  279. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  280. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  281. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  282. /* Initialize queue high/low-water, head/tail indexes */
  283. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  284. /* Tell device where to find queue, enable DMA channel. */
  285. iwl3945_hw_tx_queue_init(priv, txq);
  286. return 0;
  287. }
  288. /**
  289. * iwl3945_tx_queue_free - Deallocate DMA queue.
  290. * @txq: Transmit queue to deallocate.
  291. *
  292. * Empty queue by removing and destroying all BD's.
  293. * Free all buffers.
  294. * 0-fill, but do not free "txq" descriptor structure.
  295. */
  296. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  297. {
  298. struct iwl3945_queue *q = &txq->q;
  299. struct pci_dev *dev = priv->pci_dev;
  300. int len;
  301. if (q->n_bd == 0)
  302. return;
  303. /* first, empty all BD's */
  304. for (; q->write_ptr != q->read_ptr;
  305. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  306. iwl3945_hw_txq_free_tfd(priv, txq);
  307. len = sizeof(struct iwl3945_cmd) * q->n_window;
  308. if (q->id == IWL_CMD_QUEUE_NUM)
  309. len += IWL_MAX_SCAN_SIZE;
  310. /* De-alloc array of command/tx buffers */
  311. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  312. /* De-alloc circular buffer of TFDs */
  313. if (txq->q.n_bd)
  314. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  315. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  316. /* De-alloc array of per-TFD driver data */
  317. if (txq->txb) {
  318. kfree(txq->txb);
  319. txq->txb = NULL;
  320. }
  321. /* 0-fill queue descriptor structure */
  322. memset(txq, 0, sizeof(*txq));
  323. }
  324. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  325. /*************** STATION TABLE MANAGEMENT ****
  326. * mac80211 should be examined to determine if sta_info is duplicating
  327. * the functionality provided here
  328. */
  329. /**************************************************************/
  330. #if 0 /* temporary disable till we add real remove station */
  331. /**
  332. * iwl3945_remove_station - Remove driver's knowledge of station.
  333. *
  334. * NOTE: This does not remove station from device's station table.
  335. */
  336. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  337. {
  338. int index = IWL_INVALID_STATION;
  339. int i;
  340. unsigned long flags;
  341. spin_lock_irqsave(&priv->sta_lock, flags);
  342. if (is_ap)
  343. index = IWL_AP_ID;
  344. else if (is_broadcast_ether_addr(addr))
  345. index = priv->hw_setting.bcast_sta_id;
  346. else
  347. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  348. if (priv->stations[i].used &&
  349. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  350. addr)) {
  351. index = i;
  352. break;
  353. }
  354. if (unlikely(index == IWL_INVALID_STATION))
  355. goto out;
  356. if (priv->stations[index].used) {
  357. priv->stations[index].used = 0;
  358. priv->num_stations--;
  359. }
  360. BUG_ON(priv->num_stations < 0);
  361. out:
  362. spin_unlock_irqrestore(&priv->sta_lock, flags);
  363. return 0;
  364. }
  365. #endif
  366. /**
  367. * iwl3945_clear_stations_table - Clear the driver's station table
  368. *
  369. * NOTE: This does not clear or otherwise alter the device's station table.
  370. */
  371. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  372. {
  373. unsigned long flags;
  374. spin_lock_irqsave(&priv->sta_lock, flags);
  375. priv->num_stations = 0;
  376. memset(priv->stations, 0, sizeof(priv->stations));
  377. spin_unlock_irqrestore(&priv->sta_lock, flags);
  378. }
  379. /**
  380. * iwl3945_add_station - Add station to station tables in driver and device
  381. */
  382. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  383. {
  384. int i;
  385. int index = IWL_INVALID_STATION;
  386. struct iwl3945_station_entry *station;
  387. unsigned long flags_spin;
  388. DECLARE_MAC_BUF(mac);
  389. u8 rate;
  390. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  391. if (is_ap)
  392. index = IWL_AP_ID;
  393. else if (is_broadcast_ether_addr(addr))
  394. index = priv->hw_setting.bcast_sta_id;
  395. else
  396. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  397. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  398. addr)) {
  399. index = i;
  400. break;
  401. }
  402. if (!priv->stations[i].used &&
  403. index == IWL_INVALID_STATION)
  404. index = i;
  405. }
  406. /* These two conditions has the same outcome but keep them separate
  407. since they have different meaning */
  408. if (unlikely(index == IWL_INVALID_STATION)) {
  409. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  410. return index;
  411. }
  412. if (priv->stations[index].used &&
  413. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  414. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  415. return index;
  416. }
  417. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  418. station = &priv->stations[index];
  419. station->used = 1;
  420. priv->num_stations++;
  421. /* Set up the REPLY_ADD_STA command to send to device */
  422. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  423. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  424. station->sta.mode = 0;
  425. station->sta.sta.sta_id = index;
  426. station->sta.station_flags = 0;
  427. if (priv->band == IEEE80211_BAND_5GHZ)
  428. rate = IWL_RATE_6M_PLCP;
  429. else
  430. rate = IWL_RATE_1M_PLCP;
  431. /* Turn on both antennas for the station... */
  432. station->sta.rate_n_flags =
  433. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  434. station->current_rate.rate_n_flags =
  435. le16_to_cpu(station->sta.rate_n_flags);
  436. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  437. /* Add station to device's station table */
  438. iwl3945_send_add_station(priv, &station->sta, flags);
  439. return index;
  440. }
  441. /*************** DRIVER STATUS FUNCTIONS *****/
  442. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  443. {
  444. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  445. * set but EXIT_PENDING is not */
  446. return test_bit(STATUS_READY, &priv->status) &&
  447. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  448. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  449. }
  450. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  451. {
  452. return test_bit(STATUS_ALIVE, &priv->status);
  453. }
  454. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  455. {
  456. return test_bit(STATUS_INIT, &priv->status);
  457. }
  458. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  459. {
  460. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  461. test_bit(STATUS_RF_KILL_SW, &priv->status);
  462. }
  463. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  464. {
  465. if (iwl3945_is_rfkill(priv))
  466. return 0;
  467. return iwl3945_is_ready(priv);
  468. }
  469. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  470. #define IWL_CMD(x) case x : return #x
  471. static const char *get_cmd_string(u8 cmd)
  472. {
  473. switch (cmd) {
  474. IWL_CMD(REPLY_ALIVE);
  475. IWL_CMD(REPLY_ERROR);
  476. IWL_CMD(REPLY_RXON);
  477. IWL_CMD(REPLY_RXON_ASSOC);
  478. IWL_CMD(REPLY_QOS_PARAM);
  479. IWL_CMD(REPLY_RXON_TIMING);
  480. IWL_CMD(REPLY_ADD_STA);
  481. IWL_CMD(REPLY_REMOVE_STA);
  482. IWL_CMD(REPLY_REMOVE_ALL_STA);
  483. IWL_CMD(REPLY_3945_RX);
  484. IWL_CMD(REPLY_TX);
  485. IWL_CMD(REPLY_RATE_SCALE);
  486. IWL_CMD(REPLY_LEDS_CMD);
  487. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  488. IWL_CMD(RADAR_NOTIFICATION);
  489. IWL_CMD(REPLY_QUIET_CMD);
  490. IWL_CMD(REPLY_CHANNEL_SWITCH);
  491. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  492. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  493. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  494. IWL_CMD(POWER_TABLE_CMD);
  495. IWL_CMD(PM_SLEEP_NOTIFICATION);
  496. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  497. IWL_CMD(REPLY_SCAN_CMD);
  498. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  499. IWL_CMD(SCAN_START_NOTIFICATION);
  500. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  501. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  502. IWL_CMD(BEACON_NOTIFICATION);
  503. IWL_CMD(REPLY_TX_BEACON);
  504. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  505. IWL_CMD(QUIET_NOTIFICATION);
  506. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  507. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  508. IWL_CMD(REPLY_BT_CONFIG);
  509. IWL_CMD(REPLY_STATISTICS_CMD);
  510. IWL_CMD(STATISTICS_NOTIFICATION);
  511. IWL_CMD(REPLY_CARD_STATE_CMD);
  512. IWL_CMD(CARD_STATE_NOTIFICATION);
  513. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  514. default:
  515. return "UNKNOWN";
  516. }
  517. }
  518. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  519. /**
  520. * iwl3945_enqueue_hcmd - enqueue a uCode command
  521. * @priv: device private data point
  522. * @cmd: a point to the ucode command structure
  523. *
  524. * The function returns < 0 values to indicate the operation is
  525. * failed. On success, it turns the index (> 0) of command in the
  526. * command queue.
  527. */
  528. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  529. {
  530. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  531. struct iwl3945_queue *q = &txq->q;
  532. struct iwl3945_tfd_frame *tfd;
  533. u32 *control_flags;
  534. struct iwl3945_cmd *out_cmd;
  535. u32 idx;
  536. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  537. dma_addr_t phys_addr;
  538. int pad;
  539. u16 count;
  540. int ret;
  541. unsigned long flags;
  542. /* If any of the command structures end up being larger than
  543. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  544. * we will need to increase the size of the TFD entries */
  545. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  546. !(cmd->meta.flags & CMD_SIZE_HUGE));
  547. if (iwl3945_is_rfkill(priv)) {
  548. IWL_DEBUG_INFO("Not sending command - RF KILL");
  549. return -EIO;
  550. }
  551. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  552. IWL_ERROR("No space for Tx\n");
  553. return -ENOSPC;
  554. }
  555. spin_lock_irqsave(&priv->hcmd_lock, flags);
  556. tfd = &txq->bd[q->write_ptr];
  557. memset(tfd, 0, sizeof(*tfd));
  558. control_flags = (u32 *) tfd;
  559. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  560. out_cmd = &txq->cmd[idx];
  561. out_cmd->hdr.cmd = cmd->id;
  562. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  563. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  564. /* At this point, the out_cmd now has all of the incoming cmd
  565. * information */
  566. out_cmd->hdr.flags = 0;
  567. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  568. INDEX_TO_SEQ(q->write_ptr));
  569. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  570. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  571. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  572. offsetof(struct iwl3945_cmd, hdr);
  573. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  574. pad = U32_PAD(cmd->len);
  575. count = TFD_CTL_COUNT_GET(*control_flags);
  576. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  577. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  578. "%d bytes at %d[%d]:%d\n",
  579. get_cmd_string(out_cmd->hdr.cmd),
  580. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  581. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  582. txq->need_update = 1;
  583. /* Increment and update queue's write index */
  584. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  585. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  586. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  587. return ret ? ret : idx;
  588. }
  589. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  590. {
  591. int ret;
  592. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  593. /* An asynchronous command can not expect an SKB to be set. */
  594. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  595. /* An asynchronous command MUST have a callback. */
  596. BUG_ON(!cmd->meta.u.callback);
  597. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  598. return -EBUSY;
  599. ret = iwl3945_enqueue_hcmd(priv, cmd);
  600. if (ret < 0) {
  601. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  602. get_cmd_string(cmd->id), ret);
  603. return ret;
  604. }
  605. return 0;
  606. }
  607. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  608. {
  609. int cmd_idx;
  610. int ret;
  611. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  612. /* A synchronous command can not have a callback set. */
  613. BUG_ON(cmd->meta.u.callback != NULL);
  614. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  615. IWL_ERROR("Error sending %s: Already sending a host command\n",
  616. get_cmd_string(cmd->id));
  617. ret = -EBUSY;
  618. goto out;
  619. }
  620. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  621. if (cmd->meta.flags & CMD_WANT_SKB)
  622. cmd->meta.source = &cmd->meta;
  623. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  624. if (cmd_idx < 0) {
  625. ret = cmd_idx;
  626. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  627. get_cmd_string(cmd->id), ret);
  628. goto out;
  629. }
  630. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  631. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  632. HOST_COMPLETE_TIMEOUT);
  633. if (!ret) {
  634. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  635. IWL_ERROR("Error sending %s: time out after %dms.\n",
  636. get_cmd_string(cmd->id),
  637. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  638. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  639. ret = -ETIMEDOUT;
  640. goto cancel;
  641. }
  642. }
  643. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  644. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  645. get_cmd_string(cmd->id));
  646. ret = -ECANCELED;
  647. goto fail;
  648. }
  649. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  650. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  651. get_cmd_string(cmd->id));
  652. ret = -EIO;
  653. goto fail;
  654. }
  655. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  656. IWL_ERROR("Error: Response NULL in '%s'\n",
  657. get_cmd_string(cmd->id));
  658. ret = -EIO;
  659. goto out;
  660. }
  661. ret = 0;
  662. goto out;
  663. cancel:
  664. if (cmd->meta.flags & CMD_WANT_SKB) {
  665. struct iwl3945_cmd *qcmd;
  666. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  667. * TX cmd queue. Otherwise in case the cmd comes
  668. * in later, it will possibly set an invalid
  669. * address (cmd->meta.source). */
  670. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  671. qcmd->meta.flags &= ~CMD_WANT_SKB;
  672. }
  673. fail:
  674. if (cmd->meta.u.skb) {
  675. dev_kfree_skb_any(cmd->meta.u.skb);
  676. cmd->meta.u.skb = NULL;
  677. }
  678. out:
  679. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  680. return ret;
  681. }
  682. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  683. {
  684. if (cmd->meta.flags & CMD_ASYNC)
  685. return iwl3945_send_cmd_async(priv, cmd);
  686. return iwl3945_send_cmd_sync(priv, cmd);
  687. }
  688. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  689. {
  690. struct iwl3945_host_cmd cmd = {
  691. .id = id,
  692. .len = len,
  693. .data = data,
  694. };
  695. return iwl3945_send_cmd_sync(priv, &cmd);
  696. }
  697. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  698. {
  699. struct iwl3945_host_cmd cmd = {
  700. .id = id,
  701. .len = sizeof(val),
  702. .data = &val,
  703. };
  704. return iwl3945_send_cmd_sync(priv, &cmd);
  705. }
  706. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  707. {
  708. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  709. }
  710. /**
  711. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  712. * @band: 2.4 or 5 GHz band
  713. * @channel: Any channel valid for the requested band
  714. * In addition to setting the staging RXON, priv->band is also set.
  715. *
  716. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  717. * in the staging RXON flag structure based on the band
  718. */
  719. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  720. enum ieee80211_band band,
  721. u16 channel)
  722. {
  723. if (!iwl3945_get_channel_info(priv, band, channel)) {
  724. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  725. channel, band);
  726. return -EINVAL;
  727. }
  728. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  729. (priv->band == band))
  730. return 0;
  731. priv->staging_rxon.channel = cpu_to_le16(channel);
  732. if (band == IEEE80211_BAND_5GHZ)
  733. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  734. else
  735. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  736. priv->band = band;
  737. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  738. return 0;
  739. }
  740. /**
  741. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  742. *
  743. * NOTE: This is really only useful during development and can eventually
  744. * be #ifdef'd out once the driver is stable and folks aren't actively
  745. * making changes
  746. */
  747. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  748. {
  749. int error = 0;
  750. int counter = 1;
  751. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  752. error |= le32_to_cpu(rxon->flags &
  753. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  754. RXON_FLG_RADAR_DETECT_MSK));
  755. if (error)
  756. IWL_WARNING("check 24G fields %d | %d\n",
  757. counter++, error);
  758. } else {
  759. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  760. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  761. if (error)
  762. IWL_WARNING("check 52 fields %d | %d\n",
  763. counter++, error);
  764. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  765. if (error)
  766. IWL_WARNING("check 52 CCK %d | %d\n",
  767. counter++, error);
  768. }
  769. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  770. if (error)
  771. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  772. /* make sure basic rates 6Mbps and 1Mbps are supported */
  773. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  774. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  775. if (error)
  776. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  777. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  778. if (error)
  779. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  780. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  781. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  782. if (error)
  783. IWL_WARNING("check CCK and short slot %d | %d\n",
  784. counter++, error);
  785. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  786. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  787. if (error)
  788. IWL_WARNING("check CCK & auto detect %d | %d\n",
  789. counter++, error);
  790. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  791. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  792. if (error)
  793. IWL_WARNING("check TGG and auto detect %d | %d\n",
  794. counter++, error);
  795. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  796. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  797. RXON_FLG_ANT_A_MSK)) == 0);
  798. if (error)
  799. IWL_WARNING("check antenna %d %d\n", counter++, error);
  800. if (error)
  801. IWL_WARNING("Tuning to channel %d\n",
  802. le16_to_cpu(rxon->channel));
  803. if (error) {
  804. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  805. return -1;
  806. }
  807. return 0;
  808. }
  809. /**
  810. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  811. * @priv: staging_rxon is compared to active_rxon
  812. *
  813. * If the RXON structure is changing enough to require a new tune,
  814. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  815. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  816. */
  817. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  818. {
  819. /* These items are only settable from the full RXON command */
  820. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  821. compare_ether_addr(priv->staging_rxon.bssid_addr,
  822. priv->active_rxon.bssid_addr) ||
  823. compare_ether_addr(priv->staging_rxon.node_addr,
  824. priv->active_rxon.node_addr) ||
  825. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  826. priv->active_rxon.wlap_bssid_addr) ||
  827. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  828. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  829. (priv->staging_rxon.air_propagation !=
  830. priv->active_rxon.air_propagation) ||
  831. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  832. return 1;
  833. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  834. * be updated with the RXON_ASSOC command -- however only some
  835. * flag transitions are allowed using RXON_ASSOC */
  836. /* Check if we are not switching bands */
  837. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  838. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  839. return 1;
  840. /* Check if we are switching association toggle */
  841. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  842. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  843. return 1;
  844. return 0;
  845. }
  846. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  847. {
  848. int rc = 0;
  849. struct iwl3945_rx_packet *res = NULL;
  850. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  851. struct iwl3945_host_cmd cmd = {
  852. .id = REPLY_RXON_ASSOC,
  853. .len = sizeof(rxon_assoc),
  854. .meta.flags = CMD_WANT_SKB,
  855. .data = &rxon_assoc,
  856. };
  857. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  858. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  859. if ((rxon1->flags == rxon2->flags) &&
  860. (rxon1->filter_flags == rxon2->filter_flags) &&
  861. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  862. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  863. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  864. return 0;
  865. }
  866. rxon_assoc.flags = priv->staging_rxon.flags;
  867. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  868. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  869. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  870. rxon_assoc.reserved = 0;
  871. rc = iwl3945_send_cmd_sync(priv, &cmd);
  872. if (rc)
  873. return rc;
  874. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  875. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  876. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  877. rc = -EIO;
  878. }
  879. priv->alloc_rxb_skb--;
  880. dev_kfree_skb_any(cmd.meta.u.skb);
  881. return rc;
  882. }
  883. /**
  884. * iwl3945_commit_rxon - commit staging_rxon to hardware
  885. *
  886. * The RXON command in staging_rxon is committed to the hardware and
  887. * the active_rxon structure is updated with the new data. This
  888. * function correctly transitions out of the RXON_ASSOC_MSK state if
  889. * a HW tune is required based on the RXON structure changes.
  890. */
  891. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  892. {
  893. /* cast away the const for active_rxon in this function */
  894. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  895. int rc = 0;
  896. DECLARE_MAC_BUF(mac);
  897. if (!iwl3945_is_alive(priv))
  898. return -1;
  899. /* always get timestamp with Rx frame */
  900. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  901. /* select antenna */
  902. priv->staging_rxon.flags &=
  903. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  904. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  905. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  906. if (rc) {
  907. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  908. return -EINVAL;
  909. }
  910. /* If we don't need to send a full RXON, we can use
  911. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  912. * and other flags for the current radio configuration. */
  913. if (!iwl3945_full_rxon_required(priv)) {
  914. rc = iwl3945_send_rxon_assoc(priv);
  915. if (rc) {
  916. IWL_ERROR("Error setting RXON_ASSOC "
  917. "configuration (%d).\n", rc);
  918. return rc;
  919. }
  920. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  921. return 0;
  922. }
  923. /* If we are currently associated and the new config requires
  924. * an RXON_ASSOC and the new config wants the associated mask enabled,
  925. * we must clear the associated from the active configuration
  926. * before we apply the new config */
  927. if (iwl3945_is_associated(priv) &&
  928. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  929. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  930. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  931. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  932. sizeof(struct iwl3945_rxon_cmd),
  933. &priv->active_rxon);
  934. /* If the mask clearing failed then we set
  935. * active_rxon back to what it was previously */
  936. if (rc) {
  937. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  938. IWL_ERROR("Error clearing ASSOC_MSK on current "
  939. "configuration (%d).\n", rc);
  940. return rc;
  941. }
  942. }
  943. IWL_DEBUG_INFO("Sending RXON\n"
  944. "* with%s RXON_FILTER_ASSOC_MSK\n"
  945. "* channel = %d\n"
  946. "* bssid = %s\n",
  947. ((priv->staging_rxon.filter_flags &
  948. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  949. le16_to_cpu(priv->staging_rxon.channel),
  950. print_mac(mac, priv->staging_rxon.bssid_addr));
  951. /* Apply the new configuration */
  952. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  953. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  954. if (rc) {
  955. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  956. return rc;
  957. }
  958. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  959. iwl3945_clear_stations_table(priv);
  960. /* If we issue a new RXON command which required a tune then we must
  961. * send a new TXPOWER command or we won't be able to Tx any frames */
  962. rc = iwl3945_hw_reg_send_txpower(priv);
  963. if (rc) {
  964. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  965. return rc;
  966. }
  967. /* Add the broadcast address so we can send broadcast frames */
  968. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  969. IWL_INVALID_STATION) {
  970. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  971. return -EIO;
  972. }
  973. /* If we have set the ASSOC_MSK and we are in BSS mode then
  974. * add the IWL_AP_ID to the station rate table */
  975. if (iwl3945_is_associated(priv) &&
  976. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  977. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  978. == IWL_INVALID_STATION) {
  979. IWL_ERROR("Error adding AP address for transmit.\n");
  980. return -EIO;
  981. }
  982. /* Init the hardware's rate fallback order based on the band */
  983. rc = iwl3945_init_hw_rate_table(priv);
  984. if (rc) {
  985. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  986. return -EIO;
  987. }
  988. return 0;
  989. }
  990. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  991. {
  992. struct iwl3945_bt_cmd bt_cmd = {
  993. .flags = 3,
  994. .lead_time = 0xAA,
  995. .max_kill = 1,
  996. .kill_ack_mask = 0,
  997. .kill_cts_mask = 0,
  998. };
  999. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1000. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  1001. }
  1002. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  1003. {
  1004. int rc = 0;
  1005. struct iwl3945_rx_packet *res;
  1006. struct iwl3945_host_cmd cmd = {
  1007. .id = REPLY_SCAN_ABORT_CMD,
  1008. .meta.flags = CMD_WANT_SKB,
  1009. };
  1010. /* If there isn't a scan actively going on in the hardware
  1011. * then we are in between scan bands and not actually
  1012. * actively scanning, so don't send the abort command */
  1013. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1014. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1015. return 0;
  1016. }
  1017. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1018. if (rc) {
  1019. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1020. return rc;
  1021. }
  1022. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1023. if (res->u.status != CAN_ABORT_STATUS) {
  1024. /* The scan abort will return 1 for success or
  1025. * 2 for "failure". A failure condition can be
  1026. * due to simply not being in an active scan which
  1027. * can occur if we send the scan abort before we
  1028. * the microcode has notified us that a scan is
  1029. * completed. */
  1030. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1031. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1032. clear_bit(STATUS_SCAN_HW, &priv->status);
  1033. }
  1034. dev_kfree_skb_any(cmd.meta.u.skb);
  1035. return rc;
  1036. }
  1037. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1038. struct iwl3945_cmd *cmd,
  1039. struct sk_buff *skb)
  1040. {
  1041. return 1;
  1042. }
  1043. /*
  1044. * CARD_STATE_CMD
  1045. *
  1046. * Use: Sets the device's internal card state to enable, disable, or halt
  1047. *
  1048. * When in the 'enable' state the card operates as normal.
  1049. * When in the 'disable' state, the card enters into a low power mode.
  1050. * When in the 'halt' state, the card is shut down and must be fully
  1051. * restarted to come back on.
  1052. */
  1053. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1054. {
  1055. struct iwl3945_host_cmd cmd = {
  1056. .id = REPLY_CARD_STATE_CMD,
  1057. .len = sizeof(u32),
  1058. .data = &flags,
  1059. .meta.flags = meta_flag,
  1060. };
  1061. if (meta_flag & CMD_ASYNC)
  1062. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1063. return iwl3945_send_cmd(priv, &cmd);
  1064. }
  1065. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1066. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1067. {
  1068. struct iwl3945_rx_packet *res = NULL;
  1069. if (!skb) {
  1070. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1071. return 1;
  1072. }
  1073. res = (struct iwl3945_rx_packet *)skb->data;
  1074. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1075. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1076. res->hdr.flags);
  1077. return 1;
  1078. }
  1079. switch (res->u.add_sta.status) {
  1080. case ADD_STA_SUCCESS_MSK:
  1081. break;
  1082. default:
  1083. break;
  1084. }
  1085. /* We didn't cache the SKB; let the caller free it */
  1086. return 1;
  1087. }
  1088. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1089. struct iwl3945_addsta_cmd *sta, u8 flags)
  1090. {
  1091. struct iwl3945_rx_packet *res = NULL;
  1092. int rc = 0;
  1093. struct iwl3945_host_cmd cmd = {
  1094. .id = REPLY_ADD_STA,
  1095. .len = sizeof(struct iwl3945_addsta_cmd),
  1096. .meta.flags = flags,
  1097. .data = sta,
  1098. };
  1099. if (flags & CMD_ASYNC)
  1100. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1101. else
  1102. cmd.meta.flags |= CMD_WANT_SKB;
  1103. rc = iwl3945_send_cmd(priv, &cmd);
  1104. if (rc || (flags & CMD_ASYNC))
  1105. return rc;
  1106. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1107. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1108. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1109. res->hdr.flags);
  1110. rc = -EIO;
  1111. }
  1112. if (rc == 0) {
  1113. switch (res->u.add_sta.status) {
  1114. case ADD_STA_SUCCESS_MSK:
  1115. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1116. break;
  1117. default:
  1118. rc = -EIO;
  1119. IWL_WARNING("REPLY_ADD_STA failed\n");
  1120. break;
  1121. }
  1122. }
  1123. priv->alloc_rxb_skb--;
  1124. dev_kfree_skb_any(cmd.meta.u.skb);
  1125. return rc;
  1126. }
  1127. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1128. struct ieee80211_key_conf *keyconf,
  1129. u8 sta_id)
  1130. {
  1131. unsigned long flags;
  1132. __le16 key_flags = 0;
  1133. switch (keyconf->alg) {
  1134. case ALG_CCMP:
  1135. key_flags |= STA_KEY_FLG_CCMP;
  1136. key_flags |= cpu_to_le16(
  1137. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1138. key_flags &= ~STA_KEY_FLG_INVALID;
  1139. break;
  1140. case ALG_TKIP:
  1141. case ALG_WEP:
  1142. default:
  1143. return -EINVAL;
  1144. }
  1145. spin_lock_irqsave(&priv->sta_lock, flags);
  1146. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1147. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1148. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1149. keyconf->keylen);
  1150. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1151. keyconf->keylen);
  1152. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1153. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1154. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1155. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1156. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1157. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1158. return 0;
  1159. }
  1160. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1161. {
  1162. unsigned long flags;
  1163. spin_lock_irqsave(&priv->sta_lock, flags);
  1164. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1165. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1166. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1167. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1168. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1169. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1170. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1171. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1172. return 0;
  1173. }
  1174. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1175. {
  1176. struct list_head *element;
  1177. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1178. priv->frames_count);
  1179. while (!list_empty(&priv->free_frames)) {
  1180. element = priv->free_frames.next;
  1181. list_del(element);
  1182. kfree(list_entry(element, struct iwl3945_frame, list));
  1183. priv->frames_count--;
  1184. }
  1185. if (priv->frames_count) {
  1186. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1187. priv->frames_count);
  1188. priv->frames_count = 0;
  1189. }
  1190. }
  1191. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1192. {
  1193. struct iwl3945_frame *frame;
  1194. struct list_head *element;
  1195. if (list_empty(&priv->free_frames)) {
  1196. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1197. if (!frame) {
  1198. IWL_ERROR("Could not allocate frame!\n");
  1199. return NULL;
  1200. }
  1201. priv->frames_count++;
  1202. return frame;
  1203. }
  1204. element = priv->free_frames.next;
  1205. list_del(element);
  1206. return list_entry(element, struct iwl3945_frame, list);
  1207. }
  1208. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1209. {
  1210. memset(frame, 0, sizeof(*frame));
  1211. list_add(&frame->list, &priv->free_frames);
  1212. }
  1213. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1214. struct ieee80211_hdr *hdr,
  1215. const u8 *dest, int left)
  1216. {
  1217. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1218. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1219. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1220. return 0;
  1221. if (priv->ibss_beacon->len > left)
  1222. return 0;
  1223. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1224. return priv->ibss_beacon->len;
  1225. }
  1226. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1227. {
  1228. u8 i;
  1229. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1230. i = iwl3945_rates[i].next_ieee) {
  1231. if (rate_mask & (1 << i))
  1232. return iwl3945_rates[i].plcp;
  1233. }
  1234. return IWL_RATE_INVALID;
  1235. }
  1236. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1237. {
  1238. struct iwl3945_frame *frame;
  1239. unsigned int frame_size;
  1240. int rc;
  1241. u8 rate;
  1242. frame = iwl3945_get_free_frame(priv);
  1243. if (!frame) {
  1244. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1245. "command.\n");
  1246. return -ENOMEM;
  1247. }
  1248. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1249. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1250. 0xFF0);
  1251. if (rate == IWL_INVALID_RATE)
  1252. rate = IWL_RATE_6M_PLCP;
  1253. } else {
  1254. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1255. if (rate == IWL_INVALID_RATE)
  1256. rate = IWL_RATE_1M_PLCP;
  1257. }
  1258. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1259. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1260. &frame->u.cmd[0]);
  1261. iwl3945_free_frame(priv, frame);
  1262. return rc;
  1263. }
  1264. /******************************************************************************
  1265. *
  1266. * EEPROM related functions
  1267. *
  1268. ******************************************************************************/
  1269. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1270. {
  1271. memcpy(mac, priv->eeprom.mac_address, 6);
  1272. }
  1273. /*
  1274. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1275. * embedded controller) as EEPROM reader; each read is a series of pulses
  1276. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1277. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1278. * simply claims ownership, which should be safe when this function is called
  1279. * (i.e. before loading uCode!).
  1280. */
  1281. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1282. {
  1283. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1284. return 0;
  1285. }
  1286. /**
  1287. * iwl3945_eeprom_init - read EEPROM contents
  1288. *
  1289. * Load the EEPROM contents from adapter into priv->eeprom
  1290. *
  1291. * NOTE: This routine uses the non-debug IO access functions.
  1292. */
  1293. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1294. {
  1295. u16 *e = (u16 *)&priv->eeprom;
  1296. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1297. u32 r;
  1298. int sz = sizeof(priv->eeprom);
  1299. int rc;
  1300. int i;
  1301. u16 addr;
  1302. /* The EEPROM structure has several padding buffers within it
  1303. * and when adding new EEPROM maps is subject to programmer errors
  1304. * which may be very difficult to identify without explicitly
  1305. * checking the resulting size of the eeprom map. */
  1306. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1307. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1308. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1309. return -ENOENT;
  1310. }
  1311. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1312. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1313. if (rc < 0) {
  1314. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1315. return -ENOENT;
  1316. }
  1317. /* eeprom is an array of 16bit values */
  1318. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1319. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1320. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1321. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1322. i += IWL_EEPROM_ACCESS_DELAY) {
  1323. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1324. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1325. break;
  1326. udelay(IWL_EEPROM_ACCESS_DELAY);
  1327. }
  1328. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1329. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1330. return -ETIMEDOUT;
  1331. }
  1332. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1333. }
  1334. return 0;
  1335. }
  1336. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1337. {
  1338. if (priv->hw_setting.shared_virt)
  1339. pci_free_consistent(priv->pci_dev,
  1340. sizeof(struct iwl3945_shared),
  1341. priv->hw_setting.shared_virt,
  1342. priv->hw_setting.shared_phys);
  1343. }
  1344. /**
  1345. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1346. *
  1347. * return : set the bit for each supported rate insert in ie
  1348. */
  1349. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1350. u16 basic_rate, int *left)
  1351. {
  1352. u16 ret_rates = 0, bit;
  1353. int i;
  1354. u8 *cnt = ie;
  1355. u8 *rates = ie + 1;
  1356. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1357. if (bit & supported_rate) {
  1358. ret_rates |= bit;
  1359. rates[*cnt] = iwl3945_rates[i].ieee |
  1360. ((bit & basic_rate) ? 0x80 : 0x00);
  1361. (*cnt)++;
  1362. (*left)--;
  1363. if ((*left <= 0) ||
  1364. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1365. break;
  1366. }
  1367. }
  1368. return ret_rates;
  1369. }
  1370. /**
  1371. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1372. */
  1373. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1374. struct ieee80211_mgmt *frame,
  1375. int left, int is_direct)
  1376. {
  1377. int len = 0;
  1378. u8 *pos = NULL;
  1379. u16 active_rates, ret_rates, cck_rates;
  1380. /* Make sure there is enough space for the probe request,
  1381. * two mandatory IEs and the data */
  1382. left -= 24;
  1383. if (left < 0)
  1384. return 0;
  1385. len += 24;
  1386. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1387. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1388. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1389. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1390. frame->seq_ctrl = 0;
  1391. /* fill in our indirect SSID IE */
  1392. /* ...next IE... */
  1393. left -= 2;
  1394. if (left < 0)
  1395. return 0;
  1396. len += 2;
  1397. pos = &(frame->u.probe_req.variable[0]);
  1398. *pos++ = WLAN_EID_SSID;
  1399. *pos++ = 0;
  1400. /* fill in our direct SSID IE... */
  1401. if (is_direct) {
  1402. /* ...next IE... */
  1403. left -= 2 + priv->essid_len;
  1404. if (left < 0)
  1405. return 0;
  1406. /* ... fill it in... */
  1407. *pos++ = WLAN_EID_SSID;
  1408. *pos++ = priv->essid_len;
  1409. memcpy(pos, priv->essid, priv->essid_len);
  1410. pos += priv->essid_len;
  1411. len += 2 + priv->essid_len;
  1412. }
  1413. /* fill in supported rate */
  1414. /* ...next IE... */
  1415. left -= 2;
  1416. if (left < 0)
  1417. return 0;
  1418. /* ... fill it in... */
  1419. *pos++ = WLAN_EID_SUPP_RATES;
  1420. *pos = 0;
  1421. priv->active_rate = priv->rates_mask;
  1422. active_rates = priv->active_rate;
  1423. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1424. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1425. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1426. priv->active_rate_basic, &left);
  1427. active_rates &= ~ret_rates;
  1428. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1429. priv->active_rate_basic, &left);
  1430. active_rates &= ~ret_rates;
  1431. len += 2 + *pos;
  1432. pos += (*pos) + 1;
  1433. if (active_rates == 0)
  1434. goto fill_end;
  1435. /* fill in supported extended rate */
  1436. /* ...next IE... */
  1437. left -= 2;
  1438. if (left < 0)
  1439. return 0;
  1440. /* ... fill it in... */
  1441. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1442. *pos = 0;
  1443. iwl3945_supported_rate_to_ie(pos, active_rates,
  1444. priv->active_rate_basic, &left);
  1445. if (*pos > 0)
  1446. len += 2 + *pos;
  1447. fill_end:
  1448. return (u16)len;
  1449. }
  1450. /*
  1451. * QoS support
  1452. */
  1453. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1454. struct iwl3945_qosparam_cmd *qos)
  1455. {
  1456. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1457. sizeof(struct iwl3945_qosparam_cmd), qos);
  1458. }
  1459. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1460. {
  1461. u16 cw_min = 15;
  1462. u16 cw_max = 1023;
  1463. u8 aifs = 2;
  1464. u8 is_legacy = 0;
  1465. unsigned long flags;
  1466. int i;
  1467. spin_lock_irqsave(&priv->lock, flags);
  1468. priv->qos_data.qos_active = 0;
  1469. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1470. if (priv->qos_data.qos_enable)
  1471. priv->qos_data.qos_active = 1;
  1472. if (!(priv->active_rate & 0xfff0)) {
  1473. cw_min = 31;
  1474. is_legacy = 1;
  1475. }
  1476. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1477. if (priv->qos_data.qos_enable)
  1478. priv->qos_data.qos_active = 1;
  1479. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1480. cw_min = 31;
  1481. is_legacy = 1;
  1482. }
  1483. if (priv->qos_data.qos_active)
  1484. aifs = 3;
  1485. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1486. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1487. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1488. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1489. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1490. if (priv->qos_data.qos_active) {
  1491. i = 1;
  1492. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1493. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1494. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1495. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1496. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1497. i = 2;
  1498. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1499. cpu_to_le16((cw_min + 1) / 2 - 1);
  1500. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1501. cpu_to_le16(cw_max);
  1502. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1503. if (is_legacy)
  1504. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1505. cpu_to_le16(6016);
  1506. else
  1507. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1508. cpu_to_le16(3008);
  1509. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1510. i = 3;
  1511. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1512. cpu_to_le16((cw_min + 1) / 4 - 1);
  1513. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1514. cpu_to_le16((cw_max + 1) / 2 - 1);
  1515. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1516. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1517. if (is_legacy)
  1518. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1519. cpu_to_le16(3264);
  1520. else
  1521. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1522. cpu_to_le16(1504);
  1523. } else {
  1524. for (i = 1; i < 4; i++) {
  1525. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1526. cpu_to_le16(cw_min);
  1527. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1528. cpu_to_le16(cw_max);
  1529. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1530. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1531. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1532. }
  1533. }
  1534. IWL_DEBUG_QOS("set QoS to default \n");
  1535. spin_unlock_irqrestore(&priv->lock, flags);
  1536. }
  1537. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1538. {
  1539. unsigned long flags;
  1540. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1541. return;
  1542. if (!priv->qos_data.qos_enable)
  1543. return;
  1544. spin_lock_irqsave(&priv->lock, flags);
  1545. priv->qos_data.def_qos_parm.qos_flags = 0;
  1546. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1547. !priv->qos_data.qos_cap.q_AP.txop_request)
  1548. priv->qos_data.def_qos_parm.qos_flags |=
  1549. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1550. if (priv->qos_data.qos_active)
  1551. priv->qos_data.def_qos_parm.qos_flags |=
  1552. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1553. spin_unlock_irqrestore(&priv->lock, flags);
  1554. if (force || iwl3945_is_associated(priv)) {
  1555. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1556. priv->qos_data.qos_active);
  1557. iwl3945_send_qos_params_command(priv,
  1558. &(priv->qos_data.def_qos_parm));
  1559. }
  1560. }
  1561. /*
  1562. * Power management (not Tx power!) functions
  1563. */
  1564. #define MSEC_TO_USEC 1024
  1565. #define NOSLP __constant_cpu_to_le32(0)
  1566. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1567. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1568. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1569. __constant_cpu_to_le32(X1), \
  1570. __constant_cpu_to_le32(X2), \
  1571. __constant_cpu_to_le32(X3), \
  1572. __constant_cpu_to_le32(X4)}
  1573. /* default power management (not Tx power) table values */
  1574. /* for tim 0-10 */
  1575. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1576. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1577. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1578. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1579. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1580. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1581. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1582. };
  1583. /* for tim > 10 */
  1584. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1585. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1586. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1587. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1588. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1589. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1590. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1591. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1592. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1593. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1594. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1595. };
  1596. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1597. {
  1598. int rc = 0, i;
  1599. struct iwl3945_power_mgr *pow_data;
  1600. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1601. u16 pci_pm;
  1602. IWL_DEBUG_POWER("Initialize power \n");
  1603. pow_data = &(priv->power_data);
  1604. memset(pow_data, 0, sizeof(*pow_data));
  1605. pow_data->active_index = IWL_POWER_RANGE_0;
  1606. pow_data->dtim_val = 0xffff;
  1607. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1608. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1609. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1610. if (rc != 0)
  1611. return 0;
  1612. else {
  1613. struct iwl3945_powertable_cmd *cmd;
  1614. IWL_DEBUG_POWER("adjust power command flags\n");
  1615. for (i = 0; i < IWL_POWER_AC; i++) {
  1616. cmd = &pow_data->pwr_range_0[i].cmd;
  1617. if (pci_pm & 0x1)
  1618. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1619. else
  1620. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1621. }
  1622. }
  1623. return rc;
  1624. }
  1625. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1626. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1627. {
  1628. int rc = 0, i;
  1629. u8 skip;
  1630. u32 max_sleep = 0;
  1631. struct iwl3945_power_vec_entry *range;
  1632. u8 period = 0;
  1633. struct iwl3945_power_mgr *pow_data;
  1634. if (mode > IWL_POWER_INDEX_5) {
  1635. IWL_DEBUG_POWER("Error invalid power mode \n");
  1636. return -1;
  1637. }
  1638. pow_data = &(priv->power_data);
  1639. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1640. range = &pow_data->pwr_range_0[0];
  1641. else
  1642. range = &pow_data->pwr_range_1[1];
  1643. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1644. #ifdef IWL_MAC80211_DISABLE
  1645. if (priv->assoc_network != NULL) {
  1646. unsigned long flags;
  1647. period = priv->assoc_network->tim.tim_period;
  1648. }
  1649. #endif /*IWL_MAC80211_DISABLE */
  1650. skip = range[mode].no_dtim;
  1651. if (period == 0) {
  1652. period = 1;
  1653. skip = 0;
  1654. }
  1655. if (skip == 0) {
  1656. max_sleep = period;
  1657. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1658. } else {
  1659. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1660. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1661. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1662. }
  1663. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1664. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1665. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1666. }
  1667. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1668. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1669. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1670. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1671. le32_to_cpu(cmd->sleep_interval[0]),
  1672. le32_to_cpu(cmd->sleep_interval[1]),
  1673. le32_to_cpu(cmd->sleep_interval[2]),
  1674. le32_to_cpu(cmd->sleep_interval[3]),
  1675. le32_to_cpu(cmd->sleep_interval[4]));
  1676. return rc;
  1677. }
  1678. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1679. {
  1680. u32 uninitialized_var(final_mode);
  1681. int rc;
  1682. struct iwl3945_powertable_cmd cmd;
  1683. /* If on battery, set to 3,
  1684. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1685. * else user level */
  1686. switch (mode) {
  1687. case IWL_POWER_BATTERY:
  1688. final_mode = IWL_POWER_INDEX_3;
  1689. break;
  1690. case IWL_POWER_AC:
  1691. final_mode = IWL_POWER_MODE_CAM;
  1692. break;
  1693. default:
  1694. final_mode = mode;
  1695. break;
  1696. }
  1697. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1698. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1699. if (final_mode == IWL_POWER_MODE_CAM)
  1700. clear_bit(STATUS_POWER_PMI, &priv->status);
  1701. else
  1702. set_bit(STATUS_POWER_PMI, &priv->status);
  1703. return rc;
  1704. }
  1705. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1706. {
  1707. /* Filter incoming packets to determine if they are targeted toward
  1708. * this network, discarding packets coming from ourselves */
  1709. switch (priv->iw_mode) {
  1710. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1711. /* packets from our adapter are dropped (echo) */
  1712. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1713. return 0;
  1714. /* {broad,multi}cast packets to our IBSS go through */
  1715. if (is_multicast_ether_addr(header->addr1))
  1716. return !compare_ether_addr(header->addr3, priv->bssid);
  1717. /* packets to our adapter go through */
  1718. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1719. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1720. /* packets from our adapter are dropped (echo) */
  1721. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1722. return 0;
  1723. /* {broad,multi}cast packets to our BSS go through */
  1724. if (is_multicast_ether_addr(header->addr1))
  1725. return !compare_ether_addr(header->addr2, priv->bssid);
  1726. /* packets to our adapter go through */
  1727. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1728. default:
  1729. return 1;
  1730. }
  1731. return 1;
  1732. }
  1733. /**
  1734. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1735. *
  1736. * NOTE: priv->mutex is not required before calling this function
  1737. */
  1738. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1739. {
  1740. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1741. clear_bit(STATUS_SCANNING, &priv->status);
  1742. return 0;
  1743. }
  1744. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1745. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1746. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1747. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1748. queue_work(priv->workqueue, &priv->abort_scan);
  1749. } else
  1750. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1751. return test_bit(STATUS_SCANNING, &priv->status);
  1752. }
  1753. return 0;
  1754. }
  1755. /**
  1756. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1757. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1758. *
  1759. * NOTE: priv->mutex must be held before calling this function
  1760. */
  1761. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1762. {
  1763. unsigned long now = jiffies;
  1764. int ret;
  1765. ret = iwl3945_scan_cancel(priv);
  1766. if (ret && ms) {
  1767. mutex_unlock(&priv->mutex);
  1768. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1769. test_bit(STATUS_SCANNING, &priv->status))
  1770. msleep(1);
  1771. mutex_lock(&priv->mutex);
  1772. return test_bit(STATUS_SCANNING, &priv->status);
  1773. }
  1774. return ret;
  1775. }
  1776. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1777. {
  1778. /* Reset ieee stats */
  1779. /* We don't reset the net_device_stats (ieee->stats) on
  1780. * re-association */
  1781. priv->last_seq_num = -1;
  1782. priv->last_frag_num = -1;
  1783. priv->last_packet_time = 0;
  1784. iwl3945_scan_cancel(priv);
  1785. }
  1786. #define MAX_UCODE_BEACON_INTERVAL 1024
  1787. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1788. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1789. {
  1790. u16 new_val = 0;
  1791. u16 beacon_factor = 0;
  1792. beacon_factor =
  1793. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1794. / MAX_UCODE_BEACON_INTERVAL;
  1795. new_val = beacon_val / beacon_factor;
  1796. return cpu_to_le16(new_val);
  1797. }
  1798. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1799. {
  1800. u64 interval_tm_unit;
  1801. u64 tsf, result;
  1802. unsigned long flags;
  1803. struct ieee80211_conf *conf = NULL;
  1804. u16 beacon_int = 0;
  1805. conf = ieee80211_get_hw_conf(priv->hw);
  1806. spin_lock_irqsave(&priv->lock, flags);
  1807. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1808. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1809. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1810. tsf = priv->timestamp1;
  1811. tsf = ((tsf << 32) | priv->timestamp0);
  1812. beacon_int = priv->beacon_int;
  1813. spin_unlock_irqrestore(&priv->lock, flags);
  1814. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1815. if (beacon_int == 0) {
  1816. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1817. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1818. } else {
  1819. priv->rxon_timing.beacon_interval =
  1820. cpu_to_le16(beacon_int);
  1821. priv->rxon_timing.beacon_interval =
  1822. iwl3945_adjust_beacon_interval(
  1823. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1824. }
  1825. priv->rxon_timing.atim_window = 0;
  1826. } else {
  1827. priv->rxon_timing.beacon_interval =
  1828. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1829. /* TODO: we need to get atim_window from upper stack
  1830. * for now we set to 0 */
  1831. priv->rxon_timing.atim_window = 0;
  1832. }
  1833. interval_tm_unit =
  1834. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1835. result = do_div(tsf, interval_tm_unit);
  1836. priv->rxon_timing.beacon_init_val =
  1837. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1838. IWL_DEBUG_ASSOC
  1839. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1840. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1841. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1842. le16_to_cpu(priv->rxon_timing.atim_window));
  1843. }
  1844. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1845. {
  1846. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1847. IWL_ERROR("APs don't scan.\n");
  1848. return 0;
  1849. }
  1850. if (!iwl3945_is_ready_rf(priv)) {
  1851. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1852. return -EIO;
  1853. }
  1854. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1855. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1856. return -EAGAIN;
  1857. }
  1858. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1859. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1860. "Queuing.\n");
  1861. return -EAGAIN;
  1862. }
  1863. IWL_DEBUG_INFO("Starting scan...\n");
  1864. priv->scan_bands = 2;
  1865. set_bit(STATUS_SCANNING, &priv->status);
  1866. priv->scan_start = jiffies;
  1867. priv->scan_pass_start = priv->scan_start;
  1868. queue_work(priv->workqueue, &priv->request_scan);
  1869. return 0;
  1870. }
  1871. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1872. {
  1873. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1874. if (hw_decrypt)
  1875. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1876. else
  1877. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1878. return 0;
  1879. }
  1880. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1881. enum ieee80211_band band)
  1882. {
  1883. if (band == IEEE80211_BAND_5GHZ) {
  1884. priv->staging_rxon.flags &=
  1885. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1886. | RXON_FLG_CCK_MSK);
  1887. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1888. } else {
  1889. /* Copied from iwl3945_bg_post_associate() */
  1890. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1891. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1892. else
  1893. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1894. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  1895. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1896. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1897. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1898. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1899. }
  1900. }
  1901. /*
  1902. * initialize rxon structure with default values from eeprom
  1903. */
  1904. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1905. {
  1906. const struct iwl3945_channel_info *ch_info;
  1907. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1908. switch (priv->iw_mode) {
  1909. case IEEE80211_IF_TYPE_AP:
  1910. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1911. break;
  1912. case IEEE80211_IF_TYPE_STA:
  1913. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1914. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1915. break;
  1916. case IEEE80211_IF_TYPE_IBSS:
  1917. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1918. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1919. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1920. RXON_FILTER_ACCEPT_GRP_MSK;
  1921. break;
  1922. case IEEE80211_IF_TYPE_MNTR:
  1923. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1924. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1925. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1926. break;
  1927. default:
  1928. IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
  1929. break;
  1930. }
  1931. #if 0
  1932. /* TODO: Figure out when short_preamble would be set and cache from
  1933. * that */
  1934. if (!hw_to_local(priv->hw)->short_preamble)
  1935. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1936. else
  1937. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1938. #endif
  1939. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1940. le16_to_cpu(priv->staging_rxon.channel));
  1941. if (!ch_info)
  1942. ch_info = &priv->channel_info[0];
  1943. /*
  1944. * in some case A channels are all non IBSS
  1945. * in this case force B/G channel
  1946. */
  1947. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  1948. !(is_channel_ibss(ch_info)))
  1949. ch_info = &priv->channel_info[0];
  1950. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1951. if (is_channel_a_band(ch_info))
  1952. priv->band = IEEE80211_BAND_5GHZ;
  1953. else
  1954. priv->band = IEEE80211_BAND_2GHZ;
  1955. iwl3945_set_flags_for_phymode(priv, priv->band);
  1956. priv->staging_rxon.ofdm_basic_rates =
  1957. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1958. priv->staging_rxon.cck_basic_rates =
  1959. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1960. }
  1961. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1962. {
  1963. if (mode == IEEE80211_IF_TYPE_IBSS) {
  1964. const struct iwl3945_channel_info *ch_info;
  1965. ch_info = iwl3945_get_channel_info(priv,
  1966. priv->band,
  1967. le16_to_cpu(priv->staging_rxon.channel));
  1968. if (!ch_info || !is_channel_ibss(ch_info)) {
  1969. IWL_ERROR("channel %d not IBSS channel\n",
  1970. le16_to_cpu(priv->staging_rxon.channel));
  1971. return -EINVAL;
  1972. }
  1973. }
  1974. priv->iw_mode = mode;
  1975. iwl3945_connection_init_rx_config(priv);
  1976. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1977. iwl3945_clear_stations_table(priv);
  1978. /* dont commit rxon if rf-kill is on*/
  1979. if (!iwl3945_is_ready_rf(priv))
  1980. return -EAGAIN;
  1981. cancel_delayed_work(&priv->scan_check);
  1982. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1983. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1984. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1985. return -EAGAIN;
  1986. }
  1987. iwl3945_commit_rxon(priv);
  1988. return 0;
  1989. }
  1990. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1991. struct ieee80211_tx_control *ctl,
  1992. struct iwl3945_cmd *cmd,
  1993. struct sk_buff *skb_frag,
  1994. int last_frag)
  1995. {
  1996. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  1997. switch (keyinfo->alg) {
  1998. case ALG_CCMP:
  1999. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2000. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2001. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2002. break;
  2003. case ALG_TKIP:
  2004. #if 0
  2005. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2006. if (last_frag)
  2007. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2008. 8);
  2009. else
  2010. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2011. #endif
  2012. break;
  2013. case ALG_WEP:
  2014. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2015. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2016. if (keyinfo->keylen == 13)
  2017. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2018. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2019. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2020. "with key %d\n", ctl->key_idx);
  2021. break;
  2022. default:
  2023. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2024. break;
  2025. }
  2026. }
  2027. /*
  2028. * handle build REPLY_TX command notification.
  2029. */
  2030. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2031. struct iwl3945_cmd *cmd,
  2032. struct ieee80211_tx_control *ctrl,
  2033. struct ieee80211_hdr *hdr,
  2034. int is_unicast, u8 std_id)
  2035. {
  2036. __le16 *qc;
  2037. u16 fc = le16_to_cpu(hdr->frame_control);
  2038. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2039. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2040. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2041. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2042. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2043. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2044. if (ieee80211_is_probe_response(fc) &&
  2045. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2046. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2047. } else {
  2048. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2049. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2050. }
  2051. cmd->cmd.tx.sta_id = std_id;
  2052. if (ieee80211_get_morefrag(hdr))
  2053. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2054. qc = ieee80211_get_qos_ctrl(hdr);
  2055. if (qc) {
  2056. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2057. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2058. } else
  2059. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2060. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2061. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2062. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2063. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2064. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2065. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2066. }
  2067. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2068. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2069. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2070. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2071. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2072. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2073. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2074. else
  2075. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2076. } else {
  2077. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2078. #ifdef CONFIG_IWL3945_LEDS
  2079. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  2080. #endif
  2081. }
  2082. cmd->cmd.tx.driver_txop = 0;
  2083. cmd->cmd.tx.tx_flags = tx_flags;
  2084. cmd->cmd.tx.next_frame_len = 0;
  2085. }
  2086. /**
  2087. * iwl3945_get_sta_id - Find station's index within station table
  2088. */
  2089. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2090. {
  2091. int sta_id;
  2092. u16 fc = le16_to_cpu(hdr->frame_control);
  2093. /* If this frame is broadcast or management, use broadcast station id */
  2094. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2095. is_multicast_ether_addr(hdr->addr1))
  2096. return priv->hw_setting.bcast_sta_id;
  2097. switch (priv->iw_mode) {
  2098. /* If we are a client station in a BSS network, use the special
  2099. * AP station entry (that's the only station we communicate with) */
  2100. case IEEE80211_IF_TYPE_STA:
  2101. return IWL_AP_ID;
  2102. /* If we are an AP, then find the station, or use BCAST */
  2103. case IEEE80211_IF_TYPE_AP:
  2104. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2105. if (sta_id != IWL_INVALID_STATION)
  2106. return sta_id;
  2107. return priv->hw_setting.bcast_sta_id;
  2108. /* If this frame is going out to an IBSS network, find the station,
  2109. * or create a new station table entry */
  2110. case IEEE80211_IF_TYPE_IBSS: {
  2111. DECLARE_MAC_BUF(mac);
  2112. /* Create new station table entry */
  2113. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2114. if (sta_id != IWL_INVALID_STATION)
  2115. return sta_id;
  2116. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2117. if (sta_id != IWL_INVALID_STATION)
  2118. return sta_id;
  2119. IWL_DEBUG_DROP("Station %s not in station map. "
  2120. "Defaulting to broadcast...\n",
  2121. print_mac(mac, hdr->addr1));
  2122. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2123. return priv->hw_setting.bcast_sta_id;
  2124. }
  2125. default:
  2126. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2127. return priv->hw_setting.bcast_sta_id;
  2128. }
  2129. }
  2130. /*
  2131. * start REPLY_TX command process
  2132. */
  2133. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2134. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2135. {
  2136. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2137. struct iwl3945_tfd_frame *tfd;
  2138. u32 *control_flags;
  2139. int txq_id = ctl->queue;
  2140. struct iwl3945_tx_queue *txq = NULL;
  2141. struct iwl3945_queue *q = NULL;
  2142. dma_addr_t phys_addr;
  2143. dma_addr_t txcmd_phys;
  2144. struct iwl3945_cmd *out_cmd = NULL;
  2145. u16 len, idx, len_org;
  2146. u8 id, hdr_len, unicast;
  2147. u8 sta_id;
  2148. u16 seq_number = 0;
  2149. u16 fc;
  2150. __le16 *qc;
  2151. u8 wait_write_ptr = 0;
  2152. unsigned long flags;
  2153. int rc;
  2154. spin_lock_irqsave(&priv->lock, flags);
  2155. if (iwl3945_is_rfkill(priv)) {
  2156. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2157. goto drop_unlock;
  2158. }
  2159. if (!priv->vif) {
  2160. IWL_DEBUG_DROP("Dropping - !priv->vif\n");
  2161. goto drop_unlock;
  2162. }
  2163. if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2164. IWL_ERROR("ERROR: No TX rate available.\n");
  2165. goto drop_unlock;
  2166. }
  2167. unicast = !is_multicast_ether_addr(hdr->addr1);
  2168. id = 0;
  2169. fc = le16_to_cpu(hdr->frame_control);
  2170. #ifdef CONFIG_IWL3945_DEBUG
  2171. if (ieee80211_is_auth(fc))
  2172. IWL_DEBUG_TX("Sending AUTH frame\n");
  2173. else if (ieee80211_is_assoc_request(fc))
  2174. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2175. else if (ieee80211_is_reassoc_request(fc))
  2176. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2177. #endif
  2178. /* drop all data frame if we are not associated */
  2179. if ((!iwl3945_is_associated(priv) ||
  2180. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
  2181. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2182. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2183. goto drop_unlock;
  2184. }
  2185. spin_unlock_irqrestore(&priv->lock, flags);
  2186. hdr_len = ieee80211_get_hdrlen(fc);
  2187. /* Find (or create) index into station table for destination station */
  2188. sta_id = iwl3945_get_sta_id(priv, hdr);
  2189. if (sta_id == IWL_INVALID_STATION) {
  2190. DECLARE_MAC_BUF(mac);
  2191. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2192. print_mac(mac, hdr->addr1));
  2193. goto drop;
  2194. }
  2195. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2196. qc = ieee80211_get_qos_ctrl(hdr);
  2197. if (qc) {
  2198. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2199. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2200. IEEE80211_SCTL_SEQ;
  2201. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2202. (hdr->seq_ctrl &
  2203. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2204. seq_number += 0x10;
  2205. }
  2206. /* Descriptor for chosen Tx queue */
  2207. txq = &priv->txq[txq_id];
  2208. q = &txq->q;
  2209. spin_lock_irqsave(&priv->lock, flags);
  2210. /* Set up first empty TFD within this queue's circular TFD buffer */
  2211. tfd = &txq->bd[q->write_ptr];
  2212. memset(tfd, 0, sizeof(*tfd));
  2213. control_flags = (u32 *) tfd;
  2214. idx = get_cmd_index(q, q->write_ptr, 0);
  2215. /* Set up driver data for this TFD */
  2216. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2217. txq->txb[q->write_ptr].skb[0] = skb;
  2218. memcpy(&(txq->txb[q->write_ptr].status.control),
  2219. ctl, sizeof(struct ieee80211_tx_control));
  2220. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2221. out_cmd = &txq->cmd[idx];
  2222. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2223. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2224. /*
  2225. * Set up the Tx-command (not MAC!) header.
  2226. * Store the chosen Tx queue and TFD index within the sequence field;
  2227. * after Tx, uCode's Tx response will return this value so driver can
  2228. * locate the frame within the tx queue and do post-tx processing.
  2229. */
  2230. out_cmd->hdr.cmd = REPLY_TX;
  2231. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2232. INDEX_TO_SEQ(q->write_ptr)));
  2233. /* Copy MAC header from skb into command buffer */
  2234. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2235. /*
  2236. * Use the first empty entry in this queue's command buffer array
  2237. * to contain the Tx command and MAC header concatenated together
  2238. * (payload data will be in another buffer).
  2239. * Size of this varies, due to varying MAC header length.
  2240. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2241. * of the MAC header (device reads on dword boundaries).
  2242. * We'll tell device about this padding later.
  2243. */
  2244. len = priv->hw_setting.tx_cmd_len +
  2245. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2246. len_org = len;
  2247. len = (len + 3) & ~3;
  2248. if (len_org != len)
  2249. len_org = 1;
  2250. else
  2251. len_org = 0;
  2252. /* Physical address of this Tx command's header (not MAC header!),
  2253. * within command buffer array. */
  2254. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2255. offsetof(struct iwl3945_cmd, hdr);
  2256. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2257. * first entry */
  2258. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2259. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2260. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2261. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2262. * if any (802.11 null frames have no payload). */
  2263. len = skb->len - hdr_len;
  2264. if (len) {
  2265. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2266. len, PCI_DMA_TODEVICE);
  2267. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2268. }
  2269. if (!len)
  2270. /* If there is no payload, then we use only one Tx buffer */
  2271. *control_flags = TFD_CTL_COUNT_SET(1);
  2272. else
  2273. /* Else use 2 buffers.
  2274. * Tell 3945 about any padding after MAC header */
  2275. *control_flags = TFD_CTL_COUNT_SET(2) |
  2276. TFD_CTL_PAD_SET(U32_PAD(len));
  2277. /* Total # bytes to be transmitted */
  2278. len = (u16)skb->len;
  2279. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2280. /* TODO need this for burst mode later on */
  2281. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2282. /* set is_hcca to 0; it probably will never be implemented */
  2283. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2284. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2285. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2286. if (!ieee80211_get_morefrag(hdr)) {
  2287. txq->need_update = 1;
  2288. if (qc) {
  2289. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2290. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2291. }
  2292. } else {
  2293. wait_write_ptr = 1;
  2294. txq->need_update = 0;
  2295. }
  2296. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2297. sizeof(out_cmd->cmd.tx));
  2298. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2299. ieee80211_get_hdrlen(fc));
  2300. /* Tell device the write index *just past* this latest filled TFD */
  2301. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2302. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2303. spin_unlock_irqrestore(&priv->lock, flags);
  2304. if (rc)
  2305. return rc;
  2306. if ((iwl3945_queue_space(q) < q->high_mark)
  2307. && priv->mac80211_registered) {
  2308. if (wait_write_ptr) {
  2309. spin_lock_irqsave(&priv->lock, flags);
  2310. txq->need_update = 1;
  2311. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2312. spin_unlock_irqrestore(&priv->lock, flags);
  2313. }
  2314. ieee80211_stop_queue(priv->hw, ctl->queue);
  2315. }
  2316. return 0;
  2317. drop_unlock:
  2318. spin_unlock_irqrestore(&priv->lock, flags);
  2319. drop:
  2320. return -1;
  2321. }
  2322. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2323. {
  2324. const struct ieee80211_supported_band *sband = NULL;
  2325. struct ieee80211_rate *rate;
  2326. int i;
  2327. sband = iwl3945_get_band(priv, priv->band);
  2328. if (!sband) {
  2329. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2330. return;
  2331. }
  2332. priv->active_rate = 0;
  2333. priv->active_rate_basic = 0;
  2334. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2335. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2336. for (i = 0; i < sband->n_bitrates; i++) {
  2337. rate = &sband->bitrates[i];
  2338. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2339. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2340. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2341. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2342. priv->active_rate |= (1 << rate->hw_value);
  2343. }
  2344. }
  2345. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2346. priv->active_rate, priv->active_rate_basic);
  2347. /*
  2348. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2349. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2350. * OFDM
  2351. */
  2352. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2353. priv->staging_rxon.cck_basic_rates =
  2354. ((priv->active_rate_basic &
  2355. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2356. else
  2357. priv->staging_rxon.cck_basic_rates =
  2358. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2359. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2360. priv->staging_rxon.ofdm_basic_rates =
  2361. ((priv->active_rate_basic &
  2362. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2363. IWL_FIRST_OFDM_RATE) & 0xFF;
  2364. else
  2365. priv->staging_rxon.ofdm_basic_rates =
  2366. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2367. }
  2368. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2369. {
  2370. unsigned long flags;
  2371. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2372. return;
  2373. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2374. disable_radio ? "OFF" : "ON");
  2375. if (disable_radio) {
  2376. iwl3945_scan_cancel(priv);
  2377. /* FIXME: This is a workaround for AP */
  2378. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2379. spin_lock_irqsave(&priv->lock, flags);
  2380. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2381. CSR_UCODE_SW_BIT_RFKILL);
  2382. spin_unlock_irqrestore(&priv->lock, flags);
  2383. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2384. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2385. }
  2386. return;
  2387. }
  2388. spin_lock_irqsave(&priv->lock, flags);
  2389. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2390. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2391. spin_unlock_irqrestore(&priv->lock, flags);
  2392. /* wake up ucode */
  2393. msleep(10);
  2394. spin_lock_irqsave(&priv->lock, flags);
  2395. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2396. if (!iwl3945_grab_nic_access(priv))
  2397. iwl3945_release_nic_access(priv);
  2398. spin_unlock_irqrestore(&priv->lock, flags);
  2399. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2400. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2401. "disabled by HW switch\n");
  2402. return;
  2403. }
  2404. queue_work(priv->workqueue, &priv->restart);
  2405. return;
  2406. }
  2407. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2408. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2409. {
  2410. u16 fc =
  2411. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2412. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2413. return;
  2414. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2415. return;
  2416. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2417. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2418. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2419. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2420. RX_RES_STATUS_BAD_ICV_MIC)
  2421. stats->flag |= RX_FLAG_MMIC_ERROR;
  2422. case RX_RES_STATUS_SEC_TYPE_WEP:
  2423. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2424. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2425. RX_RES_STATUS_DECRYPT_OK) {
  2426. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2427. stats->flag |= RX_FLAG_DECRYPTED;
  2428. }
  2429. break;
  2430. default:
  2431. break;
  2432. }
  2433. }
  2434. #define IWL_PACKET_RETRY_TIME HZ
  2435. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2436. {
  2437. u16 sc = le16_to_cpu(header->seq_ctrl);
  2438. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2439. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2440. u16 *last_seq, *last_frag;
  2441. unsigned long *last_time;
  2442. switch (priv->iw_mode) {
  2443. case IEEE80211_IF_TYPE_IBSS:{
  2444. struct list_head *p;
  2445. struct iwl3945_ibss_seq *entry = NULL;
  2446. u8 *mac = header->addr2;
  2447. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2448. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2449. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2450. if (!compare_ether_addr(entry->mac, mac))
  2451. break;
  2452. }
  2453. if (p == &priv->ibss_mac_hash[index]) {
  2454. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2455. if (!entry) {
  2456. IWL_ERROR("Cannot malloc new mac entry\n");
  2457. return 0;
  2458. }
  2459. memcpy(entry->mac, mac, ETH_ALEN);
  2460. entry->seq_num = seq;
  2461. entry->frag_num = frag;
  2462. entry->packet_time = jiffies;
  2463. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2464. return 0;
  2465. }
  2466. last_seq = &entry->seq_num;
  2467. last_frag = &entry->frag_num;
  2468. last_time = &entry->packet_time;
  2469. break;
  2470. }
  2471. case IEEE80211_IF_TYPE_STA:
  2472. last_seq = &priv->last_seq_num;
  2473. last_frag = &priv->last_frag_num;
  2474. last_time = &priv->last_packet_time;
  2475. break;
  2476. default:
  2477. return 0;
  2478. }
  2479. if ((*last_seq == seq) &&
  2480. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2481. if (*last_frag == frag)
  2482. goto drop;
  2483. if (*last_frag + 1 != frag)
  2484. /* out-of-order fragment */
  2485. goto drop;
  2486. } else
  2487. *last_seq = seq;
  2488. *last_frag = frag;
  2489. *last_time = jiffies;
  2490. return 0;
  2491. drop:
  2492. return 1;
  2493. }
  2494. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2495. #include "iwl-spectrum.h"
  2496. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2497. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2498. #define TIME_UNIT 1024
  2499. /*
  2500. * extended beacon time format
  2501. * time in usec will be changed into a 32-bit value in 8:24 format
  2502. * the high 1 byte is the beacon counts
  2503. * the lower 3 bytes is the time in usec within one beacon interval
  2504. */
  2505. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2506. {
  2507. u32 quot;
  2508. u32 rem;
  2509. u32 interval = beacon_interval * 1024;
  2510. if (!interval || !usec)
  2511. return 0;
  2512. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2513. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2514. return (quot << 24) + rem;
  2515. }
  2516. /* base is usually what we get from ucode with each received frame,
  2517. * the same as HW timer counter counting down
  2518. */
  2519. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2520. {
  2521. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2522. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2523. u32 interval = beacon_interval * TIME_UNIT;
  2524. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2525. (addon & BEACON_TIME_MASK_HIGH);
  2526. if (base_low > addon_low)
  2527. res += base_low - addon_low;
  2528. else if (base_low < addon_low) {
  2529. res += interval + base_low - addon_low;
  2530. res += (1 << 24);
  2531. } else
  2532. res += (1 << 24);
  2533. return cpu_to_le32(res);
  2534. }
  2535. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2536. struct ieee80211_measurement_params *params,
  2537. u8 type)
  2538. {
  2539. struct iwl3945_spectrum_cmd spectrum;
  2540. struct iwl3945_rx_packet *res;
  2541. struct iwl3945_host_cmd cmd = {
  2542. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2543. .data = (void *)&spectrum,
  2544. .meta.flags = CMD_WANT_SKB,
  2545. };
  2546. u32 add_time = le64_to_cpu(params->start_time);
  2547. int rc;
  2548. int spectrum_resp_status;
  2549. int duration = le16_to_cpu(params->duration);
  2550. if (iwl3945_is_associated(priv))
  2551. add_time =
  2552. iwl3945_usecs_to_beacons(
  2553. le64_to_cpu(params->start_time) - priv->last_tsf,
  2554. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2555. memset(&spectrum, 0, sizeof(spectrum));
  2556. spectrum.channel_count = cpu_to_le16(1);
  2557. spectrum.flags =
  2558. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2559. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2560. cmd.len = sizeof(spectrum);
  2561. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2562. if (iwl3945_is_associated(priv))
  2563. spectrum.start_time =
  2564. iwl3945_add_beacon_time(priv->last_beacon_time,
  2565. add_time,
  2566. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2567. else
  2568. spectrum.start_time = 0;
  2569. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2570. spectrum.channels[0].channel = params->channel;
  2571. spectrum.channels[0].type = type;
  2572. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2573. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2574. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2575. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2576. if (rc)
  2577. return rc;
  2578. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2579. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2580. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2581. rc = -EIO;
  2582. }
  2583. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2584. switch (spectrum_resp_status) {
  2585. case 0: /* Command will be handled */
  2586. if (res->u.spectrum.id != 0xff) {
  2587. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2588. res->u.spectrum.id);
  2589. priv->measurement_status &= ~MEASUREMENT_READY;
  2590. }
  2591. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2592. rc = 0;
  2593. break;
  2594. case 1: /* Command will not be handled */
  2595. rc = -EAGAIN;
  2596. break;
  2597. }
  2598. dev_kfree_skb_any(cmd.meta.u.skb);
  2599. return rc;
  2600. }
  2601. #endif
  2602. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2603. struct iwl3945_rx_mem_buffer *rxb)
  2604. {
  2605. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2606. struct iwl3945_alive_resp *palive;
  2607. struct delayed_work *pwork;
  2608. palive = &pkt->u.alive_frame;
  2609. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2610. "0x%01X 0x%01X\n",
  2611. palive->is_valid, palive->ver_type,
  2612. palive->ver_subtype);
  2613. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2614. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2615. memcpy(&priv->card_alive_init,
  2616. &pkt->u.alive_frame,
  2617. sizeof(struct iwl3945_init_alive_resp));
  2618. pwork = &priv->init_alive_start;
  2619. } else {
  2620. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2621. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2622. sizeof(struct iwl3945_alive_resp));
  2623. pwork = &priv->alive_start;
  2624. iwl3945_disable_events(priv);
  2625. }
  2626. /* We delay the ALIVE response by 5ms to
  2627. * give the HW RF Kill time to activate... */
  2628. if (palive->is_valid == UCODE_VALID_OK)
  2629. queue_delayed_work(priv->workqueue, pwork,
  2630. msecs_to_jiffies(5));
  2631. else
  2632. IWL_WARNING("uCode did not respond OK.\n");
  2633. }
  2634. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2635. struct iwl3945_rx_mem_buffer *rxb)
  2636. {
  2637. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2638. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2639. return;
  2640. }
  2641. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2642. struct iwl3945_rx_mem_buffer *rxb)
  2643. {
  2644. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2645. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2646. "seq 0x%04X ser 0x%08X\n",
  2647. le32_to_cpu(pkt->u.err_resp.error_type),
  2648. get_cmd_string(pkt->u.err_resp.cmd_id),
  2649. pkt->u.err_resp.cmd_id,
  2650. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2651. le32_to_cpu(pkt->u.err_resp.error_info));
  2652. }
  2653. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2654. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2655. {
  2656. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2657. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2658. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2659. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2660. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2661. rxon->channel = csa->channel;
  2662. priv->staging_rxon.channel = csa->channel;
  2663. }
  2664. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2665. struct iwl3945_rx_mem_buffer *rxb)
  2666. {
  2667. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2668. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2669. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2670. if (!report->state) {
  2671. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2672. "Spectrum Measure Notification: Start\n");
  2673. return;
  2674. }
  2675. memcpy(&priv->measure_report, report, sizeof(*report));
  2676. priv->measurement_status |= MEASUREMENT_READY;
  2677. #endif
  2678. }
  2679. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2680. struct iwl3945_rx_mem_buffer *rxb)
  2681. {
  2682. #ifdef CONFIG_IWL3945_DEBUG
  2683. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2684. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2685. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2686. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2687. #endif
  2688. }
  2689. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2690. struct iwl3945_rx_mem_buffer *rxb)
  2691. {
  2692. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2693. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2694. "notification for %s:\n",
  2695. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2696. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2697. }
  2698. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2699. {
  2700. struct iwl3945_priv *priv =
  2701. container_of(work, struct iwl3945_priv, beacon_update);
  2702. struct sk_buff *beacon;
  2703. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2704. beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
  2705. if (!beacon) {
  2706. IWL_ERROR("update beacon failed\n");
  2707. return;
  2708. }
  2709. mutex_lock(&priv->mutex);
  2710. /* new beacon skb is allocated every time; dispose previous.*/
  2711. if (priv->ibss_beacon)
  2712. dev_kfree_skb(priv->ibss_beacon);
  2713. priv->ibss_beacon = beacon;
  2714. mutex_unlock(&priv->mutex);
  2715. iwl3945_send_beacon_cmd(priv);
  2716. }
  2717. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2718. struct iwl3945_rx_mem_buffer *rxb)
  2719. {
  2720. #ifdef CONFIG_IWL3945_DEBUG
  2721. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2722. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2723. u8 rate = beacon->beacon_notify_hdr.rate;
  2724. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2725. "tsf %d %d rate %d\n",
  2726. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2727. beacon->beacon_notify_hdr.failure_frame,
  2728. le32_to_cpu(beacon->ibss_mgr_status),
  2729. le32_to_cpu(beacon->high_tsf),
  2730. le32_to_cpu(beacon->low_tsf), rate);
  2731. #endif
  2732. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2733. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2734. queue_work(priv->workqueue, &priv->beacon_update);
  2735. }
  2736. /* Service response to REPLY_SCAN_CMD (0x80) */
  2737. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2738. struct iwl3945_rx_mem_buffer *rxb)
  2739. {
  2740. #ifdef CONFIG_IWL3945_DEBUG
  2741. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2742. struct iwl3945_scanreq_notification *notif =
  2743. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2744. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2745. #endif
  2746. }
  2747. /* Service SCAN_START_NOTIFICATION (0x82) */
  2748. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2749. struct iwl3945_rx_mem_buffer *rxb)
  2750. {
  2751. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2752. struct iwl3945_scanstart_notification *notif =
  2753. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2754. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2755. IWL_DEBUG_SCAN("Scan start: "
  2756. "%d [802.11%s] "
  2757. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2758. notif->channel,
  2759. notif->band ? "bg" : "a",
  2760. notif->tsf_high,
  2761. notif->tsf_low, notif->status, notif->beacon_timer);
  2762. }
  2763. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2764. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2765. struct iwl3945_rx_mem_buffer *rxb)
  2766. {
  2767. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2768. struct iwl3945_scanresults_notification *notif =
  2769. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2770. IWL_DEBUG_SCAN("Scan ch.res: "
  2771. "%d [802.11%s] "
  2772. "(TSF: 0x%08X:%08X) - %d "
  2773. "elapsed=%lu usec (%dms since last)\n",
  2774. notif->channel,
  2775. notif->band ? "bg" : "a",
  2776. le32_to_cpu(notif->tsf_high),
  2777. le32_to_cpu(notif->tsf_low),
  2778. le32_to_cpu(notif->statistics[0]),
  2779. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2780. jiffies_to_msecs(elapsed_jiffies
  2781. (priv->last_scan_jiffies, jiffies)));
  2782. priv->last_scan_jiffies = jiffies;
  2783. priv->next_scan_jiffies = 0;
  2784. }
  2785. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2786. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2787. struct iwl3945_rx_mem_buffer *rxb)
  2788. {
  2789. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2790. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2791. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2792. scan_notif->scanned_channels,
  2793. scan_notif->tsf_low,
  2794. scan_notif->tsf_high, scan_notif->status);
  2795. /* The HW is no longer scanning */
  2796. clear_bit(STATUS_SCAN_HW, &priv->status);
  2797. /* The scan completion notification came in, so kill that timer... */
  2798. cancel_delayed_work(&priv->scan_check);
  2799. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2800. (priv->scan_bands == 2) ? "2.4" : "5.2",
  2801. jiffies_to_msecs(elapsed_jiffies
  2802. (priv->scan_pass_start, jiffies)));
  2803. /* Remove this scanned band from the list
  2804. * of pending bands to scan */
  2805. priv->scan_bands--;
  2806. /* If a request to abort was given, or the scan did not succeed
  2807. * then we reset the scan state machine and terminate,
  2808. * re-queuing another scan if one has been requested */
  2809. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2810. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2811. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2812. } else {
  2813. /* If there are more bands on this scan pass reschedule */
  2814. if (priv->scan_bands > 0)
  2815. goto reschedule;
  2816. }
  2817. priv->last_scan_jiffies = jiffies;
  2818. priv->next_scan_jiffies = 0;
  2819. IWL_DEBUG_INFO("Setting scan to off\n");
  2820. clear_bit(STATUS_SCANNING, &priv->status);
  2821. IWL_DEBUG_INFO("Scan took %dms\n",
  2822. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2823. queue_work(priv->workqueue, &priv->scan_completed);
  2824. return;
  2825. reschedule:
  2826. priv->scan_pass_start = jiffies;
  2827. queue_work(priv->workqueue, &priv->request_scan);
  2828. }
  2829. /* Handle notification from uCode that card's power state is changing
  2830. * due to software, hardware, or critical temperature RFKILL */
  2831. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2832. struct iwl3945_rx_mem_buffer *rxb)
  2833. {
  2834. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2835. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2836. unsigned long status = priv->status;
  2837. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2838. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2839. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2840. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2841. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2842. if (flags & HW_CARD_DISABLED)
  2843. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2844. else
  2845. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2846. if (flags & SW_CARD_DISABLED)
  2847. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2848. else
  2849. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2850. iwl3945_scan_cancel(priv);
  2851. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2852. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2853. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2854. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2855. queue_work(priv->workqueue, &priv->rf_kill);
  2856. else
  2857. wake_up_interruptible(&priv->wait_command_queue);
  2858. }
  2859. /**
  2860. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2861. *
  2862. * Setup the RX handlers for each of the reply types sent from the uCode
  2863. * to the host.
  2864. *
  2865. * This function chains into the hardware specific files for them to setup
  2866. * any hardware specific handlers as well.
  2867. */
  2868. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2869. {
  2870. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2871. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2872. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2873. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2874. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2875. iwl3945_rx_spectrum_measure_notif;
  2876. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2877. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2878. iwl3945_rx_pm_debug_statistics_notif;
  2879. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2880. /*
  2881. * The same handler is used for both the REPLY to a discrete
  2882. * statistics request from the host as well as for the periodic
  2883. * statistics notifications (after received beacons) from the uCode.
  2884. */
  2885. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2886. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2887. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2888. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2889. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2890. iwl3945_rx_scan_results_notif;
  2891. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2892. iwl3945_rx_scan_complete_notif;
  2893. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2894. /* Set up hardware specific Rx handlers */
  2895. iwl3945_hw_rx_handler_setup(priv);
  2896. }
  2897. /**
  2898. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2899. * When FW advances 'R' index, all entries between old and new 'R' index
  2900. * need to be reclaimed.
  2901. */
  2902. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2903. int txq_id, int index)
  2904. {
  2905. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2906. struct iwl3945_queue *q = &txq->q;
  2907. int nfreed = 0;
  2908. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2909. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2910. "is out of range [0-%d] %d %d.\n", txq_id,
  2911. index, q->n_bd, q->write_ptr, q->read_ptr);
  2912. return;
  2913. }
  2914. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2915. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2916. if (nfreed > 1) {
  2917. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2918. q->write_ptr, q->read_ptr);
  2919. queue_work(priv->workqueue, &priv->restart);
  2920. break;
  2921. }
  2922. nfreed++;
  2923. }
  2924. }
  2925. /**
  2926. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2927. * @rxb: Rx buffer to reclaim
  2928. *
  2929. * If an Rx buffer has an async callback associated with it the callback
  2930. * will be executed. The attached skb (if present) will only be freed
  2931. * if the callback returns 1
  2932. */
  2933. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2934. struct iwl3945_rx_mem_buffer *rxb)
  2935. {
  2936. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2937. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2938. int txq_id = SEQ_TO_QUEUE(sequence);
  2939. int index = SEQ_TO_INDEX(sequence);
  2940. int huge = sequence & SEQ_HUGE_FRAME;
  2941. int cmd_index;
  2942. struct iwl3945_cmd *cmd;
  2943. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2944. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2945. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2946. /* Input error checking is done when commands are added to queue. */
  2947. if (cmd->meta.flags & CMD_WANT_SKB) {
  2948. cmd->meta.source->u.skb = rxb->skb;
  2949. rxb->skb = NULL;
  2950. } else if (cmd->meta.u.callback &&
  2951. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2952. rxb->skb = NULL;
  2953. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2954. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2955. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2956. wake_up_interruptible(&priv->wait_command_queue);
  2957. }
  2958. }
  2959. /************************** RX-FUNCTIONS ****************************/
  2960. /*
  2961. * Rx theory of operation
  2962. *
  2963. * The host allocates 32 DMA target addresses and passes the host address
  2964. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2965. * 0 to 31
  2966. *
  2967. * Rx Queue Indexes
  2968. * The host/firmware share two index registers for managing the Rx buffers.
  2969. *
  2970. * The READ index maps to the first position that the firmware may be writing
  2971. * to -- the driver can read up to (but not including) this position and get
  2972. * good data.
  2973. * The READ index is managed by the firmware once the card is enabled.
  2974. *
  2975. * The WRITE index maps to the last position the driver has read from -- the
  2976. * position preceding WRITE is the last slot the firmware can place a packet.
  2977. *
  2978. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2979. * WRITE = READ.
  2980. *
  2981. * During initialization, the host sets up the READ queue position to the first
  2982. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2983. *
  2984. * When the firmware places a packet in a buffer, it will advance the READ index
  2985. * and fire the RX interrupt. The driver can then query the READ index and
  2986. * process as many packets as possible, moving the WRITE index forward as it
  2987. * resets the Rx queue buffers with new memory.
  2988. *
  2989. * The management in the driver is as follows:
  2990. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2991. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2992. * to replenish the iwl->rxq->rx_free.
  2993. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2994. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2995. * 'processed' and 'read' driver indexes as well)
  2996. * + A received packet is processed and handed to the kernel network stack,
  2997. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2998. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2999. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3000. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3001. * were enough free buffers and RX_STALLED is set it is cleared.
  3002. *
  3003. *
  3004. * Driver sequence:
  3005. *
  3006. * iwl3945_rx_queue_alloc() Allocates rx_free
  3007. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3008. * iwl3945_rx_queue_restock
  3009. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3010. * queue, updates firmware pointers, and updates
  3011. * the WRITE index. If insufficient rx_free buffers
  3012. * are available, schedules iwl3945_rx_replenish
  3013. *
  3014. * -- enable interrupts --
  3015. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3016. * READ INDEX, detaching the SKB from the pool.
  3017. * Moves the packet buffer from queue to rx_used.
  3018. * Calls iwl3945_rx_queue_restock to refill any empty
  3019. * slots.
  3020. * ...
  3021. *
  3022. */
  3023. /**
  3024. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3025. */
  3026. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3027. {
  3028. int s = q->read - q->write;
  3029. if (s <= 0)
  3030. s += RX_QUEUE_SIZE;
  3031. /* keep some buffer to not confuse full and empty queue */
  3032. s -= 2;
  3033. if (s < 0)
  3034. s = 0;
  3035. return s;
  3036. }
  3037. /**
  3038. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3039. */
  3040. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3041. {
  3042. u32 reg = 0;
  3043. int rc = 0;
  3044. unsigned long flags;
  3045. spin_lock_irqsave(&q->lock, flags);
  3046. if (q->need_update == 0)
  3047. goto exit_unlock;
  3048. /* If power-saving is in use, make sure device is awake */
  3049. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3050. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3051. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3052. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3053. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3054. goto exit_unlock;
  3055. }
  3056. rc = iwl3945_grab_nic_access(priv);
  3057. if (rc)
  3058. goto exit_unlock;
  3059. /* Device expects a multiple of 8 */
  3060. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3061. q->write & ~0x7);
  3062. iwl3945_release_nic_access(priv);
  3063. /* Else device is assumed to be awake */
  3064. } else
  3065. /* Device expects a multiple of 8 */
  3066. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3067. q->need_update = 0;
  3068. exit_unlock:
  3069. spin_unlock_irqrestore(&q->lock, flags);
  3070. return rc;
  3071. }
  3072. /**
  3073. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3074. */
  3075. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3076. dma_addr_t dma_addr)
  3077. {
  3078. return cpu_to_le32((u32)dma_addr);
  3079. }
  3080. /**
  3081. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3082. *
  3083. * If there are slots in the RX queue that need to be restocked,
  3084. * and we have free pre-allocated buffers, fill the ranks as much
  3085. * as we can, pulling from rx_free.
  3086. *
  3087. * This moves the 'write' index forward to catch up with 'processed', and
  3088. * also updates the memory address in the firmware to reference the new
  3089. * target buffer.
  3090. */
  3091. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3092. {
  3093. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3094. struct list_head *element;
  3095. struct iwl3945_rx_mem_buffer *rxb;
  3096. unsigned long flags;
  3097. int write, rc;
  3098. spin_lock_irqsave(&rxq->lock, flags);
  3099. write = rxq->write & ~0x7;
  3100. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3101. /* Get next free Rx buffer, remove from free list */
  3102. element = rxq->rx_free.next;
  3103. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3104. list_del(element);
  3105. /* Point to Rx buffer via next RBD in circular buffer */
  3106. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3107. rxq->queue[rxq->write] = rxb;
  3108. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3109. rxq->free_count--;
  3110. }
  3111. spin_unlock_irqrestore(&rxq->lock, flags);
  3112. /* If the pre-allocated buffer pool is dropping low, schedule to
  3113. * refill it */
  3114. if (rxq->free_count <= RX_LOW_WATERMARK)
  3115. queue_work(priv->workqueue, &priv->rx_replenish);
  3116. /* If we've added more space for the firmware to place data, tell it.
  3117. * Increment device's write pointer in multiples of 8. */
  3118. if ((write != (rxq->write & ~0x7))
  3119. || (abs(rxq->write - rxq->read) > 7)) {
  3120. spin_lock_irqsave(&rxq->lock, flags);
  3121. rxq->need_update = 1;
  3122. spin_unlock_irqrestore(&rxq->lock, flags);
  3123. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3124. if (rc)
  3125. return rc;
  3126. }
  3127. return 0;
  3128. }
  3129. /**
  3130. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3131. *
  3132. * When moving to rx_free an SKB is allocated for the slot.
  3133. *
  3134. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3135. * This is called as a scheduled work item (except for during initialization)
  3136. */
  3137. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3138. {
  3139. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3140. struct list_head *element;
  3141. struct iwl3945_rx_mem_buffer *rxb;
  3142. unsigned long flags;
  3143. spin_lock_irqsave(&rxq->lock, flags);
  3144. while (!list_empty(&rxq->rx_used)) {
  3145. element = rxq->rx_used.next;
  3146. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3147. /* Alloc a new receive buffer */
  3148. rxb->skb =
  3149. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3150. if (!rxb->skb) {
  3151. if (net_ratelimit())
  3152. printk(KERN_CRIT DRV_NAME
  3153. ": Can not allocate SKB buffers\n");
  3154. /* We don't reschedule replenish work here -- we will
  3155. * call the restock method and if it still needs
  3156. * more buffers it will schedule replenish */
  3157. break;
  3158. }
  3159. /* If radiotap head is required, reserve some headroom here.
  3160. * The physical head count is a variable rx_stats->phy_count.
  3161. * We reserve 4 bytes here. Plus these extra bytes, the
  3162. * headroom of the physical head should be enough for the
  3163. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3164. */
  3165. skb_reserve(rxb->skb, 4);
  3166. priv->alloc_rxb_skb++;
  3167. list_del(element);
  3168. /* Get physical address of RB/SKB */
  3169. rxb->dma_addr =
  3170. pci_map_single(priv->pci_dev, rxb->skb->data,
  3171. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3172. list_add_tail(&rxb->list, &rxq->rx_free);
  3173. rxq->free_count++;
  3174. }
  3175. spin_unlock_irqrestore(&rxq->lock, flags);
  3176. }
  3177. /*
  3178. * this should be called while priv->lock is locked
  3179. */
  3180. static void __iwl3945_rx_replenish(void *data)
  3181. {
  3182. struct iwl3945_priv *priv = data;
  3183. iwl3945_rx_allocate(priv);
  3184. iwl3945_rx_queue_restock(priv);
  3185. }
  3186. void iwl3945_rx_replenish(void *data)
  3187. {
  3188. struct iwl3945_priv *priv = data;
  3189. unsigned long flags;
  3190. iwl3945_rx_allocate(priv);
  3191. spin_lock_irqsave(&priv->lock, flags);
  3192. iwl3945_rx_queue_restock(priv);
  3193. spin_unlock_irqrestore(&priv->lock, flags);
  3194. }
  3195. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3196. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3197. * This free routine walks the list of POOL entries and if SKB is set to
  3198. * non NULL it is unmapped and freed
  3199. */
  3200. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3201. {
  3202. int i;
  3203. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3204. if (rxq->pool[i].skb != NULL) {
  3205. pci_unmap_single(priv->pci_dev,
  3206. rxq->pool[i].dma_addr,
  3207. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3208. dev_kfree_skb(rxq->pool[i].skb);
  3209. }
  3210. }
  3211. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3212. rxq->dma_addr);
  3213. rxq->bd = NULL;
  3214. }
  3215. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3216. {
  3217. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3218. struct pci_dev *dev = priv->pci_dev;
  3219. int i;
  3220. spin_lock_init(&rxq->lock);
  3221. INIT_LIST_HEAD(&rxq->rx_free);
  3222. INIT_LIST_HEAD(&rxq->rx_used);
  3223. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3224. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3225. if (!rxq->bd)
  3226. return -ENOMEM;
  3227. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3228. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3229. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3230. /* Set us so that we have processed and used all buffers, but have
  3231. * not restocked the Rx queue with fresh buffers */
  3232. rxq->read = rxq->write = 0;
  3233. rxq->free_count = 0;
  3234. rxq->need_update = 0;
  3235. return 0;
  3236. }
  3237. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3238. {
  3239. unsigned long flags;
  3240. int i;
  3241. spin_lock_irqsave(&rxq->lock, flags);
  3242. INIT_LIST_HEAD(&rxq->rx_free);
  3243. INIT_LIST_HEAD(&rxq->rx_used);
  3244. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3245. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3246. /* In the reset function, these buffers may have been allocated
  3247. * to an SKB, so we need to unmap and free potential storage */
  3248. if (rxq->pool[i].skb != NULL) {
  3249. pci_unmap_single(priv->pci_dev,
  3250. rxq->pool[i].dma_addr,
  3251. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3252. priv->alloc_rxb_skb--;
  3253. dev_kfree_skb(rxq->pool[i].skb);
  3254. rxq->pool[i].skb = NULL;
  3255. }
  3256. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3257. }
  3258. /* Set us so that we have processed and used all buffers, but have
  3259. * not restocked the Rx queue with fresh buffers */
  3260. rxq->read = rxq->write = 0;
  3261. rxq->free_count = 0;
  3262. spin_unlock_irqrestore(&rxq->lock, flags);
  3263. }
  3264. /* Convert linear signal-to-noise ratio into dB */
  3265. static u8 ratio2dB[100] = {
  3266. /* 0 1 2 3 4 5 6 7 8 9 */
  3267. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3268. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3269. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3270. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3271. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3272. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3273. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3274. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3275. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3276. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3277. };
  3278. /* Calculates a relative dB value from a ratio of linear
  3279. * (i.e. not dB) signal levels.
  3280. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3281. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3282. {
  3283. /* 1000:1 or higher just report as 60 dB */
  3284. if (sig_ratio >= 1000)
  3285. return 60;
  3286. /* 100:1 or higher, divide by 10 and use table,
  3287. * add 20 dB to make up for divide by 10 */
  3288. if (sig_ratio >= 100)
  3289. return (20 + (int)ratio2dB[sig_ratio/10]);
  3290. /* We shouldn't see this */
  3291. if (sig_ratio < 1)
  3292. return 0;
  3293. /* Use table for ratios 1:1 - 99:1 */
  3294. return (int)ratio2dB[sig_ratio];
  3295. }
  3296. #define PERFECT_RSSI (-20) /* dBm */
  3297. #define WORST_RSSI (-95) /* dBm */
  3298. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3299. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3300. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3301. * about formulas used below. */
  3302. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3303. {
  3304. int sig_qual;
  3305. int degradation = PERFECT_RSSI - rssi_dbm;
  3306. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3307. * as indicator; formula is (signal dbm - noise dbm).
  3308. * SNR at or above 40 is a great signal (100%).
  3309. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3310. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3311. if (noise_dbm) {
  3312. if (rssi_dbm - noise_dbm >= 40)
  3313. return 100;
  3314. else if (rssi_dbm < noise_dbm)
  3315. return 0;
  3316. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3317. /* Else use just the signal level.
  3318. * This formula is a least squares fit of data points collected and
  3319. * compared with a reference system that had a percentage (%) display
  3320. * for signal quality. */
  3321. } else
  3322. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3323. (15 * RSSI_RANGE + 62 * degradation)) /
  3324. (RSSI_RANGE * RSSI_RANGE);
  3325. if (sig_qual > 100)
  3326. sig_qual = 100;
  3327. else if (sig_qual < 1)
  3328. sig_qual = 0;
  3329. return sig_qual;
  3330. }
  3331. /**
  3332. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3333. *
  3334. * Uses the priv->rx_handlers callback function array to invoke
  3335. * the appropriate handlers, including command responses,
  3336. * frame-received notifications, and other notifications.
  3337. */
  3338. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3339. {
  3340. struct iwl3945_rx_mem_buffer *rxb;
  3341. struct iwl3945_rx_packet *pkt;
  3342. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3343. u32 r, i;
  3344. int reclaim;
  3345. unsigned long flags;
  3346. u8 fill_rx = 0;
  3347. u32 count = 8;
  3348. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3349. * buffer that the driver may process (last buffer filled by ucode). */
  3350. r = iwl3945_hw_get_rx_read(priv);
  3351. i = rxq->read;
  3352. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3353. fill_rx = 1;
  3354. /* Rx interrupt, but nothing sent from uCode */
  3355. if (i == r)
  3356. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3357. while (i != r) {
  3358. rxb = rxq->queue[i];
  3359. /* If an RXB doesn't have a Rx queue slot associated with it,
  3360. * then a bug has been introduced in the queue refilling
  3361. * routines -- catch it here */
  3362. BUG_ON(rxb == NULL);
  3363. rxq->queue[i] = NULL;
  3364. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3365. IWL_RX_BUF_SIZE,
  3366. PCI_DMA_FROMDEVICE);
  3367. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3368. /* Reclaim a command buffer only if this packet is a response
  3369. * to a (driver-originated) command.
  3370. * If the packet (e.g. Rx frame) originated from uCode,
  3371. * there is no command buffer to reclaim.
  3372. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3373. * but apparently a few don't get set; catch them here. */
  3374. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3375. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3376. (pkt->hdr.cmd != REPLY_TX);
  3377. /* Based on type of command response or notification,
  3378. * handle those that need handling via function in
  3379. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3380. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3381. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3382. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3383. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3384. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3385. } else {
  3386. /* No handling needed */
  3387. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3388. "r %d i %d No handler needed for %s, 0x%02x\n",
  3389. r, i, get_cmd_string(pkt->hdr.cmd),
  3390. pkt->hdr.cmd);
  3391. }
  3392. if (reclaim) {
  3393. /* Invoke any callbacks, transfer the skb to caller, and
  3394. * fire off the (possibly) blocking iwl3945_send_cmd()
  3395. * as we reclaim the driver command queue */
  3396. if (rxb && rxb->skb)
  3397. iwl3945_tx_cmd_complete(priv, rxb);
  3398. else
  3399. IWL_WARNING("Claim null rxb?\n");
  3400. }
  3401. /* For now we just don't re-use anything. We can tweak this
  3402. * later to try and re-use notification packets and SKBs that
  3403. * fail to Rx correctly */
  3404. if (rxb->skb != NULL) {
  3405. priv->alloc_rxb_skb--;
  3406. dev_kfree_skb_any(rxb->skb);
  3407. rxb->skb = NULL;
  3408. }
  3409. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3410. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3411. spin_lock_irqsave(&rxq->lock, flags);
  3412. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3413. spin_unlock_irqrestore(&rxq->lock, flags);
  3414. i = (i + 1) & RX_QUEUE_MASK;
  3415. /* If there are a lot of unused frames,
  3416. * restock the Rx queue so ucode won't assert. */
  3417. if (fill_rx) {
  3418. count++;
  3419. if (count >= 8) {
  3420. priv->rxq.read = i;
  3421. __iwl3945_rx_replenish(priv);
  3422. count = 0;
  3423. }
  3424. }
  3425. }
  3426. /* Backtrack one entry */
  3427. priv->rxq.read = i;
  3428. iwl3945_rx_queue_restock(priv);
  3429. }
  3430. /**
  3431. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3432. */
  3433. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3434. struct iwl3945_tx_queue *txq)
  3435. {
  3436. u32 reg = 0;
  3437. int rc = 0;
  3438. int txq_id = txq->q.id;
  3439. if (txq->need_update == 0)
  3440. return rc;
  3441. /* if we're trying to save power */
  3442. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3443. /* wake up nic if it's powered down ...
  3444. * uCode will wake up, and interrupt us again, so next
  3445. * time we'll skip this part. */
  3446. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3447. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3448. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3449. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3450. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3451. return rc;
  3452. }
  3453. /* restore this queue's parameters in nic hardware. */
  3454. rc = iwl3945_grab_nic_access(priv);
  3455. if (rc)
  3456. return rc;
  3457. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3458. txq->q.write_ptr | (txq_id << 8));
  3459. iwl3945_release_nic_access(priv);
  3460. /* else not in power-save mode, uCode will never sleep when we're
  3461. * trying to tx (during RFKILL, we're not trying to tx). */
  3462. } else
  3463. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3464. txq->q.write_ptr | (txq_id << 8));
  3465. txq->need_update = 0;
  3466. return rc;
  3467. }
  3468. #ifdef CONFIG_IWL3945_DEBUG
  3469. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3470. {
  3471. DECLARE_MAC_BUF(mac);
  3472. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3473. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3474. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3475. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3476. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3477. le32_to_cpu(rxon->filter_flags));
  3478. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3479. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3480. rxon->ofdm_basic_rates);
  3481. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3482. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3483. print_mac(mac, rxon->node_addr));
  3484. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3485. print_mac(mac, rxon->bssid_addr));
  3486. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3487. }
  3488. #endif
  3489. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3490. {
  3491. IWL_DEBUG_ISR("Enabling interrupts\n");
  3492. set_bit(STATUS_INT_ENABLED, &priv->status);
  3493. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3494. }
  3495. /* call this function to flush any scheduled tasklet */
  3496. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3497. {
  3498. /* wait to make sure we flush pedding tasklet*/
  3499. synchronize_irq(priv->pci_dev->irq);
  3500. tasklet_kill(&priv->irq_tasklet);
  3501. }
  3502. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3503. {
  3504. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3505. /* disable interrupts from uCode/NIC to host */
  3506. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3507. /* acknowledge/clear/reset any interrupts still pending
  3508. * from uCode or flow handler (Rx/Tx DMA) */
  3509. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3510. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3511. IWL_DEBUG_ISR("Disabled interrupts\n");
  3512. }
  3513. static const char *desc_lookup(int i)
  3514. {
  3515. switch (i) {
  3516. case 1:
  3517. return "FAIL";
  3518. case 2:
  3519. return "BAD_PARAM";
  3520. case 3:
  3521. return "BAD_CHECKSUM";
  3522. case 4:
  3523. return "NMI_INTERRUPT";
  3524. case 5:
  3525. return "SYSASSERT";
  3526. case 6:
  3527. return "FATAL_ERROR";
  3528. }
  3529. return "UNKNOWN";
  3530. }
  3531. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3532. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3533. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3534. {
  3535. u32 i;
  3536. u32 desc, time, count, base, data1;
  3537. u32 blink1, blink2, ilink1, ilink2;
  3538. int rc;
  3539. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3540. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3541. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3542. return;
  3543. }
  3544. rc = iwl3945_grab_nic_access(priv);
  3545. if (rc) {
  3546. IWL_WARNING("Can not read from adapter at this time.\n");
  3547. return;
  3548. }
  3549. count = iwl3945_read_targ_mem(priv, base);
  3550. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3551. IWL_ERROR("Start IWL Error Log Dump:\n");
  3552. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3553. }
  3554. IWL_ERROR("Desc Time asrtPC blink2 "
  3555. "ilink1 nmiPC Line\n");
  3556. for (i = ERROR_START_OFFSET;
  3557. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3558. i += ERROR_ELEM_SIZE) {
  3559. desc = iwl3945_read_targ_mem(priv, base + i);
  3560. time =
  3561. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3562. blink1 =
  3563. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3564. blink2 =
  3565. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3566. ilink1 =
  3567. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3568. ilink2 =
  3569. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3570. data1 =
  3571. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3572. IWL_ERROR
  3573. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3574. desc_lookup(desc), desc, time, blink1, blink2,
  3575. ilink1, ilink2, data1);
  3576. }
  3577. iwl3945_release_nic_access(priv);
  3578. }
  3579. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3580. /**
  3581. * iwl3945_print_event_log - Dump error event log to syslog
  3582. *
  3583. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3584. */
  3585. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3586. u32 num_events, u32 mode)
  3587. {
  3588. u32 i;
  3589. u32 base; /* SRAM byte address of event log header */
  3590. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3591. u32 ptr; /* SRAM byte address of log data */
  3592. u32 ev, time, data; /* event log data */
  3593. if (num_events == 0)
  3594. return;
  3595. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3596. if (mode == 0)
  3597. event_size = 2 * sizeof(u32);
  3598. else
  3599. event_size = 3 * sizeof(u32);
  3600. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3601. /* "time" is actually "data" for mode 0 (no timestamp).
  3602. * place event id # at far right for easier visual parsing. */
  3603. for (i = 0; i < num_events; i++) {
  3604. ev = iwl3945_read_targ_mem(priv, ptr);
  3605. ptr += sizeof(u32);
  3606. time = iwl3945_read_targ_mem(priv, ptr);
  3607. ptr += sizeof(u32);
  3608. if (mode == 0)
  3609. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3610. else {
  3611. data = iwl3945_read_targ_mem(priv, ptr);
  3612. ptr += sizeof(u32);
  3613. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3614. }
  3615. }
  3616. }
  3617. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3618. {
  3619. int rc;
  3620. u32 base; /* SRAM byte address of event log header */
  3621. u32 capacity; /* event log capacity in # entries */
  3622. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3623. u32 num_wraps; /* # times uCode wrapped to top of log */
  3624. u32 next_entry; /* index of next entry to be written by uCode */
  3625. u32 size; /* # entries that we'll print */
  3626. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3627. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3628. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3629. return;
  3630. }
  3631. rc = iwl3945_grab_nic_access(priv);
  3632. if (rc) {
  3633. IWL_WARNING("Can not read from adapter at this time.\n");
  3634. return;
  3635. }
  3636. /* event log header */
  3637. capacity = iwl3945_read_targ_mem(priv, base);
  3638. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3639. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3640. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3641. size = num_wraps ? capacity : next_entry;
  3642. /* bail out if nothing in log */
  3643. if (size == 0) {
  3644. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3645. iwl3945_release_nic_access(priv);
  3646. return;
  3647. }
  3648. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3649. size, num_wraps);
  3650. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3651. * i.e the next one that uCode would fill. */
  3652. if (num_wraps)
  3653. iwl3945_print_event_log(priv, next_entry,
  3654. capacity - next_entry, mode);
  3655. /* (then/else) start at top of log */
  3656. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3657. iwl3945_release_nic_access(priv);
  3658. }
  3659. /**
  3660. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3661. */
  3662. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3663. {
  3664. /* Set the FW error flag -- cleared on iwl3945_down */
  3665. set_bit(STATUS_FW_ERROR, &priv->status);
  3666. /* Cancel currently queued command. */
  3667. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3668. #ifdef CONFIG_IWL3945_DEBUG
  3669. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3670. iwl3945_dump_nic_error_log(priv);
  3671. iwl3945_dump_nic_event_log(priv);
  3672. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3673. }
  3674. #endif
  3675. wake_up_interruptible(&priv->wait_command_queue);
  3676. /* Keep the restart process from trying to send host
  3677. * commands by clearing the INIT status bit */
  3678. clear_bit(STATUS_READY, &priv->status);
  3679. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3680. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3681. "Restarting adapter due to uCode error.\n");
  3682. if (iwl3945_is_associated(priv)) {
  3683. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3684. sizeof(priv->recovery_rxon));
  3685. priv->error_recovering = 1;
  3686. }
  3687. queue_work(priv->workqueue, &priv->restart);
  3688. }
  3689. }
  3690. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3691. {
  3692. unsigned long flags;
  3693. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3694. sizeof(priv->staging_rxon));
  3695. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3696. iwl3945_commit_rxon(priv);
  3697. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3698. spin_lock_irqsave(&priv->lock, flags);
  3699. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3700. priv->error_recovering = 0;
  3701. spin_unlock_irqrestore(&priv->lock, flags);
  3702. }
  3703. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3704. {
  3705. u32 inta, handled = 0;
  3706. u32 inta_fh;
  3707. unsigned long flags;
  3708. #ifdef CONFIG_IWL3945_DEBUG
  3709. u32 inta_mask;
  3710. #endif
  3711. spin_lock_irqsave(&priv->lock, flags);
  3712. /* Ack/clear/reset pending uCode interrupts.
  3713. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3714. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3715. inta = iwl3945_read32(priv, CSR_INT);
  3716. iwl3945_write32(priv, CSR_INT, inta);
  3717. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3718. * Any new interrupts that happen after this, either while we're
  3719. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3720. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3721. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3722. #ifdef CONFIG_IWL3945_DEBUG
  3723. if (iwl3945_debug_level & IWL_DL_ISR) {
  3724. /* just for debug */
  3725. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3726. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3727. inta, inta_mask, inta_fh);
  3728. }
  3729. #endif
  3730. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3731. * atomic, make sure that inta covers all the interrupts that
  3732. * we've discovered, even if FH interrupt came in just after
  3733. * reading CSR_INT. */
  3734. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3735. inta |= CSR_INT_BIT_FH_RX;
  3736. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3737. inta |= CSR_INT_BIT_FH_TX;
  3738. /* Now service all interrupt bits discovered above. */
  3739. if (inta & CSR_INT_BIT_HW_ERR) {
  3740. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3741. /* Tell the device to stop sending interrupts */
  3742. iwl3945_disable_interrupts(priv);
  3743. iwl3945_irq_handle_error(priv);
  3744. handled |= CSR_INT_BIT_HW_ERR;
  3745. spin_unlock_irqrestore(&priv->lock, flags);
  3746. return;
  3747. }
  3748. #ifdef CONFIG_IWL3945_DEBUG
  3749. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3750. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3751. if (inta & CSR_INT_BIT_SCD)
  3752. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3753. "the frame/frames.\n");
  3754. /* Alive notification via Rx interrupt will do the real work */
  3755. if (inta & CSR_INT_BIT_ALIVE)
  3756. IWL_DEBUG_ISR("Alive interrupt\n");
  3757. }
  3758. #endif
  3759. /* Safely ignore these bits for debug checks below */
  3760. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3761. /* HW RF KILL switch toggled (4965 only) */
  3762. if (inta & CSR_INT_BIT_RF_KILL) {
  3763. int hw_rf_kill = 0;
  3764. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3765. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3766. hw_rf_kill = 1;
  3767. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3768. "RF_KILL bit toggled to %s.\n",
  3769. hw_rf_kill ? "disable radio":"enable radio");
  3770. /* Queue restart only if RF_KILL switch was set to "kill"
  3771. * when we loaded driver, and is now set to "enable".
  3772. * After we're Alive, RF_KILL gets handled by
  3773. * iwl3945_rx_card_state_notif() */
  3774. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3775. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3776. queue_work(priv->workqueue, &priv->restart);
  3777. }
  3778. handled |= CSR_INT_BIT_RF_KILL;
  3779. }
  3780. /* Chip got too hot and stopped itself (4965 only) */
  3781. if (inta & CSR_INT_BIT_CT_KILL) {
  3782. IWL_ERROR("Microcode CT kill error detected.\n");
  3783. handled |= CSR_INT_BIT_CT_KILL;
  3784. }
  3785. /* Error detected by uCode */
  3786. if (inta & CSR_INT_BIT_SW_ERR) {
  3787. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3788. inta);
  3789. iwl3945_irq_handle_error(priv);
  3790. handled |= CSR_INT_BIT_SW_ERR;
  3791. }
  3792. /* uCode wakes up after power-down sleep */
  3793. if (inta & CSR_INT_BIT_WAKEUP) {
  3794. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3795. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3796. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3797. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3798. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3799. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3800. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3801. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3802. handled |= CSR_INT_BIT_WAKEUP;
  3803. }
  3804. /* All uCode command responses, including Tx command responses,
  3805. * Rx "responses" (frame-received notification), and other
  3806. * notifications from uCode come through here*/
  3807. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3808. iwl3945_rx_handle(priv);
  3809. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3810. }
  3811. if (inta & CSR_INT_BIT_FH_TX) {
  3812. IWL_DEBUG_ISR("Tx interrupt\n");
  3813. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3814. if (!iwl3945_grab_nic_access(priv)) {
  3815. iwl3945_write_direct32(priv,
  3816. FH_TCSR_CREDIT
  3817. (ALM_FH_SRVC_CHNL), 0x0);
  3818. iwl3945_release_nic_access(priv);
  3819. }
  3820. handled |= CSR_INT_BIT_FH_TX;
  3821. }
  3822. if (inta & ~handled)
  3823. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3824. if (inta & ~CSR_INI_SET_MASK) {
  3825. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3826. inta & ~CSR_INI_SET_MASK);
  3827. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3828. }
  3829. /* Re-enable all interrupts */
  3830. /* only Re-enable if disabled by irq */
  3831. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3832. iwl3945_enable_interrupts(priv);
  3833. #ifdef CONFIG_IWL3945_DEBUG
  3834. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3835. inta = iwl3945_read32(priv, CSR_INT);
  3836. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3837. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3838. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3839. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3840. }
  3841. #endif
  3842. spin_unlock_irqrestore(&priv->lock, flags);
  3843. }
  3844. static irqreturn_t iwl3945_isr(int irq, void *data)
  3845. {
  3846. struct iwl3945_priv *priv = data;
  3847. u32 inta, inta_mask;
  3848. u32 inta_fh;
  3849. if (!priv)
  3850. return IRQ_NONE;
  3851. spin_lock(&priv->lock);
  3852. /* Disable (but don't clear!) interrupts here to avoid
  3853. * back-to-back ISRs and sporadic interrupts from our NIC.
  3854. * If we have something to service, the tasklet will re-enable ints.
  3855. * If we *don't* have something, we'll re-enable before leaving here. */
  3856. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3857. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3858. /* Discover which interrupts are active/pending */
  3859. inta = iwl3945_read32(priv, CSR_INT);
  3860. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3861. /* Ignore interrupt if there's nothing in NIC to service.
  3862. * This may be due to IRQ shared with another device,
  3863. * or due to sporadic interrupts thrown from our NIC. */
  3864. if (!inta && !inta_fh) {
  3865. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3866. goto none;
  3867. }
  3868. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3869. /* Hardware disappeared */
  3870. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3871. goto unplugged;
  3872. }
  3873. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3874. inta, inta_mask, inta_fh);
  3875. inta &= ~CSR_INT_BIT_SCD;
  3876. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3877. if (likely(inta || inta_fh))
  3878. tasklet_schedule(&priv->irq_tasklet);
  3879. unplugged:
  3880. spin_unlock(&priv->lock);
  3881. return IRQ_HANDLED;
  3882. none:
  3883. /* re-enable interrupts here since we don't have anything to service. */
  3884. /* only Re-enable if disabled by irq */
  3885. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3886. iwl3945_enable_interrupts(priv);
  3887. spin_unlock(&priv->lock);
  3888. return IRQ_NONE;
  3889. }
  3890. /************************** EEPROM BANDS ****************************
  3891. *
  3892. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3893. * EEPROM contents to the specific channel number supported for each
  3894. * band.
  3895. *
  3896. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3897. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3898. * The specific geography and calibration information for that channel
  3899. * is contained in the eeprom map itself.
  3900. *
  3901. * During init, we copy the eeprom information and channel map
  3902. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3903. *
  3904. * channel_map_24/52 provides the index in the channel_info array for a
  3905. * given channel. We have to have two separate maps as there is channel
  3906. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3907. * band_2
  3908. *
  3909. * A value of 0xff stored in the channel_map indicates that the channel
  3910. * is not supported by the hardware at all.
  3911. *
  3912. * A value of 0xfe in the channel_map indicates that the channel is not
  3913. * valid for Tx with the current hardware. This means that
  3914. * while the system can tune and receive on a given channel, it may not
  3915. * be able to associate or transmit any frames on that
  3916. * channel. There is no corresponding channel information for that
  3917. * entry.
  3918. *
  3919. *********************************************************************/
  3920. /* 2.4 GHz */
  3921. static const u8 iwl3945_eeprom_band_1[14] = {
  3922. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3923. };
  3924. /* 5.2 GHz bands */
  3925. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3926. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3927. };
  3928. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3929. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3930. };
  3931. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3932. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3933. };
  3934. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3935. 145, 149, 153, 157, 161, 165
  3936. };
  3937. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3938. int *eeprom_ch_count,
  3939. const struct iwl3945_eeprom_channel
  3940. **eeprom_ch_info,
  3941. const u8 **eeprom_ch_index)
  3942. {
  3943. switch (band) {
  3944. case 1: /* 2.4GHz band */
  3945. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3946. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3947. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3948. break;
  3949. case 2: /* 4.9GHz band */
  3950. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3951. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3952. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3953. break;
  3954. case 3: /* 5.2GHz band */
  3955. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3956. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3957. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3958. break;
  3959. case 4: /* 5.5GHz band */
  3960. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3961. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3962. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3963. break;
  3964. case 5: /* 5.7GHz band */
  3965. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3966. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3967. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3968. break;
  3969. default:
  3970. BUG();
  3971. return;
  3972. }
  3973. }
  3974. /**
  3975. * iwl3945_get_channel_info - Find driver's private channel info
  3976. *
  3977. * Based on band and channel number.
  3978. */
  3979. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3980. enum ieee80211_band band, u16 channel)
  3981. {
  3982. int i;
  3983. switch (band) {
  3984. case IEEE80211_BAND_5GHZ:
  3985. for (i = 14; i < priv->channel_count; i++) {
  3986. if (priv->channel_info[i].channel == channel)
  3987. return &priv->channel_info[i];
  3988. }
  3989. break;
  3990. case IEEE80211_BAND_2GHZ:
  3991. if (channel >= 1 && channel <= 14)
  3992. return &priv->channel_info[channel - 1];
  3993. break;
  3994. case IEEE80211_NUM_BANDS:
  3995. WARN_ON(1);
  3996. }
  3997. return NULL;
  3998. }
  3999. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4000. ? # x " " : "")
  4001. /**
  4002. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4003. */
  4004. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4005. {
  4006. int eeprom_ch_count = 0;
  4007. const u8 *eeprom_ch_index = NULL;
  4008. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4009. int band, ch;
  4010. struct iwl3945_channel_info *ch_info;
  4011. if (priv->channel_count) {
  4012. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4013. return 0;
  4014. }
  4015. if (priv->eeprom.version < 0x2f) {
  4016. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4017. priv->eeprom.version);
  4018. return -EINVAL;
  4019. }
  4020. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4021. priv->channel_count =
  4022. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4023. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4024. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4025. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4026. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4027. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4028. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4029. priv->channel_count, GFP_KERNEL);
  4030. if (!priv->channel_info) {
  4031. IWL_ERROR("Could not allocate channel_info\n");
  4032. priv->channel_count = 0;
  4033. return -ENOMEM;
  4034. }
  4035. ch_info = priv->channel_info;
  4036. /* Loop through the 5 EEPROM bands adding them in order to the
  4037. * channel map we maintain (that contains additional information than
  4038. * what just in the EEPROM) */
  4039. for (band = 1; band <= 5; band++) {
  4040. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4041. &eeprom_ch_info, &eeprom_ch_index);
  4042. /* Loop through each band adding each of the channels */
  4043. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4044. ch_info->channel = eeprom_ch_index[ch];
  4045. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4046. IEEE80211_BAND_5GHZ;
  4047. /* permanently store EEPROM's channel regulatory flags
  4048. * and max power in channel info database. */
  4049. ch_info->eeprom = eeprom_ch_info[ch];
  4050. /* Copy the run-time flags so they are there even on
  4051. * invalid channels */
  4052. ch_info->flags = eeprom_ch_info[ch].flags;
  4053. if (!(is_channel_valid(ch_info))) {
  4054. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4055. "No traffic\n",
  4056. ch_info->channel,
  4057. ch_info->flags,
  4058. is_channel_a_band(ch_info) ?
  4059. "5.2" : "2.4");
  4060. ch_info++;
  4061. continue;
  4062. }
  4063. /* Initialize regulatory-based run-time data */
  4064. ch_info->max_power_avg = ch_info->curr_txpow =
  4065. eeprom_ch_info[ch].max_power_avg;
  4066. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4067. ch_info->min_power = 0;
  4068. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x"
  4069. " %ddBm): Ad-Hoc %ssupported\n",
  4070. ch_info->channel,
  4071. is_channel_a_band(ch_info) ?
  4072. "5.2" : "2.4",
  4073. CHECK_AND_PRINT(VALID),
  4074. CHECK_AND_PRINT(IBSS),
  4075. CHECK_AND_PRINT(ACTIVE),
  4076. CHECK_AND_PRINT(RADAR),
  4077. CHECK_AND_PRINT(WIDE),
  4078. CHECK_AND_PRINT(NARROW),
  4079. CHECK_AND_PRINT(DFS),
  4080. eeprom_ch_info[ch].flags,
  4081. eeprom_ch_info[ch].max_power_avg,
  4082. ((eeprom_ch_info[ch].
  4083. flags & EEPROM_CHANNEL_IBSS)
  4084. && !(eeprom_ch_info[ch].
  4085. flags & EEPROM_CHANNEL_RADAR))
  4086. ? "" : "not ");
  4087. /* Set the user_txpower_limit to the highest power
  4088. * supported by any channel */
  4089. if (eeprom_ch_info[ch].max_power_avg >
  4090. priv->user_txpower_limit)
  4091. priv->user_txpower_limit =
  4092. eeprom_ch_info[ch].max_power_avg;
  4093. ch_info++;
  4094. }
  4095. }
  4096. /* Set up txpower settings in driver for all channels */
  4097. if (iwl3945_txpower_set_from_eeprom(priv))
  4098. return -EIO;
  4099. return 0;
  4100. }
  4101. /*
  4102. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4103. */
  4104. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4105. {
  4106. kfree(priv->channel_info);
  4107. priv->channel_count = 0;
  4108. }
  4109. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4110. * sending probe req. This should be set long enough to hear probe responses
  4111. * from more than one AP. */
  4112. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4113. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4114. /* For faster active scanning, scan will move to the next channel if fewer than
  4115. * PLCP_QUIET_THRESH packets are heard on this channel within
  4116. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4117. * time if it's a quiet channel (nothing responded to our probe, and there's
  4118. * no other traffic).
  4119. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4120. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4121. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4122. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4123. * Must be set longer than active dwell time.
  4124. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4125. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4126. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4127. #define IWL_PASSIVE_DWELL_BASE (100)
  4128. #define IWL_CHANNEL_TUNE_TIME 5
  4129. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4130. enum ieee80211_band band)
  4131. {
  4132. if (band == IEEE80211_BAND_5GHZ)
  4133. return IWL_ACTIVE_DWELL_TIME_52;
  4134. else
  4135. return IWL_ACTIVE_DWELL_TIME_24;
  4136. }
  4137. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4138. enum ieee80211_band band)
  4139. {
  4140. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4141. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4142. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4143. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4144. if (iwl3945_is_associated(priv)) {
  4145. /* If we're associated, we clamp the maximum passive
  4146. * dwell time to be 98% of the beacon interval (minus
  4147. * 2 * channel tune time) */
  4148. passive = priv->beacon_int;
  4149. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4150. passive = IWL_PASSIVE_DWELL_BASE;
  4151. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4152. }
  4153. if (passive <= active)
  4154. passive = active + 1;
  4155. return passive;
  4156. }
  4157. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4158. enum ieee80211_band band,
  4159. u8 is_active, u8 direct_mask,
  4160. struct iwl3945_scan_channel *scan_ch)
  4161. {
  4162. const struct ieee80211_channel *channels = NULL;
  4163. const struct ieee80211_supported_band *sband;
  4164. const struct iwl3945_channel_info *ch_info;
  4165. u16 passive_dwell = 0;
  4166. u16 active_dwell = 0;
  4167. int added, i;
  4168. sband = iwl3945_get_band(priv, band);
  4169. if (!sband)
  4170. return 0;
  4171. channels = sband->channels;
  4172. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4173. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4174. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4175. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4176. continue;
  4177. if (channels[i].hw_value ==
  4178. le16_to_cpu(priv->active_rxon.channel)) {
  4179. if (iwl3945_is_associated(priv)) {
  4180. IWL_DEBUG_SCAN
  4181. ("Skipping current channel %d\n",
  4182. le16_to_cpu(priv->active_rxon.channel));
  4183. continue;
  4184. }
  4185. } else if (priv->only_active_channel)
  4186. continue;
  4187. scan_ch->channel = channels[i].hw_value;
  4188. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4189. if (!is_channel_valid(ch_info)) {
  4190. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4191. scan_ch->channel);
  4192. continue;
  4193. }
  4194. if (!is_active || is_channel_passive(ch_info) ||
  4195. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4196. scan_ch->type = 0; /* passive */
  4197. else
  4198. scan_ch->type = 1; /* active */
  4199. if (scan_ch->type & 1)
  4200. scan_ch->type |= (direct_mask << 1);
  4201. if (is_channel_narrow(ch_info))
  4202. scan_ch->type |= (1 << 7);
  4203. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4204. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4205. /* Set txpower levels to defaults */
  4206. scan_ch->tpc.dsp_atten = 110;
  4207. /* scan_pwr_info->tpc.dsp_atten; */
  4208. /*scan_pwr_info->tpc.tx_gain; */
  4209. if (band == IEEE80211_BAND_5GHZ)
  4210. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4211. else {
  4212. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4213. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4214. * power level:
  4215. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4216. */
  4217. }
  4218. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4219. scan_ch->channel,
  4220. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4221. (scan_ch->type & 1) ?
  4222. active_dwell : passive_dwell);
  4223. scan_ch++;
  4224. added++;
  4225. }
  4226. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4227. return added;
  4228. }
  4229. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4230. struct ieee80211_rate *rates)
  4231. {
  4232. int i;
  4233. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4234. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4235. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4236. rates[i].hw_value_short = i;
  4237. rates[i].flags = 0;
  4238. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4239. /*
  4240. * If CCK != 1M then set short preamble rate flag.
  4241. */
  4242. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4243. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4244. }
  4245. }
  4246. }
  4247. /**
  4248. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4249. */
  4250. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4251. {
  4252. struct iwl3945_channel_info *ch;
  4253. struct ieee80211_supported_band *sband;
  4254. struct ieee80211_channel *channels;
  4255. struct ieee80211_channel *geo_ch;
  4256. struct ieee80211_rate *rates;
  4257. int i = 0;
  4258. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4259. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4260. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4261. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4262. return 0;
  4263. }
  4264. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4265. priv->channel_count, GFP_KERNEL);
  4266. if (!channels)
  4267. return -ENOMEM;
  4268. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4269. GFP_KERNEL);
  4270. if (!rates) {
  4271. kfree(channels);
  4272. return -ENOMEM;
  4273. }
  4274. /* 5.2GHz channels start after the 2.4GHz channels */
  4275. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4276. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4277. /* just OFDM */
  4278. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4279. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4280. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4281. sband->channels = channels;
  4282. /* OFDM & CCK */
  4283. sband->bitrates = rates;
  4284. sband->n_bitrates = IWL_RATE_COUNT;
  4285. priv->ieee_channels = channels;
  4286. priv->ieee_rates = rates;
  4287. iwl3945_init_hw_rates(priv, rates);
  4288. for (i = 0; i < priv->channel_count; i++) {
  4289. ch = &priv->channel_info[i];
  4290. /* FIXME: might be removed if scan is OK*/
  4291. if (!is_channel_valid(ch))
  4292. continue;
  4293. if (is_channel_a_band(ch))
  4294. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4295. else
  4296. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4297. geo_ch = &sband->channels[sband->n_channels++];
  4298. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4299. geo_ch->max_power = ch->max_power_avg;
  4300. geo_ch->max_antenna_gain = 0xff;
  4301. geo_ch->hw_value = ch->channel;
  4302. if (is_channel_valid(ch)) {
  4303. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4304. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4305. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4306. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4307. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4308. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4309. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4310. priv->max_channel_txpower_limit =
  4311. ch->max_power_avg;
  4312. } else {
  4313. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4314. }
  4315. /* Save flags for reg domain usage */
  4316. geo_ch->orig_flags = geo_ch->flags;
  4317. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4318. ch->channel, geo_ch->center_freq,
  4319. is_channel_a_band(ch) ? "5.2" : "2.4",
  4320. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4321. "restricted" : "valid",
  4322. geo_ch->flags);
  4323. }
  4324. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4325. priv->cfg->sku & IWL_SKU_A) {
  4326. printk(KERN_INFO DRV_NAME
  4327. ": Incorrectly detected BG card as ABG. Please send "
  4328. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4329. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4330. priv->cfg->sku &= ~IWL_SKU_A;
  4331. }
  4332. printk(KERN_INFO DRV_NAME
  4333. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4334. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4335. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4336. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4337. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4338. &priv->bands[IEEE80211_BAND_2GHZ];
  4339. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4340. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4341. &priv->bands[IEEE80211_BAND_5GHZ];
  4342. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4343. return 0;
  4344. }
  4345. /*
  4346. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4347. */
  4348. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4349. {
  4350. kfree(priv->ieee_channels);
  4351. kfree(priv->ieee_rates);
  4352. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4353. }
  4354. /******************************************************************************
  4355. *
  4356. * uCode download functions
  4357. *
  4358. ******************************************************************************/
  4359. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4360. {
  4361. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4362. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4363. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4364. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4365. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4366. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4367. }
  4368. /**
  4369. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4370. * looking at all data.
  4371. */
  4372. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4373. {
  4374. u32 val;
  4375. u32 save_len = len;
  4376. int rc = 0;
  4377. u32 errcnt;
  4378. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4379. rc = iwl3945_grab_nic_access(priv);
  4380. if (rc)
  4381. return rc;
  4382. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4383. errcnt = 0;
  4384. for (; len > 0; len -= sizeof(u32), image++) {
  4385. /* read data comes through single port, auto-incr addr */
  4386. /* NOTE: Use the debugless read so we don't flood kernel log
  4387. * if IWL_DL_IO is set */
  4388. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4389. if (val != le32_to_cpu(*image)) {
  4390. IWL_ERROR("uCode INST section is invalid at "
  4391. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4392. save_len - len, val, le32_to_cpu(*image));
  4393. rc = -EIO;
  4394. errcnt++;
  4395. if (errcnt >= 20)
  4396. break;
  4397. }
  4398. }
  4399. iwl3945_release_nic_access(priv);
  4400. if (!errcnt)
  4401. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4402. return rc;
  4403. }
  4404. /**
  4405. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4406. * using sample data 100 bytes apart. If these sample points are good,
  4407. * it's a pretty good bet that everything between them is good, too.
  4408. */
  4409. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4410. {
  4411. u32 val;
  4412. int rc = 0;
  4413. u32 errcnt = 0;
  4414. u32 i;
  4415. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4416. rc = iwl3945_grab_nic_access(priv);
  4417. if (rc)
  4418. return rc;
  4419. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4420. /* read data comes through single port, auto-incr addr */
  4421. /* NOTE: Use the debugless read so we don't flood kernel log
  4422. * if IWL_DL_IO is set */
  4423. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4424. i + RTC_INST_LOWER_BOUND);
  4425. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4426. if (val != le32_to_cpu(*image)) {
  4427. #if 0 /* Enable this if you want to see details */
  4428. IWL_ERROR("uCode INST section is invalid at "
  4429. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4430. i, val, *image);
  4431. #endif
  4432. rc = -EIO;
  4433. errcnt++;
  4434. if (errcnt >= 3)
  4435. break;
  4436. }
  4437. }
  4438. iwl3945_release_nic_access(priv);
  4439. return rc;
  4440. }
  4441. /**
  4442. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4443. * and verify its contents
  4444. */
  4445. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4446. {
  4447. __le32 *image;
  4448. u32 len;
  4449. int rc = 0;
  4450. /* Try bootstrap */
  4451. image = (__le32 *)priv->ucode_boot.v_addr;
  4452. len = priv->ucode_boot.len;
  4453. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4454. if (rc == 0) {
  4455. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4456. return 0;
  4457. }
  4458. /* Try initialize */
  4459. image = (__le32 *)priv->ucode_init.v_addr;
  4460. len = priv->ucode_init.len;
  4461. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4462. if (rc == 0) {
  4463. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4464. return 0;
  4465. }
  4466. /* Try runtime/protocol */
  4467. image = (__le32 *)priv->ucode_code.v_addr;
  4468. len = priv->ucode_code.len;
  4469. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4470. if (rc == 0) {
  4471. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4472. return 0;
  4473. }
  4474. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4475. /* Since nothing seems to match, show first several data entries in
  4476. * instruction SRAM, so maybe visual inspection will give a clue.
  4477. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4478. image = (__le32 *)priv->ucode_boot.v_addr;
  4479. len = priv->ucode_boot.len;
  4480. rc = iwl3945_verify_inst_full(priv, image, len);
  4481. return rc;
  4482. }
  4483. /* check contents of special bootstrap uCode SRAM */
  4484. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4485. {
  4486. __le32 *image = priv->ucode_boot.v_addr;
  4487. u32 len = priv->ucode_boot.len;
  4488. u32 reg;
  4489. u32 val;
  4490. IWL_DEBUG_INFO("Begin verify bsm\n");
  4491. /* verify BSM SRAM contents */
  4492. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4493. for (reg = BSM_SRAM_LOWER_BOUND;
  4494. reg < BSM_SRAM_LOWER_BOUND + len;
  4495. reg += sizeof(u32), image ++) {
  4496. val = iwl3945_read_prph(priv, reg);
  4497. if (val != le32_to_cpu(*image)) {
  4498. IWL_ERROR("BSM uCode verification failed at "
  4499. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4500. BSM_SRAM_LOWER_BOUND,
  4501. reg - BSM_SRAM_LOWER_BOUND, len,
  4502. val, le32_to_cpu(*image));
  4503. return -EIO;
  4504. }
  4505. }
  4506. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4507. return 0;
  4508. }
  4509. /**
  4510. * iwl3945_load_bsm - Load bootstrap instructions
  4511. *
  4512. * BSM operation:
  4513. *
  4514. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4515. * in special SRAM that does not power down during RFKILL. When powering back
  4516. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4517. * the bootstrap program into the on-board processor, and starts it.
  4518. *
  4519. * The bootstrap program loads (via DMA) instructions and data for a new
  4520. * program from host DRAM locations indicated by the host driver in the
  4521. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4522. * automatically.
  4523. *
  4524. * When initializing the NIC, the host driver points the BSM to the
  4525. * "initialize" uCode image. This uCode sets up some internal data, then
  4526. * notifies host via "initialize alive" that it is complete.
  4527. *
  4528. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4529. * normal runtime uCode instructions and a backup uCode data cache buffer
  4530. * (filled initially with starting data values for the on-board processor),
  4531. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4532. * which begins normal operation.
  4533. *
  4534. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4535. * the backup data cache in DRAM before SRAM is powered down.
  4536. *
  4537. * When powering back up, the BSM loads the bootstrap program. This reloads
  4538. * the runtime uCode instructions and the backup data cache into SRAM,
  4539. * and re-launches the runtime uCode from where it left off.
  4540. */
  4541. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4542. {
  4543. __le32 *image = priv->ucode_boot.v_addr;
  4544. u32 len = priv->ucode_boot.len;
  4545. dma_addr_t pinst;
  4546. dma_addr_t pdata;
  4547. u32 inst_len;
  4548. u32 data_len;
  4549. int rc;
  4550. int i;
  4551. u32 done;
  4552. u32 reg_offset;
  4553. IWL_DEBUG_INFO("Begin load bsm\n");
  4554. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4555. if (len > IWL_MAX_BSM_SIZE)
  4556. return -EINVAL;
  4557. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4558. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4559. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4560. * after the "initialize" uCode has run, to point to
  4561. * runtime/protocol instructions and backup data cache. */
  4562. pinst = priv->ucode_init.p_addr;
  4563. pdata = priv->ucode_init_data.p_addr;
  4564. inst_len = priv->ucode_init.len;
  4565. data_len = priv->ucode_init_data.len;
  4566. rc = iwl3945_grab_nic_access(priv);
  4567. if (rc)
  4568. return rc;
  4569. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4570. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4571. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4572. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4573. /* Fill BSM memory with bootstrap instructions */
  4574. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4575. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4576. reg_offset += sizeof(u32), image++)
  4577. _iwl3945_write_prph(priv, reg_offset,
  4578. le32_to_cpu(*image));
  4579. rc = iwl3945_verify_bsm(priv);
  4580. if (rc) {
  4581. iwl3945_release_nic_access(priv);
  4582. return rc;
  4583. }
  4584. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4585. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4586. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4587. RTC_INST_LOWER_BOUND);
  4588. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4589. /* Load bootstrap code into instruction SRAM now,
  4590. * to prepare to load "initialize" uCode */
  4591. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4592. BSM_WR_CTRL_REG_BIT_START);
  4593. /* Wait for load of bootstrap uCode to finish */
  4594. for (i = 0; i < 100; i++) {
  4595. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4596. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4597. break;
  4598. udelay(10);
  4599. }
  4600. if (i < 100)
  4601. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4602. else {
  4603. IWL_ERROR("BSM write did not complete!\n");
  4604. return -EIO;
  4605. }
  4606. /* Enable future boot loads whenever power management unit triggers it
  4607. * (e.g. when powering back up after power-save shutdown) */
  4608. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4609. BSM_WR_CTRL_REG_BIT_START_EN);
  4610. iwl3945_release_nic_access(priv);
  4611. return 0;
  4612. }
  4613. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4614. {
  4615. /* Remove all resets to allow NIC to operate */
  4616. iwl3945_write32(priv, CSR_RESET, 0);
  4617. }
  4618. /**
  4619. * iwl3945_read_ucode - Read uCode images from disk file.
  4620. *
  4621. * Copy into buffers for card to fetch via bus-mastering
  4622. */
  4623. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4624. {
  4625. struct iwl3945_ucode *ucode;
  4626. int ret = 0;
  4627. const struct firmware *ucode_raw;
  4628. /* firmware file name contains uCode/driver compatibility version */
  4629. const char *name = priv->cfg->fw_name;
  4630. u8 *src;
  4631. size_t len;
  4632. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4633. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4634. * request_firmware() is synchronous, file is in memory on return. */
  4635. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4636. if (ret < 0) {
  4637. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4638. name, ret);
  4639. goto error;
  4640. }
  4641. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4642. name, ucode_raw->size);
  4643. /* Make sure that we got at least our header! */
  4644. if (ucode_raw->size < sizeof(*ucode)) {
  4645. IWL_ERROR("File size way too small!\n");
  4646. ret = -EINVAL;
  4647. goto err_release;
  4648. }
  4649. /* Data from ucode file: header followed by uCode images */
  4650. ucode = (void *)ucode_raw->data;
  4651. ver = le32_to_cpu(ucode->ver);
  4652. inst_size = le32_to_cpu(ucode->inst_size);
  4653. data_size = le32_to_cpu(ucode->data_size);
  4654. init_size = le32_to_cpu(ucode->init_size);
  4655. init_data_size = le32_to_cpu(ucode->init_data_size);
  4656. boot_size = le32_to_cpu(ucode->boot_size);
  4657. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4658. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4659. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4660. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4661. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4662. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4663. /* Verify size of file vs. image size info in file's header */
  4664. if (ucode_raw->size < sizeof(*ucode) +
  4665. inst_size + data_size + init_size +
  4666. init_data_size + boot_size) {
  4667. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4668. (int)ucode_raw->size);
  4669. ret = -EINVAL;
  4670. goto err_release;
  4671. }
  4672. /* Verify that uCode images will fit in card's SRAM */
  4673. if (inst_size > IWL_MAX_INST_SIZE) {
  4674. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4675. inst_size);
  4676. ret = -EINVAL;
  4677. goto err_release;
  4678. }
  4679. if (data_size > IWL_MAX_DATA_SIZE) {
  4680. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4681. data_size);
  4682. ret = -EINVAL;
  4683. goto err_release;
  4684. }
  4685. if (init_size > IWL_MAX_INST_SIZE) {
  4686. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4687. init_size);
  4688. ret = -EINVAL;
  4689. goto err_release;
  4690. }
  4691. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4692. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4693. init_data_size);
  4694. ret = -EINVAL;
  4695. goto err_release;
  4696. }
  4697. if (boot_size > IWL_MAX_BSM_SIZE) {
  4698. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4699. boot_size);
  4700. ret = -EINVAL;
  4701. goto err_release;
  4702. }
  4703. /* Allocate ucode buffers for card's bus-master loading ... */
  4704. /* Runtime instructions and 2 copies of data:
  4705. * 1) unmodified from disk
  4706. * 2) backup cache for save/restore during power-downs */
  4707. priv->ucode_code.len = inst_size;
  4708. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4709. priv->ucode_data.len = data_size;
  4710. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4711. priv->ucode_data_backup.len = data_size;
  4712. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4713. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4714. !priv->ucode_data_backup.v_addr)
  4715. goto err_pci_alloc;
  4716. /* Initialization instructions and data */
  4717. if (init_size && init_data_size) {
  4718. priv->ucode_init.len = init_size;
  4719. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4720. priv->ucode_init_data.len = init_data_size;
  4721. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4722. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4723. goto err_pci_alloc;
  4724. }
  4725. /* Bootstrap (instructions only, no data) */
  4726. if (boot_size) {
  4727. priv->ucode_boot.len = boot_size;
  4728. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4729. if (!priv->ucode_boot.v_addr)
  4730. goto err_pci_alloc;
  4731. }
  4732. /* Copy images into buffers for card's bus-master reads ... */
  4733. /* Runtime instructions (first block of data in file) */
  4734. src = &ucode->data[0];
  4735. len = priv->ucode_code.len;
  4736. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4737. memcpy(priv->ucode_code.v_addr, src, len);
  4738. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4739. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4740. /* Runtime data (2nd block)
  4741. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4742. src = &ucode->data[inst_size];
  4743. len = priv->ucode_data.len;
  4744. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4745. memcpy(priv->ucode_data.v_addr, src, len);
  4746. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4747. /* Initialization instructions (3rd block) */
  4748. if (init_size) {
  4749. src = &ucode->data[inst_size + data_size];
  4750. len = priv->ucode_init.len;
  4751. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4752. len);
  4753. memcpy(priv->ucode_init.v_addr, src, len);
  4754. }
  4755. /* Initialization data (4th block) */
  4756. if (init_data_size) {
  4757. src = &ucode->data[inst_size + data_size + init_size];
  4758. len = priv->ucode_init_data.len;
  4759. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4760. (int)len);
  4761. memcpy(priv->ucode_init_data.v_addr, src, len);
  4762. }
  4763. /* Bootstrap instructions (5th block) */
  4764. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4765. len = priv->ucode_boot.len;
  4766. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4767. (int)len);
  4768. memcpy(priv->ucode_boot.v_addr, src, len);
  4769. /* We have our copies now, allow OS release its copies */
  4770. release_firmware(ucode_raw);
  4771. return 0;
  4772. err_pci_alloc:
  4773. IWL_ERROR("failed to allocate pci memory\n");
  4774. ret = -ENOMEM;
  4775. iwl3945_dealloc_ucode_pci(priv);
  4776. err_release:
  4777. release_firmware(ucode_raw);
  4778. error:
  4779. return ret;
  4780. }
  4781. /**
  4782. * iwl3945_set_ucode_ptrs - Set uCode address location
  4783. *
  4784. * Tell initialization uCode where to find runtime uCode.
  4785. *
  4786. * BSM registers initially contain pointers to initialization uCode.
  4787. * We need to replace them to load runtime uCode inst and data,
  4788. * and to save runtime data when powering down.
  4789. */
  4790. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4791. {
  4792. dma_addr_t pinst;
  4793. dma_addr_t pdata;
  4794. int rc = 0;
  4795. unsigned long flags;
  4796. /* bits 31:0 for 3945 */
  4797. pinst = priv->ucode_code.p_addr;
  4798. pdata = priv->ucode_data_backup.p_addr;
  4799. spin_lock_irqsave(&priv->lock, flags);
  4800. rc = iwl3945_grab_nic_access(priv);
  4801. if (rc) {
  4802. spin_unlock_irqrestore(&priv->lock, flags);
  4803. return rc;
  4804. }
  4805. /* Tell bootstrap uCode where to find image to load */
  4806. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4807. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4808. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4809. priv->ucode_data.len);
  4810. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4811. * that all new ptr/size info is in place */
  4812. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4813. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4814. iwl3945_release_nic_access(priv);
  4815. spin_unlock_irqrestore(&priv->lock, flags);
  4816. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4817. return rc;
  4818. }
  4819. /**
  4820. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4821. *
  4822. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4823. *
  4824. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4825. */
  4826. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4827. {
  4828. /* Check alive response for "valid" sign from uCode */
  4829. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4830. /* We had an error bringing up the hardware, so take it
  4831. * all the way back down so we can try again */
  4832. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4833. goto restart;
  4834. }
  4835. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4836. * This is a paranoid check, because we would not have gotten the
  4837. * "initialize" alive if code weren't properly loaded. */
  4838. if (iwl3945_verify_ucode(priv)) {
  4839. /* Runtime instruction load was bad;
  4840. * take it all the way back down so we can try again */
  4841. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4842. goto restart;
  4843. }
  4844. /* Send pointers to protocol/runtime uCode image ... init code will
  4845. * load and launch runtime uCode, which will send us another "Alive"
  4846. * notification. */
  4847. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4848. if (iwl3945_set_ucode_ptrs(priv)) {
  4849. /* Runtime instruction load won't happen;
  4850. * take it all the way back down so we can try again */
  4851. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4852. goto restart;
  4853. }
  4854. return;
  4855. restart:
  4856. queue_work(priv->workqueue, &priv->restart);
  4857. }
  4858. /**
  4859. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4860. * from protocol/runtime uCode (initialization uCode's
  4861. * Alive gets handled by iwl3945_init_alive_start()).
  4862. */
  4863. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4864. {
  4865. int rc = 0;
  4866. int thermal_spin = 0;
  4867. u32 rfkill;
  4868. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4869. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4870. /* We had an error bringing up the hardware, so take it
  4871. * all the way back down so we can try again */
  4872. IWL_DEBUG_INFO("Alive failed.\n");
  4873. goto restart;
  4874. }
  4875. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4876. * This is a paranoid check, because we would not have gotten the
  4877. * "runtime" alive if code weren't properly loaded. */
  4878. if (iwl3945_verify_ucode(priv)) {
  4879. /* Runtime instruction load was bad;
  4880. * take it all the way back down so we can try again */
  4881. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4882. goto restart;
  4883. }
  4884. iwl3945_clear_stations_table(priv);
  4885. rc = iwl3945_grab_nic_access(priv);
  4886. if (rc) {
  4887. IWL_WARNING("Can not read rfkill status from adapter\n");
  4888. return;
  4889. }
  4890. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4891. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4892. iwl3945_release_nic_access(priv);
  4893. if (rfkill & 0x1) {
  4894. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4895. /* if rfkill is not on, then wait for thermal
  4896. * sensor in adapter to kick in */
  4897. while (iwl3945_hw_get_temperature(priv) == 0) {
  4898. thermal_spin++;
  4899. udelay(10);
  4900. }
  4901. if (thermal_spin)
  4902. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4903. thermal_spin * 10);
  4904. } else
  4905. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4906. /* After the ALIVE response, we can send commands to 3945 uCode */
  4907. set_bit(STATUS_ALIVE, &priv->status);
  4908. /* Clear out the uCode error bit if it is set */
  4909. clear_bit(STATUS_FW_ERROR, &priv->status);
  4910. if (iwl3945_is_rfkill(priv))
  4911. return;
  4912. ieee80211_start_queues(priv->hw);
  4913. priv->active_rate = priv->rates_mask;
  4914. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4915. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4916. if (iwl3945_is_associated(priv)) {
  4917. struct iwl3945_rxon_cmd *active_rxon =
  4918. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4919. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4920. sizeof(priv->staging_rxon));
  4921. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4922. } else {
  4923. /* Initialize our rx_config data */
  4924. iwl3945_connection_init_rx_config(priv);
  4925. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4926. }
  4927. /* Configure Bluetooth device coexistence support */
  4928. iwl3945_send_bt_config(priv);
  4929. /* Configure the adapter for unassociated operation */
  4930. iwl3945_commit_rxon(priv);
  4931. /* At this point, the NIC is initialized and operational */
  4932. priv->notif_missed_beacons = 0;
  4933. iwl3945_reg_txpower_periodic(priv);
  4934. iwl3945_led_register(priv);
  4935. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4936. set_bit(STATUS_READY, &priv->status);
  4937. wake_up_interruptible(&priv->wait_command_queue);
  4938. if (priv->error_recovering)
  4939. iwl3945_error_recovery(priv);
  4940. ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
  4941. return;
  4942. restart:
  4943. queue_work(priv->workqueue, &priv->restart);
  4944. }
  4945. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4946. static void __iwl3945_down(struct iwl3945_priv *priv)
  4947. {
  4948. unsigned long flags;
  4949. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4950. struct ieee80211_conf *conf = NULL;
  4951. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4952. conf = ieee80211_get_hw_conf(priv->hw);
  4953. if (!exit_pending)
  4954. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4955. iwl3945_led_unregister(priv);
  4956. iwl3945_clear_stations_table(priv);
  4957. /* Unblock any waiting calls */
  4958. wake_up_interruptible_all(&priv->wait_command_queue);
  4959. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4960. * exiting the module */
  4961. if (!exit_pending)
  4962. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4963. /* stop and reset the on-board processor */
  4964. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4965. /* tell the device to stop sending interrupts */
  4966. spin_lock_irqsave(&priv->lock, flags);
  4967. iwl3945_disable_interrupts(priv);
  4968. spin_unlock_irqrestore(&priv->lock, flags);
  4969. iwl_synchronize_irq(priv);
  4970. if (priv->mac80211_registered)
  4971. ieee80211_stop_queues(priv->hw);
  4972. /* If we have not previously called iwl3945_init() then
  4973. * clear all bits but the RF Kill and SUSPEND bits and return */
  4974. if (!iwl3945_is_init(priv)) {
  4975. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4976. STATUS_RF_KILL_HW |
  4977. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4978. STATUS_RF_KILL_SW |
  4979. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4980. STATUS_GEO_CONFIGURED |
  4981. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4982. STATUS_IN_SUSPEND;
  4983. goto exit;
  4984. }
  4985. /* ...otherwise clear out all the status bits but the RF Kill and
  4986. * SUSPEND bits and continue taking the NIC down. */
  4987. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4988. STATUS_RF_KILL_HW |
  4989. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4990. STATUS_RF_KILL_SW |
  4991. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4992. STATUS_GEO_CONFIGURED |
  4993. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4994. STATUS_IN_SUSPEND |
  4995. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4996. STATUS_FW_ERROR;
  4997. spin_lock_irqsave(&priv->lock, flags);
  4998. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4999. spin_unlock_irqrestore(&priv->lock, flags);
  5000. iwl3945_hw_txq_ctx_stop(priv);
  5001. iwl3945_hw_rxq_stop(priv);
  5002. spin_lock_irqsave(&priv->lock, flags);
  5003. if (!iwl3945_grab_nic_access(priv)) {
  5004. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5005. APMG_CLK_VAL_DMA_CLK_RQT);
  5006. iwl3945_release_nic_access(priv);
  5007. }
  5008. spin_unlock_irqrestore(&priv->lock, flags);
  5009. udelay(5);
  5010. iwl3945_hw_nic_stop_master(priv);
  5011. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5012. iwl3945_hw_nic_reset(priv);
  5013. exit:
  5014. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5015. if (priv->ibss_beacon)
  5016. dev_kfree_skb(priv->ibss_beacon);
  5017. priv->ibss_beacon = NULL;
  5018. /* clear out any free frames */
  5019. iwl3945_clear_free_frames(priv);
  5020. }
  5021. static void iwl3945_down(struct iwl3945_priv *priv)
  5022. {
  5023. mutex_lock(&priv->mutex);
  5024. __iwl3945_down(priv);
  5025. mutex_unlock(&priv->mutex);
  5026. iwl3945_cancel_deferred_work(priv);
  5027. }
  5028. #define MAX_HW_RESTARTS 5
  5029. static int __iwl3945_up(struct iwl3945_priv *priv)
  5030. {
  5031. int rc, i;
  5032. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5033. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5034. return -EIO;
  5035. }
  5036. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5037. IWL_WARNING("Radio disabled by SW RF kill (module "
  5038. "parameter)\n");
  5039. return -ENODEV;
  5040. }
  5041. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5042. IWL_ERROR("ucode not available for device bringup\n");
  5043. return -EIO;
  5044. }
  5045. /* If platform's RF_KILL switch is NOT set to KILL */
  5046. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5047. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5048. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5049. else {
  5050. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5051. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5052. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5053. return -ENODEV;
  5054. }
  5055. }
  5056. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5057. rc = iwl3945_hw_nic_init(priv);
  5058. if (rc) {
  5059. IWL_ERROR("Unable to int nic\n");
  5060. return rc;
  5061. }
  5062. /* make sure rfkill handshake bits are cleared */
  5063. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5064. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5065. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5066. /* clear (again), then enable host interrupts */
  5067. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5068. iwl3945_enable_interrupts(priv);
  5069. /* really make sure rfkill handshake bits are cleared */
  5070. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5071. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5072. /* Copy original ucode data image from disk into backup cache.
  5073. * This will be used to initialize the on-board processor's
  5074. * data SRAM for a clean start when the runtime program first loads. */
  5075. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5076. priv->ucode_data.len);
  5077. /* We return success when we resume from suspend and rf_kill is on. */
  5078. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5079. return 0;
  5080. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5081. iwl3945_clear_stations_table(priv);
  5082. /* load bootstrap state machine,
  5083. * load bootstrap program into processor's memory,
  5084. * prepare to load the "initialize" uCode */
  5085. rc = iwl3945_load_bsm(priv);
  5086. if (rc) {
  5087. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5088. continue;
  5089. }
  5090. /* start card; "initialize" will load runtime ucode */
  5091. iwl3945_nic_start(priv);
  5092. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5093. return 0;
  5094. }
  5095. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5096. __iwl3945_down(priv);
  5097. /* tried to restart and config the device for as long as our
  5098. * patience could withstand */
  5099. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5100. return -EIO;
  5101. }
  5102. /*****************************************************************************
  5103. *
  5104. * Workqueue callbacks
  5105. *
  5106. *****************************************************************************/
  5107. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5108. {
  5109. struct iwl3945_priv *priv =
  5110. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5111. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5112. return;
  5113. mutex_lock(&priv->mutex);
  5114. iwl3945_init_alive_start(priv);
  5115. mutex_unlock(&priv->mutex);
  5116. }
  5117. static void iwl3945_bg_alive_start(struct work_struct *data)
  5118. {
  5119. struct iwl3945_priv *priv =
  5120. container_of(data, struct iwl3945_priv, alive_start.work);
  5121. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5122. return;
  5123. mutex_lock(&priv->mutex);
  5124. iwl3945_alive_start(priv);
  5125. mutex_unlock(&priv->mutex);
  5126. }
  5127. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5128. {
  5129. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5130. wake_up_interruptible(&priv->wait_command_queue);
  5131. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5132. return;
  5133. mutex_lock(&priv->mutex);
  5134. if (!iwl3945_is_rfkill(priv)) {
  5135. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5136. "HW and/or SW RF Kill no longer active, restarting "
  5137. "device\n");
  5138. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5139. queue_work(priv->workqueue, &priv->restart);
  5140. } else {
  5141. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5142. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5143. "disabled by SW switch\n");
  5144. else
  5145. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5146. "Kill switch must be turned off for "
  5147. "wireless networking to work.\n");
  5148. }
  5149. mutex_unlock(&priv->mutex);
  5150. }
  5151. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5152. static void iwl3945_bg_scan_check(struct work_struct *data)
  5153. {
  5154. struct iwl3945_priv *priv =
  5155. container_of(data, struct iwl3945_priv, scan_check.work);
  5156. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5157. return;
  5158. mutex_lock(&priv->mutex);
  5159. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5160. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5161. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5162. "Scan completion watchdog resetting adapter (%dms)\n",
  5163. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5164. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5165. iwl3945_send_scan_abort(priv);
  5166. }
  5167. mutex_unlock(&priv->mutex);
  5168. }
  5169. static void iwl3945_bg_request_scan(struct work_struct *data)
  5170. {
  5171. struct iwl3945_priv *priv =
  5172. container_of(data, struct iwl3945_priv, request_scan);
  5173. struct iwl3945_host_cmd cmd = {
  5174. .id = REPLY_SCAN_CMD,
  5175. .len = sizeof(struct iwl3945_scan_cmd),
  5176. .meta.flags = CMD_SIZE_HUGE,
  5177. };
  5178. int rc = 0;
  5179. struct iwl3945_scan_cmd *scan;
  5180. struct ieee80211_conf *conf = NULL;
  5181. u8 direct_mask;
  5182. enum ieee80211_band band;
  5183. conf = ieee80211_get_hw_conf(priv->hw);
  5184. mutex_lock(&priv->mutex);
  5185. if (!iwl3945_is_ready(priv)) {
  5186. IWL_WARNING("request scan called when driver not ready.\n");
  5187. goto done;
  5188. }
  5189. /* Make sure the scan wasn't cancelled before this queued work
  5190. * was given the chance to run... */
  5191. if (!test_bit(STATUS_SCANNING, &priv->status))
  5192. goto done;
  5193. /* This should never be called or scheduled if there is currently
  5194. * a scan active in the hardware. */
  5195. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5196. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5197. "Ignoring second request.\n");
  5198. rc = -EIO;
  5199. goto done;
  5200. }
  5201. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5202. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5203. goto done;
  5204. }
  5205. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5206. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5207. goto done;
  5208. }
  5209. if (iwl3945_is_rfkill(priv)) {
  5210. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5211. goto done;
  5212. }
  5213. if (!test_bit(STATUS_READY, &priv->status)) {
  5214. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5215. goto done;
  5216. }
  5217. if (!priv->scan_bands) {
  5218. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5219. goto done;
  5220. }
  5221. if (!priv->scan) {
  5222. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5223. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5224. if (!priv->scan) {
  5225. rc = -ENOMEM;
  5226. goto done;
  5227. }
  5228. }
  5229. scan = priv->scan;
  5230. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5231. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5232. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5233. if (iwl3945_is_associated(priv)) {
  5234. u16 interval = 0;
  5235. u32 extra;
  5236. u32 suspend_time = 100;
  5237. u32 scan_suspend_time = 100;
  5238. unsigned long flags;
  5239. IWL_DEBUG_INFO("Scanning while associated...\n");
  5240. spin_lock_irqsave(&priv->lock, flags);
  5241. interval = priv->beacon_int;
  5242. spin_unlock_irqrestore(&priv->lock, flags);
  5243. scan->suspend_time = 0;
  5244. scan->max_out_time = cpu_to_le32(200 * 1024);
  5245. if (!interval)
  5246. interval = suspend_time;
  5247. /*
  5248. * suspend time format:
  5249. * 0-19: beacon interval in usec (time before exec.)
  5250. * 20-23: 0
  5251. * 24-31: number of beacons (suspend between channels)
  5252. */
  5253. extra = (suspend_time / interval) << 24;
  5254. scan_suspend_time = 0xFF0FFFFF &
  5255. (extra | ((suspend_time % interval) * 1024));
  5256. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5257. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5258. scan_suspend_time, interval);
  5259. }
  5260. /* We should add the ability for user to lock to PASSIVE ONLY */
  5261. if (priv->one_direct_scan) {
  5262. IWL_DEBUG_SCAN
  5263. ("Kicking off one direct scan for '%s'\n",
  5264. iwl3945_escape_essid(priv->direct_ssid,
  5265. priv->direct_ssid_len));
  5266. scan->direct_scan[0].id = WLAN_EID_SSID;
  5267. scan->direct_scan[0].len = priv->direct_ssid_len;
  5268. memcpy(scan->direct_scan[0].ssid,
  5269. priv->direct_ssid, priv->direct_ssid_len);
  5270. direct_mask = 1;
  5271. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5272. scan->direct_scan[0].id = WLAN_EID_SSID;
  5273. scan->direct_scan[0].len = priv->essid_len;
  5274. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5275. direct_mask = 1;
  5276. } else
  5277. direct_mask = 0;
  5278. /* We don't build a direct scan probe request; the uCode will do
  5279. * that based on the direct_mask added to each channel entry */
  5280. scan->tx_cmd.len = cpu_to_le16(
  5281. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5282. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5283. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5284. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5285. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5286. /* flags + rate selection */
  5287. switch (priv->scan_bands) {
  5288. case 2:
  5289. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5290. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5291. scan->good_CRC_th = 0;
  5292. band = IEEE80211_BAND_2GHZ;
  5293. break;
  5294. case 1:
  5295. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5296. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5297. band = IEEE80211_BAND_5GHZ;
  5298. break;
  5299. default:
  5300. IWL_WARNING("Invalid scan band count\n");
  5301. goto done;
  5302. }
  5303. /* select Rx antennas */
  5304. scan->flags |= iwl3945_get_antenna_flags(priv);
  5305. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5306. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5307. if (direct_mask) {
  5308. IWL_DEBUG_SCAN
  5309. ("Initiating direct scan for %s.\n",
  5310. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5311. scan->channel_count =
  5312. iwl3945_get_channels_for_scan(
  5313. priv, band, 1, /* active */
  5314. direct_mask,
  5315. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5316. } else {
  5317. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5318. scan->channel_count =
  5319. iwl3945_get_channels_for_scan(
  5320. priv, band, 0, /* passive */
  5321. direct_mask,
  5322. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5323. }
  5324. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5325. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5326. cmd.data = scan;
  5327. scan->len = cpu_to_le16(cmd.len);
  5328. set_bit(STATUS_SCAN_HW, &priv->status);
  5329. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5330. if (rc)
  5331. goto done;
  5332. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5333. IWL_SCAN_CHECK_WATCHDOG);
  5334. mutex_unlock(&priv->mutex);
  5335. return;
  5336. done:
  5337. /* inform mac80211 scan aborted */
  5338. queue_work(priv->workqueue, &priv->scan_completed);
  5339. mutex_unlock(&priv->mutex);
  5340. }
  5341. static void iwl3945_bg_up(struct work_struct *data)
  5342. {
  5343. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5344. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5345. return;
  5346. mutex_lock(&priv->mutex);
  5347. __iwl3945_up(priv);
  5348. mutex_unlock(&priv->mutex);
  5349. }
  5350. static void iwl3945_bg_restart(struct work_struct *data)
  5351. {
  5352. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5353. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5354. return;
  5355. iwl3945_down(priv);
  5356. queue_work(priv->workqueue, &priv->up);
  5357. }
  5358. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5359. {
  5360. struct iwl3945_priv *priv =
  5361. container_of(data, struct iwl3945_priv, rx_replenish);
  5362. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5363. return;
  5364. mutex_lock(&priv->mutex);
  5365. iwl3945_rx_replenish(priv);
  5366. mutex_unlock(&priv->mutex);
  5367. }
  5368. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5369. static void iwl3945_bg_post_associate(struct work_struct *data)
  5370. {
  5371. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5372. post_associate.work);
  5373. int rc = 0;
  5374. struct ieee80211_conf *conf = NULL;
  5375. DECLARE_MAC_BUF(mac);
  5376. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5377. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5378. return;
  5379. }
  5380. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5381. priv->assoc_id,
  5382. print_mac(mac, priv->active_rxon.bssid_addr));
  5383. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5384. return;
  5385. mutex_lock(&priv->mutex);
  5386. if (!priv->vif || !priv->is_open) {
  5387. mutex_unlock(&priv->mutex);
  5388. return;
  5389. }
  5390. iwl3945_scan_cancel_timeout(priv, 200);
  5391. conf = ieee80211_get_hw_conf(priv->hw);
  5392. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5393. iwl3945_commit_rxon(priv);
  5394. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5395. iwl3945_setup_rxon_timing(priv);
  5396. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5397. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5398. if (rc)
  5399. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5400. "Attempting to continue.\n");
  5401. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5402. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5403. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5404. priv->assoc_id, priv->beacon_int);
  5405. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5406. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5407. else
  5408. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5409. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5410. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5411. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5412. else
  5413. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5414. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5415. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5416. }
  5417. iwl3945_commit_rxon(priv);
  5418. switch (priv->iw_mode) {
  5419. case IEEE80211_IF_TYPE_STA:
  5420. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5421. break;
  5422. case IEEE80211_IF_TYPE_IBSS:
  5423. /* clear out the station table */
  5424. iwl3945_clear_stations_table(priv);
  5425. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5426. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5427. iwl3945_sync_sta(priv, IWL_STA_ID,
  5428. (priv->band == IEEE80211_BAND_5GHZ) ?
  5429. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5430. CMD_ASYNC);
  5431. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5432. iwl3945_send_beacon_cmd(priv);
  5433. break;
  5434. default:
  5435. IWL_ERROR("%s Should not be called in %d mode\n",
  5436. __FUNCTION__, priv->iw_mode);
  5437. break;
  5438. }
  5439. iwl3945_sequence_reset(priv);
  5440. iwl3945_activate_qos(priv, 0);
  5441. /* we have just associated, don't start scan too early */
  5442. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5443. mutex_unlock(&priv->mutex);
  5444. }
  5445. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5446. {
  5447. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5448. if (!iwl3945_is_ready(priv))
  5449. return;
  5450. mutex_lock(&priv->mutex);
  5451. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5452. iwl3945_send_scan_abort(priv);
  5453. mutex_unlock(&priv->mutex);
  5454. }
  5455. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5456. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5457. {
  5458. struct iwl3945_priv *priv =
  5459. container_of(work, struct iwl3945_priv, scan_completed);
  5460. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5461. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5462. return;
  5463. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5464. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5465. ieee80211_scan_completed(priv->hw);
  5466. /* Since setting the TXPOWER may have been deferred while
  5467. * performing the scan, fire one off */
  5468. mutex_lock(&priv->mutex);
  5469. iwl3945_hw_reg_send_txpower(priv);
  5470. mutex_unlock(&priv->mutex);
  5471. }
  5472. /*****************************************************************************
  5473. *
  5474. * mac80211 entry point functions
  5475. *
  5476. *****************************************************************************/
  5477. #define UCODE_READY_TIMEOUT (2 * HZ)
  5478. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5479. {
  5480. struct iwl3945_priv *priv = hw->priv;
  5481. int ret;
  5482. IWL_DEBUG_MAC80211("enter\n");
  5483. if (pci_enable_device(priv->pci_dev)) {
  5484. IWL_ERROR("Fail to pci_enable_device\n");
  5485. return -ENODEV;
  5486. }
  5487. pci_restore_state(priv->pci_dev);
  5488. pci_enable_msi(priv->pci_dev);
  5489. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5490. DRV_NAME, priv);
  5491. if (ret) {
  5492. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5493. goto out_disable_msi;
  5494. }
  5495. /* we should be verifying the device is ready to be opened */
  5496. mutex_lock(&priv->mutex);
  5497. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5498. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5499. * ucode filename and max sizes are card-specific. */
  5500. if (!priv->ucode_code.len) {
  5501. ret = iwl3945_read_ucode(priv);
  5502. if (ret) {
  5503. IWL_ERROR("Could not read microcode: %d\n", ret);
  5504. mutex_unlock(&priv->mutex);
  5505. goto out_release_irq;
  5506. }
  5507. }
  5508. ret = __iwl3945_up(priv);
  5509. mutex_unlock(&priv->mutex);
  5510. if (ret)
  5511. goto out_release_irq;
  5512. IWL_DEBUG_INFO("Start UP work.\n");
  5513. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5514. return 0;
  5515. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5516. * mac80211 will not be run successfully. */
  5517. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5518. test_bit(STATUS_READY, &priv->status),
  5519. UCODE_READY_TIMEOUT);
  5520. if (!ret) {
  5521. if (!test_bit(STATUS_READY, &priv->status)) {
  5522. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5523. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5524. ret = -ETIMEDOUT;
  5525. goto out_release_irq;
  5526. }
  5527. }
  5528. priv->is_open = 1;
  5529. IWL_DEBUG_MAC80211("leave\n");
  5530. return 0;
  5531. out_release_irq:
  5532. free_irq(priv->pci_dev->irq, priv);
  5533. out_disable_msi:
  5534. pci_disable_msi(priv->pci_dev);
  5535. pci_disable_device(priv->pci_dev);
  5536. priv->is_open = 0;
  5537. IWL_DEBUG_MAC80211("leave - failed\n");
  5538. return ret;
  5539. }
  5540. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5541. {
  5542. struct iwl3945_priv *priv = hw->priv;
  5543. IWL_DEBUG_MAC80211("enter\n");
  5544. if (!priv->is_open) {
  5545. IWL_DEBUG_MAC80211("leave - skip\n");
  5546. return;
  5547. }
  5548. priv->is_open = 0;
  5549. if (iwl3945_is_ready_rf(priv)) {
  5550. /* stop mac, cancel any scan request and clear
  5551. * RXON_FILTER_ASSOC_MSK BIT
  5552. */
  5553. mutex_lock(&priv->mutex);
  5554. iwl3945_scan_cancel_timeout(priv, 100);
  5555. cancel_delayed_work(&priv->post_associate);
  5556. mutex_unlock(&priv->mutex);
  5557. }
  5558. iwl3945_down(priv);
  5559. flush_workqueue(priv->workqueue);
  5560. free_irq(priv->pci_dev->irq, priv);
  5561. pci_disable_msi(priv->pci_dev);
  5562. pci_save_state(priv->pci_dev);
  5563. pci_disable_device(priv->pci_dev);
  5564. IWL_DEBUG_MAC80211("leave\n");
  5565. }
  5566. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5567. struct ieee80211_tx_control *ctl)
  5568. {
  5569. struct iwl3945_priv *priv = hw->priv;
  5570. IWL_DEBUG_MAC80211("enter\n");
  5571. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5572. IWL_DEBUG_MAC80211("leave - monitor\n");
  5573. return -1;
  5574. }
  5575. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5576. ctl->tx_rate->bitrate);
  5577. if (iwl3945_tx_skb(priv, skb, ctl))
  5578. dev_kfree_skb_any(skb);
  5579. IWL_DEBUG_MAC80211("leave\n");
  5580. return 0;
  5581. }
  5582. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5583. struct ieee80211_if_init_conf *conf)
  5584. {
  5585. struct iwl3945_priv *priv = hw->priv;
  5586. unsigned long flags;
  5587. DECLARE_MAC_BUF(mac);
  5588. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5589. if (priv->vif) {
  5590. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5591. return -EOPNOTSUPP;
  5592. }
  5593. spin_lock_irqsave(&priv->lock, flags);
  5594. priv->vif = conf->vif;
  5595. spin_unlock_irqrestore(&priv->lock, flags);
  5596. mutex_lock(&priv->mutex);
  5597. if (conf->mac_addr) {
  5598. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5599. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5600. }
  5601. if (iwl3945_is_ready(priv))
  5602. iwl3945_set_mode(priv, conf->type);
  5603. mutex_unlock(&priv->mutex);
  5604. IWL_DEBUG_MAC80211("leave\n");
  5605. return 0;
  5606. }
  5607. /**
  5608. * iwl3945_mac_config - mac80211 config callback
  5609. *
  5610. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5611. * be set inappropriately and the driver currently sets the hardware up to
  5612. * use it whenever needed.
  5613. */
  5614. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5615. {
  5616. struct iwl3945_priv *priv = hw->priv;
  5617. const struct iwl3945_channel_info *ch_info;
  5618. unsigned long flags;
  5619. int ret = 0;
  5620. mutex_lock(&priv->mutex);
  5621. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5622. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5623. if (!iwl3945_is_ready(priv)) {
  5624. IWL_DEBUG_MAC80211("leave - not ready\n");
  5625. ret = -EIO;
  5626. goto out;
  5627. }
  5628. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5629. test_bit(STATUS_SCANNING, &priv->status))) {
  5630. IWL_DEBUG_MAC80211("leave - scanning\n");
  5631. set_bit(STATUS_CONF_PENDING, &priv->status);
  5632. mutex_unlock(&priv->mutex);
  5633. return 0;
  5634. }
  5635. spin_lock_irqsave(&priv->lock, flags);
  5636. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5637. conf->channel->hw_value);
  5638. if (!is_channel_valid(ch_info)) {
  5639. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5640. conf->channel->hw_value, conf->channel->band);
  5641. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5642. spin_unlock_irqrestore(&priv->lock, flags);
  5643. ret = -EINVAL;
  5644. goto out;
  5645. }
  5646. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5647. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5648. /* The list of supported rates and rate mask can be different
  5649. * for each phymode; since the phymode may have changed, reset
  5650. * the rate mask to what mac80211 lists */
  5651. iwl3945_set_rate(priv);
  5652. spin_unlock_irqrestore(&priv->lock, flags);
  5653. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5654. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5655. iwl3945_hw_channel_switch(priv, conf->channel);
  5656. goto out;
  5657. }
  5658. #endif
  5659. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5660. if (!conf->radio_enabled) {
  5661. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5662. goto out;
  5663. }
  5664. if (iwl3945_is_rfkill(priv)) {
  5665. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5666. ret = -EIO;
  5667. goto out;
  5668. }
  5669. iwl3945_set_rate(priv);
  5670. if (memcmp(&priv->active_rxon,
  5671. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5672. iwl3945_commit_rxon(priv);
  5673. else
  5674. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5675. IWL_DEBUG_MAC80211("leave\n");
  5676. out:
  5677. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5678. mutex_unlock(&priv->mutex);
  5679. return ret;
  5680. }
  5681. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5682. {
  5683. int rc = 0;
  5684. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5685. return;
  5686. /* The following should be done only at AP bring up */
  5687. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5688. /* RXON - unassoc (to set timing command) */
  5689. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5690. iwl3945_commit_rxon(priv);
  5691. /* RXON Timing */
  5692. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5693. iwl3945_setup_rxon_timing(priv);
  5694. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5695. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5696. if (rc)
  5697. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5698. "Attempting to continue.\n");
  5699. /* FIXME: what should be the assoc_id for AP? */
  5700. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5701. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5702. priv->staging_rxon.flags |=
  5703. RXON_FLG_SHORT_PREAMBLE_MSK;
  5704. else
  5705. priv->staging_rxon.flags &=
  5706. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5707. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5708. if (priv->assoc_capability &
  5709. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5710. priv->staging_rxon.flags |=
  5711. RXON_FLG_SHORT_SLOT_MSK;
  5712. else
  5713. priv->staging_rxon.flags &=
  5714. ~RXON_FLG_SHORT_SLOT_MSK;
  5715. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5716. priv->staging_rxon.flags &=
  5717. ~RXON_FLG_SHORT_SLOT_MSK;
  5718. }
  5719. /* restore RXON assoc */
  5720. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5721. iwl3945_commit_rxon(priv);
  5722. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5723. }
  5724. iwl3945_send_beacon_cmd(priv);
  5725. /* FIXME - we need to add code here to detect a totally new
  5726. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5727. * clear sta table, add BCAST sta... */
  5728. }
  5729. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5730. struct ieee80211_vif *vif,
  5731. struct ieee80211_if_conf *conf)
  5732. {
  5733. struct iwl3945_priv *priv = hw->priv;
  5734. DECLARE_MAC_BUF(mac);
  5735. unsigned long flags;
  5736. int rc;
  5737. if (conf == NULL)
  5738. return -EIO;
  5739. if (priv->vif != vif) {
  5740. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5741. return 0;
  5742. }
  5743. /* XXX: this MUST use conf->mac_addr */
  5744. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5745. (!conf->beacon || !conf->ssid_len)) {
  5746. IWL_DEBUG_MAC80211
  5747. ("Leaving in AP mode because HostAPD is not ready.\n");
  5748. return 0;
  5749. }
  5750. if (!iwl3945_is_alive(priv))
  5751. return -EAGAIN;
  5752. mutex_lock(&priv->mutex);
  5753. if (conf->bssid)
  5754. IWL_DEBUG_MAC80211("bssid: %s\n",
  5755. print_mac(mac, conf->bssid));
  5756. /*
  5757. * very dubious code was here; the probe filtering flag is never set:
  5758. *
  5759. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5760. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5761. */
  5762. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5763. if (!conf->bssid) {
  5764. conf->bssid = priv->mac_addr;
  5765. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5766. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5767. print_mac(mac, conf->bssid));
  5768. }
  5769. if (priv->ibss_beacon)
  5770. dev_kfree_skb(priv->ibss_beacon);
  5771. priv->ibss_beacon = conf->beacon;
  5772. }
  5773. if (iwl3945_is_rfkill(priv))
  5774. goto done;
  5775. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5776. !is_multicast_ether_addr(conf->bssid)) {
  5777. /* If there is currently a HW scan going on in the background
  5778. * then we need to cancel it else the RXON below will fail. */
  5779. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5780. IWL_WARNING("Aborted scan still in progress "
  5781. "after 100ms\n");
  5782. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5783. mutex_unlock(&priv->mutex);
  5784. return -EAGAIN;
  5785. }
  5786. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5787. /* TODO: Audit driver for usage of these members and see
  5788. * if mac80211 deprecates them (priv->bssid looks like it
  5789. * shouldn't be there, but I haven't scanned the IBSS code
  5790. * to verify) - jpk */
  5791. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5792. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5793. iwl3945_config_ap(priv);
  5794. else {
  5795. rc = iwl3945_commit_rxon(priv);
  5796. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5797. iwl3945_add_station(priv,
  5798. priv->active_rxon.bssid_addr, 1, 0);
  5799. }
  5800. } else {
  5801. iwl3945_scan_cancel_timeout(priv, 100);
  5802. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5803. iwl3945_commit_rxon(priv);
  5804. }
  5805. done:
  5806. spin_lock_irqsave(&priv->lock, flags);
  5807. if (!conf->ssid_len)
  5808. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5809. else
  5810. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5811. priv->essid_len = conf->ssid_len;
  5812. spin_unlock_irqrestore(&priv->lock, flags);
  5813. IWL_DEBUG_MAC80211("leave\n");
  5814. mutex_unlock(&priv->mutex);
  5815. return 0;
  5816. }
  5817. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5818. unsigned int changed_flags,
  5819. unsigned int *total_flags,
  5820. int mc_count, struct dev_addr_list *mc_list)
  5821. {
  5822. /*
  5823. * XXX: dummy
  5824. * see also iwl3945_connection_init_rx_config
  5825. */
  5826. *total_flags = 0;
  5827. }
  5828. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5829. struct ieee80211_if_init_conf *conf)
  5830. {
  5831. struct iwl3945_priv *priv = hw->priv;
  5832. IWL_DEBUG_MAC80211("enter\n");
  5833. mutex_lock(&priv->mutex);
  5834. if (iwl3945_is_ready_rf(priv)) {
  5835. iwl3945_scan_cancel_timeout(priv, 100);
  5836. cancel_delayed_work(&priv->post_associate);
  5837. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5838. iwl3945_commit_rxon(priv);
  5839. }
  5840. if (priv->vif == conf->vif) {
  5841. priv->vif = NULL;
  5842. memset(priv->bssid, 0, ETH_ALEN);
  5843. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5844. priv->essid_len = 0;
  5845. }
  5846. mutex_unlock(&priv->mutex);
  5847. IWL_DEBUG_MAC80211("leave\n");
  5848. }
  5849. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5850. {
  5851. int rc = 0;
  5852. unsigned long flags;
  5853. struct iwl3945_priv *priv = hw->priv;
  5854. IWL_DEBUG_MAC80211("enter\n");
  5855. mutex_lock(&priv->mutex);
  5856. spin_lock_irqsave(&priv->lock, flags);
  5857. if (!iwl3945_is_ready_rf(priv)) {
  5858. rc = -EIO;
  5859. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5860. goto out_unlock;
  5861. }
  5862. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  5863. rc = -EIO;
  5864. IWL_ERROR("ERROR: APs don't scan\n");
  5865. goto out_unlock;
  5866. }
  5867. /* we don't schedule scan within next_scan_jiffies period */
  5868. if (priv->next_scan_jiffies &&
  5869. time_after(priv->next_scan_jiffies, jiffies)) {
  5870. rc = -EAGAIN;
  5871. goto out_unlock;
  5872. }
  5873. /* if we just finished scan ask for delay */
  5874. if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
  5875. IWL_DELAY_NEXT_SCAN, jiffies)) {
  5876. rc = -EAGAIN;
  5877. goto out_unlock;
  5878. }
  5879. if (len) {
  5880. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5881. iwl3945_escape_essid(ssid, len), (int)len);
  5882. priv->one_direct_scan = 1;
  5883. priv->direct_ssid_len = (u8)
  5884. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5885. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5886. } else
  5887. priv->one_direct_scan = 0;
  5888. rc = iwl3945_scan_initiate(priv);
  5889. IWL_DEBUG_MAC80211("leave\n");
  5890. out_unlock:
  5891. spin_unlock_irqrestore(&priv->lock, flags);
  5892. mutex_unlock(&priv->mutex);
  5893. return rc;
  5894. }
  5895. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5896. const u8 *local_addr, const u8 *addr,
  5897. struct ieee80211_key_conf *key)
  5898. {
  5899. struct iwl3945_priv *priv = hw->priv;
  5900. int rc = 0;
  5901. u8 sta_id;
  5902. IWL_DEBUG_MAC80211("enter\n");
  5903. if (!iwl3945_param_hwcrypto) {
  5904. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5905. return -EOPNOTSUPP;
  5906. }
  5907. if (is_zero_ether_addr(addr))
  5908. /* only support pairwise keys */
  5909. return -EOPNOTSUPP;
  5910. sta_id = iwl3945_hw_find_station(priv, addr);
  5911. if (sta_id == IWL_INVALID_STATION) {
  5912. DECLARE_MAC_BUF(mac);
  5913. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  5914. print_mac(mac, addr));
  5915. return -EINVAL;
  5916. }
  5917. mutex_lock(&priv->mutex);
  5918. iwl3945_scan_cancel_timeout(priv, 100);
  5919. switch (cmd) {
  5920. case SET_KEY:
  5921. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5922. if (!rc) {
  5923. iwl3945_set_rxon_hwcrypto(priv, 1);
  5924. iwl3945_commit_rxon(priv);
  5925. key->hw_key_idx = sta_id;
  5926. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5927. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5928. }
  5929. break;
  5930. case DISABLE_KEY:
  5931. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5932. if (!rc) {
  5933. iwl3945_set_rxon_hwcrypto(priv, 0);
  5934. iwl3945_commit_rxon(priv);
  5935. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5936. }
  5937. break;
  5938. default:
  5939. rc = -EINVAL;
  5940. }
  5941. IWL_DEBUG_MAC80211("leave\n");
  5942. mutex_unlock(&priv->mutex);
  5943. return rc;
  5944. }
  5945. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  5946. const struct ieee80211_tx_queue_params *params)
  5947. {
  5948. struct iwl3945_priv *priv = hw->priv;
  5949. unsigned long flags;
  5950. int q;
  5951. IWL_DEBUG_MAC80211("enter\n");
  5952. if (!iwl3945_is_ready_rf(priv)) {
  5953. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5954. return -EIO;
  5955. }
  5956. if (queue >= AC_NUM) {
  5957. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5958. return 0;
  5959. }
  5960. if (!priv->qos_data.qos_enable) {
  5961. priv->qos_data.qos_active = 0;
  5962. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  5963. return 0;
  5964. }
  5965. q = AC_NUM - 1 - queue;
  5966. spin_lock_irqsave(&priv->lock, flags);
  5967. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5968. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5969. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5970. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5971. cpu_to_le16((params->txop * 32));
  5972. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5973. priv->qos_data.qos_active = 1;
  5974. spin_unlock_irqrestore(&priv->lock, flags);
  5975. mutex_lock(&priv->mutex);
  5976. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5977. iwl3945_activate_qos(priv, 1);
  5978. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5979. iwl3945_activate_qos(priv, 0);
  5980. mutex_unlock(&priv->mutex);
  5981. IWL_DEBUG_MAC80211("leave\n");
  5982. return 0;
  5983. }
  5984. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5985. struct ieee80211_tx_queue_stats *stats)
  5986. {
  5987. struct iwl3945_priv *priv = hw->priv;
  5988. int i, avail;
  5989. struct iwl3945_tx_queue *txq;
  5990. struct iwl3945_queue *q;
  5991. unsigned long flags;
  5992. IWL_DEBUG_MAC80211("enter\n");
  5993. if (!iwl3945_is_ready_rf(priv)) {
  5994. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5995. return -EIO;
  5996. }
  5997. spin_lock_irqsave(&priv->lock, flags);
  5998. for (i = 0; i < AC_NUM; i++) {
  5999. txq = &priv->txq[i];
  6000. q = &txq->q;
  6001. avail = iwl3945_queue_space(q);
  6002. stats->data[i].len = q->n_window - avail;
  6003. stats->data[i].limit = q->n_window - q->high_mark;
  6004. stats->data[i].count = q->n_window;
  6005. }
  6006. spin_unlock_irqrestore(&priv->lock, flags);
  6007. IWL_DEBUG_MAC80211("leave\n");
  6008. return 0;
  6009. }
  6010. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6011. struct ieee80211_low_level_stats *stats)
  6012. {
  6013. IWL_DEBUG_MAC80211("enter\n");
  6014. IWL_DEBUG_MAC80211("leave\n");
  6015. return 0;
  6016. }
  6017. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6018. {
  6019. IWL_DEBUG_MAC80211("enter\n");
  6020. IWL_DEBUG_MAC80211("leave\n");
  6021. return 0;
  6022. }
  6023. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6024. {
  6025. struct iwl3945_priv *priv = hw->priv;
  6026. unsigned long flags;
  6027. mutex_lock(&priv->mutex);
  6028. IWL_DEBUG_MAC80211("enter\n");
  6029. iwl3945_reset_qos(priv);
  6030. cancel_delayed_work(&priv->post_associate);
  6031. spin_lock_irqsave(&priv->lock, flags);
  6032. priv->assoc_id = 0;
  6033. priv->assoc_capability = 0;
  6034. priv->call_post_assoc_from_beacon = 0;
  6035. /* new association get rid of ibss beacon skb */
  6036. if (priv->ibss_beacon)
  6037. dev_kfree_skb(priv->ibss_beacon);
  6038. priv->ibss_beacon = NULL;
  6039. priv->beacon_int = priv->hw->conf.beacon_int;
  6040. priv->timestamp1 = 0;
  6041. priv->timestamp0 = 0;
  6042. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6043. priv->beacon_int = 0;
  6044. spin_unlock_irqrestore(&priv->lock, flags);
  6045. if (!iwl3945_is_ready_rf(priv)) {
  6046. IWL_DEBUG_MAC80211("leave - not ready\n");
  6047. mutex_unlock(&priv->mutex);
  6048. return;
  6049. }
  6050. /* we are restarting association process
  6051. * clear RXON_FILTER_ASSOC_MSK bit
  6052. */
  6053. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6054. iwl3945_scan_cancel_timeout(priv, 100);
  6055. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6056. iwl3945_commit_rxon(priv);
  6057. }
  6058. /* Per mac80211.h: This is only used in IBSS mode... */
  6059. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6060. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6061. mutex_unlock(&priv->mutex);
  6062. return;
  6063. }
  6064. priv->only_active_channel = 0;
  6065. iwl3945_set_rate(priv);
  6066. mutex_unlock(&priv->mutex);
  6067. IWL_DEBUG_MAC80211("leave\n");
  6068. }
  6069. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6070. struct ieee80211_tx_control *control)
  6071. {
  6072. struct iwl3945_priv *priv = hw->priv;
  6073. unsigned long flags;
  6074. mutex_lock(&priv->mutex);
  6075. IWL_DEBUG_MAC80211("enter\n");
  6076. if (!iwl3945_is_ready_rf(priv)) {
  6077. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6078. mutex_unlock(&priv->mutex);
  6079. return -EIO;
  6080. }
  6081. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6082. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6083. mutex_unlock(&priv->mutex);
  6084. return -EIO;
  6085. }
  6086. spin_lock_irqsave(&priv->lock, flags);
  6087. if (priv->ibss_beacon)
  6088. dev_kfree_skb(priv->ibss_beacon);
  6089. priv->ibss_beacon = skb;
  6090. priv->assoc_id = 0;
  6091. IWL_DEBUG_MAC80211("leave\n");
  6092. spin_unlock_irqrestore(&priv->lock, flags);
  6093. iwl3945_reset_qos(priv);
  6094. queue_work(priv->workqueue, &priv->post_associate.work);
  6095. mutex_unlock(&priv->mutex);
  6096. return 0;
  6097. }
  6098. /*****************************************************************************
  6099. *
  6100. * sysfs attributes
  6101. *
  6102. *****************************************************************************/
  6103. #ifdef CONFIG_IWL3945_DEBUG
  6104. /*
  6105. * The following adds a new attribute to the sysfs representation
  6106. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6107. * used for controlling the debug level.
  6108. *
  6109. * See the level definitions in iwl for details.
  6110. */
  6111. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6112. {
  6113. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6114. }
  6115. static ssize_t store_debug_level(struct device_driver *d,
  6116. const char *buf, size_t count)
  6117. {
  6118. char *p = (char *)buf;
  6119. u32 val;
  6120. val = simple_strtoul(p, &p, 0);
  6121. if (p == buf)
  6122. printk(KERN_INFO DRV_NAME
  6123. ": %s is not in hex or decimal form.\n", buf);
  6124. else
  6125. iwl3945_debug_level = val;
  6126. return strnlen(buf, count);
  6127. }
  6128. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6129. show_debug_level, store_debug_level);
  6130. #endif /* CONFIG_IWL3945_DEBUG */
  6131. static ssize_t show_rf_kill(struct device *d,
  6132. struct device_attribute *attr, char *buf)
  6133. {
  6134. /*
  6135. * 0 - RF kill not enabled
  6136. * 1 - SW based RF kill active (sysfs)
  6137. * 2 - HW based RF kill active
  6138. * 3 - Both HW and SW based RF kill active
  6139. */
  6140. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6141. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6142. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6143. return sprintf(buf, "%i\n", val);
  6144. }
  6145. static ssize_t store_rf_kill(struct device *d,
  6146. struct device_attribute *attr,
  6147. const char *buf, size_t count)
  6148. {
  6149. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6150. mutex_lock(&priv->mutex);
  6151. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6152. mutex_unlock(&priv->mutex);
  6153. return count;
  6154. }
  6155. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6156. static ssize_t show_temperature(struct device *d,
  6157. struct device_attribute *attr, char *buf)
  6158. {
  6159. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6160. if (!iwl3945_is_alive(priv))
  6161. return -EAGAIN;
  6162. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6163. }
  6164. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6165. static ssize_t show_rs_window(struct device *d,
  6166. struct device_attribute *attr,
  6167. char *buf)
  6168. {
  6169. struct iwl3945_priv *priv = d->driver_data;
  6170. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6171. }
  6172. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6173. static ssize_t show_tx_power(struct device *d,
  6174. struct device_attribute *attr, char *buf)
  6175. {
  6176. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6177. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6178. }
  6179. static ssize_t store_tx_power(struct device *d,
  6180. struct device_attribute *attr,
  6181. const char *buf, size_t count)
  6182. {
  6183. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6184. char *p = (char *)buf;
  6185. u32 val;
  6186. val = simple_strtoul(p, &p, 10);
  6187. if (p == buf)
  6188. printk(KERN_INFO DRV_NAME
  6189. ": %s is not in decimal form.\n", buf);
  6190. else
  6191. iwl3945_hw_reg_set_txpower(priv, val);
  6192. return count;
  6193. }
  6194. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6195. static ssize_t show_flags(struct device *d,
  6196. struct device_attribute *attr, char *buf)
  6197. {
  6198. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6199. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6200. }
  6201. static ssize_t store_flags(struct device *d,
  6202. struct device_attribute *attr,
  6203. const char *buf, size_t count)
  6204. {
  6205. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6206. u32 flags = simple_strtoul(buf, NULL, 0);
  6207. mutex_lock(&priv->mutex);
  6208. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6209. /* Cancel any currently running scans... */
  6210. if (iwl3945_scan_cancel_timeout(priv, 100))
  6211. IWL_WARNING("Could not cancel scan.\n");
  6212. else {
  6213. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6214. flags);
  6215. priv->staging_rxon.flags = cpu_to_le32(flags);
  6216. iwl3945_commit_rxon(priv);
  6217. }
  6218. }
  6219. mutex_unlock(&priv->mutex);
  6220. return count;
  6221. }
  6222. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6223. static ssize_t show_filter_flags(struct device *d,
  6224. struct device_attribute *attr, char *buf)
  6225. {
  6226. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6227. return sprintf(buf, "0x%04X\n",
  6228. le32_to_cpu(priv->active_rxon.filter_flags));
  6229. }
  6230. static ssize_t store_filter_flags(struct device *d,
  6231. struct device_attribute *attr,
  6232. const char *buf, size_t count)
  6233. {
  6234. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6235. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6236. mutex_lock(&priv->mutex);
  6237. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6238. /* Cancel any currently running scans... */
  6239. if (iwl3945_scan_cancel_timeout(priv, 100))
  6240. IWL_WARNING("Could not cancel scan.\n");
  6241. else {
  6242. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6243. "0x%04X\n", filter_flags);
  6244. priv->staging_rxon.filter_flags =
  6245. cpu_to_le32(filter_flags);
  6246. iwl3945_commit_rxon(priv);
  6247. }
  6248. }
  6249. mutex_unlock(&priv->mutex);
  6250. return count;
  6251. }
  6252. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6253. store_filter_flags);
  6254. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6255. static ssize_t show_measurement(struct device *d,
  6256. struct device_attribute *attr, char *buf)
  6257. {
  6258. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6259. struct iwl3945_spectrum_notification measure_report;
  6260. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6261. u8 *data = (u8 *) & measure_report;
  6262. unsigned long flags;
  6263. spin_lock_irqsave(&priv->lock, flags);
  6264. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6265. spin_unlock_irqrestore(&priv->lock, flags);
  6266. return 0;
  6267. }
  6268. memcpy(&measure_report, &priv->measure_report, size);
  6269. priv->measurement_status = 0;
  6270. spin_unlock_irqrestore(&priv->lock, flags);
  6271. while (size && (PAGE_SIZE - len)) {
  6272. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6273. PAGE_SIZE - len, 1);
  6274. len = strlen(buf);
  6275. if (PAGE_SIZE - len)
  6276. buf[len++] = '\n';
  6277. ofs += 16;
  6278. size -= min(size, 16U);
  6279. }
  6280. return len;
  6281. }
  6282. static ssize_t store_measurement(struct device *d,
  6283. struct device_attribute *attr,
  6284. const char *buf, size_t count)
  6285. {
  6286. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6287. struct ieee80211_measurement_params params = {
  6288. .channel = le16_to_cpu(priv->active_rxon.channel),
  6289. .start_time = cpu_to_le64(priv->last_tsf),
  6290. .duration = cpu_to_le16(1),
  6291. };
  6292. u8 type = IWL_MEASURE_BASIC;
  6293. u8 buffer[32];
  6294. u8 channel;
  6295. if (count) {
  6296. char *p = buffer;
  6297. strncpy(buffer, buf, min(sizeof(buffer), count));
  6298. channel = simple_strtoul(p, NULL, 0);
  6299. if (channel)
  6300. params.channel = channel;
  6301. p = buffer;
  6302. while (*p && *p != ' ')
  6303. p++;
  6304. if (*p)
  6305. type = simple_strtoul(p + 1, NULL, 0);
  6306. }
  6307. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6308. "channel %d (for '%s')\n", type, params.channel, buf);
  6309. iwl3945_get_measurement(priv, &params, type);
  6310. return count;
  6311. }
  6312. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6313. show_measurement, store_measurement);
  6314. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6315. static ssize_t store_retry_rate(struct device *d,
  6316. struct device_attribute *attr,
  6317. const char *buf, size_t count)
  6318. {
  6319. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6320. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6321. if (priv->retry_rate <= 0)
  6322. priv->retry_rate = 1;
  6323. return count;
  6324. }
  6325. static ssize_t show_retry_rate(struct device *d,
  6326. struct device_attribute *attr, char *buf)
  6327. {
  6328. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6329. return sprintf(buf, "%d", priv->retry_rate);
  6330. }
  6331. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6332. store_retry_rate);
  6333. static ssize_t store_power_level(struct device *d,
  6334. struct device_attribute *attr,
  6335. const char *buf, size_t count)
  6336. {
  6337. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6338. int rc;
  6339. int mode;
  6340. mode = simple_strtoul(buf, NULL, 0);
  6341. mutex_lock(&priv->mutex);
  6342. if (!iwl3945_is_ready(priv)) {
  6343. rc = -EAGAIN;
  6344. goto out;
  6345. }
  6346. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6347. mode = IWL_POWER_AC;
  6348. else
  6349. mode |= IWL_POWER_ENABLED;
  6350. if (mode != priv->power_mode) {
  6351. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6352. if (rc) {
  6353. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6354. goto out;
  6355. }
  6356. priv->power_mode = mode;
  6357. }
  6358. rc = count;
  6359. out:
  6360. mutex_unlock(&priv->mutex);
  6361. return rc;
  6362. }
  6363. #define MAX_WX_STRING 80
  6364. /* Values are in microsecond */
  6365. static const s32 timeout_duration[] = {
  6366. 350000,
  6367. 250000,
  6368. 75000,
  6369. 37000,
  6370. 25000,
  6371. };
  6372. static const s32 period_duration[] = {
  6373. 400000,
  6374. 700000,
  6375. 1000000,
  6376. 1000000,
  6377. 1000000
  6378. };
  6379. static ssize_t show_power_level(struct device *d,
  6380. struct device_attribute *attr, char *buf)
  6381. {
  6382. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6383. int level = IWL_POWER_LEVEL(priv->power_mode);
  6384. char *p = buf;
  6385. p += sprintf(p, "%d ", level);
  6386. switch (level) {
  6387. case IWL_POWER_MODE_CAM:
  6388. case IWL_POWER_AC:
  6389. p += sprintf(p, "(AC)");
  6390. break;
  6391. case IWL_POWER_BATTERY:
  6392. p += sprintf(p, "(BATTERY)");
  6393. break;
  6394. default:
  6395. p += sprintf(p,
  6396. "(Timeout %dms, Period %dms)",
  6397. timeout_duration[level - 1] / 1000,
  6398. period_duration[level - 1] / 1000);
  6399. }
  6400. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6401. p += sprintf(p, " OFF\n");
  6402. else
  6403. p += sprintf(p, " \n");
  6404. return (p - buf + 1);
  6405. }
  6406. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6407. store_power_level);
  6408. static ssize_t show_channels(struct device *d,
  6409. struct device_attribute *attr, char *buf)
  6410. {
  6411. /* all this shit doesn't belong into sysfs anyway */
  6412. return 0;
  6413. }
  6414. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6415. static ssize_t show_statistics(struct device *d,
  6416. struct device_attribute *attr, char *buf)
  6417. {
  6418. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6419. u32 size = sizeof(struct iwl3945_notif_statistics);
  6420. u32 len = 0, ofs = 0;
  6421. u8 *data = (u8 *) & priv->statistics;
  6422. int rc = 0;
  6423. if (!iwl3945_is_alive(priv))
  6424. return -EAGAIN;
  6425. mutex_lock(&priv->mutex);
  6426. rc = iwl3945_send_statistics_request(priv);
  6427. mutex_unlock(&priv->mutex);
  6428. if (rc) {
  6429. len = sprintf(buf,
  6430. "Error sending statistics request: 0x%08X\n", rc);
  6431. return len;
  6432. }
  6433. while (size && (PAGE_SIZE - len)) {
  6434. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6435. PAGE_SIZE - len, 1);
  6436. len = strlen(buf);
  6437. if (PAGE_SIZE - len)
  6438. buf[len++] = '\n';
  6439. ofs += 16;
  6440. size -= min(size, 16U);
  6441. }
  6442. return len;
  6443. }
  6444. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6445. static ssize_t show_antenna(struct device *d,
  6446. struct device_attribute *attr, char *buf)
  6447. {
  6448. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6449. if (!iwl3945_is_alive(priv))
  6450. return -EAGAIN;
  6451. return sprintf(buf, "%d\n", priv->antenna);
  6452. }
  6453. static ssize_t store_antenna(struct device *d,
  6454. struct device_attribute *attr,
  6455. const char *buf, size_t count)
  6456. {
  6457. int ant;
  6458. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6459. if (count == 0)
  6460. return 0;
  6461. if (sscanf(buf, "%1i", &ant) != 1) {
  6462. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6463. return count;
  6464. }
  6465. if ((ant >= 0) && (ant <= 2)) {
  6466. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6467. priv->antenna = (enum iwl3945_antenna)ant;
  6468. } else
  6469. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6470. return count;
  6471. }
  6472. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6473. static ssize_t show_status(struct device *d,
  6474. struct device_attribute *attr, char *buf)
  6475. {
  6476. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6477. if (!iwl3945_is_alive(priv))
  6478. return -EAGAIN;
  6479. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6480. }
  6481. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6482. static ssize_t dump_error_log(struct device *d,
  6483. struct device_attribute *attr,
  6484. const char *buf, size_t count)
  6485. {
  6486. char *p = (char *)buf;
  6487. if (p[0] == '1')
  6488. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6489. return strnlen(buf, count);
  6490. }
  6491. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6492. static ssize_t dump_event_log(struct device *d,
  6493. struct device_attribute *attr,
  6494. const char *buf, size_t count)
  6495. {
  6496. char *p = (char *)buf;
  6497. if (p[0] == '1')
  6498. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6499. return strnlen(buf, count);
  6500. }
  6501. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6502. /*****************************************************************************
  6503. *
  6504. * driver setup and teardown
  6505. *
  6506. *****************************************************************************/
  6507. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6508. {
  6509. priv->workqueue = create_workqueue(DRV_NAME);
  6510. init_waitqueue_head(&priv->wait_command_queue);
  6511. INIT_WORK(&priv->up, iwl3945_bg_up);
  6512. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6513. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6514. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6515. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6516. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6517. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6518. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6519. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6520. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6521. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6522. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6523. iwl3945_hw_setup_deferred_work(priv);
  6524. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6525. iwl3945_irq_tasklet, (unsigned long)priv);
  6526. }
  6527. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6528. {
  6529. iwl3945_hw_cancel_deferred_work(priv);
  6530. cancel_delayed_work_sync(&priv->init_alive_start);
  6531. cancel_delayed_work(&priv->scan_check);
  6532. cancel_delayed_work(&priv->alive_start);
  6533. cancel_delayed_work(&priv->post_associate);
  6534. cancel_work_sync(&priv->beacon_update);
  6535. }
  6536. static struct attribute *iwl3945_sysfs_entries[] = {
  6537. &dev_attr_antenna.attr,
  6538. &dev_attr_channels.attr,
  6539. &dev_attr_dump_errors.attr,
  6540. &dev_attr_dump_events.attr,
  6541. &dev_attr_flags.attr,
  6542. &dev_attr_filter_flags.attr,
  6543. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6544. &dev_attr_measurement.attr,
  6545. #endif
  6546. &dev_attr_power_level.attr,
  6547. &dev_attr_retry_rate.attr,
  6548. &dev_attr_rf_kill.attr,
  6549. &dev_attr_rs_window.attr,
  6550. &dev_attr_statistics.attr,
  6551. &dev_attr_status.attr,
  6552. &dev_attr_temperature.attr,
  6553. &dev_attr_tx_power.attr,
  6554. NULL
  6555. };
  6556. static struct attribute_group iwl3945_attribute_group = {
  6557. .name = NULL, /* put in device directory */
  6558. .attrs = iwl3945_sysfs_entries,
  6559. };
  6560. static struct ieee80211_ops iwl3945_hw_ops = {
  6561. .tx = iwl3945_mac_tx,
  6562. .start = iwl3945_mac_start,
  6563. .stop = iwl3945_mac_stop,
  6564. .add_interface = iwl3945_mac_add_interface,
  6565. .remove_interface = iwl3945_mac_remove_interface,
  6566. .config = iwl3945_mac_config,
  6567. .config_interface = iwl3945_mac_config_interface,
  6568. .configure_filter = iwl3945_configure_filter,
  6569. .set_key = iwl3945_mac_set_key,
  6570. .get_stats = iwl3945_mac_get_stats,
  6571. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6572. .conf_tx = iwl3945_mac_conf_tx,
  6573. .get_tsf = iwl3945_mac_get_tsf,
  6574. .reset_tsf = iwl3945_mac_reset_tsf,
  6575. .beacon_update = iwl3945_mac_beacon_update,
  6576. .hw_scan = iwl3945_mac_hw_scan
  6577. };
  6578. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6579. {
  6580. int err = 0;
  6581. struct iwl3945_priv *priv;
  6582. struct ieee80211_hw *hw;
  6583. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6584. int i;
  6585. unsigned long flags;
  6586. DECLARE_MAC_BUF(mac);
  6587. /* Disabling hardware scan means that mac80211 will perform scans
  6588. * "the hard way", rather than using device's scan. */
  6589. if (iwl3945_param_disable_hw_scan) {
  6590. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6591. iwl3945_hw_ops.hw_scan = NULL;
  6592. }
  6593. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6594. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6595. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6596. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6597. err = -EINVAL;
  6598. goto out;
  6599. }
  6600. /* mac80211 allocates memory for this device instance, including
  6601. * space for this driver's private structure */
  6602. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6603. if (hw == NULL) {
  6604. IWL_ERROR("Can not allocate network device\n");
  6605. err = -ENOMEM;
  6606. goto out;
  6607. }
  6608. SET_IEEE80211_DEV(hw, &pdev->dev);
  6609. hw->rate_control_algorithm = "iwl-3945-rs";
  6610. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6611. priv = hw->priv;
  6612. priv->hw = hw;
  6613. priv->pci_dev = pdev;
  6614. priv->cfg = cfg;
  6615. /* Select antenna (may be helpful if only one antenna is connected) */
  6616. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6617. #ifdef CONFIG_IWL3945_DEBUG
  6618. iwl3945_debug_level = iwl3945_param_debug;
  6619. atomic_set(&priv->restrict_refcnt, 0);
  6620. #endif
  6621. priv->retry_rate = 1;
  6622. priv->ibss_beacon = NULL;
  6623. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  6624. * the range of signal quality values that we'll provide.
  6625. * Negative values for level/noise indicate that we'll provide dBm.
  6626. * For WE, at least, non-0 values here *enable* display of values
  6627. * in app (iwconfig). */
  6628. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  6629. hw->max_noise = -20; /* noise level, negative indicates dBm */
  6630. hw->max_signal = 100; /* link quality indication (%) */
  6631. /* Tell mac80211 our Tx characteristics */
  6632. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  6633. /* 4 EDCA QOS priorities */
  6634. hw->queues = 4;
  6635. spin_lock_init(&priv->lock);
  6636. spin_lock_init(&priv->power_data.lock);
  6637. spin_lock_init(&priv->sta_lock);
  6638. spin_lock_init(&priv->hcmd_lock);
  6639. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6640. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6641. INIT_LIST_HEAD(&priv->free_frames);
  6642. mutex_init(&priv->mutex);
  6643. if (pci_enable_device(pdev)) {
  6644. err = -ENODEV;
  6645. goto out_ieee80211_free_hw;
  6646. }
  6647. pci_set_master(pdev);
  6648. /* Clear the driver's (not device's) station table */
  6649. iwl3945_clear_stations_table(priv);
  6650. priv->data_retry_limit = -1;
  6651. priv->ieee_channels = NULL;
  6652. priv->ieee_rates = NULL;
  6653. priv->band = IEEE80211_BAND_2GHZ;
  6654. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6655. if (!err)
  6656. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6657. if (err) {
  6658. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6659. goto out_pci_disable_device;
  6660. }
  6661. pci_set_drvdata(pdev, priv);
  6662. err = pci_request_regions(pdev, DRV_NAME);
  6663. if (err)
  6664. goto out_pci_disable_device;
  6665. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6666. * PCI Tx retries from interfering with C3 CPU state */
  6667. pci_write_config_byte(pdev, 0x41, 0x00);
  6668. priv->hw_base = pci_iomap(pdev, 0, 0);
  6669. if (!priv->hw_base) {
  6670. err = -ENODEV;
  6671. goto out_pci_release_regions;
  6672. }
  6673. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6674. (unsigned long long) pci_resource_len(pdev, 0));
  6675. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6676. /* Initialize module parameter values here */
  6677. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6678. if (iwl3945_param_disable) {
  6679. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6680. IWL_DEBUG_INFO("Radio disabled.\n");
  6681. }
  6682. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6683. printk(KERN_INFO DRV_NAME
  6684. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6685. /* Device-specific setup */
  6686. if (iwl3945_hw_set_hw_setting(priv)) {
  6687. IWL_ERROR("failed to set hw settings\n");
  6688. goto out_iounmap;
  6689. }
  6690. if (iwl3945_param_qos_enable)
  6691. priv->qos_data.qos_enable = 1;
  6692. iwl3945_reset_qos(priv);
  6693. priv->qos_data.qos_active = 0;
  6694. priv->qos_data.qos_cap.val = 0;
  6695. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6696. iwl3945_setup_deferred_work(priv);
  6697. iwl3945_setup_rx_handlers(priv);
  6698. priv->rates_mask = IWL_RATES_MASK;
  6699. /* If power management is turned on, default to AC mode */
  6700. priv->power_mode = IWL_POWER_AC;
  6701. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6702. spin_lock_irqsave(&priv->lock, flags);
  6703. iwl3945_disable_interrupts(priv);
  6704. spin_unlock_irqrestore(&priv->lock, flags);
  6705. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6706. if (err) {
  6707. IWL_ERROR("failed to create sysfs device attributes\n");
  6708. goto out_release_irq;
  6709. }
  6710. /* nic init */
  6711. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6712. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6713. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6714. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6715. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6716. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6717. if (err < 0) {
  6718. IWL_DEBUG_INFO("Failed to init the card\n");
  6719. goto out_remove_sysfs;
  6720. }
  6721. /* Read the EEPROM */
  6722. err = iwl3945_eeprom_init(priv);
  6723. if (err) {
  6724. IWL_ERROR("Unable to init EEPROM\n");
  6725. goto out_remove_sysfs;
  6726. }
  6727. /* MAC Address location in EEPROM same for 3945/4965 */
  6728. get_eeprom_mac(priv, priv->mac_addr);
  6729. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6730. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6731. err = iwl3945_init_channel_map(priv);
  6732. if (err) {
  6733. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6734. goto out_remove_sysfs;
  6735. }
  6736. err = iwl3945_init_geos(priv);
  6737. if (err) {
  6738. IWL_ERROR("initializing geos failed: %d\n", err);
  6739. goto out_free_channel_map;
  6740. }
  6741. err = ieee80211_register_hw(priv->hw);
  6742. if (err) {
  6743. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6744. goto out_free_geos;
  6745. }
  6746. priv->hw->conf.beacon_int = 100;
  6747. priv->mac80211_registered = 1;
  6748. pci_save_state(pdev);
  6749. pci_disable_device(pdev);
  6750. return 0;
  6751. out_free_geos:
  6752. iwl3945_free_geos(priv);
  6753. out_free_channel_map:
  6754. iwl3945_free_channel_map(priv);
  6755. out_remove_sysfs:
  6756. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6757. out_release_irq:
  6758. destroy_workqueue(priv->workqueue);
  6759. priv->workqueue = NULL;
  6760. iwl3945_unset_hw_setting(priv);
  6761. out_iounmap:
  6762. pci_iounmap(pdev, priv->hw_base);
  6763. out_pci_release_regions:
  6764. pci_release_regions(pdev);
  6765. out_pci_disable_device:
  6766. pci_disable_device(pdev);
  6767. pci_set_drvdata(pdev, NULL);
  6768. out_ieee80211_free_hw:
  6769. ieee80211_free_hw(priv->hw);
  6770. out:
  6771. return err;
  6772. }
  6773. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6774. {
  6775. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6776. struct list_head *p, *q;
  6777. int i;
  6778. unsigned long flags;
  6779. if (!priv)
  6780. return;
  6781. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6782. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6783. iwl3945_down(priv);
  6784. /* make sure we flush any pending irq or
  6785. * tasklet for the driver
  6786. */
  6787. spin_lock_irqsave(&priv->lock, flags);
  6788. iwl3945_disable_interrupts(priv);
  6789. spin_unlock_irqrestore(&priv->lock, flags);
  6790. iwl_synchronize_irq(priv);
  6791. /* Free MAC hash list for ADHOC */
  6792. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  6793. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  6794. list_del(p);
  6795. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  6796. }
  6797. }
  6798. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6799. iwl3945_dealloc_ucode_pci(priv);
  6800. if (priv->rxq.bd)
  6801. iwl3945_rx_queue_free(priv, &priv->rxq);
  6802. iwl3945_hw_txq_ctx_free(priv);
  6803. iwl3945_unset_hw_setting(priv);
  6804. iwl3945_clear_stations_table(priv);
  6805. if (priv->mac80211_registered) {
  6806. ieee80211_unregister_hw(priv->hw);
  6807. }
  6808. /*netif_stop_queue(dev); */
  6809. flush_workqueue(priv->workqueue);
  6810. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6811. * priv->workqueue... so we can't take down the workqueue
  6812. * until now... */
  6813. destroy_workqueue(priv->workqueue);
  6814. priv->workqueue = NULL;
  6815. pci_iounmap(pdev, priv->hw_base);
  6816. pci_release_regions(pdev);
  6817. pci_disable_device(pdev);
  6818. pci_set_drvdata(pdev, NULL);
  6819. iwl3945_free_channel_map(priv);
  6820. iwl3945_free_geos(priv);
  6821. if (priv->ibss_beacon)
  6822. dev_kfree_skb(priv->ibss_beacon);
  6823. ieee80211_free_hw(priv->hw);
  6824. }
  6825. #ifdef CONFIG_PM
  6826. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6827. {
  6828. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6829. if (priv->is_open) {
  6830. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6831. iwl3945_mac_stop(priv->hw);
  6832. priv->is_open = 1;
  6833. }
  6834. pci_set_power_state(pdev, PCI_D3hot);
  6835. return 0;
  6836. }
  6837. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6838. {
  6839. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6840. pci_set_power_state(pdev, PCI_D0);
  6841. if (priv->is_open)
  6842. iwl3945_mac_start(priv->hw);
  6843. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6844. return 0;
  6845. }
  6846. #endif /* CONFIG_PM */
  6847. /*****************************************************************************
  6848. *
  6849. * driver and module entry point
  6850. *
  6851. *****************************************************************************/
  6852. static struct pci_driver iwl3945_driver = {
  6853. .name = DRV_NAME,
  6854. .id_table = iwl3945_hw_card_ids,
  6855. .probe = iwl3945_pci_probe,
  6856. .remove = __devexit_p(iwl3945_pci_remove),
  6857. #ifdef CONFIG_PM
  6858. .suspend = iwl3945_pci_suspend,
  6859. .resume = iwl3945_pci_resume,
  6860. #endif
  6861. };
  6862. static int __init iwl3945_init(void)
  6863. {
  6864. int ret;
  6865. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6866. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6867. ret = iwl3945_rate_control_register();
  6868. if (ret) {
  6869. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6870. return ret;
  6871. }
  6872. ret = pci_register_driver(&iwl3945_driver);
  6873. if (ret) {
  6874. IWL_ERROR("Unable to initialize PCI module\n");
  6875. goto error_register;
  6876. }
  6877. #ifdef CONFIG_IWL3945_DEBUG
  6878. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6879. if (ret) {
  6880. IWL_ERROR("Unable to create driver sysfs file\n");
  6881. goto error_debug;
  6882. }
  6883. #endif
  6884. return ret;
  6885. #ifdef CONFIG_IWL3945_DEBUG
  6886. error_debug:
  6887. pci_unregister_driver(&iwl3945_driver);
  6888. #endif
  6889. error_register:
  6890. iwl3945_rate_control_unregister();
  6891. return ret;
  6892. }
  6893. static void __exit iwl3945_exit(void)
  6894. {
  6895. #ifdef CONFIG_IWL3945_DEBUG
  6896. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6897. #endif
  6898. pci_unregister_driver(&iwl3945_driver);
  6899. iwl3945_rate_control_unregister();
  6900. }
  6901. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6902. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6903. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6904. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6905. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6906. MODULE_PARM_DESC(hwcrypto,
  6907. "using hardware crypto engine (default 0 [software])\n");
  6908. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6909. MODULE_PARM_DESC(debug, "debug output mask");
  6910. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6911. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6912. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6913. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6914. /* QoS */
  6915. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6916. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6917. module_exit(iwl3945_exit);
  6918. module_init(iwl3945_init);